MFC r302785, r308300, r308441

r302785 (jmcneill):
H3/A83T: Use PLL_PERIPH/2 for AHB2 parent clock.

Reviewed by:	manu

r308300:
For AHB clock we need to set the assigned parents for cpufreq(4) to work.

r308441:
Do not fail to attach the clock if we cannot set the assigned parents as this
property isn't mandatory.

1 files changed, 12 insertions, 7 deletions

diff --git a/sys/arm/allwinner/clk/aw_ahbclk.c b/sys/arm/allwinner/clk/aw_ahbclk.c
index f2c7005..36a7356 100644
--- a/sys/arm/allwinner/clk/aw_ahbclk.c
+++ b/sys/arm/allwinner/clk/aw_ahbclk.c
@@ -140,10 +140,14 @@ aw_ahbclk_init(struct clknode *clk, device_t dev)
 		    A83T_AHB1_CLK_SRC_SEL_SHIFT;
 		break;
 	case AW_H3_AHB2:
+		/* Set source to PLL_PERIPH/2 */
+		index = H3_AHB2_CLK_CFG_PLL_PERIPH_DIV2;
 		DEVICE_LOCK(sc);
 		AHBCLK_READ(sc, &val);
+		val &= ~H3_AHB2_CLK_CFG;
+		val |= (index << H3_AHB2_CLK_CFG_SHIFT);
+		AHBCLK_WRITE(sc, val);
 		DEVICE_UNLOCK(sc);
-		index = (val & H3_AHB2_CLK_CFG) >> H3_AHB2_CLK_CFG_SHIFT;
 		break;
 	default:
 		return (ENXIO);
@@ -189,12 +193,7 @@ aw_ahbclk_recalc_freq(struct clknode *clk, uint64_t *freq)
 			pre_div = 1;
 		break;
 	case AW_H3_AHB2:
-		src_sel = (val & H3_AHB2_CLK_CFG) >> H3_AHB2_CLK_CFG_SHIFT;
-		if (src_sel == H3_AHB2_CLK_CFG_PLL_PERIPH_DIV2)
-			div = 2;
-		else
-			div = 1;
-		pre_div = 1;
+		div = pre_div = 1;
 		break;
 	default:
 		div = 1 << ((val & A10_AHB_CLK_DIV_RATIO) >>
@@ -351,6 +350,12 @@ aw_ahbclk_attach(device_t dev)
 		goto fail;
 	}
 
+	error = clk_set_assigned(dev, node);
+	if (error != 0 && error != ENOENT) {
+		device_printf(dev, "cannot set assigned parents: %d\n", error);
+		goto fail;
+	}
+
 	if (bootverbose)
 		clkdom_dump(clkdom);