sys/arm: Minor spelling fixes.

Only affects comments: no functional change.

8 files changed, 10 insertions, 10 deletions

diff --git a/sys/arm/xscale/i8134x/crb_machdep.c b/sys/arm/xscale/i8134x/crb_machdep.c
index 5268ca9..898bbaa 100644
--- a/sys/arm/xscale/i8134x/crb_machdep.c
+++ b/sys/arm/xscale/i8134x/crb_machdep.c
@@ -38,7 +38,7 @@
  *
  * machdep.c
  *
- * Machine dependant functions for kernel setup
+ * Machine dependent functions for kernel setup
  *
  * This file needs a lot of work.
  *
diff --git a/sys/arm/xscale/i8134x/i81342reg.h b/sys/arm/xscale/i8134x/i81342reg.h
index fd087ce..2402194 100644
--- a/sys/arm/xscale/i8134x/i81342reg.h
+++ b/sys/arm/xscale/i8134x/i81342reg.h
@@ -184,7 +184,7 @@
 #define ATU_IATVR2	0x005c /* Inbound ATU Translate Value Register 2 */
 #define ATU_IAUTVR2	0x0060 /* Inbound ATU Upper Translate Value Register 2*/
 #define ATU_ERLR	0x0064 /* Expansion ROM Limit Register */
-#define ATU_ERTVR	0x0068 /* Expansion ROM Translater Value Register */
+#define ATU_ERTVR	0x0068 /* Expansion ROM Translator Value Register */
 #define ATU_ERUTVR	0x006c /* Expansion ROM Upper Translate Value Register*/
 #define ATU_CR		0x0070 /* ATU Configuration Register */
 #define ATU_CR_OUT_EN	(1 << 1)
diff --git a/sys/arm/xscale/ixp425/avila_machdep.c b/sys/arm/xscale/ixp425/avila_machdep.c
index 46e4b10..f26d3ca 100644
--- a/sys/arm/xscale/ixp425/avila_machdep.c
+++ b/sys/arm/xscale/ixp425/avila_machdep.c
@@ -38,7 +38,7 @@
  *
  * machdep.c
  *
- * Machine dependant functions for kernel setup
+ * Machine dependent functions for kernel setup
  *
  * This file needs a lot of work.
  *
diff --git a/sys/arm/xscale/ixp425/cambria_gpio.c b/sys/arm/xscale/ixp425/cambria_gpio.c
index aa3947b..c871418 100644
--- a/sys/arm/xscale/ixp425/cambria_gpio.c
+++ b/sys/arm/xscale/ixp425/cambria_gpio.c
@@ -32,7 +32,7 @@
  * The Cambria PLD does not set the i2c ack bit after each write, if we used the
  * regular iicbus interface it would abort the xfer after the address byte
  * times out and not write our latch. To get around this we grab the iicbus and
- * then do our own bit banging. This is a comprimise to changing all the iicbb
+ * then do our own bit banging. This is a compromise to changing all the iicbb
  * device methods to allow a flag to be passed down and is similir to how Linux
  * does it.
  *
diff --git a/sys/arm/xscale/ixp425/ixp425_npe.c b/sys/arm/xscale/ixp425/ixp425_npe.c
index 6dbce4c..95facb4 100644
--- a/sys/arm/xscale/ixp425/ixp425_npe.c
+++ b/sys/arm/xscale/ixp425/ixp425_npe.c
@@ -507,7 +507,7 @@ ixpnpe_load_firmware(struct ixpnpe_softc *sc, const char *imageName,
 
 	/*
 	 * If download was successful, store image Id in list of
-	 * currently loaded images. If a critical error occured
+	 * currently loaded images. If a critical error occurred
 	 * during download, record that the NPE has an invalid image
 	 */
 	mtx_lock(&sc->sc_mtx);
@@ -864,7 +864,7 @@ npe_cpu_reset(struct ixpnpe_softc *sc)
 	while (npe_checkbits(sc,
 	      IX_NPEDL_REG_OFFSET_STAT, IX_NPEDL_MASK_STAT_IFNE)) {
 		/*
-		 * Step execution of the NPE intruction to read inFIFO using
+		 * Step execution of the NPE instruction to read inFIFO using
 		 * the Debug Executing Context stack.
 		 */
 		error = npe_cpu_step(sc, IX_NPEDL_INSTR_RD_FIFO, 0, 0);
@@ -1307,7 +1307,7 @@ npe_logical_reg_write(struct ixpnpe_softc *sc, uint32_t regAddr, uint32_t regVal
 		    ((regVal & IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA) <<
 		     IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA);
 
-		/* step execution of NPE intruction using Debug ECS */
+		/* step execution of NPE instruction using Debug ECS */
 		error = npe_cpu_step(sc, npeInstruction,
 		    ctxtNum, IX_NPEDL_WR_INSTR_LDUR);
 	}
diff --git a/sys/arm/xscale/ixp425/ixp425_npereg.h b/sys/arm/xscale/ixp425/ixp425_npereg.h
index 069e9d7..94aff85 100644
--- a/sys/arm/xscale/ixp425/ixp425_npereg.h
+++ b/sys/arm/xscale/ixp425/ixp425_npereg.h
@@ -125,7 +125,7 @@
 
 /*
  * Reset value for Mailbox (MBST) register
- * NOTE that if used, it should be complemented with an NPE intruction
+ * NOTE that if used, it should be complemented with an NPE instruction
  * to clear the Mailbox at the NPE side as well
  */
 #define IX_NPEDL_REG_RESET_MBST              0x0000F0F0
diff --git a/sys/arm/xscale/ixp425/ixp425_qmgr.c b/sys/arm/xscale/ixp425/ixp425_qmgr.c
index 822623c..d6db260 100644
--- a/sys/arm/xscale/ixp425/ixp425_qmgr.c
+++ b/sys/arm/xscale/ixp425/ixp425_qmgr.c
@@ -421,7 +421,7 @@ ixpqmgr_qwrite(int qId, uint32_t entry)
 		    return ENOSPC;
 		}
 		/*
-		 * No overflow occured : someone is draining the queue
+		 * No overflow occurred : someone is draining the queue
 		 * and the current counter needs to be
 		 * updated from the current number of entries in the queue
 		 */
diff --git a/sys/arm/xscale/pxa/pxa_machdep.c b/sys/arm/xscale/pxa/pxa_machdep.c
index 32cbcd8..bc3ab6f 100644
--- a/sys/arm/xscale/pxa/pxa_machdep.c
+++ b/sys/arm/xscale/pxa/pxa_machdep.c
@@ -38,7 +38,7 @@
  *
  * machdep.c
  *
- * Machine dependant functions for kernel setup
+ * Machine dependent functions for kernel setup
  *
  * This file needs a lot of work.
  *