When mapping device memory, use PTE_DEVICE rather than PTE_NOCACHE.

On armv4 these are defined as synonyms right now, but it's a bit ambiguous
what NOCACHE means (is buffering/write-combining also enabled or not?); this
is a first step towards replacing PTE_NOCACHE with a less ambiguous name.

5 files changed, 28 insertions, 28 deletions

diff --git a/sys/arm/xscale/i80321/ep80219_machdep.c b/sys/arm/xscale/i80321/ep80219_machdep.c
index 3112fe4..54fdfbb 100644
--- a/sys/arm/xscale/i80321/ep80219_machdep.c
+++ b/sys/arm/xscale/i80321/ep80219_machdep.c
@@ -130,21 +130,21 @@ static const struct arm_devmap_entry ep80219_devmap[] = {
 		IQ80321_OBIO_BASE,
 		IQ80321_OBIO_SIZE,
 		VM_PROT_READ|VM_PROT_WRITE,
-		PTE_NOCACHE,
+		PTE_DEVICE,
 	},
 	{
 		IQ80321_IOW_VBASE,
 		VERDE_OUT_XLATE_IO_WIN0_BASE,
 		VERDE_OUT_XLATE_IO_WIN_SIZE,
 		VM_PROT_READ|VM_PROT_WRITE,
-		PTE_NOCACHE,
+		PTE_DEVICE,
 	},	
 	{
 		IQ80321_80321_VBASE,
 		VERDE_PMMR_BASE,
 		VERDE_PMMR_SIZE,
 		VM_PROT_READ|VM_PROT_WRITE,
-		PTE_NOCACHE,
+		PTE_DEVICE,
 	},
 	{
 		0,
diff --git a/sys/arm/xscale/i80321/iq31244_machdep.c b/sys/arm/xscale/i80321/iq31244_machdep.c
index 3882729..e1ca22b 100644
--- a/sys/arm/xscale/i80321/iq31244_machdep.c
+++ b/sys/arm/xscale/i80321/iq31244_machdep.c
@@ -128,14 +128,14 @@ static const struct arm_devmap_entry iq80321_devmap[] = {
 		    IQ80321_OBIO_BASE,
 		    IQ80321_OBIO_SIZE,
 		    VM_PROT_READ|VM_PROT_WRITE,
-		    PTE_NOCACHE,
+		    PTE_DEVICE,
 	    },
 	    {
 	    	    IQ80321_IOW_VBASE,
 		    VERDE_OUT_XLATE_IO_WIN0_BASE,
 		    VERDE_OUT_XLATE_IO_WIN_SIZE,
 		    VM_PROT_READ|VM_PROT_WRITE,
-		    PTE_NOCACHE,
+		    PTE_DEVICE,
 	    },
 	
 	    {
@@ -143,7 +143,7 @@ static const struct arm_devmap_entry iq80321_devmap[] = {
 		    VERDE_PMMR_BASE,
 		    VERDE_PMMR_SIZE,
 		    VM_PROT_READ|VM_PROT_WRITE,
-		    PTE_NOCACHE,
+		    PTE_DEVICE,
 	    },
 	    {
 		    0,
diff --git a/sys/arm/xscale/i8134x/crb_machdep.c b/sys/arm/xscale/i8134x/crb_machdep.c
index 98e1ca6..13e62c4 100644
--- a/sys/arm/xscale/i8134x/crb_machdep.c
+++ b/sys/arm/xscale/i8134x/crb_machdep.c
@@ -124,7 +124,7 @@ static const struct arm_devmap_entry iq81342_devmap[] = {
 		    IOP34X_HWADDR,
 		    IOP34X_SIZE,
 		    VM_PROT_READ|VM_PROT_WRITE,
-		    PTE_NOCACHE,
+		    PTE_DEVICE,
 	    },
 	    {
 		    /*
@@ -135,14 +135,14 @@ static const struct arm_devmap_entry iq81342_devmap[] = {
 		    IOP34X_PCIX_OIOBAR &~ (0x100000 - 1),
 		    0x100000,
 		    VM_PROT_READ|VM_PROT_WRITE,
-		    PTE_NOCACHE,
+		    PTE_DEVICE,
 	    },
 	    {
 		    IOP34X_PCE1_VADDR,
 		    IOP34X_PCE1,
 		    IOP34X_PCE1_SIZE,
 		    VM_PROT_READ|VM_PROT_WRITE,
-		    PTE_NOCACHE,
+		    PTE_DEVICE,
 	    },
 	    {	
 		    0,
diff --git a/sys/arm/xscale/ixp425/avila_machdep.c b/sys/arm/xscale/ixp425/avila_machdep.c
index 2ef2adc..2b27a66 100644
--- a/sys/arm/xscale/ixp425/avila_machdep.c
+++ b/sys/arm/xscale/ixp425/avila_machdep.c
@@ -118,31 +118,31 @@ struct pv_addr minidataclean;
 static const struct arm_devmap_entry ixp425_devmap[] = {
 	/* Physical/Virtual address for I/O space */
     { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* Expansion Bus */
     { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* CFI Flash on the Expansion Bus */
     { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE,
-      IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* IXP425 PCI Configuration */
     { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* SDRAM Controller */
     { IXP425_MCU_VBASE, IXP425_MCU_HWBASE, IXP425_MCU_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* PCI Memory Space */
     { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* Q-Mgr Memory Space */
     { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
     { 0 },
 };
@@ -151,45 +151,45 @@ static const struct arm_devmap_entry ixp425_devmap[] = {
 static const struct arm_devmap_entry ixp435_devmap[] = {
 	/* Physical/Virtual address for I/O space */
     { IXP425_IO_VBASE, IXP425_IO_HWBASE, IXP425_IO_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
     { IXP425_EXP_VBASE, IXP425_EXP_HWBASE, IXP425_EXP_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* IXP425 PCI Configuration */
     { IXP425_PCI_VBASE, IXP425_PCI_HWBASE, IXP425_PCI_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* DDRII Controller NB: mapped same place as IXP425 */
     { IXP425_MCU_VBASE, IXP435_MCU_HWBASE, IXP425_MCU_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* PCI Memory Space */
     { IXP425_PCI_MEM_VBASE, IXP425_PCI_MEM_HWBASE, IXP425_PCI_MEM_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* Q-Mgr Memory Space */
     { IXP425_QMGR_VBASE, IXP425_QMGR_HWBASE, IXP425_QMGR_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* CFI Flash on the Expansion Bus */
     { IXP425_EXP_BUS_CS0_VBASE, IXP425_EXP_BUS_CS0_HWBASE,
-      IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      IXP425_EXP_BUS_CS0_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* USB1 Memory Space */
     { IXP435_USB1_VBASE, IXP435_USB1_HWBASE, IXP435_USB1_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 	/* USB2 Memory Space */
     { IXP435_USB2_VBASE, IXP435_USB2_HWBASE, IXP435_USB2_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* GPS Memory Space */
     { CAMBRIA_GPS_VBASE, CAMBRIA_GPS_HWBASE, CAMBRIA_GPS_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
 	/* RS485 Memory Space */
     { CAMBRIA_RS485_VBASE, CAMBRIA_RS485_HWBASE, CAMBRIA_RS485_SIZE,
-      VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE, },
+      VM_PROT_READ|VM_PROT_WRITE, PTE_DEVICE, },
 
     { 0 }
 };
diff --git a/sys/arm/xscale/pxa/pxa_machdep.c b/sys/arm/xscale/pxa/pxa_machdep.c
index 2e235f0..6bf58d3 100644
--- a/sys/arm/xscale/pxa/pxa_machdep.c
+++ b/sys/arm/xscale/pxa/pxa_machdep.c
@@ -129,7 +129,7 @@ static const struct arm_devmap_entry pxa_devmap[] = {
 		PXA2X0_PERIPH_START,
 		PXA250_PERIPH_END - PXA2X0_PERIPH_START,
 		VM_PROT_READ|VM_PROT_WRITE,
-		PTE_NOCACHE,
+		PTE_DEVICE,
 	},
 	{ 0, 0, 0, 0, 0, }
 };