diff options
| author | loos <loos@FreeBSD.org> | 2016-12-31 01:54:48 +0000 |
|---|---|---|
| committer | loos <loos@FreeBSD.org> | 2016-12-31 01:54:48 +0000 |
| commit | 94e07a4b48a5f04fe2a736f2dca31158b09fed52 (patch) | |
| tree | 345c9cbca5d7c25939f228c4065bc6f33aecfa47 /sys/arm/ti | |
| parent | b27ff02f45134fdeb70f8c5efaebaeaaa1fe1801 (diff) | |
| download | FreeBSD-src-94e07a4b48a5f04fe2a736f2dca31158b09fed52.zip FreeBSD-src-94e07a4b48a5f04fe2a736f2dca31158b09fed52.tar.gz | |
MFC r309345:
The RX_FREEBUFFER registers are a write to increment field.
Writing the full queue size to it every time was makeing it overflow with a
lot of bogus values.
This fixes the interrupt storms on irq 40.
MFC r309347:
MDIO_PHYACCESS_ACK is only valid for read access, remove it from
miibus_writereg.
Reduce the DELAY() between reads while waiting for MII access.
Spotted by: yongari
Sponsored by: Rubicon Communications, LLC (Netgate)
Diffstat (limited to 'sys/arm/ti')
| -rw-r--r-- | sys/arm/ti/cpsw/if_cpsw.c | 5 | ||||
| -rw-r--r-- | sys/arm/ti/cpsw/if_cpswvar.h | 4 |
2 files changed, 3 insertions, 6 deletions
diff --git a/sys/arm/ti/cpsw/if_cpsw.c b/sys/arm/ti/cpsw/if_cpsw.c index 3acb26c..8a72aa1 100644 --- a/sys/arm/ti/cpsw/if_cpsw.c +++ b/sys/arm/ti/cpsw/if_cpsw.c @@ -1513,9 +1513,6 @@ cpswp_miibus_writereg(device_t dev, int phy, int reg, int value) return (0); } - if ((cpsw_read_4(sc->swsc, sc->phyaccess) & MDIO_PHYACCESS_ACK) == 0) - device_printf(dev, "Failed to write to PHY.\n"); - return (0); } @@ -1761,7 +1758,7 @@ cpsw_rx_enqueue(struct cpsw_softc *sc) sc->rx.queue_adds += added; sc->rx.avail_queue_len -= added; sc->rx.active_queue_len += added; - cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), sc->rx.active_queue_len); + cpsw_write_4(sc, CPSW_CPDMA_RX_FREEBUFFER(0), added); if (sc->rx.active_queue_len > sc->rx.max_active_queue_len) { sc->rx.max_active_queue_len = sc->rx.active_queue_len; } diff --git a/sys/arm/ti/cpsw/if_cpswvar.h b/sys/arm/ti/cpsw/if_cpswvar.h index 4024c52..f037dd5 100644 --- a/sys/arm/ti/cpsw/if_cpswvar.h +++ b/sys/arm/ti/cpsw/if_cpswvar.h @@ -33,8 +33,8 @@ #define CPSW_INTR_COUNT 4 /* MII BUS */ -#define CPSW_MIIBUS_RETRIES 5 -#define CPSW_MIIBUS_DELAY 1000 +#define CPSW_MIIBUS_RETRIES 20 +#define CPSW_MIIBUS_DELAY 100 #define CPSW_MAX_ALE_ENTRIES 1024 |
