diff options
author | br <br@FreeBSD.org> | 2014-08-01 06:20:25 +0000 |
---|---|---|
committer | br <br@FreeBSD.org> | 2014-08-01 06:20:25 +0000 |
commit | f484e00cba11cc9a0349663251cca555828fdfe7 (patch) | |
tree | 2690befd8438972b435cc7a807b51e807001efe9 /sys/arm/samsung/exynos/exynos5_pad.c | |
parent | 0fddfcfca33730558212923fe091b556985ac271 (diff) | |
download | FreeBSD-src-f484e00cba11cc9a0349663251cca555828fdfe7.zip FreeBSD-src-f484e00cba11cc9a0349663251cca555828fdfe7.tar.gz |
Add support for Chromebook2 -- next-generation 8-core
(4 in operation), 4GB ram (3.5 usable) ARM machine.
Support covers device drivers for:
- Serial Peripheral Interface (SPI)
- Chrome Embedded Controller (EC) - SPI-based version
- XHCI and USB 3.0 dual-role device PHY
Also:
- Add support for Exynos5420 in Pad module
- Move power-related functions to separate driver --
Power Management Unit (PMU)
- Enable XHCI for Chromebook1
Special thanks to grehan@ for hardware, and to
hselasky@ for r269139.
Diffstat (limited to 'sys/arm/samsung/exynos/exynos5_pad.c')
-rw-r--r-- | sys/arm/samsung/exynos/exynos5_pad.c | 311 |
1 files changed, 217 insertions, 94 deletions
diff --git a/sys/arm/samsung/exynos/exynos5_pad.c b/sys/arm/samsung/exynos/exynos5_pad.c index 10e1a25..6a2c401 100644 --- a/sys/arm/samsung/exynos/exynos5_pad.c +++ b/sys/arm/samsung/exynos/exynos5_pad.c @@ -65,10 +65,13 @@ __FBSDID("$FreeBSD$"); #define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT) -#define NPORTS 4 -#define NGRP 40 -#define NGPIO 253 -#define NINTS 16 +#define MAX_PORTS 5 +#define MAX_NGPIO 253 + +#define N_EXT_INTS 16 + +#define EXYNOS5250 1 +#define EXYNOS5420 2 #define PIN_IN 0 #define PIN_OUT 1 @@ -90,45 +93,81 @@ static int pad_pin_set(device_t, uint32_t, unsigned int); static int pad_pin_get(device_t, uint32_t, unsigned int *); static int pad_pin_toggle(device_t, uint32_t pin); +struct gpio_bank { + char *name; + uint32_t port; + uint32_t con; + uint32_t ngpio; + uint32_t ext_con; + uint32_t ext_flt_con; + uint32_t mask; + uint32_t pend; +}; + struct pad_softc { - struct resource *res[NPORTS+4]; - bus_space_tag_t bst[NPORTS]; - bus_space_handle_t bsh[NPORTS]; + struct resource *res[MAX_PORTS * 2]; + bus_space_tag_t bst[MAX_PORTS]; + bus_space_handle_t bsh[MAX_PORTS]; struct mtx sc_mtx; int gpio_npins; - struct gpio_pin gpio_pins[NGPIO]; - void *gpio_ih[NPORTS+4]; + struct gpio_pin gpio_pins[MAX_NGPIO]; + void *gpio_ih[MAX_PORTS]; device_t dev; + int model; + struct resource_spec *pad_spec; + struct gpio_bank *gpio_map; + struct interrupt_entry *interrupt_table; + int nports; }; struct pad_softc *gpio_sc; -static struct resource_spec pad_spec[] = { +static struct resource_spec pad_spec_5250[] = { + { SYS_RES_MEMORY, 0, RF_ACTIVE }, + { SYS_RES_MEMORY, 1, RF_ACTIVE }, + { SYS_RES_MEMORY, 2, RF_ACTIVE }, + { SYS_RES_MEMORY, 3, RF_ACTIVE }, + { SYS_RES_IRQ, 0, RF_ACTIVE }, + { SYS_RES_IRQ, 1, RF_ACTIVE }, + { SYS_RES_IRQ, 2, RF_ACTIVE }, + { SYS_RES_IRQ, 3, RF_ACTIVE }, + { -1, 0 } +}; + +static struct resource_spec pad_spec_5420[] = { { SYS_RES_MEMORY, 0, RF_ACTIVE }, { SYS_RES_MEMORY, 1, RF_ACTIVE }, { SYS_RES_MEMORY, 2, RF_ACTIVE }, { SYS_RES_MEMORY, 3, RF_ACTIVE }, + { SYS_RES_MEMORY, 4, RF_ACTIVE }, { SYS_RES_IRQ, 0, RF_ACTIVE }, { SYS_RES_IRQ, 1, RF_ACTIVE }, { SYS_RES_IRQ, 2, RF_ACTIVE }, { SYS_RES_IRQ, 3, RF_ACTIVE }, + { SYS_RES_IRQ, 4, RF_ACTIVE }, { -1, 0 } }; +static struct ofw_compat_data compat_data[] = { + {"samsung,exynos5420-padctrl", EXYNOS5420}, + {"samsung,exynos5250-padctrl", EXYNOS5250}, + {NULL, 0} +}; + struct pad_intr { uint32_t enabled; void (*ih) (void *); void *ih_user; }; -static struct pad_intr intr_map[NGPIO]; +static struct pad_intr intr_map[MAX_NGPIO]; struct interrupt_entry { int gpio_number; char *combiner_source_name; }; -struct interrupt_entry interrupt_table[NINTS] = { +struct interrupt_entry interrupt_table_5250[N_EXT_INTS] = { { 147, "EINT[15]" }, { 146, "EINT[14]" }, { 145, "EINT[13]" }, @@ -147,84 +186,144 @@ struct interrupt_entry interrupt_table[NINTS] = { { 132, "EINT[0]" }, }; -struct gpio_bank { - char *name; - uint32_t port; - uint32_t con; - uint32_t ngpio; - uint32_t ext_int_grp; - uint32_t ext_con; - uint32_t ext_flt_con; - uint32_t mask; - uint32_t pend; +struct interrupt_entry interrupt_table_5420[N_EXT_INTS] = { + { 23, "EINT[15]" }, + { 22, "EINT[14]" }, + { 21, "EINT[13]" }, + { 20, "EINT[12]" }, + { 19, "EINT[11]" }, + { 18, "EINT[10]" }, + { 17, "EINT[9]" }, + { 16, "EINT[8]" }, + { 15, "EINT[7]" }, + { 14, "EINT[6]" }, + { 13, "EINT[5]" }, + { 12, "EINT[4]" }, + { 11, "EINT[3]" }, + { 10, "EINT[2]" }, + { 9, "EINT[1]" }, + { 8, "EINT[0]" }, }; /* * 253 multi-functional input/output ports */ -static struct gpio_bank gpio_map[] = { +static struct gpio_bank gpio_map_5250[] = { /* first 132 gpio */ - { "gpa0", 0, 0x000, 8, 1, 0x700, 0x800, 0x900, 0xA00 }, - { "gpa1", 0, 0x020, 6, 2, 0x704, 0x808, 0x904, 0xA04 }, - { "gpa2", 0, 0x040, 8, 3, 0x708, 0x810, 0x908, 0xA08 }, - { "gpb0", 0, 0x060, 5, 4, 0x70C, 0x818, 0x90C, 0xA0C }, - { "gpb1", 0, 0x080, 5, 5, 0x710, 0x820, 0x910, 0xA10 }, - { "gpb2", 0, 0x0A0, 4, 6, 0x714, 0x828, 0x914, 0xA14 }, - { "gpb3", 0, 0x0C0, 4, 7, 0x718, 0x830, 0x918, 0xA18 }, - { "gpc0", 0, 0x0E0, 7, 8, 0x71C, 0x838, 0x91C, 0xA1C }, - { "gpc1", 0, 0x100, 4, 9, 0x720, 0x840, 0x920, 0xA20 }, - { "gpc2", 0, 0x120, 7, 10, 0x724, 0x848, 0x924, 0xA24 }, - { "gpc3", 0, 0x140, 7, 11, 0x728, 0x850, 0x928, 0xA28 }, - { "gpd0", 0, 0x160, 4, 12, 0x72C, 0x858, 0x92C, 0xA2C }, - { "gpd1", 0, 0x180, 8, 13, 0x730, 0x860, 0x930, 0xA30 }, - { "gpy0", 0, 0x1A0, 6, 0, 0, 0, 0, 0 }, - { "gpy1", 0, 0x1C0, 4, 0, 0, 0, 0, 0 }, - { "gpy2", 0, 0x1E0, 6, 0, 0, 0, 0, 0 }, - { "gpy3", 0, 0x200, 8, 0, 0, 0, 0, 0 }, - { "gpy4", 0, 0x220, 8, 0, 0, 0, 0, 0 }, - { "gpy5", 0, 0x240, 8, 0, 0, 0, 0, 0 }, - { "gpy6", 0, 0x260, 8, 0, 0, 0, 0, 0 }, - { "gpc4", 0, 0x2E0, 7, 30, 0x734, 0x868, 0x934, 0xA34 }, + { "gpa0", 0, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 }, + { "gpa1", 0, 0x020, 6, 0x704, 0x808, 0x904, 0xA04 }, + { "gpa2", 0, 0x040, 8, 0x708, 0x810, 0x908, 0xA08 }, + { "gpb0", 0, 0x060, 5, 0x70C, 0x818, 0x90C, 0xA0C }, + { "gpb1", 0, 0x080, 5, 0x710, 0x820, 0x910, 0xA10 }, + { "gpb2", 0, 0x0A0, 4, 0x714, 0x828, 0x914, 0xA14 }, + { "gpb3", 0, 0x0C0, 4, 0x718, 0x830, 0x918, 0xA18 }, + { "gpc0", 0, 0x0E0, 7, 0x71C, 0x838, 0x91C, 0xA1C }, + { "gpc1", 0, 0x100, 4, 0x720, 0x840, 0x920, 0xA20 }, + { "gpc2", 0, 0x120, 7, 0x724, 0x848, 0x924, 0xA24 }, + { "gpc3", 0, 0x140, 7, 0x728, 0x850, 0x928, 0xA28 }, + { "gpd0", 0, 0x160, 4, 0x72C, 0x858, 0x92C, 0xA2C }, + { "gpd1", 0, 0x180, 8, 0x730, 0x860, 0x930, 0xA30 }, + { "gpy0", 0, 0x1A0, 6, 0, 0, 0, 0 }, + { "gpy1", 0, 0x1C0, 4, 0, 0, 0, 0 }, + { "gpy2", 0, 0x1E0, 6, 0, 0, 0, 0 }, + { "gpy3", 0, 0x200, 8, 0, 0, 0, 0 }, + { "gpy4", 0, 0x220, 8, 0, 0, 0, 0 }, + { "gpy5", 0, 0x240, 8, 0, 0, 0, 0 }, + { "gpy6", 0, 0x260, 8, 0, 0, 0, 0 }, + { "gpc4", 0, 0x2E0, 7, 0x734, 0x868, 0x934, 0xA34 }, /* next 32 */ - { "gpx0", 0, 0xC00, 8, 40, 0xE00, 0xE80, 0xF00, 0xF40 }, - { "gpx1", 0, 0xC20, 8, 41, 0xE04, 0xE88, 0xF04, 0xF44 }, - { "gpx2", 0, 0xC40, 8, 42, 0xE08, 0xE90, 0xF08, 0xF48 }, - { "gpx3", 0, 0xC60, 8, 43, 0xE0C, 0xE98, 0xF0C, 0xF4C }, - - { "gpe0", 1, 0x000, 8, 14, 0x700, 0x800, 0x900, 0xA00 }, - { "gpe1", 1, 0x020, 2, 15, 0x704, 0x808, 0x904, 0xA04 }, - { "gpf0", 1, 0x040, 4, 16, 0x708, 0x810, 0x908, 0xA08 }, - { "gpf1", 1, 0x060, 4, 17, 0x70C, 0x818, 0x90C, 0xA0C }, - { "gpg0", 1, 0x080, 8, 18, 0x710, 0x820, 0x910, 0xA10 }, - { "gpg1", 1, 0x0A0, 8, 19, 0x714, 0x828, 0x914, 0xA14 }, - { "gpg2", 1, 0x0C0, 2, 20, 0x718, 0x830, 0x918, 0xA18 }, - { "gph0", 1, 0x0E0, 4, 21, 0x71C, 0x838, 0x91C, 0xA1C }, - { "gph1", 1, 0x100, 8, 22, 0x720, 0x840, 0x920, 0xA20 }, - - { "gpv0", 2, 0x000, 8, 60, 0x700, 0x800, 0x900, 0xA00 }, - { "gpv1", 2, 0x020, 8, 61, 0x704, 0x808, 0x904, 0xA04 }, - { "gpv2", 2, 0x060, 8, 62, 0x708, 0x810, 0x908, 0xA08 }, - { "gpv3", 2, 0x080, 8, 63, 0x70C, 0x818, 0x90C, 0xA0C }, - { "gpv4", 2, 0x0C0, 2, 64, 0x710, 0x820, 0x910, 0xA10 }, - - { "gpz", 3, 0x000, 7, 50, 0x700, 0x800, 0x900, 0xA00 }, + { "gpx0", 0, 0xC00, 8, 0xE00, 0xE80, 0xF00, 0xF40 }, + { "gpx1", 0, 0xC20, 8, 0xE04, 0xE88, 0xF04, 0xF44 }, + { "gpx2", 0, 0xC40, 8, 0xE08, 0xE90, 0xF08, 0xF48 }, + { "gpx3", 0, 0xC60, 8, 0xE0C, 0xE98, 0xF0C, 0xF4C }, + + { "gpe0", 1, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 }, + { "gpe1", 1, 0x020, 2, 0x704, 0x808, 0x904, 0xA04 }, + { "gpf0", 1, 0x040, 4, 0x708, 0x810, 0x908, 0xA08 }, + { "gpf1", 1, 0x060, 4, 0x70C, 0x818, 0x90C, 0xA0C }, + { "gpg0", 1, 0x080, 8, 0x710, 0x820, 0x910, 0xA10 }, + { "gpg1", 1, 0x0A0, 8, 0x714, 0x828, 0x914, 0xA14 }, + { "gpg2", 1, 0x0C0, 2, 0x718, 0x830, 0x918, 0xA18 }, + { "gph0", 1, 0x0E0, 4, 0x71C, 0x838, 0x91C, 0xA1C }, + { "gph1", 1, 0x100, 8, 0x720, 0x840, 0x920, 0xA20 }, + + { "gpv0", 2, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 }, + { "gpv1", 2, 0x020, 8, 0x704, 0x808, 0x904, 0xA04 }, + { "gpv2", 2, 0x060, 8, 0x708, 0x810, 0x908, 0xA08 }, + { "gpv3", 2, 0x080, 8, 0x70C, 0x818, 0x90C, 0xA0C }, + { "gpv4", 2, 0x0C0, 2, 0x710, 0x820, 0x910, 0xA10 }, + + { "gpz", 3, 0x000, 7, 0x700, 0x800, 0x900, 0xA00 }, + + { NULL, -1, -1, -1, -1, -1, -1, -1 }, +}; + +static struct gpio_bank gpio_map_5420[] = { + /* First 40 */ + { "gpy7", 0, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 }, + { "gpx0", 0, 0xC00, 8, 0x704, 0xE80, 0xF00, 0xF40 }, + { "gpx1", 0, 0xC20, 8, 0x708, 0xE88, 0xF04, 0xF44 }, + { "gpx2", 0, 0xC40, 8, 0x70C, 0xE90, 0xF08, 0xF48 }, + { "gpx3", 0, 0xC60, 8, 0x710, 0xE98, 0xF0C, 0xF4C }, + + /* Next 85 */ + { "gpc0", 1, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 }, + { "gpc1", 1, 0x020, 8, 0x704, 0x808, 0x904, 0xA04 }, + { "gpc2", 1, 0x040, 7, 0x708, 0x810, 0x908, 0xA08 }, + { "gpc3", 1, 0x060, 4, 0x70C, 0x818, 0x90C, 0xA0C }, + { "gpc4", 1, 0x080, 2, 0x710, 0x820, 0x910, 0xA10 }, + { "gpd1", 1, 0x0A0, 8, 0x714, 0x828, 0x914, 0xA14 }, + { "gpy0", 1, 0x0C0, 6, 0x718, 0x830, 0x918, 0xA18 }, + { "gpy1", 1, 0x0E0, 4, 0x71C, 0x838, 0x91C, 0xA1C }, + { "gpy2", 1, 0x100, 6, 0x720, 0x840, 0x920, 0xA20 }, + { "gpy3", 1, 0x120, 8, 0x724, 0x848, 0x924, 0xA24 }, + { "gpy4", 1, 0x140, 8, 0x728, 0x850, 0x928, 0xA28 }, + { "gpy5", 1, 0x160, 8, 0x72C, 0x858, 0x92C, 0xA2C }, + { "gpy6", 1, 0x180, 8, 0x730, 0x860, 0x930, 0xA30 }, + + /* Next 46 */ + { "gpe0", 2, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 }, + { "gpe1", 2, 0x020, 2, 0x704, 0x808, 0x904, 0xA04 }, + { "gpf0", 2, 0x040, 6, 0x708, 0x810, 0x908, 0xA08 }, + { "gpf1", 2, 0x060, 8, 0x70C, 0x818, 0x90C, 0xA0C }, + { "gpg0", 2, 0x080, 8, 0x710, 0x820, 0x910, 0xA10 }, + { "gpg1", 2, 0x0A0, 8, 0x714, 0x828, 0x914, 0xA14 }, + { "gpg2", 2, 0x0C0, 2, 0x718, 0x830, 0x918, 0xA18 }, + { "gpj4", 2, 0x0E0, 4, 0x71C, 0x838, 0x91C, 0xA1C }, + + /* Next 54 */ + { "gpa0", 3, 0x000, 8, 0x700, 0x800, 0x900, 0xA00 }, + { "gpa1", 3, 0x020, 6, 0x704, 0x808, 0x904, 0xA04 }, + { "gpa2", 3, 0x040, 8, 0x708, 0x810, 0x908, 0xA08 }, + { "gpb0", 3, 0x060, 5, 0x70C, 0x818, 0x90C, 0xA0C }, + { "gpb1", 3, 0x080, 5, 0x710, 0x820, 0x910, 0xA10 }, + { "gpb2", 3, 0x0A0, 4, 0x714, 0x828, 0x914, 0xA14 }, + { "gpb3", 3, 0x0C0, 8, 0x718, 0x830, 0x918, 0xA18 }, + { "gpb4", 3, 0x0E0, 2, 0x71C, 0x838, 0x91C, 0xA1C }, + { "gph0", 3, 0x100, 8, 0x720, 0x840, 0x920, 0xA20 }, + + /* Last 7 */ + { "gpz", 4, 0x000, 7, 0x700, 0x800, 0x900, 0xA00 }, + + { NULL, -1, -1, -1, -1, -1, -1, -1 }, }; static int -get_bank(int gpio_number, struct gpio_bank *bank, int *pin_shift) +get_bank(struct pad_softc *sc, int gpio_number, + struct gpio_bank *bank, int *pin_shift) { int ngpio; int i; int n; n = 0; - for (i = 0; i < NGRP; i++) { - ngpio = gpio_map[i].ngpio; + for (i = 0; sc->gpio_map[i].ngpio != -1; i++) { + ngpio = sc->gpio_map[i].ngpio; if ((n + ngpio) > gpio_number) { - *bank = gpio_map[i]; + *bank = sc->gpio_map[i]; *pin_shift = (gpio_number - n); return (0); }; @@ -260,16 +359,16 @@ ext_intr(void *arg) sc = arg; n = 0; - for (i = 0; i < NGRP; i++) { + for (i = 0; sc->gpio_map[i].ngpio != -1; i++) { found = 0; - ngpio = gpio_map[i].ngpio; + ngpio = sc->gpio_map[i].ngpio; - if (gpio_map[i].pend == 0) { + if (sc->gpio_map[i].pend == 0) { n += ngpio; continue; } - reg = READ4(sc, gpio_map[i].port, gpio_map[i].pend); + reg = READ4(sc, sc->gpio_map[i].port, sc->gpio_map[i].pend); for (j = 0; j < ngpio; j++) { if (reg & (1 << j)) { @@ -286,7 +385,7 @@ ext_intr(void *arg) if (found) { /* ACK */ - WRITE4(sc, gpio_map[i].port, gpio_map[i].pend, reg); + WRITE4(sc, sc->gpio_map[i].port, sc->gpio_map[i].pend, reg); } n += ngpio; @@ -311,13 +410,13 @@ pad_setup_intr(int gpio_number, void (*ih)(void *), void *ih_user) return (-1); } - if (get_bank(gpio_number, &bank, &pin_shift) != 0) + if (get_bank(sc, gpio_number, &bank, &pin_shift) != 0) return (-1); entry = NULL; - for (i = 0; i < NINTS; i++) - if (interrupt_table[i].gpio_number == gpio_number) - entry = &interrupt_table[i]; + for (i = 0; i < N_EXT_INTS; i++) + if (sc->interrupt_table[i].gpio_number == gpio_number) + entry = &(sc->interrupt_table[i]); if (entry == NULL) { device_printf(sc->dev, "Cant find interrupt source for %d\n", @@ -374,11 +473,12 @@ pad_probe(device_t dev) if (!ofw_bus_status_okay(dev)) return (ENXIO); - if (!ofw_bus_is_compatible(dev, "exynos,pad")) - return (ENXIO); + if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { + device_set_desc(dev, "Exynos Pad Control"); + return (BUS_PROBE_DEFAULT); + } - device_set_desc(dev, "Exynos Pad Control"); - return (BUS_PROBE_DEFAULT); + return (ENXIO); } static int @@ -391,27 +491,47 @@ pad_attach(device_t dev) int i; sc = device_get_softc(dev); + mtx_init(&sc->sc_mtx, device_get_nameunit(dev), NULL, MTX_DEF); - if (bus_alloc_resources(dev, pad_spec, sc->res)) { + sc->model = ofw_bus_search_compatible(dev, compat_data)->ocd_data; + switch (sc->model) { + case EXYNOS5250: + sc->pad_spec = pad_spec_5250; + sc->gpio_map = gpio_map_5250; + sc->interrupt_table = interrupt_table_5250; + sc->gpio_npins = 253; + sc->nports = 4; + break; + case EXYNOS5420: + sc->pad_spec = pad_spec_5420; + sc->gpio_map = gpio_map_5420; + sc->interrupt_table = interrupt_table_5420; + sc->gpio_npins = 232; + sc->nports = 5; + break; + default: + return (-1); + }; + + if (bus_alloc_resources(dev, sc->pad_spec, sc->res)) { device_printf(dev, "could not allocate resources\n"); return (ENXIO); } /* Memory interface */ - for (i = 0; i < NPORTS; i++) { + for (i = 0; i < sc->nports; i++) { sc->bst[i] = rman_get_bustag(sc->res[i]); sc->bsh[i] = rman_get_bushandle(sc->res[i]); }; sc->dev = dev; - sc->gpio_npins = NGPIO; gpio_sc = sc; - for (i = 0; i < NPORTS; i++) { - if ((bus_setup_intr(dev, sc->res[NPORTS + i], + for (i = 0; i < sc->nports; i++) { + if ((bus_setup_intr(dev, sc->res[sc->nports + i], INTR_TYPE_BIO | INTR_MPSAFE, port_intr, NULL, sc, &sc->gpio_ih[i]))) { device_printf(dev, @@ -424,7 +544,7 @@ pad_attach(device_t dev) sc->gpio_pins[i].gp_pin = i; sc->gpio_pins[i].gp_caps = DEFAULT_CAPS; - if (get_bank(i, &bank, &pin_shift) != 0) + if (get_bank(sc, i, &bank, &pin_shift) != 0) continue; pin_shift *= 4; @@ -450,8 +570,11 @@ pad_attach(device_t dev) static int pad_pin_max(device_t dev, int *maxpin) { + struct pad_softc *sc; + + sc = device_get_softc(dev); - *maxpin = NGPIO - 1; + *maxpin = sc->gpio_npins - 1; return (0); } @@ -538,7 +661,7 @@ pad_pin_get(device_t dev, uint32_t pin, unsigned int *val) if (i >= sc->gpio_npins) return (EINVAL); - if (get_bank(pin, &bank, &pin_shift) != 0) + if (get_bank(sc, pin, &bank, &pin_shift) != 0) return (EINVAL); GPIO_LOCK(sc); @@ -569,7 +692,7 @@ pad_pin_toggle(device_t dev, uint32_t pin) if (i >= sc->gpio_npins) return (EINVAL); - if (get_bank(pin, &bank, &pin_shift) != 0) + if (get_bank(sc, pin, &bank, &pin_shift) != 0) return (EINVAL); GPIO_LOCK(sc); @@ -601,7 +724,7 @@ pad_pin_configure(struct pad_softc *sc, struct gpio_pin *pin, if (flags & (GPIO_PIN_INPUT|GPIO_PIN_OUTPUT)) { pin->gp_flags &= ~(GPIO_PIN_INPUT|GPIO_PIN_OUTPUT); - if (get_bank(pin->gp_pin, &bank, &pin_shift) != 0) + if (get_bank(sc, pin->gp_pin, &bank, &pin_shift) != 0) return; pin_shift *= 4; @@ -675,7 +798,7 @@ pad_pin_set(device_t dev, uint32_t pin, unsigned int value) if (i >= sc->gpio_npins) return (EINVAL); - if (get_bank(pin, &bank, &pin_shift) != 0) + if (get_bank(sc, pin, &bank, &pin_shift) != 0) return (EINVAL); GPIO_LOCK(sc); |