Import FreeBSD/arm kernel bits.

It only supports sa1110 (on simics) right now, but xscale support should come
soon.
Some of the initial work has been provided by :
Stephane Potvin <sepotvin at videotron.ca>
Most of this comes from NetBSD.

15 files changed, 2634 insertions, 0 deletions

diff --git a/sys/arm/sa11x0/assabet_machdep.c b/sys/arm/sa11x0/assabet_machdep.c
new file mode 100644
index 0000000..269e7e4
--- /dev/null
+++ b/sys/arm/sa11x0/assabet_machdep.c
@@ -0,0 +1,497 @@
+/*	$NetBSD: hpc_machdep.c,v 1.70 2003/09/16 08:18:22 agc Exp $	*/
+
+/*
+ * Copyright (c) 1994-1998 Mark Brinicombe.
+ * Copyright (c) 1994 Brini.
+ * All rights reserved.
+ *
+ * This code is derived from software written for Brini by Mark Brinicombe
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Brini.
+ * 4. The name of the company nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * RiscBSD kernel project
+ *
+ * machdep.c
+ *
+ * Machine dependant functions for kernel setup
+ *
+ * This file needs a lot of work. 
+ *
+ * Created      : 17/09/94
+ */
+
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#define _ARM32_BUS_DMA_PRIVATE
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/sysproto.h>
+#include <sys/signalvar.h>
+#include <sys/imgact.h>
+#include <sys/kernel.h>
+#include <sys/ktr.h>
+#include <sys/linker.h>
+#include <sys/lock.h>
+#include <sys/malloc.h>
+#include <sys/mutex.h>
+#include <sys/pcpu.h>
+#include <sys/proc.h>
+#include <sys/ptrace.h>
+#include <sys/cons.h>
+#include <sys/bio.h>
+#include <sys/bus.h>
+#include <sys/buf.h>
+#include <sys/exec.h>
+#include <machine/reg.h>
+#include <machine/cpu.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm.h>
+#include <vm/vm_object.h>
+#include <vm/vm_page.h>
+#include <vm/vm_pager.h>
+#include <vm/vm_map.h>
+#include <vm/vnode_pager.h>
+#include <machine/pmap.h>
+#include <machine/vmparam.h>
+#include <machine/pcb.h>
+#include <machine/undefined.h>
+#include <machine/machdep.h>
+#include <machine/metadata.h>
+#include <machine/armreg.h>
+#include <machine/bus.h>
+#include <sys/reboot.h>
+
+#define MDROOT_ADDR 0xd0400000
+
+#define KERNEL_PT_VMEM		0	/* Page table for mapping video memory */
+#define KERNEL_PT_SYS		0	/* Page table for mapping proc0 zero page */
+#define KERNEL_PT_IO		3	/* Page table for mapping IO */
+#define KERNEL_PT_IRQ		2	/* Page table for mapping irq handler */
+#define KERNEL_PT_KERNEL	1	/* Page table for mapping kernel */
+#define	KERNEL_PT_VMDATA	4	/* Page tables for mapping kernel VM */
+#define	KERNEL_PT_VMDATA_NUM	12	/* start with 16MB of KVM */
+#define	NUM_KERNEL_PTS		(KERNEL_PT_VMDATA + KERNEL_PT_VMDATA_NUM)
+
+/* Define various stack sizes in pages */
+#define IRQ_STACK_SIZE	1
+#define ABT_STACK_SIZE	1
+#ifdef IPKDB
+#define UND_STACK_SIZE	2
+#else
+#define UND_STACK_SIZE	1
+#endif
+#define	KERNEL_VM_BASE		(KERNBASE + 0x00c00000)
+#define	KERNEL_VM_SIZE		0x05000000
+
+extern u_int data_abort_handler_address;
+extern u_int prefetch_abort_handler_address;
+extern u_int undefined_handler_address;
+
+struct pv_addr kernel_pt_table[NUM_KERNEL_PTS];
+
+extern void *_end;
+
+int got_mmu = 0;
+
+extern vm_offset_t sa1_cache_clean_addr;
+
+extern int *end;
+
+struct pcpu __pcpu;
+struct pcpu *pcpup = &__pcpu;
+
+#define MDSIZE 8192
+/* Physical and virtual addresses for some global pages */
+
+vm_paddr_t phys_avail[10];
+vm_paddr_t physical_start;
+vm_paddr_t physical_end;
+vm_paddr_t physical_freestart;
+vm_offset_t physical_pages;
+vm_offset_t clean_sva, clean_eva;
+
+struct pv_addr systempage;
+struct pv_addr irqstack;
+struct pv_addr undstack;
+struct pv_addr abtstack;
+struct pv_addr kernelstack;
+void enable_mmu(vm_offset_t);
+static struct trapframe proc0_tf;
+
+struct arm32_dma_range *
+bus_dma_get_range(void)
+{
+
+	return (NULL);
+}
+
+#define CPU_SA110_CACHE_CLEAN_SIZE (0x4000 * 2)
+
+void *
+initarm(void *arg, void *arg2)
+{
+	struct pcpu *pc;
+	struct pv_addr  kernel_l1pt;
+	struct pv_addr	proc0_uarea;
+	struct pv_addr	md_addr;
+	struct pv_addr	md_bla;
+	int loop;
+	u_int kerneldatasize, symbolsize;
+	u_int l1pagetable;
+	vm_offset_t freemempos;
+	vm_size_t pt_size;
+	int i = 0;
+	uint32_t fake_preload[35];
+
+	boothowto = RB_VERBOSE | RB_SINGLE;
+	cninit();
+	set_cpufuncs();
+	fake_preload[i++] = MODINFO_NAME;
+	fake_preload[i++] = strlen("elf kernel") + 1;
+	strcpy((char*)&fake_preload[i++], "elf kernel");
+	i += 2;
+	fake_preload[i++] = MODINFO_TYPE;
+	fake_preload[i++] = strlen("elf kernel") + 1;
+	strcpy((char*)&fake_preload[i++], "elf kernel");
+	i += 2;
+	fake_preload[i++] = MODINFO_ADDR;
+	fake_preload[i++] = sizeof(vm_offset_t);
+	fake_preload[i++] = KERNBASE;
+	fake_preload[i++] = MODINFO_SIZE;
+	fake_preload[i++] = sizeof(uint32_t);
+	fake_preload[i++] = (uint32_t)&end - KERNBASE;
+	fake_preload[i++] = MODINFO_NAME;
+	fake_preload[i++] = strlen("md root") + 1;
+	strcpy((char*)&fake_preload[i++], "md root");
+	i += 1;
+	fake_preload[i++] = MODINFO_TYPE;
+	fake_preload[i++] = strlen("md_image") + 1;
+	strcpy((char*)&fake_preload[i++], "md_image");
+	i += 2;
+	fake_preload[i++] = MODINFO_ADDR;
+	fake_preload[i++] = sizeof(uint32_t);
+	fake_preload[i++] = MDROOT_ADDR;
+	fake_preload[i++] = MODINFO_SIZE;
+	fake_preload[i++] = sizeof(uint32_t);
+	fake_preload[i++] = MDSIZE * 1024;
+	fake_preload[i++] = 0;
+	fake_preload[i] = 0;
+	preload_metadata = (void *)fake_preload;
+
+	physmem =( 16 * 1024 * 1024) / PAGE_SIZE;
+	pc = &__pcpu;
+	pcpu_init(pc, 0, sizeof(struct pcpu));
+	PCPU_SET(curthread, &thread0);
+
+	physical_start = (vm_offset_t) KERNBASE;
+	physical_end =  (vm_offset_t) &end;
+	physical_freestart = (((vm_offset_t)physical_end) + PAGE_MASK) & ~PAGE_MASK;
+	md_addr.pv_va = md_addr.pv_pa = MDROOT_ADDR;
+#define KERNEL_TEXT_BASE (KERNBASE + 0x00040000)
+	kerneldatasize = (u_int32_t)&end - (u_int32_t)KERNEL_TEXT_BASE;
+	symbolsize = 0;
+	freemempos = (vm_offset_t)round_page(physical_freestart);
+	memset((void *)freemempos, 0, 256*1024);
+		/* Define a macro to simplify memory allocation */
+#define	valloc_pages(var, np)			\
+	alloc_pages((var).pv_pa, (np));		\
+	(var).pv_va = (var).pv_pa;
+
+#define alloc_pages(var, np)			\
+	(var) = freemempos;		\
+	freemempos += ((np) * PAGE_SIZE);\
+	memset((char *)(var), 0, ((np) * PAGE_SIZE));
+
+	while ((freemempos & (L1_TABLE_SIZE - 1)) != 0)
+		freemempos += PAGE_SIZE;
+	valloc_pages(kernel_l1pt, L1_TABLE_SIZE / PAGE_SIZE);
+	valloc_pages(md_bla, L2_TABLE_SIZE / PAGE_SIZE);
+	alloc_pages(sa1_cache_clean_addr, CPU_SA110_CACHE_CLEAN_SIZE / PAGE_SIZE);
+	for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
+		valloc_pages(kernel_pt_table[loop],
+		    L2_TABLE_SIZE / PAGE_SIZE);
+	}
+
+	valloc_pages(systempage, 1);
+
+	/*
+	 * Allocate a page for the system page mapped to V0x00000000
+	 * This page will just contain the system vectors and can be
+	 * shared by all processes.
+	 */
+	pt_size = round_page(freemempos) - physical_freestart;
+
+	/* Allocate stacks for all modes */
+	valloc_pages(irqstack, IRQ_STACK_SIZE);
+	valloc_pages(abtstack, ABT_STACK_SIZE);
+	valloc_pages(undstack, UND_STACK_SIZE);
+	valloc_pages(kernelstack, KSTACK_PAGES);
+
+
+#ifdef VERBOSE_INIT_ARM
+	printf("IRQ stack: p0x%08lx v0x%08lx\n", irqstack.pv_pa,
+	    irqstack.pv_va); 
+	printf("ABT stack: p0x%08lx v0x%08lx\n", abtstack.pv_pa,
+	    abtstack.pv_va); 
+	printf("UND stack: p0x%08lx v0x%08lx\n", undstack.pv_pa,
+	    undstack.pv_va); 
+	printf("SVC stack: p0x%08lx v0x%08lx\n", kernelstack.pv_pa,
+	    kernelstack.pv_va); 
+#endif
+	/*
+	 * Allocate memory for the l1 and l2 page tables. The scheme to avoid
+	 * wasting memory by allocating the l1pt on the first 16k memory was
+	 * taken from NetBSD rpc_machdep.c. NKPT should be greater than 12 for
+	 * this to work (which is supposed to be the case).
+	 */
+
+	/* Allocate pages for process 0 kernel stack and uarea */
+	valloc_pages(proc0_uarea, UAREA_PAGES);
+	
+	/*
+	 * Now we start construction of the L1 page table
+	 * We start by mapping the L2 page tables into the L1.
+	 * This means that we can replace L1 mappings later on if necessary
+	 */
+	l1pagetable = kernel_l1pt.pv_pa;
+
+
+	/* XXX bla **/
+#if 0
+	bcopy((void*)0xd0300000, &mfs_root, MD_ROOT_SIZE*1024);
+#endif
+	/* Map the L2 pages tables in the L1 page table */
+	pmap_link_l2pt(l1pagetable, 0x00000000,
+	    &kernel_pt_table[KERNEL_PT_SYS]);
+	pmap_link_l2pt(l1pagetable, KERNBASE,
+	    &kernel_pt_table[KERNEL_PT_KERNEL]);
+	pmap_link_l2pt(l1pagetable, 0xd0000000,
+	    &kernel_pt_table[KERNEL_PT_IO]);
+	pmap_link_l2pt(l1pagetable, 0x90000000, &kernel_pt_table[KERNEL_PT_IRQ]);
+	pmap_link_l2pt(l1pagetable, MDROOT_ADDR,
+	    &md_bla);
+	for (loop = 0; loop < KERNEL_PT_VMDATA_NUM; ++loop)
+		pmap_link_l2pt(l1pagetable, KERNEL_VM_BASE + loop * 0x00400000,
+		    &kernel_pt_table[KERNEL_PT_VMDATA + loop]);
+	pmap_map_chunk(l1pagetable, KERNBASE, KERNBASE,
+	   (uint32_t)&end - KERNBASE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	/* Map the stack pages */
+	pmap_map_chunk(l1pagetable, irqstack.pv_va, irqstack.pv_pa,
+	    IRQ_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	pmap_map_chunk(l1pagetable, md_addr.pv_va, md_addr.pv_pa,
+	    MDSIZE * 1024, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	pmap_map_chunk(l1pagetable, abtstack.pv_va, abtstack.pv_pa,
+	    ABT_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	pmap_map_chunk(l1pagetable, undstack.pv_va, undstack.pv_pa,
+	    UND_STACK_SIZE * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	pmap_map_chunk(l1pagetable, kernelstack.pv_va, kernelstack.pv_pa,
+	    KSTACK_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	pmap_map_chunk(l1pagetable, proc0_uarea.pv_va, proc0_uarea.pv_pa,
+	    UAREA_PAGES * PAGE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+
+
+	pmap_map_chunk(l1pagetable, kernel_l1pt.pv_va, kernel_l1pt.pv_pa,
+	    L1_TABLE_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
+
+	for (loop = 0; loop < NUM_KERNEL_PTS; ++loop) {
+		pmap_map_chunk(l1pagetable, kernel_pt_table[loop].pv_va,
+		    kernel_pt_table[loop].pv_pa, L2_TABLE_SIZE,
+		    VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
+	}
+	pmap_map_chunk(l1pagetable, md_bla.pv_va, md_bla.pv_pa, L2_TABLE_SIZE,
+	    VM_PROT_READ|VM_PROT_WRITE, PTE_PAGETABLE);
+	/* Map the vector page. */
+	pmap_map_entry(l1pagetable, vector_page, systempage.pv_pa,
+	    VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+	/* Map SACOM3. */
+	pmap_map_entry(l1pagetable, 0xd000d000, 0x80010000, 
+	    VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE);
+	pmap_map_entry(l1pagetable, 0x90050000, 0x90050000,
+	    VM_PROT_READ|VM_PROT_WRITE, PTE_NOCACHE);
+	pmap_map_chunk(l1pagetable, sa1_cache_clean_addr, 0xf0000000, 
+	    CPU_SA110_CACHE_CLEAN_SIZE, VM_PROT_READ|VM_PROT_WRITE, PTE_CACHE);
+
+	data_abort_handler_address = (u_int)data_abort_handler;
+	prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
+	undefined_handler_address = (u_int)undefinedinstruction_bounce;
+	undefined_init();
+	cpu_domains((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT);
+	setttb(kernel_l1pt.pv_pa);
+	cpu_tlb_flushID();
+	cpu_domains(DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2));
+
+		/*
+	 * Pages were allocated during the secondary bootstrap for the
+	 * stacks for different CPU modes.
+	 * We must now set the r13 registers in the different CPU modes to
+	 * point to these stacks.
+	 * Since the ARM stacks use STMFD etc. we must set r13 to the top end
+	 * of the stack memory.
+	 */
+	printf("init subsystems: stacks\n");
+
+	set_stackptr(PSR_IRQ32_MODE,
+	    irqstack.pv_va + IRQ_STACK_SIZE * PAGE_SIZE);
+	set_stackptr(PSR_ABT32_MODE,
+	    abtstack.pv_va + ABT_STACK_SIZE * PAGE_SIZE);
+	set_stackptr(PSR_UND32_MODE,
+	    undstack.pv_va + UND_STACK_SIZE * PAGE_SIZE);
+
+
+
+	/*
+	 * We must now clean the cache again....
+	 * Cleaning may be done by reading new data to displace any
+	 * dirty data in the cache. This will have happened in setttb()
+	 * but since we are boot strapping the addresses used for the read
+	 * may have just been remapped and thus the cache could be out
+	 * of sync. A re-clean after the switch will cure this.
+	 * After booting there are no gross reloations of the kernel thus
+	 * this problem will not occur after initarm().
+	 */
+/*	cpu_idcache_wbinv_all();*/
+
+
+	bootverbose = 1;
+
+#if 0
+	set_cpufuncs();
+#endif	
+	/* Set stack for exception handlers */
+	
+#if 0
+	printf("arm_init: physical_pages = %08x\n", physical_pages);
+	printf("arm_init: kernel_l1pt: pa = %08x, va = %08x\n",
+	    kernel_l1pt.pv_pa, kernel_l1pt.pv_va);
+	printf("arm_init: proc0_uarea: pa = %08x, va = %08x\n",
+	    proc0_uarea.pv_pa, proc0_uarea.pv_va);
+	printf("arm_init: proc0_kstack: pa = %08x, va = %08x\n",
+	    proc0_kstack.pv_pa, proc0_kstack.pv_va);
+#endif
+
+/*	printf("arm_init: physfree = %08x\n", physical_freestart);
+	printf("arm_init: first = %08x\n", first);
+	printf("arm_init: end = %08x\n", (uint32_t) &end);
+	
+	printf("arm_init: params = %08x\n", params);
+	printf("arm_init: params: page_size = %08x\n", params->u1.s.page_size);
+	printf("arm_init: params: nrpages = %08x\n", params->u1.s.nr_pages);
+	printf("arm_init: params: ramdisk_size = %08x\n", params->u1.s.ramdisk_size);
+	printf("arm_init: params: flags = %08x\n", params->u1.s.flags);
+	printf("arm_init: params: rootdev = %08x\n", params->u1.s.rootdev);
+	printf("arm_init: params: video_num_cols = %08x\n", params->u1.s.video_num_cols);
+	printf("arm_init: params: video_num_rows = %08x\n", params->u1.s.video_num_rows);
+	printf("arm_init: params: video_x = %08x\n", params->u1.s.video_x);
+	printf("arm_init: params: video_y = %08x\n", params->u1.s.video_y);
+	printf("arm_init: params: memc_control_reg = %08x\n", params->u1.s.memc_control_reg);
+	printf("arm_init: params: sounddefault = %02x\n", params->u1.s.sounddefault);
+	printf("arm_init: params: adfsdrives = %02x\n", params->u1.s.adfsdrives);
+	printf("arm_init: params: bytes_per_char_h = %02x\n", params->u1.s.bytes_per_char_h);
+	printf("arm_init: params: bytes_per_char_v = %02x\n", params->u1.s.bytes_per_char_v);
+	for(i = 0; i < 4; i++) {
+		printf("arm_init: params: pages_in_bank[%d] = %08x\n", i, params->u1.s.pages_in_bank[i]);
+	}
+	printf("arm_init: params: pages_in_vram = %08x\n", params->u1.s.pages_in_vram);
+	printf("arm_init: params: initrd_start = %08x\n", params->u1.s.initrd_start);
+	printf("arm_init: params: initrd_size = %08x\n", params->u1.s.initrd_size);
+	printf("arm_init: params: rd_start = %08x\n", params->u1.s.rd_start);
+	printf("arm_init: params: system_options = %08x\n", params->u1.s.system_options);
+	printf("arm_init: params: system_serial_num = %08x\n", params->u1.s.system_serial_num);
+	for(i = 0; i < 8; i++) {
+		printf("arm_init: params: paths[%d] = %s\n", i, (params->u2.paths[i][0]) ? params->u2.paths[i] : "(null)");
+	}
+	printf("arm_init: params: magic = %08x\n", params->u2.s.magic);
+	printf("arm_init: params: commandline = %s\n", (params->commandline[0]) ? params->commandline : "(null)");
+	printf("arm_init: params: bootsetting = %s\n", (params->bootsetting[0]) ? params->bootsetting : "(null)");*/
+	
+	proc_linkup(&proc0, &ksegrp0, &kse0, &thread0);
+	proc0.p_uarea = (struct user *) proc0_uarea.pv_va;
+	thread0.td_kstack = kernelstack.pv_va;
+	thread0.td_pcb = (struct pcb *)
+		(thread0.td_kstack + KSTACK_PAGES * PAGE_SIZE) - 1;
+	thread0.td_pcb->pcb_flags = 0;
+	thread0.td_frame = &proc0_tf;
+	
+	
+	/* Enable MMU, I-cache, D-cache, write buffer. */
+#if 0
+	printf("it was %p\n", (void *)cpufunc_control(0,0));
+	printf("ca c fait\n");
+	printf("before\n");
+	printf("mmu enabled\n");
+	printf("now we have %p\n", (void*)cpufunc_control(0,0));
+#endif
+
+	cpufunc_control(0x337f, 0x107d);
+	got_mmu = 1;
+	arm_vector_init(ARM_VECTORS_LOW, ARM_VEC_ALL);
+
+
+	pmap_bootstrap(KERNEL_VM_BASE, 
+	    KERNEL_VM_BASE + KERNEL_PT_VMDATA_NUM * 0x400000, &kernel_l1pt);
+
+	
+	mutex_init();
+	
+	
+#if 0
+	phys_avail[0] = 0x00000000;
+	phys_avail[1] = physmem;
+	phys_avail[2] = 0;
+#endif
+#if 0
+	phys_avail[1] = physical_start;
+	phys_avail[2] = physical_freestart;
+	phys_avail[3] = physmem;
+#endif
+#if 0
+	phys_avail[3] = 0;
+#endif
+#if 0
+	phys_avail[1] = 0x01000000 - 1;
+#endif
+	phys_avail[0] = round_page(freemempos);
+	phys_avail[1] = 0xc0000000 + 0x02000000 - 1;
+	phys_avail[2] = 0;
+	phys_avail[3] = 0;
+#if 0
+	phys_avail[4] = 0x00000000;
+	phys_avail[5] = 0x00000000;
+#endif
+	
+	/* Do basic tuning, hz etc */
+	init_param1();
+	init_param2(physmem);
+	printf("arm_init: done!\n");
+	avail_end = 0xc0000000 + 0x02000000 - 1;
+	return ((void *)(kernelstack.pv_va + USPACE_SVC_STACK_TOP));
+}
diff --git a/sys/arm/sa11x0/files.sa11x0 b/sys/arm/sa11x0/files.sa11x0
new file mode 100644
index 0000000..a704f53
--- /dev/null
+++ b/sys/arm/sa11x0/files.sa11x0
@@ -0,0 +1,11 @@
+# $FreeBSD$
+arm/sa11x0/assabet_machdep.c	optional	assabet
+arm/sa11x0/sa11x0.c		optional	saip
+arm/sa11x0/sa11x0_ost.c		optional	saip
+arm/sa11x0/sa11x0_io.c		optional	saip
+arm/sa11x0/sa11x0_io_asm.S 	optional	saip
+arm/sa11x0/sa11x0_irq.S		optional	saip
+arm/sa11x0/sa11x0_irqhandler.c 	optional	saip
+dev/uart/uart_cpu_sa1110.c 	optional	uart saip
+dev/uart/uart_dev_sa1110.c	optional	uart saip
+dev/uart/uart_bus_sa1110.c	optional	uart saip
diff --git a/sys/arm/sa11x0/sa11x0.c b/sys/arm/sa11x0/sa11x0.c
new file mode 100644
index 0000000..9b89c8f
--- /dev/null
+++ b/sys/arm/sa11x0/sa11x0.c
@@ -0,0 +1,261 @@
+/*	$NetBSD: sa11x0.c,v 1.14 2003/07/15 00:24:50 lukem Exp $	*/
+
+/*-
+ * Copyright (c) 2001, The NetBSD Foundation, Inc.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro and Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the NetBSD
+ *      Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ */
+/*-
+ * Copyright (c) 1999
+ *         Shin Takemura and PocketBSD Project. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the PocketBSD project
+ *	and its contributors.
+ * 4. Neither the name of the project nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/reboot.h>
+#include <sys/types.h>
+#include <sys/malloc.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+
+#include <vm/vm.h>
+#include <vm/vm_extern.h>
+
+#include <machine/cpu.h>
+#include <machine/bus.h>
+#include <machine/intr.h>
+#include <arm/sa11x0/sa11x0_reg.h>
+#include <arm/sa11x0/sa11x0_var.h>
+#include <arm/sa11x0/sa11x0_dmacreg.h>
+#include <arm/sa11x0/sa11x0_ppcreg.h>
+#include <arm/sa11x0/sa11x0_gpioreg.h>
+#include <machine/bus.h>
+#include <sys/rman.h>
+
+extern struct intrhand *irqhandlers[];
+extern u_int levels[];
+
+static struct resource *sa1110_alloc_resource(device_t, device_t, int, int *,
+        u_long, u_long, u_long, u_int);
+
+static int sa1110_activate_resource(device_t, device_t, int, int,
+        struct resource *);
+static int sa1110_setup_intr(device_t, device_t, struct resource *, int,
+        driver_intr_t *, void *, void **);
+
+extern u_int irqmasks[];
+
+void irq_setmasks(void);
+void intr_calculatemasks(void);
+static int
+sa1110_setup_intr(device_t dev, device_t child,
+        struct resource *ires,  int flags, driver_intr_t *intr, void *arg,
+	    void **cookiep)
+{
+	int saved_cpsr;
+	
+	if (flags & INTR_TYPE_TTY) {
+		ires->r_start = 15;
+		irqmasks[IPL_SERIAL] |= 1 << ires->r_start;
+	} else if (flags & INTR_TYPE_CLK) {
+		if (ires->r_start == 0)
+			ires->r_start = 26;
+		else
+			ires->r_start = 27;
+		irqmasks[IPL_SERIAL] |= 1 << ires->r_start;
+	}
+#if 0
+	intr_calculatemasks();
+#endif
+	saved_cpsr = SetCPSR(I32_bit, I32_bit);                 
+
+	set_splmasks();
+	irq_setmasks();
+	SetCPSR(I32_bit, saved_cpsr & I32_bit);
+	BUS_SETUP_INTR(device_get_parent(dev), child, ires, flags, intr, arg,
+	    cookiep);
+	return (0);
+}
+
+static struct resource *
+sa1110_alloc_resource(device_t bus, device_t child, int type, int *rid,
+        u_long start, u_long end, u_long count, u_int flags)
+{
+	struct resource *res = malloc(sizeof(*res), M_DEVBUF, M_WAITOK);
+/* XXX */
+	res->r_start = *rid;
+	return (res);
+}
+static int
+sa1110_activate_resource(device_t bus, device_t child, int type, int rid,
+        struct resource *r)
+{
+	return (0);
+}
+/* prototypes */
+static int	sa11x0_probe(device_t);
+static int	sa11x0_attach(device_t);
+static void	sa11x0_identify(driver_t *, device_t);
+
+extern vm_offset_t saipic_base;
+
+
+int
+sa11x0_probe(device_t dev)
+{
+	return 0;
+}
+
+void
+sa11x0_identify(driver_t *driver, device_t parent)
+{
+	
+	BUS_ADD_CHILD(parent, 0, "saip", 0);
+}
+
+int
+sa11x0_attach(device_t dev)
+{
+	struct sa11x0_softc *sc = device_get_softc(dev);
+	int unit = device_get_unit(dev);
+	sc->sc_iot = &sa11x0_bs_tag;
+
+	/* Map the SAIP */
+
+	bzero(irqhandlers, 0x20 * sizeof(void*));
+	if (bus_space_map(sc->sc_iot, SAIPIC_BASE, SAIPIC_NPORTS,
+			0, &sc->sc_ioh))
+		panic("saip%d: Cannot map registers", unit);
+	saipic_base = sc->sc_ioh;
+
+	/* Map the GPIO registers */
+	if (bus_space_map(sc->sc_iot, SAGPIO_BASE, SAGPIO_NPORTS,
+			  0, &sc->sc_gpioh))
+		panic("saip%d: unable to map GPIO registers", unit);
+	bus_space_write_4(sc->sc_iot, sc->sc_gpioh, SAGPIO_EDR, 0xffffffff);
+
+	/* Map the PPC registers */
+	if (bus_space_map(sc->sc_iot, SAPPC_BASE, SAPPC_NPORTS,
+			  0, &sc->sc_ppch))
+		panic("saip%d: unable to map PPC registers", unit);
+
+#if 0
+	/* Map the DMA controller registers */
+	if (bus_space_map(sc->sc_iot, SADMAC_BASE, SADMAC_NPORTS,
+			  0, &sc->sc_dmach))
+		panic("saip%d: unable to map DMAC registers", unit);
+#endif
+	/* Map the reset controller registers */
+	if (bus_space_map(sc->sc_iot, SARCR_BASE, PAGE_SIZE,
+			  0, &sc->sc_reseth))
+		panic("saip%d: unable to map reset registers", unit);
+	printf("\n");
+
+	
+	/*
+	 *  Mask all interrupts.
+	 *  They are later unmasked at each device's attach routine.
+	 */
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAIPIC_MR, 0);
+
+	/* Route all bits to IRQ */
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAIPIC_LR, 0);
+
+	/* Exit idle mode only when unmasked intr is received */
+	bus_space_write_4(sc->sc_iot, sc->sc_ioh, SAIPIC_CR, 1);
+#if 0
+	/* disable all DMAC channels */
+	bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR0_CLR, 1);
+	bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR1_CLR, 1);
+	bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR2_CLR, 1);
+	bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR3_CLR, 1);
+	bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR4_CLR, 1);
+	bus_space_write_4(sc->sc_iot, sc->sc_dmach, SADMAC_DCR5_CLR, 1);
+#endif
+	/*
+	 * XXX this is probably a bad place, but intr bit shouldn't be
+	 * XXX enabled before intr mask is set.
+	 * XXX Having sane imask[] suffice??
+	 */
+#if 0
+	SetCPSR(I32_bit, 0);
+#endif
+	/*
+	 *  Attach each devices
+	 */
+	device_add_child(dev, "uart", 0);
+	device_add_child(dev, "saost", 0);
+	bus_generic_probe(dev);
+	bus_generic_attach(dev);
+	return (0);
+}
+
+static device_method_t saip_methods[] = {
+	DEVMETHOD(device_probe, sa11x0_probe),
+	DEVMETHOD(device_attach, sa11x0_attach),
+	DEVMETHOD(device_identify, sa11x0_identify),
+	DEVMETHOD(bus_alloc_resource, sa1110_alloc_resource),
+	DEVMETHOD(bus_activate_resource, sa1110_activate_resource),
+	DEVMETHOD(bus_setup_intr, sa1110_setup_intr),
+	{0, 0},
+};
+
+static driver_t saip_driver = {
+	"saip",
+	saip_methods,
+	sizeof(struct sa11x0_softc),
+};
+static devclass_t saip_devclass;
+
+DRIVER_MODULE(saip, nexus, saip_driver, saip_devclass, 0, 0);
diff --git a/sys/arm/sa11x0/sa11x0_dmacreg.h b/sys/arm/sa11x0/sa11x0_dmacreg.h
new file mode 100644
index 0000000..9112e21
--- /dev/null
+++ b/sys/arm/sa11x0/sa11x0_dmacreg.h
@@ -0,0 +1,97 @@
+/*      $NetBSD: sa11x0_dmacreg.h,v 1.1 2001/07/08 23:37:53 rjs Exp $	*/
+
+/*-
+ * Copyright (c) 2001, The NetBSD Foundation, Inc.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the NetBSD
+ *      Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+/* SA11[01]0 integrated DMA controller */
+
+#define SADMAC_NPORTS		40
+
+#define SADMAC_DAR0		0x00	/* DMA device address register */
+#define SADMAC_DCR0_SET		0x04	/* DMA control/status (set) */
+#define SADMAC_DCR0_CLR		0x08	/* DMA control/status (clear) */
+#define SADMAC_DCR0		0x0C	/* DMA control/status (read only) */
+#define SADMAC_DBSA0		0x10	/* DMA Buffer A start address */
+#define SADMAC_DBTA0		0x14	/* DMA Buffer A transfer count */
+#define SADMAC_DBSB0		0x18	/* DMA Buffer B start address */
+#define SADMAC_DBTB0		0x1C	/* DMA Buffer B transfer count */
+
+#define SADMAC_DAR1		0x20
+#define SADMAC_DCR1_SET		0x24
+#define SADMAC_DCR1_CLR		0x28
+#define SADMAC_DCR1		0x2C
+#define SADMAC_DBSA1		0x30
+#define SADMAC_DBTA1		0x34
+#define SADMAC_DBSB1		0x38
+#define SADMAC_DBTB1		0x3C
+
+#define SADMAC_DAR2		0x40
+#define SADMAC_DCR2_SET		0x44
+#define SADMAC_DCR2_CLR		0x48
+#define SADMAC_DCR2		0x4C
+#define SADMAC_DBSA2		0x50
+#define SADMAC_DBTA2		0x54
+#define SADMAC_DBSB2		0x58
+#define SADMAC_DBTB2		0x5C
+
+#define SADMAC_DAR3		0x60
+#define SADMAC_DCR3_SET		0x64
+#define SADMAC_DCR3_CLR		0x68
+#define SADMAC_DCR3		0x6C
+#define SADMAC_DBSA3		0x70
+#define SADMAC_DBTA3		0x74
+#define SADMAC_DBSB3		0x78
+#define SADMAC_DBTB3		0x7C
+
+#define SADMAC_DAR4		0x80
+#define SADMAC_DCR4_SET		0x84
+#define SADMAC_DCR4_CLR		0x88
+#define SADMAC_DCR4		0x8C
+#define SADMAC_DBSA4		0x90
+#define SADMAC_DBTA4		0x94
+#define SADMAC_DBSB4		0x98
+#define SADMAC_DBTB4		0x9C
+
+#define SADMAC_DAR5		0xA0
+#define SADMAC_DCR5_SET		0xA4
+#define SADMAC_DCR5_CLR		0xA8
+#define SADMAC_DCR5		0xAC
+#define SADMAC_DBSA5		0xB0
+#define SADMAC_DBTA5		0xB4
+#define SADMAC_DBSB5		0xB8
+#define SADMAC_DBTB5		0xBC
diff --git a/sys/arm/sa11x0/sa11x0_gpioreg.h b/sys/arm/sa11x0/sa11x0_gpioreg.h
new file mode 100644
index 0000000..9f46e9d
--- /dev/null
+++ b/sys/arm/sa11x0/sa11x0_gpioreg.h
@@ -0,0 +1,100 @@
+/*	$NetBSD: sa11x0_gpioreg.h,v 1.2 2001/07/30 15:58:56 rjs Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Ichiro FUKUHARA (ichiro@ichiro.org).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+/*
+ * SA-11x0 GPIO Register 
+ */
+
+#define SAGPIO_NPORTS	8
+
+/* GPIO pin-level register */
+#define SAGPIO_PLR	0x00
+
+/* GPIO pin direction register */
+#define SAGPIO_PDR	0x04
+
+/* GPIO pin output set register */
+#define SAGPIO_PSR	0x08
+
+/* GPIO pin output clear register */
+#define SAGPIO_PCR	0x0C
+
+/* GPIO rising-edge detect register */
+#define SAGPIO_RER	0x10
+
+/* GPIO falling-edge detect register */
+#define SAGPIO_FER	0x14
+
+/* GPIO edge-detect status register */
+#define SAGPIO_EDR	0x18
+
+/* GPIO alternate function register */
+#define SAGPIO_AFR	0x1C
+
+/* XXX */
+#define GPIO(x)		(0x00000001 << (x))
+
+/*
+ * SA-11x0 GPIOs parameter
+ */
+/*
+port	name 		desc
+0	Reserved
+1	Reserved
+2...9	LDD{8..15}	LCD DATA(8-15)
+10	SSP_TXD		SSP transmit
+11	SSP_RXD		SSP receive
+12	SSP_SCLK	SSP serial clock
+13	SSP_SFRM	SSP frameclock
+14	UART_TXD	UART transmit
+15	UART_RXD	UART receive
+16	GPCLK_OUT	General-purpose clock out
+17	Reserved
+18	UART_SCLK	Sample clock input
+19	SSP_CLK		Sample clock input
+20	UART_SCLK3	Sample clock input
+21	MCP_CLK		MCP dock in
+22	TREQA		Either TIC request A
+23	TREQB		Either TIC request B
+24	Reserved
+25	RTC		Real Time Clock
+26	RCLK_OUT	internal clock /2
+27	32KHZ_OUT	Raw 32.768kHz osc output
+ */
diff --git a/sys/arm/sa11x0/sa11x0_io.c b/sys/arm/sa11x0/sa11x0_io.c
new file mode 100644
index 0000000..7b91d5f
--- /dev/null
+++ b/sys/arm/sa11x0/sa11x0_io.c
@@ -0,0 +1,252 @@
+/*	$NetBSD: sa11x0_io.c,v 1.12 2003/07/15 00:24:51 lukem Exp $	*/
+
+/*
+ * Copyright (c) 1997 Mark Brinicombe.
+ * Copyright (c) 1997 Causality Limited.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Mark Brinicombe.
+ * 4. The name of the company nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * bus_space I/O functions for sa11x0
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/queue.h>
+#include <sys/types.h>
+#include <sys/lock.h>
+#include <sys/mutex.h>
+
+#include <vm/vm.h>
+#include <vm/pmap.h>
+#include <vm/vm_extern.h>
+#include <vm/vm_kern.h>
+
+#include <machine/bus.h>
+#include <machine/pmap.h>
+
+/* Proto types for all the bus_space structure functions */
+
+bs_protos(sa11x0);
+
+/* Declare the sa11x0 bus space tag */
+
+struct bus_space sa11x0_bs_tag = {
+	/* cookie */
+	NULL,
+
+	/* mapping/unmapping */
+	sa11x0_bs_map,
+	sa11x0_bs_unmap,
+	sa11x0_bs_subregion,
+
+	/* allocation/deallocation */
+	sa11x0_bs_alloc,
+	sa11x0_bs_free,
+
+	/* get kernel virtual address */
+	sa11x0_bs_vaddr,
+
+	/* mmap bus space for userland */
+	sa11x0_bs_mmap,
+
+	/* barrier */
+	sa11x0_bs_barrier,
+
+	/* read (single) */
+	sa11x0_bs_r_1,
+	sa11x0_bs_r_2,
+	sa11x0_bs_r_4,
+	NULL,
+
+	/* read multiple */
+	sa11x0_bs_rm_1,
+	sa11x0_bs_rm_2,
+	sa11x0_bs_rm_4,
+	NULL,
+
+	/* read region */
+	NULL,
+	sa11x0_bs_rr_2,
+	NULL,
+	NULL,
+	/* write (single) */
+	sa11x0_bs_w_1,
+	sa11x0_bs_w_2,
+	sa11x0_bs_w_4,
+	NULL,
+
+	/* write multiple */
+	sa11x0_bs_wm_1,
+	sa11x0_bs_wm_2,
+	sa11x0_bs_wm_4,
+	NULL,
+
+	/* write region */
+	NULL,
+	sa11x0_bs_wr_2,
+	NULL,
+	NULL,	
+
+	/* set multiple */
+	NULL,
+	NULL,
+	NULL,
+	NULL,
+
+	/* set region */
+	NULL,
+	sa11x0_bs_sr_2,
+	NULL,
+	NULL,
+
+	/* copy */
+	NULL,
+	sa11x0_bs_c_2,
+	NULL,
+	NULL,
+};
+
+/* bus space functions */
+
+int
+sa11x0_bs_map(t, bpa, size, cacheable, bshp)
+	void *t;
+	bus_addr_t bpa;
+	bus_size_t size;
+	int cacheable;
+	bus_space_handle_t *bshp;
+{
+	u_long startpa, endpa, pa;
+	vm_offset_t va;
+	pt_entry_t *pte;
+
+	startpa = trunc_page(bpa);
+	endpa = round_page(bpa + size);
+
+	/* XXX use extent manager to check duplicate mapping */
+
+	va = kmem_alloc(kernel_map, endpa - startpa);
+	if (! va)
+		return(ENOMEM);
+
+	*bshp = (bus_space_handle_t)(va + (bpa - startpa));
+
+	for(pa = startpa; pa < endpa; pa += PAGE_SIZE, va += PAGE_SIZE) {
+		pmap_kenter(va, pa);
+		pte = vtopte(va);
+		if (cacheable == 0) {
+			*pte &= ~L2_S_CACHE_MASK;
+			PTE_SYNC(pte);
+		}
+	}
+	pmap_update(pmap_kernel());
+	return(0);
+}
+
+int
+sa11x0_bs_alloc(t, rstart, rend, size, alignment, boundary, cacheable,
+    bpap, bshp)
+	void *t;
+	bus_addr_t rstart, rend;
+	bus_size_t size, alignment, boundary;
+	int cacheable;
+	bus_addr_t *bpap;
+	bus_space_handle_t *bshp;
+{
+	panic("sa11x0_alloc(): Help!");
+}
+
+
+void
+sa11x0_bs_unmap(t, size)
+	void *t;
+	bus_size_t size;
+{
+	/*
+	 * Temporary implementation
+	 */
+}
+
+void    
+sa11x0_bs_free(t, bsh, size)
+	void *t;
+	bus_space_handle_t bsh;
+	bus_size_t size;
+{
+
+	panic("sa11x0_free(): Help!");
+	/* sa11x0_unmap() does all that we need to do. */
+/*	sa11x0_unmap(t, bsh, size);*/
+}
+
+int
+sa11x0_bs_subregion(t, bsh, offset, size, nbshp)
+	void *t;
+	bus_space_handle_t bsh;
+	bus_size_t offset, size;
+	bus_space_handle_t *nbshp;
+{
+
+	*nbshp = bsh + offset;
+	return (0);
+}
+
+int
+sa11x0_bs_mmap(dev_t t, vm_offset_t offset, vm_paddr_t *paddr, int nprot)
+{
+	*paddr = offset;
+	return (0);
+}
+
+void *
+sa11x0_bs_vaddr(t, bsh)
+	void *t;
+	bus_space_handle_t bsh;
+{
+	return ((void *)bsh);
+}
+
+void
+sa11x0_bs_barrier(t, bsh, offset, len, flags)
+	void *t;
+	bus_space_handle_t bsh;
+	bus_size_t offset, len;
+	int flags;
+{
+/* NULL */
+}	
+
+/* End of sa11x0_io.c */
diff --git a/sys/arm/sa11x0/sa11x0_io_asm.S b/sys/arm/sa11x0/sa11x0_io_asm.S
new file mode 100644
index 0000000..cb15cd0
--- /dev/null
+++ b/sys/arm/sa11x0/sa11x0_io_asm.S
@@ -0,0 +1,290 @@
+/*	$NetBSD: sa11x0_io_asm.S,v 1.1 2001/07/08 23:37:53 rjs Exp $	*/
+
+/*
+ * Copyright (c) 1997 Mark Brinicombe.
+ * Copyright (c) 1997 Causality Limited.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by Mark Brinicombe.
+ * 4. The name of the company nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <machine/asm.h>
+__FBSDID("$FreeBSD$");
+
+/*
+ * bus_space I/O functions for sa11x0
+ */
+
+/*
+ * read single
+ */
+
+ENTRY(sa11x0_bs_r_1)
+	ldrb	r0, [r1, r2]
+	mov	pc, lr
+
+ENTRY(sa11x0_bs_r_2)
+	ldrh	r0, [r1, r2]
+	mov	pc, lr
+
+ENTRY(sa11x0_bs_r_4)
+	ldr	r0, [r1, r2]
+	mov	pc, lr
+
+/*
+ * write single
+ */
+
+ENTRY(sa11x0_bs_w_1)
+	strb	r3, [r1, r2]
+	mov	pc, lr
+
+ENTRY(sa11x0_bs_w_2)
+	strh	r3, [r1, r2]
+	mov	pc, lr
+
+ENTRY(sa11x0_bs_w_4)
+	str	r3, [r1, r2]
+	mov	pc, lr
+
+
+/*
+ * read multiple
+ */
+
+ENTRY(sa11x0_bs_rm_1)
+	add	r0, r1, r2
+	ldr	r2, [sp, #0]
+	cmp     r2, #0x00000000
+	movle   pc, lr
+
+sa11x0_bs_rm_1_loop:
+	ldrb	r1, [r0]
+	subs	r2, r2, #0x00000001
+	strb	r1, [r3], #0x0001
+	bgt	sa11x0_bs_rm_1_loop
+
+	mov	pc, lr
+
+ENTRY(sa11x0_bs_rm_2)
+	add	r0, r1, r2
+	ldr	r2, [sp, #0]
+	cmp	r2, #0x00000000
+	movle	pc, lr
+
+	tst	r2, #0x00000007
+	tsteq	r3, #0x00000003
+	beq	sa11x0_bs_rm_2_fast
+
+sa11x0_bs_rm_2_loop:
+	ldrh	r1, [r0]
+	subs	r2, r2, #0x00000001
+	strh	r1, [r3], #0x0002
+	bgt	sa11x0_bs_rm_2_loop
+
+	mov	pc, lr
+
+sa11x0_bs_rm_2_fast:
+	stmfd	sp!, {r4, r5, lr}
+
+sa11x0_bs_rm_2_fastloop:
+	ldrh	r1, [r0]
+	ldrh	lr, [r0]
+	orr	r1, r1, lr, lsl #16
+
+	ldrh	r4, [r0]
+	ldrh	lr, [r0]
+	orr	r4, r4, lr, lsl #16
+
+	ldrh	r5, [r0]
+	ldrh	lr, [r0]
+	orr	r5, r5, lr, lsl #16
+
+	ldrh	ip, [r0]
+	ldrh	lr, [r0]
+	orr	ip, ip, lr, lsl #16
+
+	stmia	r3!, {r1, r4, r5, ip}
+	subs	r2, r2, #8
+	bgt	sa11x0_bs_rm_2_fastloop
+
+	ldmfd	sp!, {r4, r5, pc}
+
+
+ENTRY(sa11x0_bs_rm_4)
+	add	r0, r1, r2
+	ldr	r2, [sp, #0]
+	cmp	r2, #0x00000000
+	movle	pc, lr
+
+sa11x0_bs_rm_4_loop:
+	ldr	r1, [r0]
+	subs	r2, r2, #0x00000001
+	str	r1, [r3], #0x0004
+	bgt	sa11x0_bs_rm_4_loop
+
+	mov	pc, lr
+
+/*
+ * write multiple
+ */
+
+ENTRY(sa11x0_bs_wm_1)
+	add	r0, r1, r2
+	ldr	r2, [sp, #0]
+	cmp	r2, #0x00000000
+	movle	pc, lr
+
+sa11x0_wm_1_loop:
+	ldrb	r1, [r3], #0x0001
+	subs	r2, r2, #0x00000001
+	strb	r1, [r0]
+	bgt	sa11x0_wm_1_loop
+
+	mov	pc, lr
+
+ENTRY(sa11x0_bs_wm_2)
+	add	r0, r1, r2
+	ldr	r2, [sp, #0]
+	cmp	r2, #0x00000000
+	movle	pc, lr
+
+sa11x0_bs_wm_2_loop:
+	ldrh	r1, [r3], #0x0002
+	subs	r2, r2, #0x00000001
+	strh	r1, [r0]
+	bgt	sa11x0_bs_wm_2_loop
+
+	mov	pc, lr
+
+ENTRY(sa11x0_bs_wm_4)
+	add	r0, r1, r2
+	ldr	r2, [sp, #0]
+	cmp	r2, #0x00000000
+	movle	pc, lr
+
+sa11x0_bs_wm_4_loop:
+	ldr	r1, [r3], #0x0004
+	subs	r2, r2, #0x00000001
+	str	r1, [r0]
+	bgt	sa11x0_bs_wm_4_loop
+
+	mov	pc, lr
+
+/*
+ * read region
+ */
+
+ENTRY(sa11x0_bs_rr_2)
+	add	r0, r1, r2
+	ldr	r2, [sp, #0]
+	cmp	r2, #0x00000000
+	movle	pc, lr
+
+sa11x0_bs_rr_2_loop:
+	ldrh	r1, [r0], #0x0002  
+	strh	r1, [r3], #0x0002
+        subs    r2, r2, #0x00000001
+	bgt	sa11x0_bs_rr_2_loop
+
+        mov     pc, lr
+
+/*
+ * write region
+ */
+
+ENTRY(sa11x0_bs_wr_2)
+	add	r0, r1, r2
+	ldr	r2, [sp, #0]
+	cmp	r2, #0x00000000  
+	movle	pc, lr
+
+sa11x0_bs_wr_2_loop:
+	ldrh	r1, [r3], #0x0002
+	strh	r1, [r0], #0x0002
+	subs	r2, r2, #0x00000001
+	bgt	sa11x0_bs_wr_2_loop
+
+	mov	pc, lr
+
+/*
+ * set regiuon
+ */
+
+ENTRY(sa11x0_bs_sr_2)
+	add	r0, r1, r2
+	ldr	r2, [sp, #0]
+	cmp	r2, #0x00000000
+	movle	pc, lr
+
+sa11x0_bs_sr_2_loop:
+	strh	r3, [r0], #0x0002
+	subs	r2, r2, #0x00000001
+	bgt	sa11x0_bs_sr_2_loop
+
+	mov	pc, lr
+
+/*
+ * copy region
+ */
+
+ENTRY(sa11x0_bs_c_2)
+	add	r0, r1, r2
+	ldr	r2, [sp, #0]
+	add	r1, r2, r3
+	ldr	r2, [sp, #4]
+	cmp	r2, #0x00000000
+	movle	pc, lr
+
+	cmp	r0, r1
+	blt	sa11x0_bs_c_2_backwards
+
+sa11x0_bs_cf_2_loop:
+	ldrh	r3, [r0], #0x0002
+	strh	r3, [r1], #0x0002
+	subs	r2, r2, #0x00000001
+	bgt	sa11x0_bs_cf_2_loop
+
+	mov	pc, lr
+
+sa11x0_bs_c_2_backwards:
+	add	r0, r0, r2, lsl #1
+	add	r1, r1, r2, lsl #1
+	sub	r0, r0, #2
+	sub	r1, r1, #2
+
+sa11x0_bs_cb_2_loop:
+	ldrh	r3, [r0], #-2
+	strh	r3, [r1], #-2
+	subs	r2, r2, #1
+	bne	sa11x0_bs_cb_2_loop
+
+	mov     pc, lr
+
+/* end of sa11x0_io_asm.S */
diff --git a/sys/arm/sa11x0/sa11x0_irq.S b/sys/arm/sa11x0/sa11x0_irq.S
new file mode 100644
index 0000000..cabeb40
--- /dev/null
+++ b/sys/arm/sa11x0/sa11x0_irq.S
@@ -0,0 +1,223 @@
+/*	$NetBSD: sa11x0_irq.S,v 1.5 2003/03/31 19:52:35 chris Exp $	*/
+
+/*
+ * Copyright (c) 1998 Mark Brinicombe.
+ * Copyright (c) 1998 Causality Limited
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to the NetBSD Foundation
+ * by IWAMOTO Toshihiro.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by Mark Brinicombe
+ *      for the NetBSD Project.
+ * 4. The name of the company nor the name of the author may be used to
+ *    endorse or promote products derived from this software without specific
+ *    prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include "assym.s"
+#include <machine/asm.h>
+#include <machine/armreg.h>
+#include <machine/asmacros.h>
+#include <arm/sa11x0/sa11x0_reg.h>
+__FBSDID("$FreeBSD$");
+Lcurrent_spl_level:	
+	.word	_C_LABEL(current_spl_level)
+Lcurrent_intr_depth:
+	.word	_C_LABEL(current_intr_depth)
+
+Lspl_masks:
+	.word	_C_LABEL(spl_masks)
+	.globl	_C_LABEL(saipic_base)
+_C_LABEL(saipic_base):
+	.word	0x00000000
+
+#ifdef INTR_DEBUG
+Ldbg_str:
+	.asciz	"irq_entry %x %x\n"
+#endif
+
+AST_ALIGNMENT_FAULT_LOCALS
+/*
+ * Regsister usage
+ *
+ *  r6  - Address of current handler
+ *  r7  - Pointer to handler pointer list
+ *  r8  - Current IRQ requests.
+ *  r9  - Used to count through possible IRQ bits.
+ *  r10 - Base address of SAIP
+ */
+
+#define _SPL_LEVELS	13 /* XXX */
+ASENTRY_NP(irq_entry)
+	sub	lr, lr, #0x00000004	/* Adjust the lr */
+
+	PUSHFRAMEINSVC			/* Push an interrupt frame */
+	ENABLE_ALIGNMENT_FAULTS
+
+	/* Load r8 with the SAIPIC interrupt requests */
+
+	ldr	r10, _C_LABEL(saipic_base)
+	ldr	r8, [r10, #(SAIPIC_IP)]	/* Load IRQ pending register */
+
+#ifdef INTR_DEBUG
+	ldr	r2, [r10, #(SAIPIC_MR)]
+	adr	r0, Ldbg_str
+	mov	r1, r8
+	bl	_C_LABEL(printf)
+#endif
+	/*
+	 * Note that we have entered the IRQ handler.
+	 * We are in SVC mode so we cannot use the processor mode
+	 * to determine if we are in an IRQ. Instead we will count the
+	 * each time the interrupt handler is nested.
+	 */
+
+	ldr	r0, Lcurrent_intr_depth
+	ldr	r1, [r0]
+	add	r1, r1, #1
+	str	r1, [r0]
+
+	/*
+ 	 * Need to block all interrupts at the IPL or lower for
+	 * all asserted interrupts.
+	 * This basically emulates hardware interrupt priority levels.
+	 * Means we need to go through the interrupt mask and for
+	 * every asserted interrupt we need to mask out all other
+	 * interrupts at the same or lower IPL.
+	 * If only we could wait until the main loop but we need to sort
+	 * this out first so interrupts can be re-enabled.
+	 *
+	 * This would benefit from a special ffs type routine
+	 */
+
+	mov	r9, #(_SPL_LEVELS - 1)
+	ldr	r7, Lspl_masks
+Lfind_highest_ipl:
+	ldr	r2, [r7, r9, lsl #2]
+	tst	r8, r2
+	subeq	r9, r9, #1
+	beq	Lfind_highest_ipl
+
+	/* r9 = SPL level of highest priority interrupt */
+	add	r9, r9, #1
+	ldr	r2, [r7, r9, lsl #2]
+	mvn	r2, r2
+
+	ldr	r0, Lcurrent_spl_level
+	ldr	r1, [r0]
+	str	r9, [r0]
+	stmfd	sp!, {r1}
+
+	/* Update the SAIP irq masks */
+	bl	_C_LABEL(irq_setmasks)
+#ifdef INTR_DEBUG
+	stmfd	sp!, {r0,r1,r2}
+	adr	r0, Ldbg_str
+	mov	r2, r9
+	bl	_C_LABEL(printf)
+	ldmia	sp!, {r0,r1,r2}
+#endif
+        mrs     r0, cpsr_all		/* Enable IRQ's */
+	bic	r0, r0, #I32_bit
+	msr	cpsr_all, r0
+	mov	r0, r8
+	bl	_C_LABEL(arm_handler_execute)
+
+	ldmfd	sp!, {r2}
+	ldr	r1, Lcurrent_spl_level
+	str	r2, [r1]
+	/* Restore previous disabled mask */
+	bl	_C_LABEL(irq_setmasks)
+	bl	_C_LABEL(dosoftints)	/* Handle the soft interrupts */
+
+	/* Kill IRQ's in preparation for exit */
+        mrs     r0, cpsr_all
+        orr     r0, r0, #(I32_bit)
+        msr     cpsr_all, r0
+
+#ifdef INTR_DEBUG
+	adr	r0, Ldbg_str
+	mov	r1, #3
+	ldr	r2, [r10, #(SAIPIC_MR)]
+	bl	_C_LABEL(printf)
+#endif
+
+	/* Decrement the nest count */
+	ldr	r0, Lcurrent_intr_depth
+	ldr	r1, [r0]
+	sub	r1, r1, #1
+	str	r1, [r0]
+
+	DO_AST_AND_RESTORE_ALIGNMENT_FAULTS
+	PULLFRAMEFROMSVCANDEXIT
+
+	/* NOT REACHED */
+	b	. - 8
+ENTRY(irq_setmasks)
+	/* Disable interrupts */
+	mrs	r3, cpsr_all
+	orr	r1, r3,  #(I32_bit)
+	msr	cpsr_all, r1
+
+	/* Calculate interrupt mask */
+	ldr	r0, Lspl_masks
+	ldr	r2, Lcurrent_spl_level
+	ldr	r2, [r2]
+	ldr	r2, [r0, r2, lsl #2]
+	ldr	r0, _C_LABEL(saipic_base)
+	str	r2, [r0, #(SAIPIC_MR)]	/* Set mask register */
+
+	/* Restore old cpsr and exit */
+	/* msr	cpsr_all, r3 XXX: not now.*/
+	mov	pc, lr
+Lcnt:
+	.word	_C_LABEL(cnt)
+
+#ifdef IRQSTATS
+Lintrcnt:
+	.word	_C_LABEL(intrcnt)
+#endif
+
+Lirqhandlers:
+	.word	_C_LABEL(irqhandlers)	/* Pointer to array of irqhandlers */
+
+
+
+
+	.global _C_LABEL(intrnames), _C_LABEL(eintrnames)
+	.global _C_LABEL(eintrcnt)
+_C_LABEL(intrnames): 
+_C_LABEL(eintrnames):
+_C_LABEL(eintrcnt):
+
+	.globl	_C_LABEL(intrcnt), _C_LABEL(sintrcnt)
+
+_C_LABEL(intrcnt):
+	.space	ICU_LEN*4  /* XXX Should be linked to number of interrupts */
+
+_C_LABEL(sintrcnt):
+	.space 32*4
diff --git a/sys/arm/sa11x0/sa11x0_irqhandler.c b/sys/arm/sa11x0/sa11x0_irqhandler.c
new file mode 100644
index 0000000..5b7e430
--- /dev/null
+++ b/sys/arm/sa11x0/sa11x0_irqhandler.c
@@ -0,0 +1,233 @@
+/*	$NetBSD: sa11x0_irqhandler.c,v 1.5 2003/08/07 16:26:54 agc Exp $	*/
+
+/*-
+ * Copyright (c) 1996, 1997, 1998, 2001 The NetBSD Foundation, Inc.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to the NetBSD Foundation
+ * by IWAMOTO Toshihiro.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Charles M. Hannum and by Jason R. Thorpe of the Numerical Aerospace
+ * Simulation Facility, NASA Ames Research Center.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/*-
+ * Copyright (c) 1991 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to Berkeley by
+ * William Jolitz.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ *	@(#)isa.c	7.2 (Berkeley) 5/13/91
+ */
+
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/param.h>
+#include <sys/kernel.h>
+#include <sys/systm.h>
+#include <sys/syslog.h>
+#include <sys/malloc.h>
+#include <sys/types.h>
+#include <sys/bus.h>
+#include <sys/interrupt.h>
+#include <vm/vm.h>
+#include <vm/vm_extern.h>
+
+#include <arm/sa11x0/sa11x0_reg.h>
+#include <arm/sa11x0/sa11x0_var.h>
+
+#include <machine/cpu.h>
+
+#define NIRQS 0x20
+struct intrhand *irqhandlers[NIRQS];
+
+int current_intr_depth;
+u_int actual_mask;
+#define IPL_LEVELS 13
+#ifdef hpcarm
+#define IPL_LEVELS (NIPL+1)
+u_int imask[NIPL];
+#else
+u_int spl_mask;
+u_int irqmasks[IPL_LEVELS];
+#endif
+u_int irqblock[NIRQS];
+u_int levels[IPL_LEVELS];
+
+
+extern void set_spl_masks(void);
+#if 0
+static int fakeintr(void *);
+#endif
+#ifdef DEBUG
+static int dumpirqhandlers(void);
+#endif
+
+/* Recalculate the interrupt masks from scratch.
+ * We could code special registry and deregistry versions of this function that
+ * would be faster, but the code would be nastier, and we don't expect this to
+ * happen very much anyway.
+ */
+void intr_calculatemasks(void);
+void
+intr_calculatemasks(void)
+{       
+	int irq;
+	int intrlevel[ICU_LEN];
+	int level;
+
+	/* First, figure out which levels each IRQ uses. */
+	for (irq = 0; irq < ICU_LEN; irq++) {
+			intrlevel[irq] = levels[irq];
+	}
+	/* Then figure out which IRQs use each level. */        
+#ifdef hpcarm
+	for (level = 0; level < NIPL; level++) {
+#else
+	for (level = 0; level <= IPL_LEVELS; level++) {
+#endif
+		int irqs = 0;
+		for (irq = 0; irq < ICU_LEN; irq++) {
+			if (intrlevel[irq] & (1 << level)) {
+				irqs |= 1 << irq;
+			}
+		}
+#ifdef hpcarm
+
+		imask[level] = irqs;
+#else
+		irqmasks[level] = irqs;
+		printf("level %d set to %x\n", level, irqs);
+#endif
+	}
+	        /*
+       		 * Enforce a hierarchy that gives slow devices a better chance at not
+		 * dropping data.                                     
+		 */
+#ifdef hpcarm
+	for (level = NIPL - 1; level > 0; level--)
+		imask[level - 1] |= imask[level];
+#else
+	for (level = IPL_LEVELS; level > 0; level--)
+		irqmasks[level - 1] |= irqmasks[level];
+#endif
+        /*
+	 * Calculate irqblock[], which emulates hardware interrupt levels.
+	 */
+#if 0
+	for (irq = 0; irq < ICU_LEN; irq++) {
+		int irqs = 1 << irq;
+		for (q = irqhandlers[irq]; q; q = q->ih_next)
+#ifdef hpcarm           
+			irqs |= ~imask[q->ih_level];
+#else                   
+			irqs |= ~irqmasks[q->ih_level];       
+#endif
+		irqblock[irq] = irqs;
+	}
+#endif
+}
+					
+const struct evcnt *sa11x0_intr_evcnt(sa11x0_chipset_tag_t, int);
+void stray_irqhandler(void *);
+
+
+const struct evcnt *
+sa11x0_intr_evcnt(sa11x0_chipset_tag_t ic, int irq)
+{
+
+	/* XXX for now, no evcnt parent reported */
+	return NULL;
+}
+
+
+void
+stray_irqhandler(void *p)
+{
+
+	printf("stray interrupt %p\n", p);
+	printf("bla\n");
+}
+
+#if 0
+int
+fakeintr(void *p)
+{
+
+	return 0;
+}
+#endif
+#ifdef DEBUG
+int
+dumpirqhandlers()
+{
+	int irq;
+	struct irqhandler *p;
+
+	for (irq = 0; irq < ICU_LEN; irq++) {
+		printf("irq %d:", irq);
+		p = irqhandlers[irq];
+		for (; p; p = p->ih_next)
+			printf("ih_func: 0x%lx, ", (unsigned long)p->ih_func);
+		printf("\n");
+	}
+	return 0;
+}
+#endif
+/* End of irqhandler.c */
diff --git a/sys/arm/sa11x0/sa11x0_ost.c b/sys/arm/sa11x0/sa11x0_ost.c
new file mode 100644
index 0000000..152d114
--- /dev/null
+++ b/sys/arm/sa11x0/sa11x0_ost.c
@@ -0,0 +1,355 @@
+/*	$NetBSD: sa11x0_ost.c,v 1.11 2003/07/15 00:24:51 lukem Exp $	*/
+
+/*
+ * Copyright (c) 1997 Mark Brinicombe.
+ * Copyright (c) 1997 Causality Limited.
+ * All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro and Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <sys/types.h>
+#include <sys/param.h>
+#include <sys/systm.h>
+#include <sys/kernel.h>
+#include <sys/time.h>
+#include <sys/bus.h>
+#include <sys/clock.h>
+
+#include <machine/bus.h>
+#include <sys/rman.h>
+#include <machine/resource.h>
+#include <machine/intr.h>
+
+#include <machine/cpufunc.h>
+
+#include <machine/katelib.h>
+
+#include <arm/sa11x0/sa11x0_reg.h> 
+#include <arm/sa11x0/sa11x0_var.h>
+#include <arm/sa11x0/sa11x0_ostreg.h>
+
+static int	saost_probe(device_t);
+static int	saost_attach(device_t);
+
+int		gettick(void);
+static void	clockintr(void *);
+#if 0
+static void	statintr(void *);
+#endif
+void		rtcinit(void);
+
+#if 0
+static struct mtx clock_lock;
+#endif
+
+struct saost_softc {
+	device_t		sc_dev;
+	bus_addr_t		sc_baseaddr;
+	bus_space_tag_t		sc_iot;
+	bus_space_handle_t	sc_ioh;
+
+	u_int32_t	sc_clock_count;
+	u_int32_t	sc_statclock_count;
+	u_int32_t	sc_statclock_step;
+};
+
+static struct saost_softc *saost_sc = NULL;
+
+#define TIMER_FREQUENCY         3686400         /* 3.6864MHz */
+#define TICKS_PER_MICROSECOND   (TIMER_FREQUENCY/1000000)
+
+#ifndef STATHZ
+#define STATHZ	64
+#endif
+
+static device_method_t saost_methods[] = {
+	DEVMETHOD(device_probe, saost_probe),
+	DEVMETHOD(device_attach, saost_attach),
+	{0, 0},
+};
+
+static driver_t saost_driver = {
+	"saost",
+	saost_methods,
+	sizeof(struct saost_softc),
+};
+static devclass_t saost_devclass;
+
+DRIVER_MODULE(saost, saip, saost_driver, saost_devclass, 0, 0);
+static int
+saost_probe(device_t dev)
+{
+
+	return (0);
+}
+
+static int
+saost_attach(device_t dev)
+{
+	struct saost_softc *sc = device_get_softc(dev);
+	struct sa11x0_softc *sa = device_get_softc(device_get_parent(dev));
+
+	sc->sc_dev = dev;
+	sc->sc_iot = sa->sc_iot;
+	sc->sc_baseaddr = 0x90000000;
+
+	saost_sc = sc;
+
+	if(bus_space_map(sa->sc_iot, sc->sc_baseaddr, 8, 0, 
+			&sc->sc_ioh))
+		panic("%s: Cannot map registers", device_get_name(dev));
+
+	/* disable all channel and clear interrupt status */
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_IR, 0);
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_SR, 0xf);
+	return (0);
+
+}
+
+static void
+clockintr(arg)
+	void *arg;
+{
+	struct clockframe *frame = arg;
+	u_int32_t oscr, nextmatch, oldmatch;
+	int s;
+
+#if 0
+	mtx_lock_spin(&clock_lock);
+#endif
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+			SAOST_SR, 1);
+
+	/* schedule next clock intr */
+	oldmatch = saost_sc->sc_clock_count;
+	nextmatch = oldmatch + TIMER_FREQUENCY / hz;
+
+	oscr = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+				SAOST_CR);
+
+	if ((nextmatch > oldmatch &&
+	     (oscr > nextmatch || oscr < oldmatch)) ||
+	    (nextmatch < oldmatch && oscr > nextmatch && oscr < oldmatch)) {
+		/*
+		 * we couldn't set the matching register in time.
+		 * just set it to some value so that next interrupt happens.
+		 * XXX is it possible to compansate lost interrupts?
+		 */
+
+		s = splhigh();
+		oscr = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+					SAOST_CR);
+		nextmatch = oscr + 10;
+		splx(s);
+	}
+	saost_sc->sc_clock_count = nextmatch;
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_MR0,
+			  nextmatch);
+	hardclock(frame);
+#if 0
+	mtx_unlock_spin(&clock_lock);
+#endif
+}
+
+#if 0
+static void
+statintr(arg)
+	void *arg;
+{
+	struct clockframe *frame = arg;
+	u_int32_t oscr, nextmatch, oldmatch;
+	int s;
+
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+			SAOST_SR, 2);
+
+	/* schedule next clock intr */
+	oldmatch = saost_sc->sc_statclock_count;
+	nextmatch = oldmatch + saost_sc->sc_statclock_step;
+
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_MR1,
+			  nextmatch);
+	oscr = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+				SAOST_CR);
+
+	if ((nextmatch > oldmatch &&
+	     (oscr > nextmatch || oscr < oldmatch)) ||
+	    (nextmatch < oldmatch && oscr > nextmatch && oscr < oldmatch)) {
+		/*
+		 * we couldn't set the matching register in time.
+		 * just set it to some value so that next interrupt happens.
+		 * XXX is it possible to compansate lost interrupts?
+		 */
+
+		s = splhigh();
+		oscr = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+					SAOST_CR);
+		nextmatch = oscr + 10;
+		bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+				  SAOST_MR1, nextmatch);
+		splx(s);
+	}
+
+	saost_sc->sc_statclock_count = nextmatch;
+	statclock(frame);
+
+}
+#endif
+
+#if 0
+void
+setstatclockrate(int hz)
+{
+	u_int32_t count;
+
+	saost_sc->sc_statclock_step = TIMER_FREQUENCY / hz;
+	count = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_CR);
+	count += saost_sc->sc_statclock_step;
+	saost_sc->sc_statclock_count = count;
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+			SAOST_MR1, count);
+}
+#endif
+void
+cpu_initclocks()
+{
+	device_t dev = saost_sc->sc_dev;
+
+	stathz = STATHZ;
+	profhz = stathz;
+#if 0
+	mtx_init(&clock_lock, "SA1110 Clock locké", NULL, MTX_SPIN);
+#endif
+	saost_sc->sc_statclock_step = TIMER_FREQUENCY / stathz;
+	struct resource *irq1, *irq2;
+	int rid = 0;
+	void *ih1/*, *ih2 */;
+	
+	printf("clock: hz=%d stathz = %d\n", hz, stathz);
+
+	/* Use the channels 0 and 1 for hardclock and statclock, respectively */
+	saost_sc->sc_clock_count = TIMER_FREQUENCY / hz;
+	saost_sc->sc_statclock_count = TIMER_FREQUENCY / stathz;
+
+	irq1 = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0,
+	    ~0, 1, RF_ACTIVE);
+	rid = 1;
+	irq2 = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1,
+	    RF_ACTIVE);
+	bus_setup_intr(dev, irq1, INTR_TYPE_CLK | INTR_FAST, clockintr, NULL,
+	    &ih1);
+#if 0
+	bus_setup_intr(dev, irq2, INTR_TYPE_CLK | INTR_FAST, statintr, NULL
+	    ,&ih2);
+#endif
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_SR, 0xf);
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_IR, 3);
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_MR0,
+			  saost_sc->sc_clock_count);
+#if 0
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_MR1,
+			  0);
+#endif
+	/* Zero the counter value */
+	bus_space_write_4(saost_sc->sc_iot, saost_sc->sc_ioh, SAOST_CR, 0);
+}
+
+int
+gettick()
+{
+	int counter;
+	u_int savedints;
+	savedints = disable_interrupts(I32_bit);
+
+	counter = bus_space_read_4(saost_sc->sc_iot, saost_sc->sc_ioh,
+			SAOST_CR);
+
+	restore_interrupts(savedints);
+	return counter;
+}
+
+void
+DELAY(usecs)
+	int usecs;
+{
+	u_int32_t tick, otick, delta;
+	int j, csec, usec;
+
+	csec = usecs / 10000;
+	usec = usecs % 10000;
+	
+	usecs = (TIMER_FREQUENCY / 100) * csec
+	    + (TIMER_FREQUENCY / 100) * usec / 10000;
+
+	if (! saost_sc) {
+		/* clock isn't initialized yet */
+		for(; usecs > 0; usecs--)
+			for(j = 100; j > 0; j--)
+				;
+		return;
+	}
+
+#if 0
+	mtx_lock_spin(&clock_lock);
+#endif
+	otick = gettick();
+
+	while (1) {
+		for(j = 100; j > 0; j--)
+			;
+		tick = gettick();
+		delta = tick - otick;
+		if (delta > usecs) {
+			break;
+		}
+		usecs -= delta;
+		otick = tick;
+	}
+#if 0
+	mtx_unlock_spin(&clock_lock);
+#endif
+}
+
+void
+cpu_startprofclock(void)
+{
+	printf("STARTPROFCLOCK\n");
+}
+
+void
+cpu_stopprofclock(void)
+{
+}
diff --git a/sys/arm/sa11x0/sa11x0_ostreg.h b/sys/arm/sa11x0/sa11x0_ostreg.h
new file mode 100644
index 0000000..c03aea1
--- /dev/null
+++ b/sys/arm/sa11x0/sa11x0_ostreg.h
@@ -0,0 +1,83 @@
+/*	$NetBSD: sa11x0_ostreg.h,v 1.1 2001/07/08 23:37:53 rjs Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+/*
+ * SA-11x0 OS Timer Register 
+ */
+
+/* OS Timer Match Register */
+#define SAOST_MR0	0x00
+#define SAOST_MR1	0x04
+#define SAOST_MR2	0x08
+#define SAOST_MR3	0x0C
+
+/* OS Timer Count Register */
+#define SAOST_CR	0x10
+
+/* OS Timer Status Register */
+#define SAOST_SR	0x14
+#define SR_CH0		(1<<0)
+#define SR_CH1		(1<<1)
+#define SR_CH2		(1<<2)
+#define SR_CH3		(1<<3)
+
+/* OS Timer Watchdog Match Enable Register */
+#define SAOST_WR	0x18
+
+/* OS Timer Interrupt Enable Register */
+#define SAOST_IR	0x1C
+
+/*
+ * SA-1110 Real Time Clock
+ */
+
+/* RTC Alarm Register */
+#define SARTC_AR	0x00
+
+/* RTC Counter Register */
+#define SARTC_CR	0x04
+
+/* RTC Trim Register */
+#define SARTC_TR	0x08
+
+/* RTC Status Register */
+#define SARTC_SR	0x0C
+
+/* end of sa11x0_ostreg.h */
diff --git a/sys/arm/sa11x0/sa11x0_ppcreg.h b/sys/arm/sa11x0/sa11x0_ppcreg.h
new file mode 100644
index 0000000..52c129a
--- /dev/null
+++ b/sys/arm/sa11x0/sa11x0_ppcreg.h
@@ -0,0 +1,67 @@
+/*      $NetBSD: sa11x0_ppcreg.h,v 1.2 2001/07/30 12:19:04 rjs Exp $	*/
+
+/*-
+ * Copyright (c) 2001, The NetBSD Foundation, Inc.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the NetBSD
+ *      Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+/* SA11[01]0 PPC (peripheral pin controller) */
+
+/* size of I/O space */
+#define SAPPC_NPORTS	13
+
+#define SAPPC_PDR	0x00	/* pin direction register */
+
+#define SAPPC_PSR	0x04	/* pin state register */
+
+#define SAPPC_PAR	0x08	/* pin assignment register */
+#define PAR_UPR		0x01000	/* UART pin assignment */
+#define PAR_SPR		0x40000	/* SSP pin assignment */
+
+#define SAPPC_SDR	0x0C	/* sleep mode direction register */
+
+#define SAPPC_PFR	0x10	/* pin flag register */
+#define PFR_LCD		0x00001	/* LCD controller flag */
+#define PFR_SP1TX	0x01000	/* serial port 1 Tx flag */
+#define PFR_SP1RX	0x02000	/* serial port 1 Rx flag */
+#define PFR_SP2TX	0x04000	/* serial port 2 Tx flag */
+#define PFR_SP2RX	0x08000	/* serial port 2 Rx flag */
+#define PFR_SP3TX	0x10000	/* serial port 3 Tx flag */
+#define PFR_SP3RX	0x20000	/* serial port 3 Rx flag */
+#define PFR_SP4		0x40000	/* serial port 4 flag */
+
+/* MCP control register 1 */
+#define SAMCP_CR1	0x30	/* MCP control register 1 */
diff --git a/sys/arm/sa11x0/sa11x0_reg.h b/sys/arm/sa11x0/sa11x0_reg.h
new file mode 100644
index 0000000..86ad31d
--- /dev/null
+++ b/sys/arm/sa11x0/sa11x0_reg.h
@@ -0,0 +1,81 @@
+/*	$NetBSD: sa11x0_reg.h,v 1.4 2002/07/19 18:26:56 ichiro Exp $	*/
+
+/*-
+ * Copyright (c) 2001 The NetBSD Foundation, Inc.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *	This product includes software developed by the NetBSD
+ *	Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
+ * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+ * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+ * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
+ * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+#ifndef _ARM_SA11X0_REG_H_
+#define _ARM_SA11X0_REG_H_
+
+/* Physical register base addresses */
+#define SAOST_BASE		0x90000000	/* OS Timer */
+#define SARTC_BASE		0x90010000	/* Real-Time Clock */
+#define SAPMR_BASE		0x90020000	/* Power Manager */
+#define SARCR_BASE		0x90030000	/* Reset Controller */
+#define SAGPIO_BASE		0x90040000	/* GPIO */
+#define SAIPIC_BASE		0x90050000	/* Interrupt Controller */
+#define SAPPC_BASE		0x90060000	/* Peripheral Pin Controller */
+#define SAUDC_BASE		0x80000000	/* USB Device Controller*/
+#define	SACOM1_BASE		0x80010000	/* GPCLK/UART 1 */
+#define SACOM3_HW_BASE		0x80050000	/* UART 3  */
+#define SAMCP_BASE		0x80060000	/* MCP Controller */
+#define SASSP_BASE		0x80070000	/* Synchronous serial port */
+
+#define SADMAC_BASE		0xB0000000	/* DMA Controller */
+#define SALCD_BASE		0xB0100000	/* LCD */
+
+/* Register base virtual addresses mapped by initarm() */
+#define SACOM3_BASE             0xd000d000
+
+/* Interrupt controller registers */
+#define SAIPIC_NPORTS		9
+#define SAIPIC_IP		0x00		/* IRQ pending register */
+#define SAIPIC_MR		0x04		/* Mask register */
+#define SAIPIC_LR		0x08		/* Level register */
+#define SAIPIC_FP		0x10		/* FIQ pending register */
+#define SAIPIC_PR		0x20		/* Pending register */
+#define SAIPIC_CR		0x0C		/* Control register */
+
+/* width of interrupt controller */
+#define ICU_LEN			32
+
+/* Reset controller registers */
+#define SARCR_RSRR		0x0		/* Software reset register */
+#define SARCR_RCSR		0x4		/* Reset status register */
+#define SARCR_TUCR		0x8		/* Test Unit control reg */
+
+#endif /* _ARM_SA11X0_REG_H_ */
diff --git a/sys/arm/sa11x0/sa11x0_var.h b/sys/arm/sa11x0/sa11x0_var.h
new file mode 100644
index 0000000..b1bf2a0
--- /dev/null
+++ b/sys/arm/sa11x0/sa11x0_var.h
@@ -0,0 +1,79 @@
+/*      $NetBSD: sa11x0_var.h,v 1.4 2003/04/14 14:18:41 rjs Exp $        */
+
+/*-
+ * Copyright (c) 2001, The NetBSD Foundation, Inc.  All rights reserved.
+ *
+ * This code is derived from software contributed to The NetBSD Foundation
+ * by IWAMOTO Toshihiro and Ichiro FUKUHARA.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. All advertising materials mentioning features or use of this software
+ *    must display the following acknowledgement:
+ *      This product includes software developed by the NetBSD
+ *      Foundation, Inc. and its contributors.
+ * 4. Neither the name of The NetBSD Foundation nor the names of its
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ *
+ */
+
+#ifndef _SA11X0_VAR_H
+#define _SA11X0_VAR_H
+
+#include <sys/conf.h>
+
+#include <sys/bus.h>
+#include <machine/bus.h>
+
+struct sa11x0_softc {
+	device_t sc_dev;
+	bus_space_tag_t sc_iot;
+	bus_space_handle_t sc_ioh;
+	bus_space_handle_t sc_gpioh;
+	bus_space_handle_t sc_ppch;
+	bus_space_handle_t sc_dmach;
+	bus_space_handle_t sc_reseth;
+	u_int32_t sc_intrmask;
+};
+
+/* Attach args all devices */
+
+typedef void *sa11x0_chipset_tag_t;
+
+extern struct bus_space sa11x0_bs_tag;
+struct sa11x0_attach_args {
+	sa11x0_chipset_tag_t	sa_sc;		
+	bus_space_tag_t		sa_iot;		/* Bus tag */
+	bus_addr_t		sa_addr;	/* i/o address  */
+	bus_size_t		sa_size;
+
+	int			sa_intr;
+	int			sa_gpio;
+};
+
+void *sa11x0_intr_establish(sa11x0_chipset_tag_t, int, int, int, 
+			    int (*)(void *), void *);
+void sa11x0_intr_disestablish(sa11x0_chipset_tag_t, void *);
+
+#endif /* _SA11X0_VAR_H */
diff --git a/sys/arm/sa11x0/std.sa11x0 b/sys/arm/sa11x0/std.sa11x0
new file mode 100644
index 0000000..f95a815
--- /dev/null
+++ b/sys/arm/sa11x0/std.sa11x0
@@ -0,0 +1,5 @@
+#StrongARM SA11x0 common options
+#$FreeBSD$
+files		"../sa11x0/files.sa11x0"
+cpu		CPU_SA1100
+cpu		CPU_SA1110