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author | wma <wma@FreeBSD.org> | 2017-05-19 08:25:40 +0000 |
---|---|---|
committer | Luiz Souza <luiz@netgate.com> | 2017-09-06 11:35:29 -0500 |
commit | 74ee194f003c8ee625adbcdd40c8a16d97f93b3a (patch) | |
tree | 83318cf4a0eeecf5d0ef56e089c8dcb1d5fae5bc /sys/arm/mv | |
parent | 5699965c97bf666c7198607ec23836585ab9bd32 (diff) | |
download | FreeBSD-src-74ee194f003c8ee625adbcdd40c8a16d97f93b3a.zip FreeBSD-src-74ee194f003c8ee625adbcdd40c8a16d97f93b3a.tar.gz |
Fix MPIC mask/unmask
Before the fix for single interrupt, both percpu and non-percpu routes
were enabled/disable at the same time.
Submitted by: Marcin Wojtas <mw@semihalf.com
Obtained from: Semihalf
Sponsored by: Stormshield, Netgate
Reviewed by: loos
Differential revision: https://reviews.freebsd.org/D10716
(cherry picked from commit 910ae5e9b5b7a13cff3654d96e0300fc3294eac9)
Diffstat (limited to 'sys/arm/mv')
-rw-r--r-- | sys/arm/mv/mpic.c | 24 |
1 files changed, 18 insertions, 6 deletions
diff --git a/sys/arm/mv/mpic.c b/sys/arm/mv/mpic.c index 70c17ae..49e4bd4 100644 --- a/sys/arm/mv/mpic.c +++ b/sys/arm/mv/mpic.c @@ -148,6 +148,7 @@ static void mpic_unmask_irq(uintptr_t nb); static void mpic_mask_irq(uintptr_t nb); static void mpic_mask_irq_err(uintptr_t nb); static void mpic_unmask_irq_err(uintptr_t nb); +static boolean_t mpic_irq_is_percpu(uintptr_t); #ifdef INTRNG static int mpic_intr(void *arg); #endif @@ -474,14 +475,24 @@ mpic_mask_irq_err(uintptr_t nb) MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ERR_MASK, mask); } +static boolean_t +mpic_irq_is_percpu(uintptr_t nb) +{ + if (nb < MPIC_PPI) + return TRUE; + + return FALSE; +} + static void mpic_unmask_irq(uintptr_t nb) { - if (nb < ERR_IRQ) { - MPIC_WRITE(mv_mpic_sc, MPIC_ISE, nb); + if (mpic_irq_is_percpu(nb)) MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ICM, nb); - } else if (nb < MSI_IRQ) + else if (nb < ERR_IRQ) + MPIC_WRITE(mv_mpic_sc, MPIC_ISE, nb); + else if (nb < MSI_IRQ) mpic_unmask_irq_err(nb); if (nb == 0) @@ -492,10 +503,11 @@ static void mpic_mask_irq(uintptr_t nb) { - if (nb < ERR_IRQ) { - MPIC_WRITE(mv_mpic_sc, MPIC_ICE, nb); + if (mpic_irq_is_percpu(nb)) MPIC_CPU_WRITE(mv_mpic_sc, MPIC_ISM, nb); - } else if (nb < MSI_IRQ) + else if (nb < ERR_IRQ) + MPIC_WRITE(mv_mpic_sc, MPIC_ICE, nb); + else if (nb < MSI_IRQ) mpic_mask_irq_err(nb); } |