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author | Luiz Souza <luiz@netgate.com> | 2017-05-11 22:48:37 -0500 |
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committer | Luiz Souza <luiz@netgate.com> | 2017-07-20 21:25:04 -0500 |
commit | 10b4e90a04d13dbc9bceb35c291aebf584050b44 (patch) | |
tree | 0024613261fa4c2efd87c5c3855249a743f724a0 /sys/arm/mv | |
parent | b2f0c6c57c61b6cbddd280ae37a0dfb5a519e26b (diff) | |
download | FreeBSD-src-10b4e90a04d13dbc9bceb35c291aebf584050b44.zip FreeBSD-src-10b4e90a04d13dbc9bceb35c291aebf584050b44.tar.gz |
Export more information about ARM CPUs and SoCs.
(cherry picked from commit 98135cfa4ef6f8bed339d3994e69b2cc6fb7a343)
Diffstat (limited to 'sys/arm/mv')
-rw-r--r-- | sys/arm/mv/mv_common.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/sys/arm/mv/mv_common.c b/sys/arm/mv/mv_common.c index 497860f..cf54a2a 100644 --- a/sys/arm/mv/mv_common.c +++ b/sys/arm/mv/mv_common.c @@ -391,6 +391,7 @@ static void soc_identify(void) { uint32_t d, r, size, mode; + char tmp[128]; const char *dev; const char *rev; @@ -480,10 +481,19 @@ soc_identify(void) break; } + memset(tmp, 0, sizeof(tmp)); + memset(mv_soc_model, 0, sizeof(mv_soc_model)); + snprintf(mv_soc_model, sizoef(mv_soc_model) - 1, "%s", dev); printf("%s", dev); - if (*rev != '\0') + if (*rev != '\0') { printf(" rev %s", rev); + snprintf(tmp, sizeof(tmp) - 1, " rev %s", rev); + strlcat(mv_soc_model, tmp, sizeof(mv_soc_model)); + } printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000); + snprintf(tmp, sizeof(tmp) - 1, ", TClock %dMHz\n", + get_tclk() / 1000 / 1000); + strlcat(mv_soc_model, tmp, sizeof(mv_soc_model)); mode = read_cpu_ctrl(CPU_CONFIG); printf(" Instruction cache prefetch %s, data cache prefetch %s\n", |