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authorraj <raj@FreeBSD.org>2009-01-08 18:31:43 +0000
committerraj <raj@FreeBSD.org>2009-01-08 18:31:43 +0000
commitfa4df0b07e913c64e1a41505b9a10843bc12f773 (patch)
tree7e1d5a2c8e0851351dd7e0f146f068deba3eba7c /sys/arm/mv/gpio.c
parent8c23321acb993cc6cbb9f540aa6b10046d7e2dcf (diff)
downloadFreeBSD-src-fa4df0b07e913c64e1a41505b9a10843bc12f773.zip
FreeBSD-src-fa4df0b07e913c64e1a41505b9a10843bc12f773.tar.gz
Improve and extend Marvell SOCs platform code.
- Allow for setting per platform MPP/GPIO configuration in the kernel, so that we can override all settings firmware might set. - Set decode windows for the remaining on-chip peripherals: CESA, SATA and XOR. - Improve handling of USB controllers so that all port are available on the given SOC/platform (e.g. up to three on DB-78xxx), this includes rework of USB decode windows set-up. - Other minor fixes and cosmetics. Obtained from: Semihalf
Diffstat (limited to 'sys/arm/mv/gpio.c')
-rw-r--r--sys/arm/mv/gpio.c28
1 files changed, 20 insertions, 8 deletions
diff --git a/sys/arm/mv/gpio.c b/sys/arm/mv/gpio.c
index 4fba619..9045455 100644
--- a/sys/arm/mv/gpio.c
+++ b/sys/arm/mv/gpio.c
@@ -62,7 +62,7 @@ struct mv_gpio_softc {
uint8_t use_high;
};
-extern struct resource_spec mv_gpio_spec[];
+extern struct resource_spec mv_gpio_res[];
static struct mv_gpio_softc *mv_gpio_softc = NULL;
static uint32_t gpio_setup[MV_GPIO_MAX_NPINS];
@@ -143,7 +143,7 @@ mv_gpio_attach(device_t dev)
return (ENXIO);
}
- error = bus_alloc_resources(dev, mv_gpio_spec, sc->res);
+ error = bus_alloc_resources(dev, mv_gpio_res, sc->res);
if (error) {
device_printf(dev, "could not allocate resources\n");
return (ENXIO);
@@ -171,21 +171,33 @@ mv_gpio_attach(device_t dev)
INTR_TYPE_MISC | INTR_FAST,
(driver_filter_t *)mv_gpio_intr, NULL,
sc, &sc->ih_cookie[i]) != 0) {
- bus_release_resources(dev, mv_gpio_spec, sc->res);
+ bus_release_resources(dev, mv_gpio_res, sc->res);
device_printf(dev, "could not set up intr %d\n", i);
return (ENXIO);
}
}
+ /* Setup GPIO lines */
+ for (i = 0; mv_gpio_config[i].gc_gpio >= 0; i++) {
+ mv_gpio_configure(mv_gpio_config[i].gc_gpio,
+ mv_gpio_config[i].gc_flags, ~0u);
+
+ if (mv_gpio_config[i].gc_output < 0)
+ mv_gpio_out_en(mv_gpio_config[i].gc_gpio, 0);
+ else
+ mv_gpio_out(mv_gpio_config[i].gc_gpio,
+ mv_gpio_config[i].gc_output, 1);
+ }
+
return (0);
}
static void
mv_gpio_intr(void *arg)
{
- uint32_t int_cause, gpio_val;
- uint32_t int_cause_hi, gpio_val_hi = 0;
- int i;
+ uint32_t int_cause, gpio_val;
+ uint32_t int_cause_hi, gpio_val_hi = 0;
+ int i;
int_cause = mv_gpio_reg_read(GPIO_INT_CAUSE);
gpio_val = mv_gpio_reg_read(GPIO_DATA_IN);
@@ -295,8 +307,8 @@ mv_gpio_configure(uint32_t pin, uint32_t flags, uint32_t mask)
if (mask & MV_GPIO_BLINK)
mv_gpio_blink(pin, flags & MV_GPIO_BLINK);
- if (mask & MV_GPIO_POLARITY)
- mv_gpio_polarity(pin, flags & MV_GPIO_POLARITY);
+ if (mask & MV_GPIO_POLAR_LOW)
+ mv_gpio_polarity(pin, flags & MV_GPIO_POLAR_LOW);
if (mask & MV_GPIO_EDGE)
mv_gpio_edge(pin, flags & MV_GPIO_EDGE);
if (mask & MV_GPIO_LEVEL)
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