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authorraj <raj@FreeBSD.org>2008-10-13 20:07:13 +0000
committerraj <raj@FreeBSD.org>2008-10-13 20:07:13 +0000
commit3226c137788c6c0c6b82bd1b88fd42a2a8ea4cb8 (patch)
treed96b4a1062d4a3a8f75bdb30e300bd1a50f23e4f /sys/arm/mv/files.mv
parent000539b88803ce11f549bc8d24154dc9a6b1c386 (diff)
downloadFreeBSD-src-3226c137788c6c0c6b82bd1b88fd42a2a8ea4cb8.zip
FreeBSD-src-3226c137788c6c0c6b82bd1b88fd42a2a8ea4cb8.tar.gz
Introduce basic support for Marvell families of system-on-chip ARM devices:
* Orion - 88F5181 - 88F5182 - 88F5281 * Kirkwood - 88F6281 * Discovery - MV78100 The above families of SOCs are built around CPU cores compliant with ARMv5TE instruction set architecture definition. They share a number of integrated peripherals. This commit brings support for the following basic elements: * GPIO * Interrupt controller * L1, L2 cache * Timers, watchdog, RTC * TWSI (I2C) * UART Other peripherals drivers will be introduced separately. Reviewed by: imp, marcel, stass (Thanks guys!) Obtained from: Marvell, Semihalf
Diffstat (limited to 'sys/arm/mv/files.mv')
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1 files changed, 34 insertions, 0 deletions
diff --git a/sys/arm/mv/files.mv b/sys/arm/mv/files.mv
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+# $FreeBSD$
+#
+# The Marvell CPU cores
+# - Compliant with V5TE architecture
+# - Super scalar dual issue CPU
+# - Big/Little Endian
+# - MMU/MPU
+# - L1 Cache: Supports streaming and write allocate
+# - Variable pipeline stages
+# - Out-of-order execution
+# - Branch Prediction
+# - JTAG/ICE
+# - Vector Floating Point (VFP) unit
+#
+arm/arm/bus_space_generic.c standard
+arm/arm/cpufunc_asm_arm10.S standard
+arm/arm/cpufunc_asm_armv5_ec.S standard
+arm/arm/cpufunc_asm_feroceon.S standard
+arm/arm/irq_dispatch.S standard
+
+arm/mv/bus_space.c standard
+arm/mv/common.c standard
+arm/mv/gpio.c standard
+arm/mv/ic.c standard
+arm/mv/mv_machdep.c standard
+arm/mv/obio.c standard
+arm/mv/timer.c standard
+arm/mv/twsi.c optional iicbus
+
+dev/mge/if_mge.c optional mge
+dev/uart/uart_bus_mbus.c optional uart
+dev/uart/uart_cpu_mv.c optional uart
+dev/uart/uart_dev_ns8250.c optional uart
+dev/usb/ehci_mbus.c optional ehci
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