diff options
| author | imp <imp@FreeBSD.org> | 2012-08-11 05:45:19 +0000 |
|---|---|---|
| committer | imp <imp@FreeBSD.org> | 2012-08-11 05:45:19 +0000 |
| commit | 5d28872c59cb8c8d5bc8f89af73af575a53ba24a (patch) | |
| tree | 338892b0584817392a198ad882703d8d288d1183 /sys/arm/at91/at91sam9g20.c | |
| parent | dc70787a30899e2581ad5a667f915fb406cce817 (diff) | |
| download | FreeBSD-src-5d28872c59cb8c8d5bc8f89af73af575a53ba24a.zip FreeBSD-src-5d28872c59cb8c8d5bc8f89af73af575a53ba24a.tar.gz | |
Correct the PLLA setting functions and centralize.
Diffstat (limited to 'sys/arm/at91/at91sam9g20.c')
| -rw-r--r-- | sys/arm/at91/at91sam9g20.c | 28 |
1 files changed, 2 insertions, 26 deletions
diff --git a/sys/arm/at91/at91sam9g20.c b/sys/arm/at91/at91sam9g20.c index 73876b0..4d9907c 100644 --- a/sys/arm/at91/at91sam9g20.c +++ b/sys/arm/at91/at91sam9g20.c @@ -122,30 +122,6 @@ static const struct cpu_devs at91_devs[] = { 0, 0, 0, 0, 0 } }; -static uint32_t -at91_pll_outa(int freq) -{ - - switch (freq / 10000000) { - case 747 ... 801: return ((1 << 29) | (0 << 14)); - case 697 ... 746: return ((1 << 29) | (1 << 14)); - case 647 ... 696: return ((1 << 29) | (2 << 14)); - case 597 ... 646: return ((1 << 29) | (3 << 14)); - case 547 ... 596: return ((1 << 29) | (1 << 14)); - case 497 ... 546: return ((1 << 29) | (2 << 14)); - case 447 ... 496: return ((1 << 29) | (3 << 14)); - case 397 ... 446: return ((1 << 29) | (4 << 14)); - default: return (1 << 29); - } -} - -static uint32_t -at91_pll_outb(int freq) -{ - - return (0); -} - static void at91_clock_init(void) { @@ -171,7 +147,7 @@ at91_clock_init(void) clk->pll_mul_mask = SAM9G20_PLL_A_MUL_MASK; clk->pll_div_shift = SAM9G20_PLL_A_DIV_SHIFT; clk->pll_div_mask = SAM9G20_PLL_A_DIV_MASK; - clk->set_outb = at91_pll_outa; + clk->set_outb = at91_pmc_800mhz_plla_outb; at91_pmc_clock_deref(clk); clk = at91_pmc_clock_ref("pllb"); @@ -183,7 +159,7 @@ at91_clock_init(void) clk->pll_mul_mask = SAM9G20_PLL_B_MUL_MASK; clk->pll_div_shift = SAM9G20_PLL_B_DIV_SHIFT; clk->pll_div_mask = SAM9G20_PLL_B_DIV_MASK; - clk->set_outb = at91_pll_outb; + clk->set_outb = at91_pmc_800mhz_pllb_outb; at91_pmc_clock_deref(clk); } |
