Create common routines for configuring the serial ports and use them

on all the at91rm9200 boards.

1 files changed, 62 insertions, 0 deletions

diff --git a/sys/arm/at91/at91rm9200_devices.c b/sys/arm/at91/at91rm9200_devices.c
index 7957fd0..f6663af 100644
--- a/sys/arm/at91/at91rm9200_devices.c
+++ b/sys/arm/at91/at91rm9200_devices.c
@@ -37,7 +37,11 @@ __FBSDID("$FreeBSD$");
 #include <machine/bus.h>
 
 #include <arm/at91/at91var.h>
+#include <arm/at91/at91board.h>
+#include <arm/at91/at91rm92reg.h>
 #include <arm/at91/at91rm9200var.h>
+#include <arm/at91/at91_pioreg.h>
+#include <arm/at91/at91_piovar.h>
 
 /*
  * The AT91RM9200 uses the same silicon for both the BGA and PQFP
@@ -60,3 +64,61 @@ at91rm9200_set_subtype(enum at91_soc_subtype st)
 		break;
 	}
 }
+
+void
+at91rm9200_config_uart(unsigned devid, unsigned unit, unsigned pinmask)
+{
+
+	/*
+	 * Since the USART supports RS-485 multidrop mode, it allows the
+	 * TX pins to float.  However, for RS-232 operations, we don't want
+	 * these pins to float.  Instead, they should be pulled up to avoid
+	 * mismatches.  Linux does something similar when it configures the
+	 * TX lines.  This implies that we also allow the RX lines to float
+	 * rather than be in the state they are left in by the boot loader.
+	 * Since they are input pins, I think that this is the right thing
+	 * to do.
+	 */
+
+	switch (devid) {
+	case AT91_ID_DBGU:
+		at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA30, 0); /* DRXD */
+		at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA31, 1); /* DTXD */
+		break;
+
+	case AT91RM9200_ID_USART0:
+		at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA17, 1); /* TXD0 */
+		at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA19, 0); /* RXD0 */
+		/* CTS PA20 */
+		/* RTS -- errata #39 PA21 */
+		break;
+
+	case AT91RM9200_ID_USART1:
+		at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PIO_PB20, 1); /* TXD1 */
+		at91_pio_use_periph_a(AT91RM92_PIOB_BASE, AT91C_PIO_PB21, 0); /* RXD1 */
+		/* RI - PB18 */
+		/* DTR - PB19 */
+		/* DCD - PB23 */
+		/* CTS - PB24 */
+		/* DSR - PB25 */
+		/* RTS - PB26 */
+		break;
+
+	case AT91RM9200_ID_USART2:
+		at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA22, 0); /* RXD2 */
+		at91_pio_use_periph_a(AT91RM92_PIOA_BASE, AT91C_PIO_PA23, 1); /* TXD2 */
+		/* CTS - PA30 B periph */
+		/* RTS - PA31 B periph */
+		break;
+
+	case AT91RM9200_ID_USART3:
+		at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PIO_PA5, 1); /* TXD3 */
+		at91_pio_use_periph_b(AT91RM92_PIOA_BASE, AT91C_PIO_PA6, 0); /* RXD3 */
+		/* CTS - PB0 B periph */
+		/* RTS - PB1 B periph */
+		break;
+
+	default:
+		break;
+	}
+}