Enhance the Atmel SoC chip identification routines to account for more

SoC variants.  Fold the AT91SAM9XE chips into the AT91SAM9260
handling, where appropriate.  The following SoCs/SoC families are recognized:
	at91cap9, at91rm9200, at91sam9260, at91sam9261, at91sam9263,
	at91sam9g10, at91sam9g20, at91sam9g45, at91sam9n12, at91sam9rl,
	at91sam9x5
and the following variations are also recognized:
	at91rm9200_bga, at91rm9200_pqfp, at91sam9xe, at91sam9g45, at91sam9m10,
	at91sam9g46, at91sam9m11, at91sam9g15, at91sam9g25, at91sam9g35,
	at91sam9x25, at91sam9x35
This is only the identification routine: no additional Atmel devices
are supported at this time.

# With these changes, I'm able to boot to the point of identification
# on a few different Atmel SoCs that we don't yet support using the
# KB920X config file -- someday tht will be an ATMEL config file...

1 files changed, 25 insertions, 17 deletions

diff --git a/sys/arm/at91/at91reg.h b/sys/arm/at91/at91reg.h
index 7493de8..0401291 100644
--- a/sys/arm/at91/at91reg.h
+++ b/sys/arm/at91/at91reg.h
@@ -46,32 +46,40 @@
 #define	AT91_SYS_BASE	0xffff000
 #define	AT91_SYS_SIZE	0x1000
 
-#if defined(AT91SAM9G45) || defined(AT91SAM9263)
-#define	AT91_DBGU_BASE	0xfffee00
-#else
-#define	AT91_DBGU_BASE	0xffff200
-#endif
 #define	AT91_DBGU_SIZE	0x200
 #define	DBGU_C1R		(64) /* Chip ID1 Register */
 #define	DBGU_C2R		(68) /* Chip ID2 Register */
 #define	DBGU_FNTR		(72) /* Force NTRST Register */
 
 #define	AT91_CPU_VERSION_MASK	0x0000001f
-#define	AT91_CPU_RM9200   	0x09290780
-#define	AT91_CPU_SAM9260  	0x019803a0
-#define	AT91_CPU_SAM9261  	0x019703a0
-#define	AT91_CPU_SAM9263  	0x019607a0
-#define	AT91_CPU_SAM9G10  	0x819903a0
-#define	AT91_CPU_SAM9G20  	0x019905a0
-#define	AT91_CPU_SAM9G45  	0x819b05a0
+#define	AT91_CPU_FAMILY_MASK    0x0ff00000
+
+#define	AT91_CPU_RM9200 	0x09290780
+#define	AT91_CPU_SAM9260	0x019803a0
+#define	AT91_CPU_SAM9261	0x019703a0
+#define	AT91_CPU_SAM9263	0x019607a0
+#define	AT91_CPU_SAM9G10	0x819903a0
+#define	AT91_CPU_SAM9G20	0x019905a0
+#define	AT91_CPU_SAM9G45	0x819b05a0
+#define	AT91_CPU_SAM9N12        0x819a07a0
+#define	AT91_CPU_SAM9RL64	0x019b03a0
+#define	AT91_CPU_SAM9X5		0x819a05a0
+
 #define	AT91_CPU_SAM9XE128	0x329973a0
 #define	AT91_CPU_SAM9XE256	0x329a93a0
 #define	AT91_CPU_SAM9XE512	0x329aa3a0
 
-#define	AT91_ARCH(chipid)	((chipid >> 20) & 0xff)
-#define	AT91_CPU(chipid)	(chipid & ~AT91_CPU_VERSION_MASK)
-#define	AT91_ARCH_SAM9		(0x19)
-#define	AT91_ARCH_SAM9XE	(0x29)
-#define	AT91_ARCH_RM92		(0x92)
+#define	AT91_CPU_CAP9           0x039a03a0
+
+#define	AT91_EXID_SAM9M11	0x00000001
+#define	AT91_EXID_SAM9M10	0x00000002
+#define	AT91_EXID_SAM9G46	0x00000003
+#define	AT91_EXID_SAM9G45	0x00000004
+
+#define	AT91_EXID_SAM9G15	0x00000000
+#define	AT91_EXID_SAM9G35	0x00000001
+#define	AT91_EXID_SAM9X35	0x00000002
+#define	AT91_EXID_SAM9G25	0x00000003
+#define	AT91_EXID_SAM9X25	0x00000004
 
 #endif /* _AT91REG_H_ */