- Prepend the device description with "AT91" to reflect its nature. [1]

- Move DMA tag and map creature to at91_spi_activate() where the other
  resource allocation also lives. [1]
- Flesh out at91_spi_deactivate(). [1]
- Work around the "Software Reset must be Written Twice" erratum.
- For now, run the bus at the slowest speed possible in order to work
  around data corruption on transit even seen with 9 MHz on ETHERNUT5
  (15 MHz maximum) and AT45DB321D (20 MHz maximum). This also serves as
  a poor man's work-around for the "NPCSx rises if no data data is to be
  transmitted" erratum of RM9200. Being able to use the appropriate bus
  speed would require:
  1) Adding a proper work-around for the RM9200 bug consisting of taking
     the chip select control away from the SPI peripheral and managing it
     directly as a GPIO line.
  2) Taking the maximum frequencies supported by the actual board and the
     slave devices into account and basing the whole thing on the master
     clock instead of hardcoding a divisor as previously done.
  3) Fixing the above mentioned data corruption.
- KASSERT that TX/RX command and data sizes match on transfers.
- Introduce a mutex ensuring that only one child device is running a SPI
  transfer at a time. [1]
- Add preliminary, #ifdef'ed out support for setting the chip select. [1]
- Use the RX instead of the TX commando size when setting up the RX side
  of a transfer.
- For controllers having SPI_SR_TXEMPTY, i.e. !RM9200, also wait for the
  completion of the TX part of transfers before stopping the whole thing
  again.
- Use DEVMETHOD_END. [1]
- Use NULL instead of 0 for pointers. [1, partially]

Additional testing by:  Ian Lepore

Submitted by:   Ian Lepore [1]
MFC after:      1 week

1 files changed, 2 insertions, 0 deletions

diff --git a/sys/arm/at91/at91_spireg.h b/sys/arm/at91/at91_spireg.h
index c57edab..251564f 100644
--- a/sys/arm/at91/at91_spireg.h
+++ b/sys/arm/at91/at91_spireg.h
@@ -54,6 +54,8 @@
 #define	  SPI_SR_ENDTX		0x00020
 #define	  SPI_SR_RXBUFF		0x00040
 #define	  SPI_SR_TXBUFE		0x00080
+#define	  SPI_SR_NSSR		0x00100
+#define	  SPI_SR_TXEMPTY	0x00200
 #define	  SPI_SR_SPIENS		0x10000
 #define	SPI_IER		0x14		/* IER: Interrupt Enable Regsiter */
 #define	SPI_IDR		0x18		/* IDR: Interrupt Disable Regsiter */