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| author | andrew <andrew@FreeBSD.org> | 2012-07-26 08:01:25 +0000 |
|---|---|---|
| committer | andrew <andrew@FreeBSD.org> | 2012-07-26 08:01:25 +0000 |
| commit | ab76299bf91c637be92880977cbd2e6fcb198045 (patch) | |
| tree | b533679dee6da783dd8c09c9da14e74960f03a11 /sys/arm/at91/at91_pmcreg.h | |
| parent | 8ebd4a20e01aa98aaab356ac5af5fdd0544153c3 (diff) | |
| download | FreeBSD-src-ab76299bf91c637be92880977cbd2e6fcb198045.zip FreeBSD-src-ab76299bf91c637be92880977cbd2e6fcb198045.tar.gz | |
Add support for the Atmel AT91SAM9G45 CPU.
Reviewed by: imp
Diffstat (limited to 'sys/arm/at91/at91_pmcreg.h')
| -rw-r--r-- | sys/arm/at91/at91_pmcreg.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/sys/arm/at91/at91_pmcreg.h b/sys/arm/at91/at91_pmcreg.h index eaf08c6..ce6165d 100644 --- a/sys/arm/at91/at91_pmcreg.h +++ b/sys/arm/at91/at91_pmcreg.h @@ -36,14 +36,14 @@ #define PMC_PCER 0x10 /* Peripheral Clock Enable Register */ #define PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ #define PMC_PCSR 0x18 /* Peripheral Clock Status Register */ - /* 0x1c reserved */ +#define CKGR_UCKR 0x1c /* UTMI Clock Configuration Register */ #define CKGR_MOR 0x20 /* Main Oscillator Register */ #define CKGR_MCFR 0x24 /* Main Clock Frequency Register */ #define CKGR_PLLAR 0x28 /* PLL A Register */ #define CKGR_PLLBR 0x2c /* PLL B Register */ #define PMC_MCKR 0x30 /* Master Clock Register */ /* 0x34 reserved */ - /* 0x38 reserved */ +#define PMC_USB 0x38 /* USB Clock Register */ /* 0x3c reserved */ #define PMC_PCK0 0x40 /* Programmable Clock 0 Register */ #define PMC_PCK1 0x44 /* Programmable Clock 1 Register */ @@ -77,6 +77,10 @@ /* PMC Peripheral Clock Status Register */ /* Each bit here is 1 << peripheral number to enable/disable/status */ +/* PMC UTMI Clock Configuration Register */ +#define CKGR_UCKR_BIASEN (1UL << 24) +#define CKGR_UCKR_UPLLEN (1UL << 16) + /* PMC Clock Generator Main Oscillator Register */ #define CKGR_MOR_MOSCEN (1UL << 0) /* MOSCEN: Main Oscillator Enable */ #define CKGR_MOR_OSCBYPASS (1UL << 1) /* Oscillator Bypass */ @@ -93,6 +97,10 @@ #define PMC_MCKR_MDIV_MASK (3 << 8) #define PMC_MCKR_PRES_MASK (7 << 2) +/* PMC USB Clock Register */ +#define PMC_USB_USBDIV(n) (((n) & 0x0F) << 8) +#define PMC_USB_USBS (1 << 0) + /* PMC Interrupt Enable Register */ /* PMC Interrupt Disable Register */ /* PMC Status Register */ @@ -101,6 +109,7 @@ #define PMC_IER_LOCKA (1UL << 1) /* PLL A Locked */ #define PMC_IER_LOCKB (1UL << 2) /* PLL B Locked */ #define PMC_IER_MCKRDY (1UL << 3) /* Master Clock Status */ +#define PMC_IER_LOCKU (1UL << 6) /* UPLL Locked */ #define PMC_IER_PCK0RDY (1UL << 8) /* Programmable Clock 0 Ready */ #define PMC_IER_PCK1RDY (1UL << 9) /* Programmable Clock 1 Ready */ #define PMC_IER_PCK2RDY (1UL << 10) /* Programmable Clock 2 Ready */ |
