MFC r257170, r257171, r257172, r257240, r257278, r257279, r257280, r257281,

    r257282, r257332

  Wait for DesignWare UART transfers completion before accessing line control

  Enable UART busy detection handling for Armada XP - based board

  Enable SATA interface on Armada XP
  Run mvs SATA driver on Armada XP instead of old mv_sata

  Retire arm_remap_nocache() and the data and constants associated with it.

  Remove hard-coded mappings related to Armada XP support

  Fix-up DTB for Armada XP registers' base according to the actual settings

  Change Armada XP kernel load address to the u-boot's end address

  Remove not working and deprecated PJ4Bv6 support

  Switch off explicit broadcasting of the TLB flush operations for PJ4B CPU

  Add missing ARMv6 CPU functions to ARM Makefile

1 files changed, 2 insertions, 112 deletions

diff --git a/sys/arm/arm/cpufunc.c b/sys/arm/arm/cpufunc.c
index 11c3e5e..d69f2f1 100644
--- a/sys/arm/arm/cpufunc.c
+++ b/sys/arm/arm/cpufunc.c
@@ -541,65 +541,6 @@ struct cpu_functions pj4bv7_cpufuncs = {
 
 	pj4bv7_setup			/* cpu setup		*/
 };
-
-struct cpu_functions pj4bv6_cpufuncs = {
-	/* CPU functions */
-
-	cpufunc_id,			/* id			*/
-	arm11_drain_writebuf,		/* cpwait		*/
-
-	/* MMU functions */
-
-	cpufunc_control,		/* control		*/
-	cpufunc_domains,		/* Domain		*/
-	pj4b_setttb,			/* Setttb		*/
-	cpufunc_faultstatus,		/* Faultstatus		*/
-	cpufunc_faultaddress,		/* Faultaddress		*/
-
-	/* TLB functions */
-
-	arm11_tlb_flushID,		/* tlb_flushID		*/
-	arm11_tlb_flushID_SE,		/* tlb_flushID_SE	*/
-	arm11_tlb_flushI,		/* tlb_flushI		*/
-	arm11_tlb_flushI_SE,		/* tlb_flushI_SE	*/
-	arm11_tlb_flushD,		/* tlb_flushD		*/
-	arm11_tlb_flushD_SE,		/* tlb_flushD_SE	*/
-
-	/* Cache operations */
-	armv6_icache_sync_all,		/* icache_sync_all	*/
-	pj4b_icache_sync_range,		/* icache_sync_range	*/
-
-	armv6_dcache_wbinv_all,		/* dcache_wbinv_all	*/
-	pj4b_dcache_wbinv_range,	/* dcache_wbinv_range	*/
-	pj4b_dcache_inv_range,		/* dcache_inv_range	*/
-	pj4b_dcache_wb_range,		/* dcache_wb_range	*/
-
-	armv6_idcache_wbinv_all,	/* idcache_wbinv_all	*/
-	pj4b_idcache_wbinv_range,	/* idcache_wbinv_all	*/
-
-	(void *)cpufunc_nullop,		/* l2cache_wbinv_all	*/
-	(void *)cpufunc_nullop,		/* l2cache_wbinv_range	*/
-	(void *)cpufunc_nullop,		/* l2cache_inv_range	*/
-	(void *)cpufunc_nullop,		/* l2cache_wb_range	*/
-
-	/* Other functions */
-
-	pj4b_drain_readbuf,		/* flush_prefetchbuf	*/
-	arm11_drain_writebuf,		/* drain_writebuf	*/
-	pj4b_flush_brnchtgt_all,	/* flush_brnchtgt_C	*/
-	pj4b_flush_brnchtgt_va,		/* flush_brnchtgt_E	*/
-
-	(void *)cpufunc_nullop,		/* sleep		*/
-
-	/* Soft functions */
-
-	cpufunc_null_fixup,		/* dataabt_fixup	*/
-	cpufunc_null_fixup,		/* prefetchabt_fixup	*/
-
-	arm11_context_switch,		/* context_switch	*/
-
-	pj4bv6_setup			/* cpu setup		*/
-};
 #endif /* CPU_MV_PJ4B */
 
 #ifdef CPU_SA110
@@ -1496,27 +1437,14 @@ set_cpufuncs()
 #endif /* CPU_CORTEXA */
 		
 #if defined(CPU_MV_PJ4B)
-	if (cputype == CPU_ID_MV88SV581X_V6 ||
-	    cputype == CPU_ID_MV88SV581X_V7 ||
+	if (cputype == CPU_ID_MV88SV581X_V7 ||
 	    cputype == CPU_ID_MV88SV584X_V7 ||
-	    cputype == CPU_ID_ARM_88SV581X_V6 ||
 	    cputype == CPU_ID_ARM_88SV581X_V7) {
-		if (cpu_pfr(0) & ARM_PFR0_THUMBEE_MASK)
-			cpufuncs = pj4bv7_cpufuncs;
-		else
-			cpufuncs = pj4bv6_cpufuncs;
-
-		get_cachetype_cp15();
-		pmap_pte_init_mmu_v6();
-		goto out;
-	} else if (cputype == CPU_ID_ARM_88SV584X_V6 ||
-	    cputype == CPU_ID_MV88SV584X_V6) {
-		cpufuncs = pj4bv6_cpufuncs;
+		cpufuncs = pj4bv7_cpufuncs;
 		get_cachetype_cp15();
 		pmap_pte_init_mmu_v6();
 		goto out;
 	}
-
 #endif /* CPU_MV_PJ4B */
 #ifdef CPU_SA110
 	if (cputype == CPU_ID_SA110) {
@@ -2446,44 +2374,6 @@ arm11x6_setup(char *args)
 
 #ifdef CPU_MV_PJ4B
 void
-pj4bv6_setup(char *args)
-{
-	int cpuctrl;
-
-	pj4b_config();
-
-	cpuctrl = CPU_CONTROL_MMU_ENABLE;
-#ifndef ARM32_DISABLE_ALIGNMENT_FAULTS
-	cpuctrl |= CPU_CONTROL_AFLT_ENABLE;
-#endif
-	cpuctrl |= CPU_CONTROL_DC_ENABLE;
-	cpuctrl |= (0xf << 3);
-#ifdef __ARMEB__
-	cpuctrl |= CPU_CONTROL_BEND_ENABLE;
-#endif
-	cpuctrl |= CPU_CONTROL_SYST_ENABLE;
-	cpuctrl |= CPU_CONTROL_BPRD_ENABLE;
-	cpuctrl |= CPU_CONTROL_IC_ENABLE;
-	if (vector_page == ARM_VECTORS_HIGH)
-		cpuctrl |= CPU_CONTROL_VECRELOC;
-	cpuctrl |= (0x5 << 16);
-	cpuctrl |= CPU_CONTROL_V6_EXTPAGE;
-	/* XXX not yet */
-	/* cpuctrl |= CPU_CONTROL_L2_ENABLE; */
-
-	/* Make sure caches are clean.  */
-	cpu_idcache_wbinv_all();
-	cpu_l2cache_wbinv_all();
-
-	/* Set the control register */
-	ctrl = cpuctrl;
-	cpu_control(0xffffffff, cpuctrl);
-
-	cpu_idcache_wbinv_all();
-	cpu_l2cache_wbinv_all();
-}
-
-void
 pj4bv7_setup(args)
 	char *args;
 {