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author | br <br@FreeBSD.org> | 2014-09-04 12:44:40 +0000 |
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committer | br <br@FreeBSD.org> | 2014-09-04 12:44:40 +0000 |
commit | f3c6b45c01969eefad06f216c13f6e4d35951527 (patch) | |
tree | b27661c49d9b7fbd0901e31fe9b23e8c213dc11b /sys/arm/altera/socfpga/socfpga_common.c | |
parent | ae21082d79820db4832b2e5dbee75b5bdba98f66 (diff) | |
download | FreeBSD-src-f3c6b45c01969eefad06f216c13f6e4d35951527.zip FreeBSD-src-f3c6b45c01969eefad06f216c13f6e4d35951527.tar.gz |
Add initial support for Altera SOCFPGA (heterogeneous ARM/FPGA) SoC family.
Include board configuration for Terasic SoCKit (Altera Cyclone V).
Sponsored by: DARPA, AFRL
Diffstat (limited to 'sys/arm/altera/socfpga/socfpga_common.c')
-rw-r--r-- | sys/arm/altera/socfpga/socfpga_common.c | 83 |
1 files changed, 83 insertions, 0 deletions
diff --git a/sys/arm/altera/socfpga/socfpga_common.c b/sys/arm/altera/socfpga/socfpga_common.c new file mode 100644 index 0000000..86d46e3 --- /dev/null +++ b/sys/arm/altera/socfpga/socfpga_common.c @@ -0,0 +1,83 @@ +/*- + * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> + * All rights reserved. + * + * This software was developed by SRI International and the University of + * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) + * ("CTSRD"), as part of the DARPA CRASH research programme. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <sys/cdefs.h> +__FBSDID("$FreeBSD$"); + +#include <sys/param.h> +#include <sys/systm.h> +#include <sys/bus.h> +#include <sys/kernel.h> + +#include <dev/fdt/fdt_common.h> +#include <dev/ofw/openfirm.h> + +#include <machine/bus.h> +#include <machine/fdt.h> + +#define RESMAN_BASE 0xFFD05000 +#define RESMAN_CTRL 0x4 +#define SWWARMRSTREQ (1 << 1) + +void +cpu_reset(void) +{ + bus_addr_t vaddr; + + if (bus_space_map(fdtbus_bs_tag, RESMAN_BASE, 0x10, 0, &vaddr) == 0) { + bus_space_write_4(fdtbus_bs_tag, vaddr, + RESMAN_CTRL, SWWARMRSTREQ); + } + + while (1); +} + +struct fdt_fixup_entry fdt_fixup_table[] = { + { NULL, NULL } +}; + +static int +fdt_pic_decode_ic(phandle_t node, pcell_t *intr, int *interrupt, int *trig, + int *pol) +{ + + if (!fdt_is_compatible(node, "arm,gic")) + return (ENXIO); + + *interrupt = fdt32_to_cpu(intr[0]); + *trig = INTR_TRIGGER_CONFORM; + *pol = INTR_POLARITY_CONFORM; + return (0); +} + +fdt_pic_decode_t fdt_pic_table[] = { + &fdt_pic_decode_ic, + NULL +}; |