Fix abuses of cpu_critical_{enter,exit} by converting to

intr_{disable,restore} as well as providing an implemenation of
intr_{disable,restore}.

Reviewed by: jake, rwatson, jhb

6 files changed, 49 insertions, 34 deletions

diff --git a/sys/amd64/amd64/fpu.c b/sys/amd64/amd64/fpu.c
index d3d6a01..50dfb9e 100644
--- a/sys/amd64/amd64/fpu.c
+++ b/sys/amd64/amd64/fpu.c
@@ -512,7 +512,7 @@ npxinit(control)
 	u_short control;
 {
 	static union savefpu dummy;
-	critical_t savecrit;
+	register_t savecrit;
 
 	if (!npx_exists)
 		return;
@@ -521,7 +521,7 @@ npxinit(control)
 	 * fnsave to throw away any junk in the fpu.  npxsave() initializes
 	 * the fpu and sets fpcurthread = NULL as important side effects.
 	 */
-	savecrit = cpu_critical_enter();
+	savecrit = intr_disable();
 	npxsave(&dummy);
 	stop_emulating();
 #ifdef CPU_ENABLE_SSE
@@ -533,7 +533,7 @@ npxinit(control)
 	if (PCPU_GET(curpcb) != NULL)
 		fpusave(&PCPU_GET(curpcb)->pcb_save);
 	start_emulating();
-	cpu_critical_exit(savecrit);
+	intr_restore(savecrit);
 }
 
 /*
@@ -543,12 +543,12 @@ void
 npxexit(td)
 	struct thread *td;
 {
-	critical_t savecrit;
+	register_t savecrit;
 
-	savecrit = cpu_critical_enter();
+	savecrit = intr_disable();
 	if (td == PCPU_GET(fpcurthread))
 		npxsave(&PCPU_GET(curpcb)->pcb_save);
-	cpu_critical_exit(savecrit);
+	intr_restore(savecrit);
 #ifdef NPX_DEBUG
 	if (npx_exists) {
 		u_int	masked_exceptions;
@@ -759,7 +759,7 @@ static char fpetable[128] = {
 int
 npxtrap()
 {
-	critical_t savecrit;
+	register_t savecrit;
 	u_short control, status;
 	u_long *exstat;
 
@@ -768,7 +768,7 @@ npxtrap()
 		       PCPU_GET(fpcurthread), curthread, npx_exists);
 		panic("npxtrap from nowhere");
 	}
-	savecrit = cpu_critical_enter();
+	savecrit = intr_disable();
 
 	/*
 	 * Interrupt handling (for another interrupt) may have pushed the
@@ -789,7 +789,7 @@ npxtrap()
 		GET_FPU_SW(curthread) &= ~0x80bf;
 	else
 		fnclex();
-	cpu_critical_exit(savecrit);
+	intr_restore(savecrit);
 	return (fpetable[status & ((~control & 0x3f) | 0x40)]);
 }
 
@@ -804,7 +804,7 @@ int
 npxdna()
 {
 	u_long *exstat;
-	critical_t s;
+	register_t s;
 
 	if (!npx_exists)
 		return (0);
@@ -813,7 +813,7 @@ npxdna()
 		       PCPU_GET(fpcurthread), curthread);
 		panic("npxdna");
 	}
-	s = cpu_critical_enter();
+	s = intr_disable();
 	stop_emulating();
 	/*
 	 * Record new context early in case frstor causes an IRQ13.
@@ -835,7 +835,7 @@ npxdna()
 	 * first FPU instruction after a context switch.
 	 */
 	fpurstor(&PCPU_GET(curpcb)->pcb_save);
-	cpu_critical_exit(s);
+	intr_restore(s);
 
 	return (1);
 }
diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c
index 6cd77e3..29ff724 100644
--- a/sys/amd64/amd64/initcpu.c
+++ b/sys/amd64/amd64/initcpu.c
@@ -657,14 +657,14 @@ void
 enable_K5_wt_alloc(void)
 {
 	u_int64_t	msr;
-	critical_t	savecrit;
+	register_t	savecrit;
 
 	/*
 	 * Write allocate is supported only on models 1, 2, and 3, with
 	 * a stepping of 4 or greater.
 	 */
 	if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) {
-		savecrit = cpu_critical_enter();
+		savecrit = intr_disable();
 		msr = rdmsr(0x83);		/* HWCR */
 		wrmsr(0x83, msr & !(0x10));
 
@@ -695,8 +695,7 @@ enable_K5_wt_alloc(void)
 
 		msr=rdmsr(0x83);
 		wrmsr(0x83, msr|0x10); /* enable write allocate */
-
-		cpu_critical_exit(savecrit);
+		intr_restore(savecrit);
 	}
 }
 
diff --git a/sys/amd64/amd64/sys_machdep.c b/sys/amd64/amd64/sys_machdep.c
index ba47686..365c25e 100644
--- a/sys/amd64/amd64/sys_machdep.c
+++ b/sys/amd64/amd64/sys_machdep.c
@@ -411,7 +411,7 @@ i386_set_ldt(td, args)
 	struct i386_ldt_args ua, *uap = &ua;
 	caddr_t old_ldt_base;
 	int old_ldt_len;
-	critical_t savecrit;
+	register_t savecrit;
 
 	if ((error = copyin(args, uap, sizeof(struct i386_ldt_args))) < 0)
 		return(error);
@@ -532,13 +532,13 @@ i386_set_ldt(td, args)
 	}
 
 	/* Fill in range */
-	savecrit = cpu_critical_enter();
+	savecrit = intr_disable();
 	error = copyin(uap->descs, 
 	    &((union descriptor *)(pldt->ldt_base))[uap->start],
 	    uap->num * sizeof(union descriptor));
 	if (!error)
 		td->td_retval[0] = uap->start;
-	cpu_critical_exit(savecrit);
+	intr_restore(savecrit);
 
 	return(error);
 }
diff --git a/sys/amd64/amd64/vm_machdep.c b/sys/amd64/amd64/vm_machdep.c
index cc4c37a..53b871a 100644
--- a/sys/amd64/amd64/vm_machdep.c
+++ b/sys/amd64/amd64/vm_machdep.c
@@ -127,7 +127,7 @@ cpu_fork(td1, p2, td2, flags)
 	struct pcb *pcb2;
 	struct mdproc *mdp2;
 #ifdef DEV_NPX
-	int savecrit;
+	register_t savecrit;
 #endif
 
 	p1 = td1->td_proc;
@@ -152,10 +152,10 @@ cpu_fork(td1, p2, td2, flags)
 #ifdef DEV_NPX
 	if (td1 == curthread)
 		td1->td_pcb->pcb_gs = rgs();
-	savecrit = cpu_critical_enter();
+	savecrit = intr_disable();
 	if (PCPU_GET(fpcurthread) == td1)
 		npxsave(&td1->td_pcb->pcb_save);
-	cpu_critical_exit(savecrit);
+	intr_restore(savecrit);
 #endif
 
 	/* Point the pcb to the top of the stack */
diff --git a/sys/amd64/include/cpufunc.h b/sys/amd64/include/cpufunc.h
index 307e3d8..6bc01fa 100644
--- a/sys/amd64/include/cpufunc.h
+++ b/sys/amd64/include/cpufunc.h
@@ -578,6 +578,22 @@ cpu_critical_exit(critical_t eflags)
 	write_eflags(eflags);
 }
 
+static __inline register_t
+intr_disable(void)
+{
+	register_t eflags;
+
+	eflags = read_eflags();
+	disable_intr();
+	return (eflags);
+}
+
+static __inline void
+intr_restore(register_t eflags)
+{
+	write_eflags(eflags);
+}
+
 #else /* !__GNUC__ */
 
 int	breakpoint(void);
diff --git a/sys/amd64/isa/npx.c b/sys/amd64/isa/npx.c
index d3d6a01..50dfb9e 100644
--- a/sys/amd64/isa/npx.c
+++ b/sys/amd64/isa/npx.c
@@ -512,7 +512,7 @@ npxinit(control)
 	u_short control;
 {
 	static union savefpu dummy;
-	critical_t savecrit;
+	register_t savecrit;
 
 	if (!npx_exists)
 		return;
@@ -521,7 +521,7 @@ npxinit(control)
 	 * fnsave to throw away any junk in the fpu.  npxsave() initializes
 	 * the fpu and sets fpcurthread = NULL as important side effects.
 	 */
-	savecrit = cpu_critical_enter();
+	savecrit = intr_disable();
 	npxsave(&dummy);
 	stop_emulating();
 #ifdef CPU_ENABLE_SSE
@@ -533,7 +533,7 @@ npxinit(control)
 	if (PCPU_GET(curpcb) != NULL)
 		fpusave(&PCPU_GET(curpcb)->pcb_save);
 	start_emulating();
-	cpu_critical_exit(savecrit);
+	intr_restore(savecrit);
 }
 
 /*
@@ -543,12 +543,12 @@ void
 npxexit(td)
 	struct thread *td;
 {
-	critical_t savecrit;
+	register_t savecrit;
 
-	savecrit = cpu_critical_enter();
+	savecrit = intr_disable();
 	if (td == PCPU_GET(fpcurthread))
 		npxsave(&PCPU_GET(curpcb)->pcb_save);
-	cpu_critical_exit(savecrit);
+	intr_restore(savecrit);
 #ifdef NPX_DEBUG
 	if (npx_exists) {
 		u_int	masked_exceptions;
@@ -759,7 +759,7 @@ static char fpetable[128] = {
 int
 npxtrap()
 {
-	critical_t savecrit;
+	register_t savecrit;
 	u_short control, status;
 	u_long *exstat;
 
@@ -768,7 +768,7 @@ npxtrap()
 		       PCPU_GET(fpcurthread), curthread, npx_exists);
 		panic("npxtrap from nowhere");
 	}
-	savecrit = cpu_critical_enter();
+	savecrit = intr_disable();
 
 	/*
 	 * Interrupt handling (for another interrupt) may have pushed the
@@ -789,7 +789,7 @@ npxtrap()
 		GET_FPU_SW(curthread) &= ~0x80bf;
 	else
 		fnclex();
-	cpu_critical_exit(savecrit);
+	intr_restore(savecrit);
 	return (fpetable[status & ((~control & 0x3f) | 0x40)]);
 }
 
@@ -804,7 +804,7 @@ int
 npxdna()
 {
 	u_long *exstat;
-	critical_t s;
+	register_t s;
 
 	if (!npx_exists)
 		return (0);
@@ -813,7 +813,7 @@ npxdna()
 		       PCPU_GET(fpcurthread), curthread);
 		panic("npxdna");
 	}
-	s = cpu_critical_enter();
+	s = intr_disable();
 	stop_emulating();
 	/*
 	 * Record new context early in case frstor causes an IRQ13.
@@ -835,7 +835,7 @@ npxdna()
 	 * first FPU instruction after a context switch.
 	 */
 	fpurstor(&PCPU_GET(curpcb)->pcb_save);
-	cpu_critical_exit(s);
+	intr_restore(s);
 
 	return (1);
 }