General cleanup of the lock pushdown code. They are grouped and enabled

from machine/smptests.h:

#define PUSHDOWN_LEVEL_1
#define PUSHDOWN_LEVEL_2
#define PUSHDOWN_LEVEL_3
#define PUSHDOWN_LEVEL_4_NOT

12 files changed, 166 insertions, 124 deletions

diff --git a/sys/amd64/amd64/apic_vector.S b/sys/amd64/amd64/apic_vector.S
index 0652b69..f460bd8 100644
--- a/sys/amd64/amd64/apic_vector.S
+++ b/sys/amd64/amd64/apic_vector.S
@@ -1,28 +1,15 @@
 /*
  *	from: vector.s, 386BSD 0.1 unknown origin
- *	$Id: apic_vector.s,v 1.33 1997/08/30 01:23:40 smp Exp smp $
+ *	$Id: apic_vector.s,v 1.37 1997/09/07 19:23:45 smp Exp smp $
  */
 
 
 #include <machine/apic.h>
 #include <machine/smp.h>
-#include <machine/smptests.h>			/** various things... */
 
 #include "i386/isa/intr_machdep.h"
 
 
-#ifdef REAL_AVCPL
-
-#define AVCPL_LOCK	CPL_LOCK
-#define AVCPL_UNLOCK	CPL_UNLOCK
-
-#else /* REAL_AVCPL */
-
-#define AVCPL_LOCK
-#define AVCPL_UNLOCK
-
-#endif /* REAL_AVCPL */
-
 #ifdef FAST_SIMPLELOCK
 
 #define GET_FAST_INTR_LOCK						\
@@ -185,17 +172,17 @@ IDTVEC(vec_name) ;							\
  *  and the EOI cycle would cause redundant INTs to occur.
  */
 #define MASK_LEVEL_IRQ(irq_num)						\
-	IMASK_LOCK ;				/* into critical reg */	\
 	testl	$IRQ_BIT(irq_num), _apic_pin_trigger ;			\
 	jz	8f ;				/* edge, don't mask */	\
+	IMASK_LOCK ;				/* into critical reg */	\
 	orl	$IRQ_BIT(irq_num), _apic_imen ;	/* set the mask bit */	\
 	movl	_ioapic, %ecx ;			/* ioapic[0] addr */	\
 	movl	$REDTBL_IDX(irq_num), (%ecx) ;	/* write the index */	\
 	movl	IOAPIC_WINDOW(%ecx), %eax ;	/* current value */	\
 	orl	$IOART_INTMASK, %eax ;		/* set the mask */	\
 	movl	%eax, IOAPIC_WINDOW(%ecx) ;	/* new value */		\
-8: ;									\
-	IMASK_UNLOCK
+	IMASK_UNLOCK ;							\
+8:
 
 /*
  * Test to see if the source is currntly masked, clear if so.
@@ -214,10 +201,24 @@ IDTVEC(vec_name) ;							\
 	IMASK_UNLOCK
 
 #ifdef INTR_SIMPLELOCK
+#define ENLOCK
+#define DELOCK
+#define LATELOCK call	_get_isrlock
+#else
+#define ENLOCK \
+	ISR_TRYLOCK ;		/* XXX this is going away... */		\
+	testl	%eax, %eax ;			/* did we get it? */	\
+	jz	1f
+#define DELOCK	ISR_RELLOCK
+#define LATELOCK
+#endif
+
+#ifdef CPL_AND_CML
 
 #define	INTR(irq_num, vec_name)						\
 	.text ;								\
 	SUPERALIGN_TEXT ;						\
+/* _XintrNN: entry point used by IDT/HWIs & splz_unpend via _vec[]. */	\
 IDTVEC(vec_name) ;							\
 	PUSH_FRAME ;							\
 	movl	$KDSEL, %eax ;	/* reload with kernel's data segment */	\
@@ -228,9 +229,7 @@ IDTVEC(vec_name) ;							\
 	btsl	$(irq_num), iactive ;		/* lazy masking */	\
 	jc	1f ;				/* already active */	\
 ;									\
-	ISR_TRYLOCK ;		/* XXX this is going away... */		\
-	testl	%eax, %eax ;			/* did we get it? */	\
-	jz	1f ;				/* no */		\
+	ENLOCK ;							\
 ;									\
 	AVCPL_LOCK ;				/* MP-safe */		\
 	testl	$IRQ_BIT(irq_num), _cpl ;				\
@@ -242,6 +241,8 @@ IDTVEC(vec_name) ;							\
 ;									\
 	movl	$0, lapic_eoi ;			/* XXX too soon? */	\
 	incb	_intr_nesting_level ;					\
+;	 								\
+  /* entry point used by doreti_unpend for HWIs. */			\
 __CONCAT(Xresume,irq_num): ;						\
 	FAKE_MCOUNT(12*4(%esp)) ;		/* XXX avoid dbl cnt */ \
 	lock ;	incl	_cnt+V_INTR ;		/* tally interrupts */	\
@@ -256,15 +257,18 @@ __CONCAT(Xresume,irq_num): ;						\
 	AVCPL_UNLOCK ;							\
 ;									\
 	pushl	_intr_unit + (irq_num) * 4 ;				\
+	incl	_inside_intr ;						\
 	sti ;								\
 	call	*_intr_handler + (irq_num) * 4 ;			\
 	cli ;								\
+	decl	_inside_intr ;						\
 ;									\
 	lock ;	andl $~IRQ_BIT(irq_num), iactive ;			\
 	lock ;	andl $~IRQ_BIT(irq_num), _cil ;				\
 	UNMASK_IRQ(irq_num) ;						\
 	sti ;				/* doreti repeats cli/sti */	\
 	MEXITCOUNT ;							\
+	LATELOCK ;							\
 	jmp	_doreti ;						\
 ;									\
 	ALIGN_TEXT ;							\
@@ -282,14 +286,15 @@ __CONCAT(Xresume,irq_num): ;						\
 	ALIGN_TEXT ;							\
 2: ;						/* masked by cpl|cml */	\
 	AVCPL_UNLOCK ;							\
-	ISR_RELLOCK ;		/* XXX this is going away... */		\
+	DELOCK ;		/* XXX this is going away... */		\
 	jmp	1b
 
-#else /* INTR_SIMPLELOCK */
+#else /* CPL_AND_CML */
 
 #define	INTR(irq_num, vec_name)						\
 	.text ;								\
 	SUPERALIGN_TEXT ;						\
+/* _XintrNN: entry point used by IDT/HWIs & splz_unpend via _vec[]. */	\
 IDTVEC(vec_name) ;							\
 	PUSH_FRAME ;							\
 	movl	$KDSEL, %eax ;	/* reload with kernel's data segment */	\
@@ -311,6 +316,8 @@ IDTVEC(vec_name) ;							\
 ;									\
 	movl	$0, lapic_eoi ;			/* XXX too soon? */	\
 	incb	_intr_nesting_level ;					\
+;	 								\
+  /* entry point used by doreti_unpend for HWIs. */			\
 __CONCAT(Xresume,irq_num): ;						\
 	FAKE_MCOUNT(12*4(%esp)) ;		/* XXX avoid dbl cnt */ \
 	lock ;	incl	_cnt+V_INTR ;		/* tally interrupts */	\
@@ -353,7 +360,7 @@ __CONCAT(Xresume,irq_num): ;						\
 	ISR_RELLOCK ;		/* XXX this is going away... */		\
 	jmp	1b
 
-#endif /* INTR_SIMPLELOCK */
+#endif /* CPL_AND_CML */
 
 
 /*
@@ -487,14 +494,26 @@ MCOUNT_LABEL(bintr)
 MCOUNT_LABEL(eintr)
 
 	.data
-ihandlers:			/* addresses of interrupt handlers */
-				/* actually resumption addresses for HWI's */
+/*
+ * Addresses of interrupt handlers.
+ *  XresumeNN: Resumption addresses for HWIs.
+ */
+ihandlers:
+/*
+ * used by:
+ *  ipl.s:	doreti_unpend
+ */
 	.long	Xresume0,  Xresume1,  Xresume2,  Xresume3 
 	.long	Xresume4,  Xresume5,  Xresume6,  Xresume7
 	.long	Xresume8,  Xresume9,  Xresume10, Xresume11
 	.long	Xresume12, Xresume13, Xresume14, Xresume15 
 	.long	Xresume16, Xresume17, Xresume18, Xresume19
 	.long	Xresume20, Xresume21, Xresume22, Xresume23
+/*
+ * used by:
+ *  ipl.s:	doreti_unpend
+ *  apic_ipl.s:	splz_unpend
+ */
 	.long	swi_tty,   swi_net
 	.long	0, 0, 0, 0
 	.long	_softclock, swi_ast
@@ -506,6 +525,12 @@ imasks:				/* masks for interrupt handlers */
 	.long	0, 0, 0, 0
 	.long	SWI_CLOCK_MASK, SWI_AST_MASK
 
+/*
+ * IDT vector entry points for the HWIs.
+ *
+ * used by:
+ *   i386/isa/clock.c:		setup Xintr8254
+ */
 	.globl _ivectors
 _ivectors:
 	.long	_Xintr0,  _Xintr1,  _Xintr2,  _Xintr3 
diff --git a/sys/amd64/amd64/cpu_switch.S b/sys/amd64/amd64/cpu_switch.S
index c21ea8c..b83af08 100644
--- a/sys/amd64/amd64/cpu_switch.S
+++ b/sys/amd64/amd64/cpu_switch.S
@@ -33,7 +33,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: swtch.s,v 1.60 1997/08/26 18:10:33 peter Exp $
+ *	$Id: swtch.s,v 1.10 1997/09/07 21:50:13 smp Exp smp $
  */
 
 #include "npx.h"
@@ -300,6 +300,7 @@ idle_loop:
 
 	cmpl	$0,_do_page_zero_idle
 	je	2f
+
 	/* XXX appears to cause panics */
 	/*
 	 * Inside zero_idle we enable interrupts and grab the mplock
@@ -311,12 +312,18 @@ idle_loop:
 2:
 
 	/* enable intrs for a halt */
+#ifdef SMP
+	movl	$0, lapic_tpr			/* 1st candidate for an INT */
+#endif
 	sti
 	call	*_hlt_vector			/* wait for interrupt */
 	cli
 	jmp	idle_loop
 
 3:
+#ifdef SMP
+	movl	$LOPRIO_LEVEL, lapic_tpr	/* arbitrate for INTs */
+#endif
 	call	_get_mplock
 	cmpl	$0,_whichrtqs			/* real-time queue */
 	CROSSJUMP(jne, sw1a, je)
@@ -384,8 +391,8 @@ idle_loop:
 CROSSJUMPTARGET(_idle)
 
 ENTRY(default_halt)
-#ifndef SMP					/* until we have a wakeup IPI */
-	hlt
+#ifndef SMP
+	hlt					/* XXX:	 until a wakeup IPI */
 #endif
 	ret
 
diff --git a/sys/amd64/amd64/exception.S b/sys/amd64/amd64/exception.S
index 9a74ca1..1ed0f90 100644
--- a/sys/amd64/amd64/exception.S
+++ b/sys/amd64/amd64/exception.S
@@ -30,7 +30,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: exception.s,v 1.42 1997/08/29 18:16:17 fsmp Exp $
+ *	$Id: exception.s,v 1.22 1997/09/07 19:26:26 smp Exp smp $
  */
 
 #include "npx.h"				/* NNPX */
@@ -39,28 +39,23 @@
 #include <machine/psl.h>			/* PSL_I */
 #include <machine/trap.h>			/* trap codes */
 #include <machine/asmacros.h>
-#include <machine/smptests.h>			/* INTR_SIMPLELOCK */
-#include <machine/lock.h>
-
-#ifndef SMP
-#undef INTR_SIMPLELOCK				/* simplifies cpp tests */
-#undef REAL_ECPL
-#undef REAL_ICPL
-#undef REAL_AICPL
-#undef REAL_AVCPL
-#endif /* !SMP */
-
-#ifdef REAL_ECPL
-
-#define ECPL_LOCK	SCPL_LOCK
-#define ECPL_UNLOCK	SCPL_UNLOCK
-
-#else /* REAL_ECPL */
 
-#define ECPL_LOCK
+#ifdef SMP
+#include <machine/smptests.h>	/** CPL_AND_CML, REAL_ */
+#else
+#define ECPL_LOCK		/* make these nops */
 #define ECPL_UNLOCK
+#define ICPL_LOCK
+#define ICPL_UNLOCK
+#define FAST_ICPL_UNLOCK
+#define AICPL_LOCK
+#define AICPL_UNLOCK
+#define AVCPL_LOCK
+#define AVCPL_UNLOCK
+#endif /* SMP */
+
+#include <machine/lock.h>
 
-#endif /* REAL_ECPL */
 
 #define	KCSEL		0x08			/* kernel code selector */
 #define	KDSEL		0x10			/* kernel data selector */
@@ -161,7 +156,7 @@ IDTVEC(fpu)
 	MPLOCKED incl _cnt+V_TRAP
 	FPU_LOCK
 	ECPL_LOCK
-#ifdef INTR_SIMPLELOCK
+#ifdef CPL_AND_CML
 	movl	_cml,%eax
 	pushl	%eax			/* save original cml */
 	orl	$SWI_AST_MASK,%eax
@@ -171,7 +166,7 @@ IDTVEC(fpu)
 	pushl	%eax			/* save original cpl */
 	orl	$SWI_AST_MASK,%eax
 	movl	%eax,_cpl
-#endif /* INTR_SIMPLELOCK */
+#endif /* CPL_AND_CML */
 	ECPL_UNLOCK
 	pushl	$0			/* dummy unit to finish intr frame */
 #else /* SMP */
@@ -211,7 +206,7 @@ calltrap:
 	MPLOCKED incl _cnt+V_TRAP
 	ALIGN_LOCK
 	ECPL_LOCK
-#ifdef INTR_SIMPLELOCK
+#ifdef CPL_AND_CML
 	orl	$SWI_AST_MASK,_cml
 #else
 	orl	$SWI_AST_MASK,_cpl
@@ -236,11 +231,11 @@ calltrap:
 
 #ifdef SMP
 	ECPL_LOCK
-#ifdef INTR_SIMPLELOCK
+#ifdef CPL_AND_CML
 	pushl	_cml			/* XXX will this work??? */
 #else
 	pushl	_cpl
-#endif /* INTR_SIMPLELOCK */
+#endif
 	ECPL_UNLOCK
 	jmp	2f
 1:
@@ -288,7 +283,7 @@ IDTVEC(syscall)
 	MPLOCKED incl _cnt+V_SYSCALL
 	SYSCALL_LOCK
 	ECPL_LOCK
-#ifdef INTR_SIMPLELOCK
+#ifdef CPL_AND_CML
 	movl	$SWI_AST_MASK,_cml
 #else
 	movl	$SWI_AST_MASK,_cpl
@@ -322,7 +317,7 @@ IDTVEC(int0x80_syscall)
 	MPLOCKED incl _cnt+V_SYSCALL
 	ALTSYSCALL_LOCK
 	ECPL_LOCK
-#ifdef INTR_SIMPLELOCK
+#ifdef CPL_AND_CML
 	movl	$SWI_AST_MASK,_cml
 #else
 	movl	$SWI_AST_MASK,_cpl
diff --git a/sys/amd64/amd64/exception.s b/sys/amd64/amd64/exception.s
index 9a74ca1..1ed0f90 100644
--- a/sys/amd64/amd64/exception.s
+++ b/sys/amd64/amd64/exception.s
@@ -30,7 +30,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: exception.s,v 1.42 1997/08/29 18:16:17 fsmp Exp $
+ *	$Id: exception.s,v 1.22 1997/09/07 19:26:26 smp Exp smp $
  */
 
 #include "npx.h"				/* NNPX */
@@ -39,28 +39,23 @@
 #include <machine/psl.h>			/* PSL_I */
 #include <machine/trap.h>			/* trap codes */
 #include <machine/asmacros.h>
-#include <machine/smptests.h>			/* INTR_SIMPLELOCK */
-#include <machine/lock.h>
-
-#ifndef SMP
-#undef INTR_SIMPLELOCK				/* simplifies cpp tests */
-#undef REAL_ECPL
-#undef REAL_ICPL
-#undef REAL_AICPL
-#undef REAL_AVCPL
-#endif /* !SMP */
-
-#ifdef REAL_ECPL
-
-#define ECPL_LOCK	SCPL_LOCK
-#define ECPL_UNLOCK	SCPL_UNLOCK
-
-#else /* REAL_ECPL */
 
-#define ECPL_LOCK
+#ifdef SMP
+#include <machine/smptests.h>	/** CPL_AND_CML, REAL_ */
+#else
+#define ECPL_LOCK		/* make these nops */
 #define ECPL_UNLOCK
+#define ICPL_LOCK
+#define ICPL_UNLOCK
+#define FAST_ICPL_UNLOCK
+#define AICPL_LOCK
+#define AICPL_UNLOCK
+#define AVCPL_LOCK
+#define AVCPL_UNLOCK
+#endif /* SMP */
+
+#include <machine/lock.h>
 
-#endif /* REAL_ECPL */
 
 #define	KCSEL		0x08			/* kernel code selector */
 #define	KDSEL		0x10			/* kernel data selector */
@@ -161,7 +156,7 @@ IDTVEC(fpu)
 	MPLOCKED incl _cnt+V_TRAP
 	FPU_LOCK
 	ECPL_LOCK
-#ifdef INTR_SIMPLELOCK
+#ifdef CPL_AND_CML
 	movl	_cml,%eax
 	pushl	%eax			/* save original cml */
 	orl	$SWI_AST_MASK,%eax
@@ -171,7 +166,7 @@ IDTVEC(fpu)
 	pushl	%eax			/* save original cpl */
 	orl	$SWI_AST_MASK,%eax
 	movl	%eax,_cpl
-#endif /* INTR_SIMPLELOCK */
+#endif /* CPL_AND_CML */
 	ECPL_UNLOCK
 	pushl	$0			/* dummy unit to finish intr frame */
 #else /* SMP */
@@ -211,7 +206,7 @@ calltrap:
 	MPLOCKED incl _cnt+V_TRAP
 	ALIGN_LOCK
 	ECPL_LOCK
-#ifdef INTR_SIMPLELOCK
+#ifdef CPL_AND_CML
 	orl	$SWI_AST_MASK,_cml
 #else
 	orl	$SWI_AST_MASK,_cpl
@@ -236,11 +231,11 @@ calltrap:
 
 #ifdef SMP
 	ECPL_LOCK
-#ifdef INTR_SIMPLELOCK
+#ifdef CPL_AND_CML
 	pushl	_cml			/* XXX will this work??? */
 #else
 	pushl	_cpl
-#endif /* INTR_SIMPLELOCK */
+#endif
 	ECPL_UNLOCK
 	jmp	2f
 1:
@@ -288,7 +283,7 @@ IDTVEC(syscall)
 	MPLOCKED incl _cnt+V_SYSCALL
 	SYSCALL_LOCK
 	ECPL_LOCK
-#ifdef INTR_SIMPLELOCK
+#ifdef CPL_AND_CML
 	movl	$SWI_AST_MASK,_cml
 #else
 	movl	$SWI_AST_MASK,_cpl
@@ -322,7 +317,7 @@ IDTVEC(int0x80_syscall)
 	MPLOCKED incl _cnt+V_SYSCALL
 	ALTSYSCALL_LOCK
 	ECPL_LOCK
-#ifdef INTR_SIMPLELOCK
+#ifdef CPL_AND_CML
 	movl	$SWI_AST_MASK,_cml
 #else
 	movl	$SWI_AST_MASK,_cpl
diff --git a/sys/amd64/amd64/locore.S b/sys/amd64/amd64/locore.S
index a3df36f..432ab04 100644
--- a/sys/amd64/amd64/locore.S
+++ b/sys/amd64/amd64/locore.S
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)locore.s	7.3 (Berkeley) 5/13/91
- *	$Id: locore.s,v 1.95 1997/08/24 00:05:33 fsmp Exp $
+ *	$Id: locore.s,v 1.5 1997/09/02 04:38:32 smp Exp smp $
  *
  *		originally from: locore.s, by William F. Jolitz
  *
@@ -105,6 +105,7 @@
 	.globl	_cpuid,_curproc,_curpcb,_npxproc,_runtime,_cpu_lockid
 	.globl	_common_tss,_other_cpus,_my_idlePTD,_ss_tpr
 	.globl	_prv_CMAP1,_prv_CMAP2,_prv_CMAP3
+	.globl	_inside_intr
 	.set	_cpuid,_SMP_prvpage+0		/* [0] */
 	.set	_curproc,_SMP_prvpage+4		/* [1] */
 	.set	_curpcb,_SMP_prvpage+8		/* [2] */
@@ -118,7 +119,8 @@
 	.set	_prv_CMAP1,_SMP_prvpage+40	/* [10] */
 	.set	_prv_CMAP2,_SMP_prvpage+44	/* [11] */
 	.set	_prv_CMAP3,_SMP_prvpage+48	/* [12] */
-	.set	_common_tss,_SMP_prvpage+52	/* 102 (ie: 104) bytes long */
+	.set	_inside_intr,_SMP_prvpage+52	/* [13] */
+	.set	_common_tss,_SMP_prvpage+56	/* 102 (ie: 104) bytes long */
 
 /* Fetch the .set's for the local apic */
 #include "i386/i386/mp_apicdefs.s"
diff --git a/sys/amd64/amd64/locore.s b/sys/amd64/amd64/locore.s
index a3df36f..432ab04 100644
--- a/sys/amd64/amd64/locore.s
+++ b/sys/amd64/amd64/locore.s
@@ -34,7 +34,7 @@
  * SUCH DAMAGE.
  *
  *	from: @(#)locore.s	7.3 (Berkeley) 5/13/91
- *	$Id: locore.s,v 1.95 1997/08/24 00:05:33 fsmp Exp $
+ *	$Id: locore.s,v 1.5 1997/09/02 04:38:32 smp Exp smp $
  *
  *		originally from: locore.s, by William F. Jolitz
  *
@@ -105,6 +105,7 @@
 	.globl	_cpuid,_curproc,_curpcb,_npxproc,_runtime,_cpu_lockid
 	.globl	_common_tss,_other_cpus,_my_idlePTD,_ss_tpr
 	.globl	_prv_CMAP1,_prv_CMAP2,_prv_CMAP3
+	.globl	_inside_intr
 	.set	_cpuid,_SMP_prvpage+0		/* [0] */
 	.set	_curproc,_SMP_prvpage+4		/* [1] */
 	.set	_curpcb,_SMP_prvpage+8		/* [2] */
@@ -118,7 +119,8 @@
 	.set	_prv_CMAP1,_SMP_prvpage+40	/* [10] */
 	.set	_prv_CMAP2,_SMP_prvpage+44	/* [11] */
 	.set	_prv_CMAP3,_SMP_prvpage+48	/* [12] */
-	.set	_common_tss,_SMP_prvpage+52	/* 102 (ie: 104) bytes long */
+	.set	_inside_intr,_SMP_prvpage+52	/* [13] */
+	.set	_common_tss,_SMP_prvpage+56	/* 102 (ie: 104) bytes long */
 
 /* Fetch the .set's for the local apic */
 #include "i386/i386/mp_apicdefs.s"
diff --git a/sys/amd64/amd64/mp_machdep.c b/sys/amd64/amd64/mp_machdep.c
index 6b402b1..8d376ae 100644
--- a/sys/amd64/amd64/mp_machdep.c
+++ b/sys/amd64/amd64/mp_machdep.c
@@ -22,7 +22,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: mp_machdep.c,v 1.49 1997/08/31 03:17:47 fsmp Exp $
+ *	$Id: mp_machdep.c,v 1.38 1997/09/05 20:23:34 smp Exp smp $
  */
 
 #include "opt_smp.h"
@@ -195,14 +195,18 @@ typedef struct BASETABLE_ENTRY {
  */
 #define MP_BOOTADDRESS_POST	0x10
 #define MP_PROBE_POST		0x11
-#define MP_START_POST		0x12
-#define MP_ANNOUNCE_POST	0x13
-#define MPTABLE_PASS1_POST	0x14
+#define MPTABLE_PASS1_POST	0x12
+
+#define MP_START_POST		0x13
+#define MP_ENABLE_POST		0x14
 #define MPTABLE_PASS2_POST	0x15
-#define MP_ENABLE_POST		0x16
-#define START_ALL_APS_POST	0x17
-#define INSTALL_AP_TRAMP_POST	0x18
-#define START_AP_POST		0x19
+
+#define START_ALL_APS_POST	0x16
+#define INSTALL_AP_TRAMP_POST	0x17
+#define START_AP_POST		0x18
+
+#define MP_ANNOUNCE_POST	0x19
+
 
 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
 int	current_postcode;
@@ -1445,7 +1449,7 @@ default_mp_table(int type)
 /* critical region around IO APIC, apic_imen */
 struct simplelock	imen_lock;
 
-/* critical region around splxx(), cpl, cil, ipending */
+/* critical region around splxx(), cpl, cml, cil, ipending */
 struct simplelock	cpl_lock;
 
 /* Make FAST_INTR() routines sequential */
diff --git a/sys/amd64/amd64/mptable.c b/sys/amd64/amd64/mptable.c
index 6b402b1..8d376ae 100644
--- a/sys/amd64/amd64/mptable.c
+++ b/sys/amd64/amd64/mptable.c
@@ -22,7 +22,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: mp_machdep.c,v 1.49 1997/08/31 03:17:47 fsmp Exp $
+ *	$Id: mp_machdep.c,v 1.38 1997/09/05 20:23:34 smp Exp smp $
  */
 
 #include "opt_smp.h"
@@ -195,14 +195,18 @@ typedef struct BASETABLE_ENTRY {
  */
 #define MP_BOOTADDRESS_POST	0x10
 #define MP_PROBE_POST		0x11
-#define MP_START_POST		0x12
-#define MP_ANNOUNCE_POST	0x13
-#define MPTABLE_PASS1_POST	0x14
+#define MPTABLE_PASS1_POST	0x12
+
+#define MP_START_POST		0x13
+#define MP_ENABLE_POST		0x14
 #define MPTABLE_PASS2_POST	0x15
-#define MP_ENABLE_POST		0x16
-#define START_ALL_APS_POST	0x17
-#define INSTALL_AP_TRAMP_POST	0x18
-#define START_AP_POST		0x19
+
+#define START_ALL_APS_POST	0x16
+#define INSTALL_AP_TRAMP_POST	0x17
+#define START_AP_POST		0x18
+
+#define MP_ANNOUNCE_POST	0x19
+
 
 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
 int	current_postcode;
@@ -1445,7 +1449,7 @@ default_mp_table(int type)
 /* critical region around IO APIC, apic_imen */
 struct simplelock	imen_lock;
 
-/* critical region around splxx(), cpl, cil, ipending */
+/* critical region around splxx(), cpl, cml, cil, ipending */
 struct simplelock	cpl_lock;
 
 /* Make FAST_INTR() routines sequential */
diff --git a/sys/amd64/amd64/swtch.s b/sys/amd64/amd64/swtch.s
index c21ea8c..b83af08 100644
--- a/sys/amd64/amd64/swtch.s
+++ b/sys/amd64/amd64/swtch.s
@@ -33,7 +33,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: swtch.s,v 1.60 1997/08/26 18:10:33 peter Exp $
+ *	$Id: swtch.s,v 1.10 1997/09/07 21:50:13 smp Exp smp $
  */
 
 #include "npx.h"
@@ -300,6 +300,7 @@ idle_loop:
 
 	cmpl	$0,_do_page_zero_idle
 	je	2f
+
 	/* XXX appears to cause panics */
 	/*
 	 * Inside zero_idle we enable interrupts and grab the mplock
@@ -311,12 +312,18 @@ idle_loop:
 2:
 
 	/* enable intrs for a halt */
+#ifdef SMP
+	movl	$0, lapic_tpr			/* 1st candidate for an INT */
+#endif
 	sti
 	call	*_hlt_vector			/* wait for interrupt */
 	cli
 	jmp	idle_loop
 
 3:
+#ifdef SMP
+	movl	$LOPRIO_LEVEL, lapic_tpr	/* arbitrate for INTs */
+#endif
 	call	_get_mplock
 	cmpl	$0,_whichrtqs			/* real-time queue */
 	CROSSJUMP(jne, sw1a, je)
@@ -384,8 +391,8 @@ idle_loop:
 CROSSJUMPTARGET(_idle)
 
 ENTRY(default_halt)
-#ifndef SMP					/* until we have a wakeup IPI */
-	hlt
+#ifndef SMP
+	hlt					/* XXX:	 until a wakeup IPI */
 #endif
 	ret
 
diff --git a/sys/amd64/include/cpufunc.h b/sys/amd64/include/cpufunc.h
index df987bd..3b7eb9c 100644
--- a/sys/amd64/include/cpufunc.h
+++ b/sys/amd64/include/cpufunc.h
@@ -30,7 +30,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: cpufunc.h,v 1.2 1997/09/01 07:37:58 smp Exp smp $
+ *	$Id: cpufunc.h,v 1.3 1997/09/05 20:20:31 smp Exp smp $
  */
 
 /*
@@ -58,17 +58,13 @@ static __inline void
 disable_intr(void)
 {
 	__asm __volatile("cli" : : : "memory");
-#ifdef SMP
-	s_lock(&mpintr_lock);
-#endif
+	MPINTR_LOCK();
 }
 
 static __inline void
 enable_intr(void)
 {
-#ifdef SMP
-	s_unlock(&mpintr_lock);
-#endif
+	MPINTR_UNLOCK();
 	__asm __volatile("sti");
 }
 
diff --git a/sys/amd64/include/mptable.h b/sys/amd64/include/mptable.h
index 6b402b1..8d376ae 100644
--- a/sys/amd64/include/mptable.h
+++ b/sys/amd64/include/mptable.h
@@ -22,7 +22,7 @@
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
  *
- *	$Id: mp_machdep.c,v 1.49 1997/08/31 03:17:47 fsmp Exp $
+ *	$Id: mp_machdep.c,v 1.38 1997/09/05 20:23:34 smp Exp smp $
  */
 
 #include "opt_smp.h"
@@ -195,14 +195,18 @@ typedef struct BASETABLE_ENTRY {
  */
 #define MP_BOOTADDRESS_POST	0x10
 #define MP_PROBE_POST		0x11
-#define MP_START_POST		0x12
-#define MP_ANNOUNCE_POST	0x13
-#define MPTABLE_PASS1_POST	0x14
+#define MPTABLE_PASS1_POST	0x12
+
+#define MP_START_POST		0x13
+#define MP_ENABLE_POST		0x14
 #define MPTABLE_PASS2_POST	0x15
-#define MP_ENABLE_POST		0x16
-#define START_ALL_APS_POST	0x17
-#define INSTALL_AP_TRAMP_POST	0x18
-#define START_AP_POST		0x19
+
+#define START_ALL_APS_POST	0x16
+#define INSTALL_AP_TRAMP_POST	0x17
+#define START_AP_POST		0x18
+
+#define MP_ANNOUNCE_POST	0x19
+
 
 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
 int	current_postcode;
@@ -1445,7 +1449,7 @@ default_mp_table(int type)
 /* critical region around IO APIC, apic_imen */
 struct simplelock	imen_lock;
 
-/* critical region around splxx(), cpl, cil, ipending */
+/* critical region around splxx(), cpl, cml, cil, ipending */
 struct simplelock	cpl_lock;
 
 /* Make FAST_INTR() routines sequential */
diff --git a/sys/amd64/include/smp.h b/sys/amd64/include/smp.h
index a7051ff..82a6c34 100644
--- a/sys/amd64/include/smp.h
+++ b/sys/amd64/include/smp.h
@@ -6,7 +6,7 @@
  * this stuff is worth it, you can buy me a beer in return.   Poul-Henning Kamp
  * ----------------------------------------------------------------------------
  *
- * $Id: smp.h,v 1.30 1997/08/26 18:10:37 peter Exp $
+ * $Id: smp.h,v 1.27 1997/09/05 18:08:57 smp Exp smp $
  *
  */
 
@@ -167,6 +167,7 @@ extern volatile int		smp_idle_loops;
 /* 'private' global data in locore.s */
 extern volatile u_int		cpuid;
 extern volatile u_int		cpu_lockid;
+extern int			inside_intr;
 extern volatile u_int		other_cpus;
 
 #endif /* !LOCORE */