summaryrefslogtreecommitdiffstats
path: root/sys/amd64
diff options
context:
space:
mode:
authoranish <anish@FreeBSD.org>2016-04-11 05:09:43 +0000
committeranish <anish@FreeBSD.org>2016-04-11 05:09:43 +0000
commit3d3fd1fdc947b21f5c141f4fe17f9e26b0bcd592 (patch)
tree45dabfbe72618cbf6867f69c5aabf4c4d0b7c34f /sys/amd64
parent7e6f8b31670ae92494f9510a48d7d589492dec6a (diff)
downloadFreeBSD-src-3d3fd1fdc947b21f5c141f4fe17f9e26b0bcd592.zip
FreeBSD-src-3d3fd1fdc947b21f5c141f4fe17f9e26b0bcd592.tar.gz
Allow guest writes to AMD microcode update[0xc0010020] MSR without updating actual hardware MSR. This allows guest microcode update to go through which otherwise failing because wrmsr() was returning EINVAL.
Submitted by:Yamagi Burmeister Approved by:grehan MFC after:2 weeks
Diffstat (limited to 'sys/amd64')
-rw-r--r--sys/amd64/vmm/amd/svm_msr.c5
1 files changed, 5 insertions, 0 deletions
diff --git a/sys/amd64/vmm/amd/svm_msr.c b/sys/amd64/vmm/amd/svm_msr.c
index 088751a..49208a3 100644
--- a/sys/amd64/vmm/amd/svm_msr.c
+++ b/sys/amd64/vmm/amd/svm_msr.c
@@ -156,6 +156,11 @@ svm_wrmsr(struct svm_softc *sc, int vcpu, u_int num, uint64_t val, bool *retu)
* Ignore writes to the "Interrupt Pending Message" MSR.
*/
break;
+ case MSR_K8_UCODE_UPDATE:
+ /*
+ * Ignore writes to microcode update register.
+ */
+ break;
default:
error = EINVAL;
break;
OpenPOWER on IntegriCloud