Add support for level triggered interrupt pins on the vioapic. Prior to this

commit level triggered interrupts would work as long as the pin was not shared
among multiple interrupt sources.

The vlapic now keeps track of level triggered interrupts in the trigger mode
register and will forward the EOI for a level triggered interrupt to the
vioapic. The vioapic in turn uses the EOI to sample the level on the pin and
re-inject the vector if the pin is still asserted.

The vhpet is the first consumer of level triggered interrupts and advertises
that it can generate interrupts on pins 20 through 23 of the vioapic.

Discussed with:	grehan@

1 files changed, 2 insertions, 2 deletions

diff --git a/sys/amd64/vmm/vmm_lapic.c b/sys/amd64/vmm/vmm_lapic.c
index b893ba4..465ce6c 100644
--- a/sys/amd64/vmm/vmm_lapic.c
+++ b/sys/amd64/vmm/vmm_lapic.c
@@ -62,7 +62,7 @@ lapic_intr_accepted(struct vm *vm, int cpu, int vector)
 }
 
 int
-lapic_set_intr(struct vm *vm, int cpu, int vector)
+lapic_set_intr(struct vm *vm, int cpu, int vector, bool level)
 {
 	struct vlapic *vlapic;
 
@@ -73,7 +73,7 @@ lapic_set_intr(struct vm *vm, int cpu, int vector)
 		return (EINVAL);
 
 	vlapic = vm_lapic(vm, cpu);
-	vlapic_set_intr_ready(vlapic, vector);
+	vlapic_set_intr_ready(vlapic, vector, level);
 
 	vm_interrupt_hostcpu(vm, cpu);