diff options
| author | alc <alc@FreeBSD.org> | 2010-03-21 00:13:11 +0000 |
|---|---|---|
| committer | alc <alc@FreeBSD.org> | 2010-03-21 00:13:11 +0000 |
| commit | 981be7060a50fc3283304bf2c4ab88ee9e679f6e (patch) | |
| tree | 1360a983c6502688b8cc951729675937b04b1bb3 /sys/amd64/include/specialreg.h | |
| parent | 2ee5d540fc032220b0c49219efe13687e3cd7c14 (diff) | |
| download | FreeBSD-src-981be7060a50fc3283304bf2c4ab88ee9e679f6e.zip FreeBSD-src-981be7060a50fc3283304bf2c4ab88ee9e679f6e.tar.gz | |
I am told by AMD that the machine check hardware on the instruction TLB
won't generate bogus exceptions. Therefore, the implementation of the
"unofficial" workaround needn't mask L1TP errors by the instruction cache
unit.
Diffstat (limited to 'sys/amd64/include/specialreg.h')
| -rw-r--r-- | sys/amd64/include/specialreg.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/sys/amd64/include/specialreg.h b/sys/amd64/include/specialreg.h index baf2466..ed54f0d 100644 --- a/sys/amd64/include/specialreg.h +++ b/sys/amd64/include/specialreg.h @@ -507,7 +507,6 @@ #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ #define MSR_MC0_CTL_MASK 0xc0010044 -#define MSR_MC1_CTL_MASK 0xc0010045 /* VIA ACE crypto featureset: for via_feature_rng */ #define VIA_HAS_RNG 1 /* cpu has RNG */ |
