- Extend the machine check record structure to include several fields useful

  for parsing model-specific and other fields in machine check events
  including the global machine check capabilities and status registers,
  CPU identification, and the FreeBSD CPU ID.
- Report these added fields in the console log of a machine check so that
  a record structure can be reconstituted from the console messages.
- Parse new architectural errors including memory controller errors.

MFC after:	1 week

1 files changed, 12 insertions, 0 deletions

diff --git a/sys/amd64/include/specialreg.h b/sys/amd64/include/specialreg.h
index b325ed4..baf2466 100644
--- a/sys/amd64/include/specialreg.h
+++ b/sys/amd64/include/specialreg.h
@@ -267,6 +267,7 @@
 #define	MSR_MTRR16kBase		0x258
 #define	MSR_MTRR4kBase		0x268
 #define	MSR_PAT			0x277
+#define	MSR_MC0_CTL2		0x280
 #define	MSR_MTRRdefType		0x2ff
 #define	MSR_MC0_CTL		0x400
 #define	MSR_MC0_STATUS		0x401
@@ -352,8 +353,10 @@
 #define	MCG_CAP_COUNT		0x000000ff
 #define	MCG_CAP_CTL_P		0x00000100
 #define	MCG_CAP_EXT_P		0x00000200
+#define	MCG_CAP_CMCI_P		0x00000400
 #define	MCG_CAP_TES_P		0x00000800
 #define	MCG_CAP_EXT_CNT		0x00ff0000
+#define	MCG_CAP_SER_P		0x01000000
 #define	MCG_STATUS_RIPV		0x00000001
 #define	MCG_STATUS_EIPV		0x00000002
 #define	MCG_STATUS_MCIP		0x00000004
@@ -363,9 +366,14 @@
 #define	MSR_MC_STATUS(x)	(MSR_MC0_STATUS + (x) * 4)
 #define	MSR_MC_ADDR(x)		(MSR_MC0_ADDR + (x) * 4)
 #define	MSR_MC_MISC(x)		(MSR_MC0_MISC + (x) * 4)
+#define	MSR_MC_CTL2(x)		(MSR_MC0_CTL2 + (x))	/* If MCG_CAP_CMCI_P */
 #define	MC_STATUS_MCA_ERROR	0x000000000000ffffUL
 #define	MC_STATUS_MODEL_ERROR	0x00000000ffff0000UL
 #define	MC_STATUS_OTHER_INFO	0x01ffffff00000000UL
+#define	MC_STATUS_COR_COUNT	0x001fffc000000000UL	/* If MCG_CAP_TES_P */
+#define	MC_STATUS_TES_STATUS	0x0060000000000000UL	/* If MCG_CAP_TES_P */
+#define	MC_STATUS_AR		0x0080000000000000UL	/* If MCG_CAP_CMCI_P */
+#define	MC_STATUS_S		0x0100000000000000UL	/* If MCG_CAP_CMCI_P */
 #define	MC_STATUS_PCC		0x0200000000000000UL
 #define	MC_STATUS_ADDRV		0x0400000000000000UL
 #define	MC_STATUS_MISCV		0x0800000000000000UL
@@ -373,6 +381,10 @@
 #define	MC_STATUS_UC		0x2000000000000000UL
 #define	MC_STATUS_OVER		0x4000000000000000UL
 #define	MC_STATUS_VAL		0x8000000000000000UL
+#define	MC_MISC_RA_LSB		0x000000000000003fUL	/* If MCG_CAP_SER_P */
+#define	MC_MISC_ADDRESS_MODE	0x00000000000001c0UL	/* If MCG_CAP_SER_P */
+#define	MC_CTL2_THRESHOLD	0x0000000000003fffUL
+#define	MC_CTL2_CMCI_EN		0x0000000040000000UL
 
 /*
  * The following four 3-byte registers control the non-cacheable regions.