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| author | jhb <jhb@FreeBSD.org> | 2008-03-12 22:09:19 +0000 |
|---|---|---|
| committer | jhb <jhb@FreeBSD.org> | 2008-03-12 22:09:19 +0000 |
| commit | 4aef4283ee40fa60ed50fb989bab0c8cef7c0388 (patch) | |
| tree | b78c9ec05ed6a1f16731030f669f0a2ee540e28d /sys/amd64/include/specialreg.h | |
| parent | 93c9f42d65475a08409d00ff4a6a78f033f6d611 (diff) | |
| download | FreeBSD-src-4aef4283ee40fa60ed50fb989bab0c8cef7c0388.zip FreeBSD-src-4aef4283ee40fa60ed50fb989bab0c8cef7c0388.tar.gz | |
The variable MTRR registers actually have variable-sized PhysBase and
PhysMask fields based on the number of physical address bits supported
by the current CPU. The old code assumed 36 bits on i386 and 40 bits on
amd64. In truth, all Intel CPUs up until recently used 36 bits (a newer
Intel CPU uses 38 bits) and all the Opteron CPUs used 40 bits.
In at least one case (the new Intel CPU) having the size of the mask field
wrong resulted in writing questionable values into the MTRR registers on
the application processors (BSP as well if you modify the MTRRs via
memcontrol or running X, etc.). The result of the questionable physmask
was that all of memory was apparently treated as uncached rather than
write-back resulting in a very significant performance hit.
Fix this by constructing a run-time mask for the PhysBase and PhysMask
fields based on the number of physical address bits supported by the CPU.
All 64-bit capable CPUs provide a count of PA bits supported via the
0x80000008 extended CPUID feature, so use that if it is available. If that
feature is not available, then assume 36 PA bits.
While I'm here, expand the (now-unused) macros for the PhysBase and
PhysMask fields to the current largest possible value (52 PA bits).
MFC after: 1 week
PR: i386/120516
Reported by: Nokia
Diffstat (limited to 'sys/amd64/include/specialreg.h')
| -rw-r--r-- | sys/amd64/include/specialreg.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/sys/amd64/include/specialreg.h b/sys/amd64/include/specialreg.h index 94d70ad..760d2c5 100644 --- a/sys/amd64/include/specialreg.h +++ b/sys/amd64/include/specialreg.h @@ -275,9 +275,9 @@ #define MTRR_DEF_ENABLE 0x0000000000000800UL #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400UL #define MTRR_DEF_TYPE 0x00000000000000ffUL -#define MTRR_PHYSBASE_PHYSBASE 0x000000fffffff000UL +#define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000UL #define MTRR_PHYSBASE_TYPE 0x00000000000000ffUL -#define MTRR_PHYSMASK_PHYSMASK 0x000000fffffff000UL +#define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000UL #define MTRR_PHYSMASK_VALID 0x0000000000000800UL /* Performance Control Register (5x86 only). */ |
