diff options
author | kato <kato@FreeBSD.org> | 1997-10-06 08:08:41 +0000 |
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committer | kato <kato@FreeBSD.org> | 1997-10-06 08:08:41 +0000 |
commit | 41003c48a0572c7408eb9ab22609681bb53181df (patch) | |
tree | 3ed8e6edb25b7c08458c3399f4645c3a4f74a903 /sys/amd64/amd64 | |
parent | de4b9bfa6f761f108512d7fcc71f5560e730b8e3 (diff) | |
download | FreeBSD-src-41003c48a0572c7408eb9ab22609681bb53181df.zip FreeBSD-src-41003c48a0572c7408eb9ab22609681bb53181df.tar.gz |
Added two Cyrix 6x86/6x86MX options.
- CPU_CYRIX_NO_LOCK enables weak locking. If this option is not set and
FAILESAFE is defined, NO_LOCK bit of CCR1 is cleared.
- CPU_WT_ALLOC enables write-through allocation.
Diffstat (limited to 'sys/amd64/amd64')
-rw-r--r-- | sys/amd64/amd64/initcpu.c | 42 |
1 files changed, 35 insertions, 7 deletions
diff --git a/sys/amd64/amd64/initcpu.c b/sys/amd64/amd64/initcpu.c index 5ed426d..077aa31 100644 --- a/sys/amd64/amd64/initcpu.c +++ b/sys/amd64/amd64/initcpu.c @@ -26,7 +26,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $Id: initcpu.c,v 1.6 1997/06/27 13:46:19 kato Exp $ + * $Id: initcpu.c,v 1.7 1997/07/24 14:19:25 kato Exp $ */ #include "opt_cpu.h" @@ -304,6 +304,15 @@ init_6x86(void) /* Initialize CCR0. */ write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); + /* Initialize CCR1. */ +#ifdef CPU_CYRIX_NO_LOCK + write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR1_NO_LOCK); +#else +#ifdef FAILSAFE + write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) & ~CCR1_NO_LOCK); +#endif +#endif + /* Initialize CCR2. */ #ifdef CPU_SUSP_HLT write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); @@ -324,6 +333,11 @@ init_6x86(void) write_cyrix_reg(CCR4, ccr4 | 7); #endif + /* Initialize CCR5. */ +#ifdef CPU_WT_ALLOC + write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); +#endif + /* Restore CCR3. */ write_cyrix_reg(CCR3, ccr3); @@ -373,6 +387,15 @@ init_6x86MX(void) /* Initialize CCR0. */ write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); + /* Initialize CCR1. */ +#ifdef CPU_CYRIX_NO_LOCK + write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR1_NO_LOCK); +#else +#ifdef FAILSAFE + write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) & ~CCR1_NO_LOCK); +#endif +#endif + /* Initialize CCR2. */ #ifdef CPU_SUSP_HLT write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); @@ -392,6 +415,11 @@ init_6x86MX(void) write_cyrix_reg(CCR4, ccr4 | 7); #endif + /* Initialize CCR5. */ +#ifdef CPU_WT_ALLOC + write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); +#endif + /* Restore CCR3. */ write_cyrix_reg(CCR3, ccr3); @@ -506,10 +534,10 @@ DB_SHOW_COMMAND(cyrixreg, cyrixreg) ccr1 = read_cyrix_reg(CCR1); ccr2 = read_cyrix_reg(CCR2); ccr3 = read_cyrix_reg(CCR3); - if ((cpu == CPU_M1SC) || (cpu == CPU_M1)) { + if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { write_cyrix_reg(CCR3, CCR3_MAPEN0); ccr4 = read_cyrix_reg(CCR4); - if (cpu == CPU_M1) + if ((cpu == CPU_M1) || (cpu == CPU_M2)) ccr5 = read_cyrix_reg(CCR5); else pcr0 = read_cyrix_reg(PCR0); @@ -522,12 +550,12 @@ DB_SHOW_COMMAND(cyrixreg, cyrixreg) printf("CCR1=%x, CCR2=%x, CCR3=%x", (u_int)ccr1, (u_int)ccr2, (u_int)ccr3); - if ((cpu == CPU_M1SC) || (cpu == CPU_M1)) { + if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { printf(", CCR4=%x, ", (u_int)ccr4); - if (cpu == CPU_M1) - printf("CCR5=%x\n", ccr5); - else + if (cpu == CPU_M1SC) printf("PCR0=%x\n", pcr0); + else + printf("CCR5=%x\n", ccr5); } } printf("CR0=%x\n", cr0); |