diff options
| author | jhb <jhb@FreeBSD.org> | 2011-01-13 17:00:22 +0000 |
|---|---|---|
| committer | jhb <jhb@FreeBSD.org> | 2011-01-13 17:00:22 +0000 |
| commit | cfd16f712573032be1fa07106485eb0667fa7411 (patch) | |
| tree | bfa614e1497554b75209bc2819f61899041b525b /sys/amd64/amd64/apic_vector.S | |
| parent | d0e4f29150b70c6db15b3bb2245e00de82a7cb7d (diff) | |
| download | FreeBSD-src-cfd16f712573032be1fa07106485eb0667fa7411.zip FreeBSD-src-cfd16f712573032be1fa07106485eb0667fa7411.tar.gz | |
If an interrupt on an I/O APIC is moved to a different CPU after it has
started to execute, it seems that the corresponding ISR bit in the "old"
local APIC can be cleared. This causes the local APIC interrupt routine
to fail to find an interrupt to service. Rather than panic'ing in this
case, simply return from the interrupt without sending an EOI to the
local APIC. If there are any other pending interrupts in other ISR
registers, the local APIC will assert a new interrupt.
Tested by: steve
Diffstat (limited to 'sys/amd64/amd64/apic_vector.S')
| -rw-r--r-- | sys/amd64/amd64/apic_vector.S | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/sys/amd64/amd64/apic_vector.S b/sys/amd64/amd64/apic_vector.S index e4c4ddf..96c778d 100644 --- a/sys/amd64/amd64/apic_vector.S +++ b/sys/amd64/amd64/apic_vector.S @@ -58,17 +58,15 @@ IDTVEC(vec_name) ; \ FAKE_MCOUNT(TF_RIP(%rsp)) ; \ movq lapic, %rdx ; /* pointer to local APIC */ \ movl LA_ISR + 16 * (index)(%rdx), %eax ; /* load ISR */ \ - bsrl %eax, %eax ; /* index of highset set bit in ISR */ \ - jz 2f ; \ + bsrl %eax, %eax ; /* index of highest set bit in ISR */ \ + jz 1f ; \ addl $(32 * index),%eax ; \ -1: ; \ movq %rsp, %rsi ; \ movl %eax, %edi ; /* pass the IRQ */ \ call lapic_handle_intr ; \ +1: ; \ MEXITCOUNT ; \ - jmp doreti ; \ -2: movl $-1, %eax ; /* send a vector of -1 */ \ - jmp 1b + jmp doreti /* * Handle "spurious INTerrupts". |
