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author | joel <joel@FreeBSD.org> | 2012-06-05 17:58:47 +0000 |
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committer | joel <joel@FreeBSD.org> | 2012-06-05 17:58:47 +0000 |
commit | f601773fa58f10f5afbef32e29f83af547b14267 (patch) | |
tree | 9082601884e02f4e09e3905c31df29cadd7790d4 /share/man/man4/bce.4 | |
parent | 6258379f2fd986e41963e0c841c6ce0b5c8f14ef (diff) | |
download | FreeBSD-src-f601773fa58f10f5afbef32e29f83af547b14267.zip FreeBSD-src-f601773fa58f10f5afbef32e29f83af547b14267.tar.gz |
Remove end of line whitespace.
Diffstat (limited to 'share/man/man4/bce.4')
-rw-r--r-- | share/man/man4/bce.4 | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/share/man/man4/bce.4 b/share/man/man4/bce.4 index 869b1da..28fdf6a 100644 --- a/share/man/man4/bce.4 +++ b/share/man/man4/bce.4 @@ -213,57 +213,57 @@ Enable/Disable strict RX frame size checking (default 0). Enable/Disable frame header/payload splitting (default 1). .It Va hw.bce.rx_pages Set the number of memory pages assigned to recieve packets by the driver. -Due to alignment issues, this value can only be of the set +Due to alignment issues, this value can only be of the set 1, 2, 4 or 8 (default 2). .It Va hw.bce.tx_pages -Set the number of memory pages assigned to transmit packets +Set the number of memory pages assigned to transmit packets by the driver. -Due to alignment issues, this value can only be of the set +Due to alignment issues, this value can only be of the set 1, 2, 4 or 8 (default 2). .It Va hw.bce.rx_ticks -Time in microsecond ticks to wait before generating a status +Time in microsecond ticks to wait before generating a status block updates due to RX processing activity. Values from 0-100 are valid. A value of 0 disables this status block update. -Cannot be set to 0 if hw.bce.rx_quick_cons_trip is also 0 +Cannot be set to 0 if hw.bce.rx_quick_cons_trip is also 0 (default 18). .It Va hw.bce.rx_ticks_int -Time in microsecond ticks to wait during RX interrupt +Time in microsecond ticks to wait during RX interrupt processing before generating a status block update. Values from 0-100 are valid. Valid values are in the range from 0-100. A value of 0 disables this status block update (default 18). .It Va hw.bce.rx_quick_cons_trip -Number of RX Quick BD Chain entries that must be completed +Number of RX Quick BD Chain entries that must be completed before a status block is generated. Values from 0-256 are valid. A value of 0 disables this status block update. Cannot be set to 0 if hw.bce.rx_ticks is also 0 (default 6). .It Va hw.bce.rx_quick_cons_trip_int -Number of RX quick BD entries that must be completed before +Number of RX quick BD entries that must be completed before a status block is generated duing interrupt processing. Values from 0-256 are valid. A value of 0 disables this status block update (default 6). .It Va hw.bce.tx_ticks -Time in microsecond ticks to wait before a status block +Time in microsecond ticks to wait before a status block update is generated due to TX activitiy. Values from 0-100 are valid. A value of 0 disables this status block update. -Cannot be set to 0 if hw.bce.tx_quick_cons_trip is also 0 +Cannot be set to 0 if hw.bce.tx_quick_cons_trip is also 0 (default 80). .It Va hw.bce.tx_ticks_int -Time in microsecond ticks to wait in interrupt processing +Time in microsecond ticks to wait in interrupt processing before a status block update is generated due to TX activity Values from 0-100 are valid. A value of 0 disables this status block update (default 80). .It Va hw.bce.tx_cons_trip -How many TX Quick BD Chain entries that must be completed +How many TX Quick BD Chain entries that must be completed before a status block is generated. Values from 0-100 are valid. A value of 0 disables this status block update. Cannot be set to 0 if hw.bce.tx_ticks is also 0 (default 20). .It Va hw.bce.tx_cons_trip_int -How many TX Quick BD Chain entries that must be completed +How many TX Quick BD Chain entries that must be completed before a status block is generated during an interrupt. Values from 0-100 are valid. A value of 0 disables this status block update (default 20). |