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authorrdivacky <rdivacky@FreeBSD.org>2010-03-03 17:27:15 +0000
committerrdivacky <rdivacky@FreeBSD.org>2010-03-03 17:27:15 +0000
commit8230c40430a1325b5cc5bc0221931487b4bd573c (patch)
tree836a05cff50ca46176117b86029f061fa4db54f0 /docs/CommandGuide/lli.pod
parentf25ddd991a5601d0101602c4c263a58c7af4b8a2 (diff)
downloadFreeBSD-src-8230c40430a1325b5cc5bc0221931487b4bd573c.zip
FreeBSD-src-8230c40430a1325b5cc5bc0221931487b4bd573c.tar.gz
Update LLVM to 97654.
Diffstat (limited to 'docs/CommandGuide/lli.pod')
-rw-r--r--docs/CommandGuide/lli.pod6
1 files changed, 3 insertions, 3 deletions
diff --git a/docs/CommandGuide/lli.pod b/docs/CommandGuide/lli.pod
index e9fdf74..6d1e1c6 100644
--- a/docs/CommandGuide/lli.pod
+++ b/docs/CommandGuide/lli.pod
@@ -73,7 +73,7 @@ architecture which is not compatible with the current system.
=item B<-march>=I<arch>
Specify the architecture for which to generate assembly, overriding the target
-encoded in the bitcode file. See the output of B<llc --help> for a list of
+encoded in the bitcode file. See the output of B<llc -help> for a list of
valid architectures. By default this is inferred from the target triple or
autodetected to the current architecture.
@@ -170,7 +170,7 @@ Instruction schedulers available (before register allocation):
=item B<-regalloc>=I<allocator>
-Register allocator to use: (default = linearscan)
+Register allocator to use (default=linearscan)
=bigblock: Big-block register allocator
=linearscan: linear scan register allocator =local - local register allocator
@@ -186,7 +186,7 @@ Choose relocation model from:
=item B<-spiller>
-Spiller to use: (default: local)
+Spiller to use (default=local)
=simple: simple spiller
=local: local spiller
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