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| author | dim <dim@FreeBSD.org> | 2012-05-03 16:50:55 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2012-05-03 16:50:55 +0000 |
| commit | 2c5e9d71aba3b1a85f07c08d2c09d40b8547264b (patch) | |
| tree | 8575c732129e272992ac5d7b4c2519238fff4735 /docs/CodeGenerator.html | |
| parent | 1fc08f5e9ef733ef1ce6f363fecedc2260e78974 (diff) | |
| download | FreeBSD-src-2c5e9d71aba3b1a85f07c08d2c09d40b8547264b.zip FreeBSD-src-2c5e9d71aba3b1a85f07c08d2c09d40b8547264b.tar.gz | |
Vendor import of llvm release_31 branch r155985:
http://llvm.org/svn/llvm-project/llvm/branches/release_31@155985
Diffstat (limited to 'docs/CodeGenerator.html')
| -rw-r--r-- | docs/CodeGenerator.html | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index a37c3dc..2dc22c1 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -1617,9 +1617,9 @@ def : Pat<(i32 imm:$imm), range from 1 to 1023. To see how this numbering is defined for a particular architecture, you can read the <tt>GenRegisterNames.inc</tt> file for that architecture. For instance, by - inspecting <tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the - 32-bit register <tt>EAX</tt> is denoted by 15, and the MMX register - <tt>MM0</tt> is mapped to 48.</p> + inspecting <tt>lib/Target/X86/X86GenRegisterInfo.inc</tt> we see that the + 32-bit register <tt>EAX</tt> is denoted by 43, and the MMX register + <tt>MM0</tt> is mapped to 65.</p> <p>Some architectures contain registers that share the same physical location. A notable example is the X86 platform. For instance, in the X86 architecture, @@ -1627,7 +1627,7 @@ def : Pat<(i32 imm:$imm), bits. These physical registers are marked as <i>aliased</i> in LLVM. Given a particular architecture, you can check which registers are aliased by inspecting its <tt>RegisterInfo.td</tt> file. Moreover, the method - <tt>TargetRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing + <tt>MCRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing all the physical registers aliased to the register <tt>p_reg</tt>.</p> <p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>. @@ -3182,7 +3182,7 @@ MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory <a href="mailto:sabre@nondot.org">Chris Lattner</a><br> <a href="http://llvm.org/">The LLVM Compiler Infrastructure</a><br> - Last modified: $Date: 2012-03-27 13:25:16 +0200 (Tue, 27 Mar 2012) $ + Last modified: $Date: 2012-04-15 22:22:36 +0200 (Sun, 15 Apr 2012) $ </address> </body> |
