From 2c5e9d71aba3b1a85f07c08d2c09d40b8547264b Mon Sep 17 00:00:00 2001 From: dim Date: Thu, 3 May 2012 16:50:55 +0000 Subject: Vendor import of llvm release_31 branch r155985: http://llvm.org/svn/llvm-project/llvm/branches/release_31@155985 --- docs/CodeGenerator.html | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) (limited to 'docs/CodeGenerator.html') diff --git a/docs/CodeGenerator.html b/docs/CodeGenerator.html index a37c3dc..2dc22c1 100644 --- a/docs/CodeGenerator.html +++ b/docs/CodeGenerator.html @@ -1617,9 +1617,9 @@ def : Pat<(i32 imm:$imm), range from 1 to 1023. To see how this numbering is defined for a particular architecture, you can read the GenRegisterNames.inc file for that architecture. For instance, by - inspecting lib/Target/X86/X86GenRegisterNames.inc we see that the - 32-bit register EAX is denoted by 15, and the MMX register - MM0 is mapped to 48.

+ inspecting lib/Target/X86/X86GenRegisterInfo.inc we see that the + 32-bit register EAX is denoted by 43, and the MMX register + MM0 is mapped to 65.

Some architectures contain registers that share the same physical location. A notable example is the X86 platform. For instance, in the X86 architecture, @@ -1627,7 +1627,7 @@ def : Pat<(i32 imm:$imm), bits. These physical registers are marked as aliased in LLVM. Given a particular architecture, you can check which registers are aliased by inspecting its RegisterInfo.td file. Moreover, the method - TargetRegisterInfo::getAliasSet(p_reg) returns an array containing + MCRegisterInfo::getAliasSet(p_reg) returns an array containing all the physical registers aliased to the register p_reg.

Physical registers, in LLVM, are grouped in Register Classes. @@ -3182,7 +3182,7 @@ MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory Chris Lattner
The LLVM Compiler Infrastructure
- Last modified: $Date: 2012-03-27 13:25:16 +0200 (Tue, 27 Mar 2012) $ + Last modified: $Date: 2012-04-15 22:22:36 +0200 (Sun, 15 Apr 2012) $ -- cgit v1.1