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authordim <dim@FreeBSD.org>2014-02-24 21:48:03 +0000
committerdim <dim@FreeBSD.org>2014-02-24 21:48:03 +0000
commit4d6ab5a180da9145c9f83969f100917669704d88 (patch)
tree58c8e8105f1121e6200f6ce6be429905aa247ee8 /contrib/llvm
parente42ec49846c3cc1c4e569ef2fe94c6a98409dee1 (diff)
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Pull in r202059 from upstream clang trunk (by Roman Divacky):
Implement getDwarfEHStackPointer() and initDwarfEHRegSizeTable() for sparcv9. Enables the libgcc-specific undocumented __builtin_dwarf_sp_column() and __builtin_init_dwarf_reg_size_table() builtins to be compiled for sparc64.
Diffstat (limited to 'contrib/llvm')
-rw-r--r--contrib/llvm/tools/clang/lib/CodeGen/TargetInfo.cpp41
1 files changed, 41 insertions, 0 deletions
diff --git a/contrib/llvm/tools/clang/lib/CodeGen/TargetInfo.cpp b/contrib/llvm/tools/clang/lib/CodeGen/TargetInfo.cpp
index 578cea6..45eaec6 100644
--- a/contrib/llvm/tools/clang/lib/CodeGen/TargetInfo.cpp
+++ b/contrib/llvm/tools/clang/lib/CodeGen/TargetInfo.cpp
@@ -5435,9 +5435,50 @@ class SparcV9TargetCodeGenInfo : public TargetCodeGenInfo {
public:
SparcV9TargetCodeGenInfo(CodeGenTypes &CGT)
: TargetCodeGenInfo(new SparcV9ABIInfo(CGT)) {}
+
+ int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const {
+ return 14;
+ }
+
+ bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
+ llvm::Value *Address) const;
};
} // end anonymous namespace
+bool
+SparcV9TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
+ llvm::Value *Address) const {
+ // This is calculated from the LLVM and GCC tables and verified
+ // against gcc output. AFAIK all ABIs use the same encoding.
+
+ CodeGen::CGBuilderTy &Builder = CGF.Builder;
+
+ llvm::IntegerType *i8 = CGF.Int8Ty;
+ llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
+ llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
+
+ // 0-31: the 8-byte general-purpose registers
+ AssignToArrayRange(Builder, Address, Eight8, 0, 31);
+
+ // 32-63: f0-31, the 4-byte floating-point registers
+ AssignToArrayRange(Builder, Address, Four8, 32, 63);
+
+ // Y = 64
+ // PSR = 65
+ // WIM = 66
+ // TBR = 67
+ // PC = 68
+ // NPC = 69
+ // FSR = 70
+ // CSR = 71
+ AssignToArrayRange(Builder, Address, Eight8, 64, 71);
+
+ // 72-87: d0-15, the 8-byte floating-point registers
+ AssignToArrayRange(Builder, Address, Eight8, 72, 87);
+
+ return false;
+}
+
//===----------------------------------------------------------------------===//
// Xcore ABI Implementation
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