Merge clang, llvm, lld, lldb, compiler-rt and libc++ 5.0.0 release.

MFC r309126 (by emaste):

  Correct lld llvm-tblgen dependency file name

MFC r309169:

  Get rid of separate Subversion mergeinfo properties for llvm-dwarfdump
  and llvm-lto.  The mergeinfo confuses Subversion enormously, and these
  directories will just use the mergeinfo for llvm itself.

MFC r312765:

  Pull in r276136 from upstream llvm trunk (by Wei Mi):

    Use ValueOffsetPair to enhance value reuse during SCEV expansion.

    In D12090, the ExprValueMap was added to reuse existing value during
    SCEV expansion. However, const folding and sext/zext distribution can
    make the reuse still difficult.

    A simplified case is: suppose we know S1 expands to V1 in
    ExprValueMap, and
      S1 = S2 + C_a
      S3 = S2 + C_b
    where C_a and C_b are different SCEVConstants. Then we'd like to
    expand S3 as V1 - C_a + C_b instead of expanding S2 literally. It is
    helpful when S2 is a complex SCEV expr and S2 has no entry in
    ExprValueMap, which is usually caused by the fact that S3 is
    generated from S1 after const folding.

    In order to do that, we represent ExprValueMap as a mapping from SCEV
    to ValueOffsetPair. We will save both S1->{V1, 0} and S2->{V1, C_a}
    into the ExprValueMap when we create SCEV for V1. When S3 is
    expanded, it will first expand S2 to V1 - C_a because of S2->{V1,
    C_a} in the map, then expand S3 to V1 - C_a + C_b.

    Differential Revision: https://reviews.llvm.org/D21313

  This should fix assertion failures when building OpenCV >= 3.1.

  PR:		215649

MFC r312831:

  Revert r312765 for now, since it causes assertions when building
  lang/spidermonkey24.

  Reported by:	antoine
  PR:		215649

MFC r316511 (by jhb):

  Add an implementation of __ffssi2() derived from __ffsdi2().

  Newer versions of GCC include an __ffssi2() symbol in libgcc and the
  compiler can emit calls to it in generated code.  This is true for at
  least GCC 6.2 when compiling world for mips and mips64.

  Reviewed by:	jmallett, dim
  Sponsored by:	DARPA / AFRL
  Differential Revision:	https://reviews.freebsd.org/D10086

MFC r318601 (by adrian):

  [libcompiler-rt] add bswapdi2/bswapsi2

  This is required for mips gcc 6.3 userland to build/run.

  Reviewed by:	emaste, dim
  Approved by:	emaste
  Differential Revision:	https://reviews.freebsd.org/D10838

MFC r318884 (by emaste):

  lldb: map TRAP_CAP to a trace trap

  In the absense of a more specific handler for TRAP_CAP (generated by
  ENOTCAPABLE or ECAPMODE while in capability mode) treat it as a trace
  trap.

  Example usage (testing the bug in PR219173):

  % proccontrol -m trapcap lldb usr.bin/hexdump/obj/hexdump -- -Cv -s 1 /bin/ls
  ...
  (lldb) run
  Process 12980 launching
  Process 12980 launched: '.../usr.bin/hexdump/obj/hexdump' (x86_64)
  Process 12980 stopped
  * thread #1, stop reason = trace
      frame #0: 0x0000004b80c65f1a libc.so.7`__sys_lseek + 10
  ...

  In the future we should have LLDB control the trapcap procctl itself
  (as it does with ASLR), as well as report a specific stop reason.
  This change eliminates an assertion failure from LLDB for now.

MFC r319796:

  Remove a few unneeded files from libllvm, libclang and liblldb.

MFC r319885 (by emaste):

  lld: ELF: Fix ICF crash on absolute symbol relocations.

  If two sections contained relocations to absolute symbols with the same
  value we would crash when trying to access their sections. Add a check that
  both symbols point to sections before accessing their sections, and treat
  absolute symbols as equal if their values are equal.

  Obtained from:	LLD commit r292578

MFC r319918:

  Revert r319796 for now, it can cause undefined references when linking
  in some circumstances.

  Reported by:	Shawn Webb <shawn.webb@hardenedbsd.org>

MFC r319957 (by emaste):

  lld: Add armelf emulation mode

  Obtained from:	LLD r305375

MFC r321369:

  Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ to
  5.0.0 (trunk r308421).  Upstream has branched for the 5.0.0 release,
  which should be in about a month.  Please report bugs and regressions,
  so we can get them into the release.

  Please note that from 3.5.0 onwards, clang, llvm and lldb require C++11
  support to build; see UPDATING for more information.

MFC r321420:

  Add a few more object files to liblldb, which should solve errors when
  linking the lldb executable in some cases.  In particular, when the
  -ffunction-sections -fdata-sections options are turned off, or
  ineffective.

  Reported by:	Shawn Webb, Mark Millard

MFC r321433:

  Cleanup stale Options.inc files from the previous libllvm build for
  clang 4.0.0.  Otherwise, these can get included before the two newly
  generated ones (which are different) for clang 5.0.0.

  Reported by:	Mark Millard

MFC r321439 (by bdrewery):

  Move llvm Options.inc hack from r321433 for NO_CLEAN to lib/clang/libllvm.

  The files are only ever generated to .OBJDIR, not to WORLDTMP (as a
  sysroot) and are only ever included from a compilation.  So using
  a beforebuild target here removes the file before the compilation
  tries to include it.

MFC r321664:

  Pull in r308891 from upstream llvm trunk (by Benjamin Kramer):

    [CodeGenPrepare] Cut off FindAllMemoryUses if there are too many uses.

    This avoids excessive compile time. The case I'm looking at is
    Function.cpp from an old version of LLVM that still had the giant
    memcmp string matcher in it. Before r308322 this compiled in about 2
    minutes, after it, clang takes infinite* time to compile it. With
    this patch we're at 5 min, which is still bad but this is a
    pathological case.

    The cut off at 20 uses was chosen by looking at other cut-offs in LLVM
    for user scanning. It's probably too high, but does the job and is
    very unlikely to regress anything.

    Fixes PR33900.

    * I'm impatient and aborted after 15 minutes, on the bug report it was
      killed after 2h.

  Pull in r308986 from upstream llvm trunk (by Simon Pilgrim):

    [X86][CGP] Reduce memcmp() expansion to 2 load pairs (PR33914)

    D35067/rL308322 attempted to support up to 4 load pairs for memcmp
    inlining which resulted in regressions for some optimized libc memcmp
    implementations (PR33914).

    Until we can match these more optimal cases, this patch reduces the
    memcmp expansion to a maximum of 2 load pairs (which matches what we
    do for -Os).

    This patch should be considered for the 5.0.0 release branch as well

    Differential Revision: https://reviews.llvm.org/D35830

  These fix a hang (or extremely long compile time) when building older
  LLVM ports.

  Reported by:    antoine
  PR:             219139

MFC r321719:

  Pull in r309503 from upstream clang trunk (by Richard Smith):

    PR33902: Invalidate line number cache when adding more text to
    existing buffer.

    This led to crashes as the line number cache would report a bogus
    line number for a line of code, and we'd try to find a nonexistent
    column within the line when printing diagnostics.

  This fixes an assertion when building the graphics/champlain port.

  Reported by:	antoine, kwm
  PR:		219139

MFC r321723:

  Upgrade our copies of clang, llvm, lld and lldb to r309439 from the
  upstream release_50 branch.  This is just after upstream's 5.0.0-rc1.

MFC r322320:

  Upgrade our copies of clang, llvm and libc++ to r310316 from the
  upstream release_50 branch.

MFC r322326 (by emaste):

  lldb: Make i386-*-freebsd expression work on JIT path

  * Enable i386 ABI creation for freebsd
  * Added an extra argument in ABISysV_i386::PrepareTrivialCall for mmap
    syscall
  * Unlike linux, the last argument of mmap is actually 64-bit(off_t).
    This requires us to push an additional word for the higher order bits.
  * Prior to this change, ktrace dump will show mmap failures due to
    invalid argument coming from the 6th mmap argument.

  Submitted by:	Karnajit Wangkhem
  Differential Revision:	https://reviews.llvm.org/D34776

MFC r322360 (by emaste):

  lldb: Report inferior signals as signals, not exceptions, on FreeBSD

  This is the FreeBSD equivalent of LLVM r238549.

  This serves 2 purposes:

  * LLDB should handle inferior process signals SIGSEGV/SIGILL/SIGBUS/
    SIGFPE the way it is suppose to be handled. Prior to this fix these
    signals will neither create a coredump, nor exit from the debugger
    or work for signal handling scenario.
  * eInvalidCrashReason need not report "unknown crash reason" if we have
    a valid si_signo

  llvm.org/pr23699

  Patch by Karnajit Wangkhem

  Differential Revision:  https://reviews.llvm.org/D35223

  Submitted by:	Karnajit Wangkhem
  Obtained from:	LLVM r310591

MFC r322474 (by emaste):

  lld: Add `-z muldefs` option.

  Obtained from:	LLVM r310757

MFC r322740:

  Upgrade our copies of clang, llvm, lld and libc++ to r311219 from the
  upstream release_50 branch.

MFC r322855:

  Upgrade our copies of clang, llvm, lldb and compiler-rt to r311606 from
  the upstream release_50 branch.

  As of this version, lib/msun's trig test should also work correctly
  again (see bug 220989 for more information).

  PR:		220989

MFC r323112:

  Upgrade our copies of clang, llvm, lldb and compiler-rt to r312293 from
  the upstream release_50 branch.  This corresponds to 5.0.0 rc4.

  As of this version, the cad/stepcode port should now compile in a more
  reasonable time on i386 (see bug 221836 for more information).

  PR:		221836

MFC r323245:

  Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ to
  5.0.0 release (upstream r312559).

  Release notes for llvm, clang and lld will be available here soon:
  <http://releases.llvm.org/5.0.0/docs/ReleaseNotes.html>
  <http://releases.llvm.org/5.0.0/tools/clang/docs/ReleaseNotes.html>
  <http://releases.llvm.org/5.0.0/tools/lld/docs/ReleaseNotes.html>

  Relnotes:	yes

(cherry picked from commit 12cd91cf4c6b96a24427c0de5374916f2808d263)

1 files changed, 559 insertions, 2 deletions

diff --git a/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp b/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
index 99caca9..d0ef688 100644
--- a/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
+++ b/contrib/llvm/tools/lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
@@ -13,13 +13,13 @@
 #include "EmulationStateARM.h"
 #include "lldb/Core/Address.h"
 #include "lldb/Core/ArchSpec.h"
-#include "lldb/Core/ConstString.h"
 #include "lldb/Core/PluginManager.h"
-#include "lldb/Core/Stream.h"
 #include "lldb/Host/PosixApi.h"
 #include "lldb/Interpreter/OptionValueArray.h"
 #include "lldb/Interpreter/OptionValueDictionary.h"
 #include "lldb/Symbol/UnwindPlan.h"
+#include "lldb/Utility/ConstString.h"
+#include "lldb/Utility/Stream.h"
 
 #include "Plugins/Process/Utility/ARMDefines.h"
 #include "Plugins/Process/Utility/ARMUtils.h"
@@ -44,6 +44,563 @@ using namespace lldb_private;
 //
 //----------------------------------------------------------------------
 
+static bool GetARMDWARFRegisterInfo(unsigned reg_num, RegisterInfo &reg_info) {
+  ::memset(&reg_info, 0, sizeof(RegisterInfo));
+  ::memset(reg_info.kinds, LLDB_INVALID_REGNUM, sizeof(reg_info.kinds));
+
+  if (reg_num >= dwarf_q0 && reg_num <= dwarf_q15) {
+    reg_info.byte_size = 16;
+    reg_info.format = eFormatVectorOfUInt8;
+    reg_info.encoding = eEncodingVector;
+  }
+
+  if (reg_num >= dwarf_d0 && reg_num <= dwarf_d31) {
+    reg_info.byte_size = 8;
+    reg_info.format = eFormatFloat;
+    reg_info.encoding = eEncodingIEEE754;
+  } else if (reg_num >= dwarf_s0 && reg_num <= dwarf_s31) {
+    reg_info.byte_size = 4;
+    reg_info.format = eFormatFloat;
+    reg_info.encoding = eEncodingIEEE754;
+  } else if (reg_num >= dwarf_f0 && reg_num <= dwarf_f7) {
+    reg_info.byte_size = 12;
+    reg_info.format = eFormatFloat;
+    reg_info.encoding = eEncodingIEEE754;
+  } else {
+    reg_info.byte_size = 4;
+    reg_info.format = eFormatHex;
+    reg_info.encoding = eEncodingUint;
+  }
+
+  reg_info.kinds[eRegisterKindDWARF] = reg_num;
+
+  switch (reg_num) {
+  case dwarf_r0:
+    reg_info.name = "r0";
+    break;
+  case dwarf_r1:
+    reg_info.name = "r1";
+    break;
+  case dwarf_r2:
+    reg_info.name = "r2";
+    break;
+  case dwarf_r3:
+    reg_info.name = "r3";
+    break;
+  case dwarf_r4:
+    reg_info.name = "r4";
+    break;
+  case dwarf_r5:
+    reg_info.name = "r5";
+    break;
+  case dwarf_r6:
+    reg_info.name = "r6";
+    break;
+  case dwarf_r7:
+    reg_info.name = "r7";
+    reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FP;
+    break;
+  case dwarf_r8:
+    reg_info.name = "r8";
+    break;
+  case dwarf_r9:
+    reg_info.name = "r9";
+    break;
+  case dwarf_r10:
+    reg_info.name = "r10";
+    break;
+  case dwarf_r11:
+    reg_info.name = "r11";
+    break;
+  case dwarf_r12:
+    reg_info.name = "r12";
+    break;
+  case dwarf_sp:
+    reg_info.name = "sp";
+    reg_info.alt_name = "r13";
+    reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_SP;
+    break;
+  case dwarf_lr:
+    reg_info.name = "lr";
+    reg_info.alt_name = "r14";
+    reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_RA;
+    break;
+  case dwarf_pc:
+    reg_info.name = "pc";
+    reg_info.alt_name = "r15";
+    reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_PC;
+    break;
+  case dwarf_cpsr:
+    reg_info.name = "cpsr";
+    reg_info.kinds[eRegisterKindGeneric] = LLDB_REGNUM_GENERIC_FLAGS;
+    break;
+
+  case dwarf_s0:
+    reg_info.name = "s0";
+    break;
+  case dwarf_s1:
+    reg_info.name = "s1";
+    break;
+  case dwarf_s2:
+    reg_info.name = "s2";
+    break;
+  case dwarf_s3:
+    reg_info.name = "s3";
+    break;
+  case dwarf_s4:
+    reg_info.name = "s4";
+    break;
+  case dwarf_s5:
+    reg_info.name = "s5";
+    break;
+  case dwarf_s6:
+    reg_info.name = "s6";
+    break;
+  case dwarf_s7:
+    reg_info.name = "s7";
+    break;
+  case dwarf_s8:
+    reg_info.name = "s8";
+    break;
+  case dwarf_s9:
+    reg_info.name = "s9";
+    break;
+  case dwarf_s10:
+    reg_info.name = "s10";
+    break;
+  case dwarf_s11:
+    reg_info.name = "s11";
+    break;
+  case dwarf_s12:
+    reg_info.name = "s12";
+    break;
+  case dwarf_s13:
+    reg_info.name = "s13";
+    break;
+  case dwarf_s14:
+    reg_info.name = "s14";
+    break;
+  case dwarf_s15:
+    reg_info.name = "s15";
+    break;
+  case dwarf_s16:
+    reg_info.name = "s16";
+    break;
+  case dwarf_s17:
+    reg_info.name = "s17";
+    break;
+  case dwarf_s18:
+    reg_info.name = "s18";
+    break;
+  case dwarf_s19:
+    reg_info.name = "s19";
+    break;
+  case dwarf_s20:
+    reg_info.name = "s20";
+    break;
+  case dwarf_s21:
+    reg_info.name = "s21";
+    break;
+  case dwarf_s22:
+    reg_info.name = "s22";
+    break;
+  case dwarf_s23:
+    reg_info.name = "s23";
+    break;
+  case dwarf_s24:
+    reg_info.name = "s24";
+    break;
+  case dwarf_s25:
+    reg_info.name = "s25";
+    break;
+  case dwarf_s26:
+    reg_info.name = "s26";
+    break;
+  case dwarf_s27:
+    reg_info.name = "s27";
+    break;
+  case dwarf_s28:
+    reg_info.name = "s28";
+    break;
+  case dwarf_s29:
+    reg_info.name = "s29";
+    break;
+  case dwarf_s30:
+    reg_info.name = "s30";
+    break;
+  case dwarf_s31:
+    reg_info.name = "s31";
+    break;
+
+  // FPA Registers 0-7
+  case dwarf_f0:
+    reg_info.name = "f0";
+    break;
+  case dwarf_f1:
+    reg_info.name = "f1";
+    break;
+  case dwarf_f2:
+    reg_info.name = "f2";
+    break;
+  case dwarf_f3:
+    reg_info.name = "f3";
+    break;
+  case dwarf_f4:
+    reg_info.name = "f4";
+    break;
+  case dwarf_f5:
+    reg_info.name = "f5";
+    break;
+  case dwarf_f6:
+    reg_info.name = "f6";
+    break;
+  case dwarf_f7:
+    reg_info.name = "f7";
+    break;
+
+  // Intel wireless MMX general purpose registers 0 - 7
+  // XScale accumulator register 0 - 7 (they do overlap with wCGR0 - wCGR7)
+  case dwarf_wCGR0:
+    reg_info.name = "wCGR0/ACC0";
+    break;
+  case dwarf_wCGR1:
+    reg_info.name = "wCGR1/ACC1";
+    break;
+  case dwarf_wCGR2:
+    reg_info.name = "wCGR2/ACC2";
+    break;
+  case dwarf_wCGR3:
+    reg_info.name = "wCGR3/ACC3";
+    break;
+  case dwarf_wCGR4:
+    reg_info.name = "wCGR4/ACC4";
+    break;
+  case dwarf_wCGR5:
+    reg_info.name = "wCGR5/ACC5";
+    break;
+  case dwarf_wCGR6:
+    reg_info.name = "wCGR6/ACC6";
+    break;
+  case dwarf_wCGR7:
+    reg_info.name = "wCGR7/ACC7";
+    break;
+
+  // Intel wireless MMX data registers 0 - 15
+  case dwarf_wR0:
+    reg_info.name = "wR0";
+    break;
+  case dwarf_wR1:
+    reg_info.name = "wR1";
+    break;
+  case dwarf_wR2:
+    reg_info.name = "wR2";
+    break;
+  case dwarf_wR3:
+    reg_info.name = "wR3";
+    break;
+  case dwarf_wR4:
+    reg_info.name = "wR4";
+    break;
+  case dwarf_wR5:
+    reg_info.name = "wR5";
+    break;
+  case dwarf_wR6:
+    reg_info.name = "wR6";
+    break;
+  case dwarf_wR7:
+    reg_info.name = "wR7";
+    break;
+  case dwarf_wR8:
+    reg_info.name = "wR8";
+    break;
+  case dwarf_wR9:
+    reg_info.name = "wR9";
+    break;
+  case dwarf_wR10:
+    reg_info.name = "wR10";
+    break;
+  case dwarf_wR11:
+    reg_info.name = "wR11";
+    break;
+  case dwarf_wR12:
+    reg_info.name = "wR12";
+    break;
+  case dwarf_wR13:
+    reg_info.name = "wR13";
+    break;
+  case dwarf_wR14:
+    reg_info.name = "wR14";
+    break;
+  case dwarf_wR15:
+    reg_info.name = "wR15";
+    break;
+
+  case dwarf_spsr:
+    reg_info.name = "spsr";
+    break;
+  case dwarf_spsr_fiq:
+    reg_info.name = "spsr_fiq";
+    break;
+  case dwarf_spsr_irq:
+    reg_info.name = "spsr_irq";
+    break;
+  case dwarf_spsr_abt:
+    reg_info.name = "spsr_abt";
+    break;
+  case dwarf_spsr_und:
+    reg_info.name = "spsr_und";
+    break;
+  case dwarf_spsr_svc:
+    reg_info.name = "spsr_svc";
+    break;
+
+  case dwarf_r8_usr:
+    reg_info.name = "r8_usr";
+    break;
+  case dwarf_r9_usr:
+    reg_info.name = "r9_usr";
+    break;
+  case dwarf_r10_usr:
+    reg_info.name = "r10_usr";
+    break;
+  case dwarf_r11_usr:
+    reg_info.name = "r11_usr";
+    break;
+  case dwarf_r12_usr:
+    reg_info.name = "r12_usr";
+    break;
+  case dwarf_r13_usr:
+    reg_info.name = "r13_usr";
+    break;
+  case dwarf_r14_usr:
+    reg_info.name = "r14_usr";
+    break;
+  case dwarf_r8_fiq:
+    reg_info.name = "r8_fiq";
+    break;
+  case dwarf_r9_fiq:
+    reg_info.name = "r9_fiq";
+    break;
+  case dwarf_r10_fiq:
+    reg_info.name = "r10_fiq";
+    break;
+  case dwarf_r11_fiq:
+    reg_info.name = "r11_fiq";
+    break;
+  case dwarf_r12_fiq:
+    reg_info.name = "r12_fiq";
+    break;
+  case dwarf_r13_fiq:
+    reg_info.name = "r13_fiq";
+    break;
+  case dwarf_r14_fiq:
+    reg_info.name = "r14_fiq";
+    break;
+  case dwarf_r13_irq:
+    reg_info.name = "r13_irq";
+    break;
+  case dwarf_r14_irq:
+    reg_info.name = "r14_irq";
+    break;
+  case dwarf_r13_abt:
+    reg_info.name = "r13_abt";
+    break;
+  case dwarf_r14_abt:
+    reg_info.name = "r14_abt";
+    break;
+  case dwarf_r13_und:
+    reg_info.name = "r13_und";
+    break;
+  case dwarf_r14_und:
+    reg_info.name = "r14_und";
+    break;
+  case dwarf_r13_svc:
+    reg_info.name = "r13_svc";
+    break;
+  case dwarf_r14_svc:
+    reg_info.name = "r14_svc";
+    break;
+
+  // Intel wireless MMX control register in co-processor 0 - 7
+  case dwarf_wC0:
+    reg_info.name = "wC0";
+    break;
+  case dwarf_wC1:
+    reg_info.name = "wC1";
+    break;
+  case dwarf_wC2:
+    reg_info.name = "wC2";
+    break;
+  case dwarf_wC3:
+    reg_info.name = "wC3";
+    break;
+  case dwarf_wC4:
+    reg_info.name = "wC4";
+    break;
+  case dwarf_wC5:
+    reg_info.name = "wC5";
+    break;
+  case dwarf_wC6:
+    reg_info.name = "wC6";
+    break;
+  case dwarf_wC7:
+    reg_info.name = "wC7";
+    break;
+
+  // VFP-v3/Neon
+  case dwarf_d0:
+    reg_info.name = "d0";
+    break;
+  case dwarf_d1:
+    reg_info.name = "d1";
+    break;
+  case dwarf_d2:
+    reg_info.name = "d2";
+    break;
+  case dwarf_d3:
+    reg_info.name = "d3";
+    break;
+  case dwarf_d4:
+    reg_info.name = "d4";
+    break;
+  case dwarf_d5:
+    reg_info.name = "d5";
+    break;
+  case dwarf_d6:
+    reg_info.name = "d6";
+    break;
+  case dwarf_d7:
+    reg_info.name = "d7";
+    break;
+  case dwarf_d8:
+    reg_info.name = "d8";
+    break;
+  case dwarf_d9:
+    reg_info.name = "d9";
+    break;
+  case dwarf_d10:
+    reg_info.name = "d10";
+    break;
+  case dwarf_d11:
+    reg_info.name = "d11";
+    break;
+  case dwarf_d12:
+    reg_info.name = "d12";
+    break;
+  case dwarf_d13:
+    reg_info.name = "d13";
+    break;
+  case dwarf_d14:
+    reg_info.name = "d14";
+    break;
+  case dwarf_d15:
+    reg_info.name = "d15";
+    break;
+  case dwarf_d16:
+    reg_info.name = "d16";
+    break;
+  case dwarf_d17:
+    reg_info.name = "d17";
+    break;
+  case dwarf_d18:
+    reg_info.name = "d18";
+    break;
+  case dwarf_d19:
+    reg_info.name = "d19";
+    break;
+  case dwarf_d20:
+    reg_info.name = "d20";
+    break;
+  case dwarf_d21:
+    reg_info.name = "d21";
+    break;
+  case dwarf_d22:
+    reg_info.name = "d22";
+    break;
+  case dwarf_d23:
+    reg_info.name = "d23";
+    break;
+  case dwarf_d24:
+    reg_info.name = "d24";
+    break;
+  case dwarf_d25:
+    reg_info.name = "d25";
+    break;
+  case dwarf_d26:
+    reg_info.name = "d26";
+    break;
+  case dwarf_d27:
+    reg_info.name = "d27";
+    break;
+  case dwarf_d28:
+    reg_info.name = "d28";
+    break;
+  case dwarf_d29:
+    reg_info.name = "d29";
+    break;
+  case dwarf_d30:
+    reg_info.name = "d30";
+    break;
+  case dwarf_d31:
+    reg_info.name = "d31";
+    break;
+
+  // NEON 128-bit vector registers (overlays the d registers)
+  case dwarf_q0:
+    reg_info.name = "q0";
+    break;
+  case dwarf_q1:
+    reg_info.name = "q1";
+    break;
+  case dwarf_q2:
+    reg_info.name = "q2";
+    break;
+  case dwarf_q3:
+    reg_info.name = "q3";
+    break;
+  case dwarf_q4:
+    reg_info.name = "q4";
+    break;
+  case dwarf_q5:
+    reg_info.name = "q5";
+    break;
+  case dwarf_q6:
+    reg_info.name = "q6";
+    break;
+  case dwarf_q7:
+    reg_info.name = "q7";
+    break;
+  case dwarf_q8:
+    reg_info.name = "q8";
+    break;
+  case dwarf_q9:
+    reg_info.name = "q9";
+    break;
+  case dwarf_q10:
+    reg_info.name = "q10";
+    break;
+  case dwarf_q11:
+    reg_info.name = "q11";
+    break;
+  case dwarf_q12:
+    reg_info.name = "q12";
+    break;
+  case dwarf_q13:
+    reg_info.name = "q13";
+    break;
+  case dwarf_q14:
+    reg_info.name = "q14";
+    break;
+  case dwarf_q15:
+    reg_info.name = "q15";
+    break;
+
+  default:
+    return false;
+  }
+  return true;
+}
+
 // A8.6.50
 // Valid return values are {1, 2, 3, 4}, with 0 signifying an error condition.
 static uint32_t CountITSize(uint32_t ITMask) {