Add clang and llvm patches corresponding to r276516 and r276537.

2 files changed, 165 insertions, 0 deletions

diff --git a/contrib/llvm/patches/patch-29-clang-r213790-type_traits-crash.diff b/contrib/llvm/patches/patch-29-clang-r213790-type_traits-crash.diff
new file mode 100644
index 0000000..e721d24
--- /dev/null
+++ b/contrib/llvm/patches/patch-29-clang-r213790-type_traits-crash.diff
@@ -0,0 +1,57 @@
+Pull in r213790 from upstream clang trunk (by Richard Smith):
+
+  PR20228: don't retain a pointer to a vector element after the
+  container has been resized.
+
+This fixes a possible crash when compiling certain parts of libc++'s
+type_traits header.
+
+Introduced here: http://svnweb.freebsd.org/changeset/base/276516
+
+Index: tools/clang/lib/Sema/SemaExprCXX.cpp
+===================================================================
+--- tools/clang/lib/Sema/SemaExprCXX.cpp
++++ tools/clang/lib/Sema/SemaExprCXX.cpp
+@@ -3642,12 +3642,13 @@ static bool evaluateTypeTrait(Sema &S, TypeTrait K
+       if (T->isObjectType() || T->isFunctionType())
+         T = S.Context.getRValueReferenceType(T);
+       OpaqueArgExprs.push_back(
+-        OpaqueValueExpr(Args[I]->getTypeLoc().getLocStart(), 
++        OpaqueValueExpr(Args[I]->getTypeLoc().getLocStart(),
+                         T.getNonLValueExprType(S.Context),
+                         Expr::getValueKindForType(T)));
+-      ArgExprs.push_back(&OpaqueArgExprs.back());
+     }
+-    
++    for (Expr &E : OpaqueArgExprs)
++      ArgExprs.push_back(&E);
++
+     // Perform the initialization in an unevaluated context within a SFINAE 
+     // trap at translation unit scope.
+     EnterExpressionEvaluationContext Unevaluated(S, Sema::Unevaluated);
+Index: tools/clang/test/SemaCXX/type-traits.cpp
+===================================================================
+--- tools/clang/test/SemaCXX/type-traits.cpp
++++ tools/clang/test/SemaCXX/type-traits.cpp
+@@ -146,6 +146,10 @@ struct ThreeArgCtor {
+   ThreeArgCtor(int*, char*, int);
+ };
+ 
++struct VariadicCtor {
++  template<typename...T> VariadicCtor(T...);
++};
++
+ void is_pod()
+ {
+   { int arr[T(__is_pod(int))]; }
+@@ -1968,6 +1972,10 @@ void constructible_checks() {
+   // PR19178
+   { int arr[F(__is_constructible(Abstract))]; }
+   { int arr[F(__is_nothrow_constructible(Abstract))]; }
++
++  // PR20228
++  { int arr[T(__is_constructible(VariadicCtor,
++                                 int, int, int, int, int, int, int, int, int))]; }
+ }
+ 
+ // Instantiation of __is_trivially_constructible
diff --git a/contrib/llvm/patches/patch-30-llvm-r222587-arm-add-pc.diff b/contrib/llvm/patches/patch-30-llvm-r222587-arm-add-pc.diff
new file mode 100644
index 0000000..46b2a04
--- /dev/null
+++ b/contrib/llvm/patches/patch-30-llvm-r222587-arm-add-pc.diff
@@ -0,0 +1,108 @@
+Pull in r222587 from upstream llvm trunk (by Jörg Sonnenberger):
+
+  Fix transformation of add with pc argument to adr for non-immediate
+  arguments.
+
+This fixes an "Unimplemented" error when assembling certain ARM add
+instructions with pc-relative arguments.
+
+Reported by:	sbruno
+PR:		196412, 196423
+
+Introduced here: http://svnweb.freebsd.org/changeset/base/276537
+
+Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+===================================================================
+--- lib/Target/ARM/AsmParser/ARMAsmParser.cpp
++++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+@@ -314,7 +314,7 @@ class ARMAsmParser : public MCTargetAsmParser {
+   void cvtThumbBranches(MCInst &Inst, const OperandVector &);
+ 
+   bool validateInstruction(MCInst &Inst, const OperandVector &Ops);
+-  bool processInstruction(MCInst &Inst, const OperandVector &Ops);
++  bool processInstruction(MCInst &Inst, const OperandVector &Ops, MCStreamer &Out);
+   bool shouldOmitCCOutOperand(StringRef Mnemonic, OperandVector &Operands);
+   bool shouldOmitPredicateOperand(StringRef Mnemonic, OperandVector &Operands);
+ 
+@@ -6175,7 +6175,8 @@ static unsigned getRealVLDOpcode(unsigned Opc, uns
+ }
+ 
+ bool ARMAsmParser::processInstruction(MCInst &Inst,
+-                                      const OperandVector &Operands) {
++                                      const OperandVector &Operands,
++                                      MCStreamer &Out) {
+   switch (Inst.getOpcode()) {
+   // Alias for alternate form of 'ldr{,b}t Rt, [Rn], #imm' instruction.
+   case ARM::LDRT_POST:
+@@ -6216,12 +6217,31 @@ bool ARMAsmParser::processInstruction(MCInst &Inst
+   // Alias for alternate form of 'ADR Rd, #imm' instruction.
+   case ARM::ADDri: {
+     if (Inst.getOperand(1).getReg() != ARM::PC ||
+-        Inst.getOperand(5).getReg() != 0)
++        Inst.getOperand(5).getReg() != 0 ||
++        !(Inst.getOperand(2).isExpr() || Inst.getOperand(2).isImm()))
+       return false;
+     MCInst TmpInst;
+     TmpInst.setOpcode(ARM::ADR);
+     TmpInst.addOperand(Inst.getOperand(0));
+-    TmpInst.addOperand(Inst.getOperand(2));
++    if (Inst.getOperand(2).isImm()) {
++      TmpInst.addOperand(Inst.getOperand(2));
++    } else {
++      // Turn PC-relative expression into absolute expression.
++      // Reading PC provides the start of the current instruction + 8 and
++      // the transform to adr is biased by that.
++      MCSymbol *Dot = getContext().CreateTempSymbol();
++      Out.EmitLabel(Dot);
++      const MCExpr *OpExpr = Inst.getOperand(2).getExpr();
++      const MCExpr *InstPC = MCSymbolRefExpr::Create(Dot,
++                                                     MCSymbolRefExpr::VK_None,
++                                                     getContext());
++      const MCExpr *Const8 = MCConstantExpr::Create(8, getContext());
++      const MCExpr *ReadPC = MCBinaryExpr::CreateAdd(InstPC, Const8,
++                                                     getContext());
++      const MCExpr *FixupAddr = MCBinaryExpr::CreateAdd(ReadPC, OpExpr,
++                                                        getContext());
++      TmpInst.addOperand(MCOperand::CreateExpr(FixupAddr));
++    }
+     TmpInst.addOperand(Inst.getOperand(3));
+     TmpInst.addOperand(Inst.getOperand(4));
+     Inst = TmpInst;
+@@ -8061,7 +8081,7 @@ bool ARMAsmParser::MatchAndEmitInstruction(SMLoc I
+       // encoding is selected. Loop on it while changes happen so the
+       // individual transformations can chain off each other. E.g.,
+       // tPOP(r8)->t2LDMIA_UPD(sp,r8)->t2STR_POST(sp,r8)
+-      while (processInstruction(Inst, Operands))
++      while (processInstruction(Inst, Operands, Out))
+         ;
+ 
+       // Only after the instruction is fully processed, we can validate it
+Index: test/MC/ARM/basic-arm-instructions.s
+===================================================================
+--- test/MC/ARM/basic-arm-instructions.s
++++ test/MC/ARM/basic-arm-instructions.s
+@@ -191,8 +191,10 @@ Lforward:
+ 
+ 	add r0, #-4
+ 	add r4, r5, #-21
+-        add r0, pc, #0xc0000000
++	add r0, pc, #0xc0000000
+ 
++	add r0, pc, #(Lback - .)
++
+ @ CHECK: add	r4, r5, #61440          @ encoding: [0x0f,0x4a,0x85,0xe2]
+ @ CHECK: add	r4, r5, r6              @ encoding: [0x06,0x40,0x85,0xe0]
+ @ CHECK: add	r4, r5, r6, lsl #5      @ encoding: [0x86,0x42,0x85,0xe0]
+@@ -222,7 +224,11 @@ Lforward:
+ 
+ @ CHECK: sub	r0, r0, #4              @ encoding: [0x04,0x00,0x40,0xe2]
+ @ CHECK: sub	r4, r5, #21             @ encoding: [0x15,0x40,0x45,0xe2]
+-@ CHECK: adr    r0, #-1073741824        @ encoding: [0x03,0x01,0x8f,0xe2]
++@ CHECK: adr	r0, #-1073741824        @ encoding: [0x03,0x01,0x8f,0xe2]
++@ CHECK:        Ltmp0:
++@ CHECK-NEXT:   Ltmp1:
++@ CHECK-NEXT:   adr	r0, (Ltmp1+8)+(Lback-Ltmp0) @ encoding: [A,A,0x0f'A',0xe2'A']
++@ CHECK-NEXT:                           @   fixup A - offset: 0, value: (Ltmp1+8)+(Lback-Ltmp0), kind: fixup_arm_adr_pcrel_12
+ 
+     @ Test right shift by 32, which is encoded as 0
+     add r3, r1, r2, lsr #32