Cleanup patch set, and update README.TXT. Add three new patches.

1 files changed, 0 insertions, 55 deletions

diff --git a/contrib/llvm/patches/patch-r262261-llvm-r199786-sparc.diff b/contrib/llvm/patches/patch-r262261-llvm-r199786-sparc.diff
deleted file mode 100644
index 004f85d..0000000
--- a/contrib/llvm/patches/patch-r262261-llvm-r199786-sparc.diff
+++ /dev/null
@@ -1,55 +0,0 @@
-Pull in r199786 from upstream llvm trunk (by Venkatraman Govindaraju):
-
-  [Sparc] Add support for inline assembly constraints which specify registers by their aliases.
-
-Introduced here: http://svnweb.freebsd.org/changeset/base/262261
-
-Index: lib/Target/Sparc/SparcISelLowering.cpp
-===================================================================
---- lib/Target/Sparc/SparcISelLowering.cpp
-+++ lib/Target/Sparc/SparcISelLowering.cpp
-@@ -2992,6 +2992,26 @@ SparcTargetLowering::getRegForInlineAsmConstraint(
-     case 'r':
-       return std::make_pair(0U, &SP::IntRegsRegClass);
-     }
-+  } else  if (!Constraint.empty() && Constraint.size() <= 5
-+              && Constraint[0] == '{' && *(Constraint.end()-1) == '}') {
-+    // constraint = '{r<d>}'
-+    // Remove the braces from around the name.
-+    StringRef name(Constraint.data()+1, Constraint.size()-2);
-+    // Handle register aliases:
-+    //       r0-r7   -> g0-g7
-+    //       r8-r15  -> o0-o7
-+    //       r16-r23 -> l0-l7
-+    //       r24-r31 -> i0-i7
-+    uint64_t intVal = 0;
-+    if (name.substr(0, 1).equals("r")
-+        && !name.substr(1).getAsInteger(10, intVal) && intVal <= 31) {
-+      const char regTypes[] = { 'g', 'o', 'l', 'i' };
-+      char regType = regTypes[intVal/8];
-+      char regIdx = '0' + (intVal % 8);
-+      char tmp[] = { '{', regType, regIdx, '}', 0 };
-+      std::string newConstraint = std::string(tmp);
-+      return TargetLowering::getRegForInlineAsmConstraint(newConstraint, VT);
-+    }
-   }
- 
-   return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
-Index: test/CodeGen/SPARC/inlineasm.ll
-===================================================================
---- test/CodeGen/SPARC/inlineasm.ll
-+++ test/CodeGen/SPARC/inlineasm.ll
-@@ -33,3 +33,13 @@ entry:
-   %0 = tail call i32 asm sideeffect "add $1, $2, $0", "=r,r,rI"(i32 %a, i32 10000)
-   ret i32 %0
- }
-+
-+; CHECK-LABEL: test_constraint_reg
-+; CHECK:       ldda [%o1] 43, %g2
-+; CHECK:       ldda [%o1] 43, %g3
-+define void @test_constraint_reg(i32 %s, i32* %ptr) {
-+entry:
-+  %0 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={r2},r,n"(i32* %ptr, i32 43)
-+  %1 = tail call i64 asm sideeffect "ldda [$1] $2, $0", "={g3},r,n"(i32* %ptr, i32 43)
-+  ret void
-+}