Cleanup patch set, and update README.TXT. Add three new patches.

1 files changed, 0 insertions, 115 deletions

diff --git a/contrib/llvm/patches/patch-r262261-llvm-r198740-sparc.diff b/contrib/llvm/patches/patch-r262261-llvm-r198740-sparc.diff
deleted file mode 100644
index 1aa2f9e..0000000
--- a/contrib/llvm/patches/patch-r262261-llvm-r198740-sparc.diff
+++ /dev/null
@@ -1,115 +0,0 @@
-Pull in r198740 from upstream llvm trunk (by Venkatraman Govindaraju):
-
-  [SparcV9] Rename operands in some sparc64 instructions so that TableGen can encode them correctly. 
-
-Introduced here: http://svnweb.freebsd.org/changeset/base/262261
-
-Index: test/MC/Sparc/sparc64-alu-instructions.s
-===================================================================
---- test/MC/Sparc/sparc64-alu-instructions.s
-+++ test/MC/Sparc/sparc64-alu-instructions.s
-@@ -0,0 +1,38 @@
-+! RUN: llvm-mc %s -triple=sparc64-unknown-linux-gnu -show-encoding | FileCheck %s
-+
-+        ! CHECK: sllx %g1, %i2, %i0  ! encoding: [0xb1,0x28,0x50,0x1a]
-+        sllx %g1, %i2, %i0
-+
-+        ! CHECK: sllx %g1, 63, %i0   ! encoding: [0xb1,0x28,0x70,0x3f]
-+        sllx %g1, 63, %i0
-+
-+        ! CHECK: srlx %g1, %i2, %i0  ! encoding: [0xb1,0x30,0x50,0x1a]
-+        srlx %g1, %i2, %i0
-+
-+        ! CHECK: srlx %g1, 63, %i0   ! encoding: [0xb1,0x30,0x70,0x3f]
-+        srlx %g1, 63, %i0
-+
-+        ! CHECK: srax %g1, %i2, %i0  ! encoding: [0xb1,0x38,0x50,0x1a]
-+        srax %g1, %i2, %i0
-+
-+        ! CHECK: srax %g1, 63, %i0   ! encoding: [0xb1,0x38,0x70,0x3f]
-+        srax %g1, 63, %i0
-+
-+        ! CHECK: mulx %g1, %i2, %i0  ! encoding: [0xb0,0x48,0x40,0x1a]
-+        mulx %g1, %i2, %i0
-+
-+        ! CHECK: mulx %g1, 63, %i0   ! encoding: [0xb0,0x48,0x60,0x3f]
-+        mulx %g1, 63, %i0
-+
-+        ! CHECK: sdivx %g1, %i2, %i0 ! encoding: [0xb1,0x68,0x40,0x1a]
-+        sdivx %g1, %i2, %i0
-+
-+        ! CHECK: sdivx %g1, 63, %i0  ! encoding: [0xb1,0x68,0x60,0x3f]
-+        sdivx %g1, 63, %i0
-+
-+        ! CHECK: udivx %g1, %i2, %i0 ! encoding: [0xb0,0x68,0x40,0x1a]
-+        udivx %g1, %i2, %i0
-+
-+        ! CHECK: udivx %g1, 63, %i0  ! encoding: [0xb0,0x68,0x60,0x3f]
-+        udivx %g1, 63, %i0
-+
-Index: lib/Target/Sparc/SparcInstr64Bit.td
-===================================================================
---- lib/Target/Sparc/SparcInstr64Bit.td
-+++ lib/Target/Sparc/SparcInstr64Bit.td
-@@ -193,9 +193,9 @@ def MULXrr : F3_1<2, 0b001001,
-                   "mulx $rs1, $rs2, $rd",
-                   [(set i64:$rd, (mul i64:$rs1, i64:$rs2))]>;
- def MULXri : F3_2<2, 0b001001,
--                  (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
--                  "mulx $rs1, $i, $rd",
--                  [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$i)))]>;
-+                  (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
-+                  "mulx $rs1, $simm13, $rd",
-+                  [(set i64:$rd, (mul i64:$rs1, (i64 simm13:$simm13)))]>;
- 
- // Division can trap.
- let hasSideEffects = 1 in {
-@@ -204,9 +204,9 @@ def SDIVXrr : F3_1<2, 0b101101,
-                    "sdivx $rs1, $rs2, $rd",
-                    [(set i64:$rd, (sdiv i64:$rs1, i64:$rs2))]>;
- def SDIVXri : F3_2<2, 0b101101,
--                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
--                   "sdivx $rs1, $i, $rd",
--                   [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$i)))]>;
-+                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
-+                   "sdivx $rs1, $simm13, $rd",
-+                   [(set i64:$rd, (sdiv i64:$rs1, (i64 simm13:$simm13)))]>;
- 
- def UDIVXrr : F3_1<2, 0b001101,
-                    (outs I64Regs:$rd), (ins I64Regs:$rs1, I64Regs:$rs2),
-@@ -213,9 +213,9 @@ def UDIVXrr : F3_1<2, 0b001101,
-                    "udivx $rs1, $rs2, $rd",
-                    [(set i64:$rd, (udiv i64:$rs1, i64:$rs2))]>;
- def UDIVXri : F3_2<2, 0b001101,
--                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$i),
--                   "udivx $rs1, $i, $rd",
--                   [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$i)))]>;
-+                   (outs IntRegs:$rd), (ins IntRegs:$rs1, i64imm:$simm13),
-+                   "udivx $rs1, $simm13, $rd",
-+                   [(set i64:$rd, (udiv i64:$rs1, (i64 simm13:$simm13)))]>;
- } // hasSideEffects = 1
- 
- } // Predicates = [Is64Bit]
-Index: lib/Target/Sparc/SparcInstrFormats.td
-===================================================================
---- lib/Target/Sparc/SparcInstrFormats.td
-+++ lib/Target/Sparc/SparcInstrFormats.td
-@@ -193,12 +193,12 @@ class F3_Si<bits<2> opVal, bits<6> op3val, bit xVa
- // Define rr and ri shift instructions with patterns.
- multiclass F3_S<string OpcStr, bits<6> Op3Val, bit XVal, SDNode OpNode,
-                 ValueType VT, RegisterClass RC> {
--  def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, IntRegs:$rs2),
--                 !strconcat(OpcStr, " $rs, $rs2, $rd"),
--                 [(set VT:$rd, (OpNode VT:$rs, i32:$rs2))]>;
--  def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs, i32imm:$shcnt),
--                 !strconcat(OpcStr, " $rs, $shcnt, $rd"),
--                 [(set VT:$rd, (OpNode VT:$rs, (i32 imm:$shcnt)))]>;
-+  def rr : F3_Sr<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, IntRegs:$rs2),
-+                 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
-+                 [(set VT:$rd, (OpNode VT:$rs1, i32:$rs2))]>;
-+  def ri : F3_Si<2, Op3Val, XVal, (outs RC:$rd), (ins RC:$rs1, i32imm:$shcnt),
-+                 !strconcat(OpcStr, " $rs1, $shcnt, $rd"),
-+                 [(set VT:$rd, (OpNode VT:$rs1, (i32 imm:$shcnt)))]>;
- }
- 
- class F4<bits<6> op3, dag outs, dag ins, string asmstr, list<dag> pattern>