Update clang, llvm, lld, lldb, compiler-rt and libc++ to 4.0.0 release:

MFC r309142 (by emaste):

Add WITH_LLD_AS_LD build knob

If set it installs LLD as /usr/bin/ld.  LLD (as of version 3.9) is not
capable of linking the world and kernel, but can self-host and link many
substantial applications. GNU ld continues to be used for the world and
kernel build, regardless of how this knob is set.

It is on by default for arm64, and off for all other CPU architectures.

Sponsored by:	The FreeBSD Foundation

MFC r310840:

Reapply 310775, now it also builds correctly if lldb is disabled:

Move llvm-objdump from CLANG_EXTRAS to installed by default

We currently install three tools from binutils 2.17.50: as, ld, and
objdump. Work is underway to migrate to a permissively-licensed
tool-chain, with one goal being the retirement of binutils 2.17.50.

LLVM's llvm-objdump is intended to be compatible with GNU objdump
although it is currently missing some options and may have formatting
differences. Enable it by default for testing and further investigation.
It may later be changed to install as /usr/bin/objdump, it becomes a
fully viable replacement.

Reviewed by:	emaste
Differential Revision:	https://reviews.freebsd.org/D8879

MFC r312855 (by emaste):

Rename LLD_AS_LD to LLD_IS_LD, for consistency with CLANG_IS_CC

Reported by:	Dan McGregor <dan.mcgregor usask.ca>

MFC r313559 | glebius | 2017-02-10 18:34:48 +0100 (Fri, 10 Feb 2017) | 5 lines

Don't check struct rtentry on FreeBSD, it is an internal kernel structure.
On other systems it may be API structure for SIOCADDRT/SIOCDELRT.

Reviewed by:	emaste, dim

MFC r314152 (by jkim):

Remove an assembler flag, which is redundant since r309124.  The upstream
took care of it by introducing a macro NO_EXEC_STACK_DIRECTIVE.

http://llvm.org/viewvc/llvm-project?rev=273500&view=rev

Reviewed by:	dim

MFC r314564:

Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ to
4.0.0 (branches/release_40 296509).  The release will follow soon.

Please note that from 3.5.0 onwards, clang, llvm and lldb require C++11
support to build; see UPDATING for more information.

Also note that as of 4.0.0, lld should be able to link the base system
on amd64 and aarch64.  See the WITH_LLD_IS_LLD setting in src.conf(5).
Though please be aware that this is work in progress.

Release notes for llvm, clang and lld will be available here:
<http://releases.llvm.org/4.0.0/docs/ReleaseNotes.html>
<http://releases.llvm.org/4.0.0/tools/clang/docs/ReleaseNotes.html>
<http://releases.llvm.org/4.0.0/tools/lld/docs/ReleaseNotes.html>

Thanks to Ed Maste, Jan Beich, Antoine Brodin and Eric Fiselier for
their help.

Relnotes:	yes
Exp-run:	antoine
PR:		215969, 216008

MFC r314708:

For now, revert r287232 from upstream llvm trunk (by Daniil Fukalov):

  [SCEV] limit recursion depth of CompareSCEVComplexity

  Summary:
  CompareSCEVComplexity goes too deep (50+ on a quite a big unrolled
  loop) and runs almost infinite time.

  Added cache of "equal" SCEV pairs to earlier cutoff of further
  estimation. Recursion depth limit was also introduced as a parameter.

  Reviewers: sanjoy

  Subscribers: mzolotukhin, tstellarAMD, llvm-commits

  Differential Revision: https://reviews.llvm.org/D26389

This commit is the cause of excessive compile times on skein_block.c
(and possibly other files) during kernel builds on amd64.

We never saw the problematic behavior described in this upstream commit,
so for now it is better to revert it.  An upstream bug has been filed
here: https://bugs.llvm.org/show_bug.cgi?id=32142

Reported by:	mjg

MFC r314795:

Reapply r287232 from upstream llvm trunk (by Daniil Fukalov):

  [SCEV] limit recursion depth of CompareSCEVComplexity

  Summary:
  CompareSCEVComplexity goes too deep (50+ on a quite a big unrolled
  loop) and runs almost infinite time.

  Added cache of "equal" SCEV pairs to earlier cutoff of further
  estimation. Recursion depth limit was also introduced as a parameter.

  Reviewers: sanjoy

  Subscribers: mzolotukhin, tstellarAMD, llvm-commits

  Differential Revision: https://reviews.llvm.org/D26389

Pull in r296992 from upstream llvm trunk (by Sanjoy Das):

  [SCEV] Decrease the recursion threshold for CompareValueComplexity

  Fixes PR32142.

  r287232 accidentally increased the recursion threshold for
  CompareValueComplexity from 2 to 32.  This change reverses that
  change by introducing a separate flag for CompareValueComplexity's
  threshold.

The latter revision fixes the excessive compile times for skein_block.c.

MFC r314907 | mmel | 2017-03-08 12:40:27 +0100 (Wed, 08 Mar 2017) | 7 lines

Unbreak ARMv6 world.

The new compiler_rt library imported with clang 4.0.0 have several fatal
issues (non-functional __udivsi3 for example) with ARM specific instrict
functions. As temporary workaround, until upstream solve these problems,
disable all thumb[1][2] related feature.

MFC r315016:

Update clang, llvm, lld, lldb, compiler-rt and libc++ to 4.0.0 release.
We were already very close to the last release candidate, so this is a
pretty minor update.

Relnotes:	yes

MFC r316005:

Revert r314907, and pull in r298713 from upstream compiler-rt trunk (by
Weiming Zhao):

  builtins: Select correct code fragments when compiling for Thumb1/Thum2/ARM ISA.

  Summary:
  Value of __ARM_ARCH_ISA_THUMB isn't based on the actual compilation
  mode (-mthumb, -marm), it reflect's capability of given CPU.

  Due to this:
   - use  __tbumb__ and __thumb2__ insteand of __ARM_ARCH_ISA_THUMB
   - use '.thumb' directive consistently  in all affected files
   - decorate all thumb functions using
     DEFINE_COMPILERRT_THUMB_FUNCTION()

  ---------
  Note: This patch doesn't fix broken Thumb1 variant of __udivsi3 !

  Reviewers: weimingz, rengolin, compnerd

  Subscribers: aemerson, dim

  Differential Revision: https://reviews.llvm.org/D30938

Discussed with:	mmel

1 files changed, 208 insertions, 0 deletions

diff --git a/contrib/llvm/lib/Target/X86/X86CallingConv.cpp b/contrib/llvm/lib/Target/X86/X86CallingConv.cpp
new file mode 100644
index 0000000..c96e76b
--- /dev/null
+++ b/contrib/llvm/lib/Target/X86/X86CallingConv.cpp
@@ -0,0 +1,208 @@
+//=== X86CallingConv.cpp - X86 Custom Calling Convention Impl   -*- C++ -*-===//

+//

+//                     The LLVM Compiler Infrastructure

+//

+// This file is distributed under the University of Illinois Open Source

+// License. See LICENSE.TXT for details.

+//

+//===----------------------------------------------------------------------===//

+//

+// This file contains the implementation of custom routines for the X86

+// Calling Convention that aren't done by tablegen.

+//

+//===----------------------------------------------------------------------===//

+

+#include "MCTargetDesc/X86MCTargetDesc.h"

+#include "X86Subtarget.h"

+#include "llvm/CodeGen/CallingConvLower.h"

+#include "llvm/IR/CallingConv.h"

+

+namespace llvm {

+

+bool CC_X86_32_RegCall_Assign2Regs(unsigned &ValNo, MVT &ValVT, MVT &LocVT,

+                                   CCValAssign::LocInfo &LocInfo,

+                                   ISD::ArgFlagsTy &ArgFlags, CCState &State) {

+  // List of GPR registers that are available to store values in regcall

+  // calling convention.

+  static const MCPhysReg RegList[] = {X86::EAX, X86::ECX, X86::EDX, X86::EDI,

+                                      X86::ESI};

+

+  // The vector will save all the available registers for allocation.

+  SmallVector<unsigned, 5> AvailableRegs;

+

+  // searching for the available registers.

+  for (auto Reg : RegList) {

+    if (!State.isAllocated(Reg))

+      AvailableRegs.push_back(Reg);

+  }

+

+  const size_t RequiredGprsUponSplit = 2;

+  if (AvailableRegs.size() < RequiredGprsUponSplit)

+    return false; // Not enough free registers - continue the search.

+

+  // Allocating the available registers.

+  for (unsigned I = 0; I < RequiredGprsUponSplit; I++) {

+

+    // Marking the register as located.

+    unsigned Reg = State.AllocateReg(AvailableRegs[I]);

+

+    // Since we previously made sure that 2 registers are available

+    // we expect that a real register number will be returned.

+    assert(Reg && "Expecting a register will be available");

+

+    // Assign the value to the allocated register

+    State.addLoc(CCValAssign::getCustomReg(ValNo, ValVT, Reg, LocVT, LocInfo));

+  }

+

+  // Successful in allocating regsiters - stop scanning next rules.

+  return true;

+}

+

+static ArrayRef<MCPhysReg> CC_X86_VectorCallGetSSEs(const MVT &ValVT) {

+  if (ValVT.is512BitVector()) {

+    static const MCPhysReg RegListZMM[] = {X86::ZMM0, X86::ZMM1, X86::ZMM2,

+                                           X86::ZMM3, X86::ZMM4, X86::ZMM5};

+    return makeArrayRef(std::begin(RegListZMM), std::end(RegListZMM));

+  }

+

+  if (ValVT.is256BitVector()) {

+    static const MCPhysReg RegListYMM[] = {X86::YMM0, X86::YMM1, X86::YMM2,

+                                           X86::YMM3, X86::YMM4, X86::YMM5};

+    return makeArrayRef(std::begin(RegListYMM), std::end(RegListYMM));

+  }

+

+  static const MCPhysReg RegListXMM[] = {X86::XMM0, X86::XMM1, X86::XMM2,

+                                         X86::XMM3, X86::XMM4, X86::XMM5};

+  return makeArrayRef(std::begin(RegListXMM), std::end(RegListXMM));

+}

+

+static ArrayRef<MCPhysReg> CC_X86_64_VectorCallGetGPRs() {

+  static const MCPhysReg RegListGPR[] = {X86::RCX, X86::RDX, X86::R8, X86::R9};

+  return makeArrayRef(std::begin(RegListGPR), std::end(RegListGPR));

+}

+

+static bool CC_X86_VectorCallAssignRegister(unsigned &ValNo, MVT &ValVT,

+                                            MVT &LocVT,

+                                            CCValAssign::LocInfo &LocInfo,

+                                            ISD::ArgFlagsTy &ArgFlags,

+                                            CCState &State) {

+

+  ArrayRef<MCPhysReg> RegList = CC_X86_VectorCallGetSSEs(ValVT);

+  bool Is64bit = static_cast<const X86Subtarget &>(

+                     State.getMachineFunction().getSubtarget())

+                     .is64Bit();

+

+  for (auto Reg : RegList) {

+    // If the register is not marked as allocated - assign to it.

+    if (!State.isAllocated(Reg)) {

+      unsigned AssigedReg = State.AllocateReg(Reg);

+      assert(AssigedReg == Reg && "Expecting a valid register allocation");

+      State.addLoc(

+          CCValAssign::getReg(ValNo, ValVT, AssigedReg, LocVT, LocInfo));

+      return true;

+    }

+    // If the register is marked as shadow allocated - assign to it.

+    if (Is64bit && State.IsShadowAllocatedReg(Reg)) {

+      State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));

+      return true;

+    }

+  }

+

+  llvm_unreachable("Clang should ensure that hva marked vectors will have "

+                   "an available register.");

+  return false;

+}

+

+bool CC_X86_64_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT,

+                          CCValAssign::LocInfo &LocInfo,

+                          ISD::ArgFlagsTy &ArgFlags, CCState &State) {

+  // On the second pass, go through the HVAs only.

+  if (ArgFlags.isSecArgPass()) {

+    if (ArgFlags.isHva())

+      return CC_X86_VectorCallAssignRegister(ValNo, ValVT, LocVT, LocInfo,

+                                             ArgFlags, State);

+    return true;

+  }

+

+  // Process only vector types as defined by vectorcall spec:

+  // "A vector type is either a floating-point type, for example,

+  //  a float or double, or an SIMD vector type, for example, __m128 or __m256".

+  if (!(ValVT.isFloatingPoint() ||

+        (ValVT.isVector() && ValVT.getSizeInBits() >= 128))) {

+    // If R9 was already assigned it means that we are after the fourth element

+    // and because this is not an HVA / Vector type, we need to allocate

+    // shadow XMM register.

+    if (State.isAllocated(X86::R9)) {

+      // Assign shadow XMM register.

+      (void)State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT));

+    }

+

+    return false;

+  }

+

+  if (!ArgFlags.isHva() || ArgFlags.isHvaStart()) {

+    // Assign shadow GPR register.

+    (void)State.AllocateReg(CC_X86_64_VectorCallGetGPRs());

+

+    // Assign XMM register - (shadow for HVA and non-shadow for non HVA).

+    if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) {

+      // In Vectorcall Calling convention, additional shadow stack can be

+      // created on top of the basic 32 bytes of win64.

+      // It can happen if the fifth or sixth argument is vector type or HVA.

+      // At that case for each argument a shadow stack of 8 bytes is allocated.

+      if (Reg == X86::XMM4 || Reg == X86::XMM5)

+        State.AllocateStack(8, 8);

+

+      if (!ArgFlags.isHva()) {

+        State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));

+        return true; // Allocated a register - Stop the search.

+      }

+    }

+  }

+

+  // If this is an HVA - Stop the search,

+  // otherwise continue the search.

+  return ArgFlags.isHva();

+}

+

+bool CC_X86_32_VectorCall(unsigned &ValNo, MVT &ValVT, MVT &LocVT,

+                          CCValAssign::LocInfo &LocInfo,

+                          ISD::ArgFlagsTy &ArgFlags, CCState &State) {

+  // On the second pass, go through the HVAs only.

+  if (ArgFlags.isSecArgPass()) {

+    if (ArgFlags.isHva())

+      return CC_X86_VectorCallAssignRegister(ValNo, ValVT, LocVT, LocInfo,

+                                             ArgFlags, State);

+    return true;

+  }

+

+  // Process only vector types as defined by vectorcall spec:

+  // "A vector type is either a floating point type, for example,

+  //  a float or double, or an SIMD vector type, for example, __m128 or __m256".

+  if (!(ValVT.isFloatingPoint() ||

+        (ValVT.isVector() && ValVT.getSizeInBits() >= 128))) {

+    return false;

+  }

+

+  if (ArgFlags.isHva())

+    return true; // If this is an HVA - Stop the search.

+

+  // Assign XMM register.

+  if (unsigned Reg = State.AllocateReg(CC_X86_VectorCallGetSSEs(ValVT))) {

+    State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));

+    return true;

+  }

+

+  // In case we did not find an available XMM register for a vector -

+  // pass it indirectly.

+  // It is similar to CCPassIndirect, with the addition of inreg.

+  if (!ValVT.isFloatingPoint()) {

+    LocVT = MVT::i32;

+    LocInfo = CCValAssign::Indirect;

+    ArgFlags.setInReg();

+  }

+

+  return false; // No register was assigned - Continue the search.

+}

+

+} // End llvm namespace