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authordim <dim@FreeBSD.org>2017-09-26 19:56:36 +0000
committerLuiz Souza <luiz@netgate.com>2018-02-21 15:12:19 -0300
commit1dcd2e8d24b295bc73e513acec2ed1514bb66be4 (patch)
tree4bd13a34c251e980e1a6b13584ca1f63b0dfe670 /contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
parentf45541ca2a56a1ba1202f94c080b04e96c1fa239 (diff)
downloadFreeBSD-src-1dcd2e8d24b295bc73e513acec2ed1514bb66be4.zip
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Merge clang, llvm, lld, lldb, compiler-rt and libc++ 5.0.0 release.
MFC r309126 (by emaste): Correct lld llvm-tblgen dependency file name MFC r309169: Get rid of separate Subversion mergeinfo properties for llvm-dwarfdump and llvm-lto. The mergeinfo confuses Subversion enormously, and these directories will just use the mergeinfo for llvm itself. MFC r312765: Pull in r276136 from upstream llvm trunk (by Wei Mi): Use ValueOffsetPair to enhance value reuse during SCEV expansion. In D12090, the ExprValueMap was added to reuse existing value during SCEV expansion. However, const folding and sext/zext distribution can make the reuse still difficult. A simplified case is: suppose we know S1 expands to V1 in ExprValueMap, and S1 = S2 + C_a S3 = S2 + C_b where C_a and C_b are different SCEVConstants. Then we'd like to expand S3 as V1 - C_a + C_b instead of expanding S2 literally. It is helpful when S2 is a complex SCEV expr and S2 has no entry in ExprValueMap, which is usually caused by the fact that S3 is generated from S1 after const folding. In order to do that, we represent ExprValueMap as a mapping from SCEV to ValueOffsetPair. We will save both S1->{V1, 0} and S2->{V1, C_a} into the ExprValueMap when we create SCEV for V1. When S3 is expanded, it will first expand S2 to V1 - C_a because of S2->{V1, C_a} in the map, then expand S3 to V1 - C_a + C_b. Differential Revision: https://reviews.llvm.org/D21313 This should fix assertion failures when building OpenCV >= 3.1. PR: 215649 MFC r312831: Revert r312765 for now, since it causes assertions when building lang/spidermonkey24. Reported by: antoine PR: 215649 MFC r316511 (by jhb): Add an implementation of __ffssi2() derived from __ffsdi2(). Newer versions of GCC include an __ffssi2() symbol in libgcc and the compiler can emit calls to it in generated code. This is true for at least GCC 6.2 when compiling world for mips and mips64. Reviewed by: jmallett, dim Sponsored by: DARPA / AFRL Differential Revision: https://reviews.freebsd.org/D10086 MFC r318601 (by adrian): [libcompiler-rt] add bswapdi2/bswapsi2 This is required for mips gcc 6.3 userland to build/run. Reviewed by: emaste, dim Approved by: emaste Differential Revision: https://reviews.freebsd.org/D10838 MFC r318884 (by emaste): lldb: map TRAP_CAP to a trace trap In the absense of a more specific handler for TRAP_CAP (generated by ENOTCAPABLE or ECAPMODE while in capability mode) treat it as a trace trap. Example usage (testing the bug in PR219173): % proccontrol -m trapcap lldb usr.bin/hexdump/obj/hexdump -- -Cv -s 1 /bin/ls ... (lldb) run Process 12980 launching Process 12980 launched: '.../usr.bin/hexdump/obj/hexdump' (x86_64) Process 12980 stopped * thread #1, stop reason = trace frame #0: 0x0000004b80c65f1a libc.so.7`__sys_lseek + 10 ... In the future we should have LLDB control the trapcap procctl itself (as it does with ASLR), as well as report a specific stop reason. This change eliminates an assertion failure from LLDB for now. MFC r319796: Remove a few unneeded files from libllvm, libclang and liblldb. MFC r319885 (by emaste): lld: ELF: Fix ICF crash on absolute symbol relocations. If two sections contained relocations to absolute symbols with the same value we would crash when trying to access their sections. Add a check that both symbols point to sections before accessing their sections, and treat absolute symbols as equal if their values are equal. Obtained from: LLD commit r292578 MFC r319918: Revert r319796 for now, it can cause undefined references when linking in some circumstances. Reported by: Shawn Webb <shawn.webb@hardenedbsd.org> MFC r319957 (by emaste): lld: Add armelf emulation mode Obtained from: LLD r305375 MFC r321369: Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ to 5.0.0 (trunk r308421). Upstream has branched for the 5.0.0 release, which should be in about a month. Please report bugs and regressions, so we can get them into the release. Please note that from 3.5.0 onwards, clang, llvm and lldb require C++11 support to build; see UPDATING for more information. MFC r321420: Add a few more object files to liblldb, which should solve errors when linking the lldb executable in some cases. In particular, when the -ffunction-sections -fdata-sections options are turned off, or ineffective. Reported by: Shawn Webb, Mark Millard MFC r321433: Cleanup stale Options.inc files from the previous libllvm build for clang 4.0.0. Otherwise, these can get included before the two newly generated ones (which are different) for clang 5.0.0. Reported by: Mark Millard MFC r321439 (by bdrewery): Move llvm Options.inc hack from r321433 for NO_CLEAN to lib/clang/libllvm. The files are only ever generated to .OBJDIR, not to WORLDTMP (as a sysroot) and are only ever included from a compilation. So using a beforebuild target here removes the file before the compilation tries to include it. MFC r321664: Pull in r308891 from upstream llvm trunk (by Benjamin Kramer): [CodeGenPrepare] Cut off FindAllMemoryUses if there are too many uses. This avoids excessive compile time. The case I'm looking at is Function.cpp from an old version of LLVM that still had the giant memcmp string matcher in it. Before r308322 this compiled in about 2 minutes, after it, clang takes infinite* time to compile it. With this patch we're at 5 min, which is still bad but this is a pathological case. The cut off at 20 uses was chosen by looking at other cut-offs in LLVM for user scanning. It's probably too high, but does the job and is very unlikely to regress anything. Fixes PR33900. * I'm impatient and aborted after 15 minutes, on the bug report it was killed after 2h. Pull in r308986 from upstream llvm trunk (by Simon Pilgrim): [X86][CGP] Reduce memcmp() expansion to 2 load pairs (PR33914) D35067/rL308322 attempted to support up to 4 load pairs for memcmp inlining which resulted in regressions for some optimized libc memcmp implementations (PR33914). Until we can match these more optimal cases, this patch reduces the memcmp expansion to a maximum of 2 load pairs (which matches what we do for -Os). This patch should be considered for the 5.0.0 release branch as well Differential Revision: https://reviews.llvm.org/D35830 These fix a hang (or extremely long compile time) when building older LLVM ports. Reported by: antoine PR: 219139 MFC r321719: Pull in r309503 from upstream clang trunk (by Richard Smith): PR33902: Invalidate line number cache when adding more text to existing buffer. This led to crashes as the line number cache would report a bogus line number for a line of code, and we'd try to find a nonexistent column within the line when printing diagnostics. This fixes an assertion when building the graphics/champlain port. Reported by: antoine, kwm PR: 219139 MFC r321723: Upgrade our copies of clang, llvm, lld and lldb to r309439 from the upstream release_50 branch. This is just after upstream's 5.0.0-rc1. MFC r322320: Upgrade our copies of clang, llvm and libc++ to r310316 from the upstream release_50 branch. MFC r322326 (by emaste): lldb: Make i386-*-freebsd expression work on JIT path * Enable i386 ABI creation for freebsd * Added an extra argument in ABISysV_i386::PrepareTrivialCall for mmap syscall * Unlike linux, the last argument of mmap is actually 64-bit(off_t). This requires us to push an additional word for the higher order bits. * Prior to this change, ktrace dump will show mmap failures due to invalid argument coming from the 6th mmap argument. Submitted by: Karnajit Wangkhem Differential Revision: https://reviews.llvm.org/D34776 MFC r322360 (by emaste): lldb: Report inferior signals as signals, not exceptions, on FreeBSD This is the FreeBSD equivalent of LLVM r238549. This serves 2 purposes: * LLDB should handle inferior process signals SIGSEGV/SIGILL/SIGBUS/ SIGFPE the way it is suppose to be handled. Prior to this fix these signals will neither create a coredump, nor exit from the debugger or work for signal handling scenario. * eInvalidCrashReason need not report "unknown crash reason" if we have a valid si_signo llvm.org/pr23699 Patch by Karnajit Wangkhem Differential Revision: https://reviews.llvm.org/D35223 Submitted by: Karnajit Wangkhem Obtained from: LLVM r310591 MFC r322474 (by emaste): lld: Add `-z muldefs` option. Obtained from: LLVM r310757 MFC r322740: Upgrade our copies of clang, llvm, lld and libc++ to r311219 from the upstream release_50 branch. MFC r322855: Upgrade our copies of clang, llvm, lldb and compiler-rt to r311606 from the upstream release_50 branch. As of this version, lib/msun's trig test should also work correctly again (see bug 220989 for more information). PR: 220989 MFC r323112: Upgrade our copies of clang, llvm, lldb and compiler-rt to r312293 from the upstream release_50 branch. This corresponds to 5.0.0 rc4. As of this version, the cad/stepcode port should now compile in a more reasonable time on i386 (see bug 221836 for more information). PR: 221836 MFC r323245: Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ to 5.0.0 release (upstream r312559). Release notes for llvm, clang and lld will be available here soon: <http://releases.llvm.org/5.0.0/docs/ReleaseNotes.html> <http://releases.llvm.org/5.0.0/tools/clang/docs/ReleaseNotes.html> <http://releases.llvm.org/5.0.0/tools/lld/docs/ReleaseNotes.html> Relnotes: yes (cherry picked from commit 12cd91cf4c6b96a24427c0de5374916f2808d263)
Diffstat (limited to 'contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp')
-rw-r--r--contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp415
1 files changed, 390 insertions, 25 deletions
diff --git a/contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index fe7278f..d75d95a 100644
--- a/contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/contrib/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -7,14 +7,12 @@
//
//===----------------------------------------------------------------------===//
-#define DEBUG_TYPE "hexbit"
-
#include "HexagonBitTracker.h"
#include "HexagonTargetMachine.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
@@ -42,10 +40,23 @@
#include <utility>
#include <vector>
+#define DEBUG_TYPE "hexbit"
+
using namespace llvm;
static cl::opt<bool> PreserveTiedOps("hexbit-keep-tied", cl::Hidden,
cl::init(true), cl::desc("Preserve subregisters in tied operands"));
+static cl::opt<bool> GenExtract("hexbit-extract", cl::Hidden,
+ cl::init(true), cl::desc("Generate extract instructions"));
+static cl::opt<bool> GenBitSplit("hexbit-bitsplit", cl::Hidden,
+ cl::init(true), cl::desc("Generate bitsplit instructions"));
+
+static cl::opt<unsigned> MaxExtract("hexbit-max-extract", cl::Hidden,
+ cl::init(UINT_MAX));
+static unsigned CountExtract = 0;
+static cl::opt<unsigned> MaxBitSplit("hexbit-max-bitsplit", cl::Hidden,
+ cl::init(UINT_MAX));
+static unsigned CountBitSplit = 0;
namespace llvm {
@@ -249,8 +260,6 @@ INITIALIZE_PASS_END(HexagonBitSimplify, "hexbit",
bool HexagonBitSimplify::visitBlock(MachineBasicBlock &B, Transformation &T,
RegisterSet &AVs) {
- MachineDomTreeNode *N = MDT->getNode(&B);
- typedef GraphTraits<MachineDomTreeNode*> GTN;
bool Changed = false;
if (T.TopDown)
@@ -262,10 +271,9 @@ bool HexagonBitSimplify::visitBlock(MachineBasicBlock &B, Transformation &T,
RegisterSet NewAVs = AVs;
NewAVs.insert(Defs);
- for (auto I = GTN::child_begin(N), E = GTN::child_end(N); I != E; ++I) {
- MachineBasicBlock *SB = (*I)->getBlock();
- Changed |= visitBlock(*SB, T, NewAVs);
- }
+ for (auto *DTN : children<MachineDomTreeNode*>(MDT->getNode(&B)))
+ Changed |= visitBlock(*(DTN->getBlock()), T, NewAVs);
+
if (!T.TopDown)
Changed |= T.processBlock(B, AVs);
@@ -399,7 +407,7 @@ bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR,
const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg);
if (RR.Sub == 0) {
Begin = 0;
- Width = RC->getSize()*8;
+ Width = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC);
return true;
}
@@ -409,7 +417,7 @@ bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR,
case Hexagon::DoubleRegsRegClassID:
case Hexagon::VecDblRegsRegClassID:
case Hexagon::VecDblRegs128BRegClassID:
- Width = RC->getSize()*8 / 2;
+ Width = MRI.getTargetRegisterInfo()->getRegSizeInBits(*RC) / 2;
if (RR.Sub == Hexagon::isub_hi || RR.Sub == Hexagon::vsub_hi)
Begin = Width;
break;
@@ -896,6 +904,7 @@ const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
*MRI.getTargetRegisterInfo());
auto VerifySR = [&HRI] (const TargetRegisterClass *RC, unsigned Sub) -> void {
+ (void)HRI;
assert(Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo) ||
Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_hi));
};
@@ -983,9 +992,9 @@ bool DeadCodeElimination::isDead(unsigned R) const {
bool DeadCodeElimination::runOnNode(MachineDomTreeNode *N) {
bool Changed = false;
- typedef GraphTraits<MachineDomTreeNode*> GTN;
- for (auto I = GTN::child_begin(N), E = GTN::child_end(N); I != E; ++I)
- Changed |= runOnNode(*I);
+
+ for (auto *DTN : children<MachineDomTreeNode*>(N))
+ Changed |= runOnNode(DTN);
MachineBasicBlock *B = N->getBlock();
std::vector<MachineInstr*> Instrs;
@@ -1045,8 +1054,8 @@ namespace {
class RedundantInstrElimination : public Transformation {
public:
RedundantInstrElimination(BitTracker &bt, const HexagonInstrInfo &hii,
- MachineRegisterInfo &mri)
- : Transformation(true), HII(hii), MRI(mri), BT(bt) {}
+ const HexagonRegisterInfo &hri, MachineRegisterInfo &mri)
+ : Transformation(true), HII(hii), HRI(hri), MRI(mri), BT(bt) {}
bool processBlock(MachineBasicBlock &B, const RegisterSet &AVs) override;
@@ -1061,6 +1070,7 @@ namespace {
bool usedBitsEqual(BitTracker::RegisterRef RD, BitTracker::RegisterRef RS);
const HexagonInstrInfo &HII;
+ const HexagonRegisterInfo &HRI;
MachineRegisterInfo &MRI;
BitTracker &BT;
};
@@ -1253,7 +1263,7 @@ bool RedundantInstrElimination::computeUsedBits(const MachineInstr &MI,
assert(MI.getOperand(OpN).isReg());
BitTracker::RegisterRef RR = MI.getOperand(OpN);
const TargetRegisterClass *RC = HBS::getFinalVRegClass(RR, MRI);
- uint16_t Width = RC->getSize()*8;
+ uint16_t Width = HRI.getRegSizeInBits(*RC);
if (!GotBits)
T.set(Begin, Begin+Width);
@@ -1735,10 +1745,11 @@ namespace {
// This is by no means complete
class BitSimplification : public Transformation {
public:
- BitSimplification(BitTracker &bt, const HexagonInstrInfo &hii,
- const HexagonRegisterInfo &hri, MachineRegisterInfo &mri,
- MachineFunction &mf)
- : Transformation(true), HII(hii), HRI(hri), MRI(mri), MF(mf), BT(bt) {}
+ BitSimplification(BitTracker &bt, const MachineDominatorTree &mdt,
+ const HexagonInstrInfo &hii, const HexagonRegisterInfo &hri,
+ MachineRegisterInfo &mri, MachineFunction &mf)
+ : Transformation(true), MDT(mdt), HII(hii), HRI(hri), MRI(mri),
+ MF(mf), BT(bt) {}
bool processBlock(MachineBasicBlock &B, const RegisterSet &AVs) override;
@@ -1765,9 +1776,18 @@ namespace {
const BitTracker::RegisterCell &RC);
bool genExtractLow(MachineInstr *MI, BitTracker::RegisterRef RD,
const BitTracker::RegisterCell &RC);
+ bool genBitSplit(MachineInstr *MI, BitTracker::RegisterRef RD,
+ const BitTracker::RegisterCell &RC, const RegisterSet &AVs);
bool simplifyTstbit(MachineInstr *MI, BitTracker::RegisterRef RD,
const BitTracker::RegisterCell &RC);
+ bool simplifyExtractLow(MachineInstr *MI, BitTracker::RegisterRef RD,
+ const BitTracker::RegisterCell &RC, const RegisterSet &AVs);
+ // Cache of created instructions to avoid creating duplicates.
+ // XXX Currently only used by genBitSplit.
+ std::vector<MachineInstr*> NewMIs;
+
+ const MachineDominatorTree &MDT;
const HexagonInstrInfo &HII;
const HexagonRegisterInfo &HRI;
MachineRegisterInfo &MRI;
@@ -1927,8 +1947,10 @@ bool BitSimplification::genStoreImmediate(MachineInstr *MI) {
switch (Opc) {
case Hexagon::S2_storeri_io:
Align++;
+ LLVM_FALLTHROUGH;
case Hexagon::S2_storerh_io:
Align++;
+ LLVM_FALLTHROUGH;
case Hexagon::S2_storerb_io:
break;
default:
@@ -2149,6 +2171,149 @@ bool BitSimplification::genExtractLow(MachineInstr *MI,
return false;
}
+bool BitSimplification::genBitSplit(MachineInstr *MI,
+ BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC,
+ const RegisterSet &AVs) {
+ if (!GenBitSplit)
+ return false;
+ if (MaxBitSplit.getNumOccurrences()) {
+ if (CountBitSplit >= MaxBitSplit)
+ return false;
+ }
+
+ unsigned Opc = MI->getOpcode();
+ switch (Opc) {
+ case Hexagon::A4_bitsplit:
+ case Hexagon::A4_bitspliti:
+ return false;
+ }
+
+ unsigned W = RC.width();
+ if (W != 32)
+ return false;
+
+ auto ctlz = [] (const BitTracker::RegisterCell &C) -> unsigned {
+ unsigned Z = C.width();
+ while (Z > 0 && C[Z-1].is(0))
+ --Z;
+ return C.width() - Z;
+ };
+
+ // Count the number of leading zeros in the target RC.
+ unsigned Z = ctlz(RC);
+ if (Z == 0 || Z == W)
+ return false;
+
+ // A simplistic analysis: assume the source register (the one being split)
+ // is fully unknown, and that all its bits are self-references.
+ const BitTracker::BitValue &B0 = RC[0];
+ if (B0.Type != BitTracker::BitValue::Ref)
+ return false;
+
+ unsigned SrcR = B0.RefI.Reg;
+ unsigned SrcSR = 0;
+ unsigned Pos = B0.RefI.Pos;
+
+ // All the non-zero bits should be consecutive bits from the same register.
+ for (unsigned i = 1; i < W-Z; ++i) {
+ const BitTracker::BitValue &V = RC[i];
+ if (V.Type != BitTracker::BitValue::Ref)
+ return false;
+ if (V.RefI.Reg != SrcR || V.RefI.Pos != Pos+i)
+ return false;
+ }
+
+ // Now, find the other bitfield among AVs.
+ for (unsigned S = AVs.find_first(); S; S = AVs.find_next(S)) {
+ // The number of leading zeros here should be the number of trailing
+ // non-zeros in RC.
+ if (!BT.has(S))
+ continue;
+ const BitTracker::RegisterCell &SC = BT.lookup(S);
+ if (SC.width() != W || ctlz(SC) != W-Z)
+ continue;
+ // The Z lower bits should now match SrcR.
+ const BitTracker::BitValue &S0 = SC[0];
+ if (S0.Type != BitTracker::BitValue::Ref || S0.RefI.Reg != SrcR)
+ continue;
+ unsigned P = S0.RefI.Pos;
+
+ if (Pos <= P && (Pos + W-Z) != P)
+ continue;
+ if (P < Pos && (P + Z) != Pos)
+ continue;
+ // The starting bitfield position must be at a subregister boundary.
+ if (std::min(P, Pos) != 0 && std::min(P, Pos) != 32)
+ continue;
+
+ unsigned I;
+ for (I = 1; I < Z; ++I) {
+ const BitTracker::BitValue &V = SC[I];
+ if (V.Type != BitTracker::BitValue::Ref)
+ break;
+ if (V.RefI.Reg != SrcR || V.RefI.Pos != P+I)
+ break;
+ }
+ if (I != Z)
+ continue;
+
+ // Generate bitsplit where S is defined.
+ if (MaxBitSplit.getNumOccurrences())
+ CountBitSplit++;
+ MachineInstr *DefS = MRI.getVRegDef(S);
+ assert(DefS != nullptr);
+ DebugLoc DL = DefS->getDebugLoc();
+ MachineBasicBlock &B = *DefS->getParent();
+ auto At = DefS->isPHI() ? B.getFirstNonPHI()
+ : MachineBasicBlock::iterator(DefS);
+ if (MRI.getRegClass(SrcR)->getID() == Hexagon::DoubleRegsRegClassID)
+ SrcSR = (std::min(Pos, P) == 32) ? Hexagon::isub_hi : Hexagon::isub_lo;
+ if (!validateReg({SrcR,SrcSR}, Hexagon::A4_bitspliti, 1))
+ continue;
+ unsigned ImmOp = Pos <= P ? W-Z : Z;
+
+ // Find an existing bitsplit instruction if one already exists.
+ unsigned NewR = 0;
+ for (MachineInstr *In : NewMIs) {
+ if (In->getOpcode() != Hexagon::A4_bitspliti)
+ continue;
+ MachineOperand &Op1 = In->getOperand(1);
+ if (Op1.getReg() != SrcR || Op1.getSubReg() != SrcSR)
+ continue;
+ if (In->getOperand(2).getImm() != ImmOp)
+ continue;
+ // Check if the target register is available here.
+ MachineOperand &Op0 = In->getOperand(0);
+ MachineInstr *DefI = MRI.getVRegDef(Op0.getReg());
+ assert(DefI != nullptr);
+ if (!MDT.dominates(DefI, &*At))
+ continue;
+
+ // Found one that can be reused.
+ assert(Op0.getSubReg() == 0);
+ NewR = Op0.getReg();
+ break;
+ }
+ if (!NewR) {
+ NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass);
+ auto NewBS = BuildMI(B, At, DL, HII.get(Hexagon::A4_bitspliti), NewR)
+ .addReg(SrcR, 0, SrcSR)
+ .addImm(ImmOp);
+ NewMIs.push_back(NewBS);
+ }
+ if (Pos <= P) {
+ HBS::replaceRegWithSub(RD.Reg, NewR, Hexagon::isub_lo, MRI);
+ HBS::replaceRegWithSub(S, NewR, Hexagon::isub_hi, MRI);
+ } else {
+ HBS::replaceRegWithSub(S, NewR, Hexagon::isub_lo, MRI);
+ HBS::replaceRegWithSub(RD.Reg, NewR, Hexagon::isub_hi, MRI);
+ }
+ return true;
+ }
+
+ return false;
+}
+
// Check for tstbit simplification opportunity, where the bit being checked
// can be tracked back to another register. For example:
// vreg2 = S2_lsr_i_r vreg1, 5
@@ -2210,6 +2375,203 @@ bool BitSimplification::simplifyTstbit(MachineInstr *MI,
return false;
}
+// Detect whether RD is a bitfield extract (sign- or zero-extended) of
+// some register from the AVs set. Create a new corresponding instruction
+// at the location of MI. The intent is to recognize situations where
+// a sequence of instructions performs an operation that is equivalent to
+// an extract operation, such as a shift left followed by a shift right.
+bool BitSimplification::simplifyExtractLow(MachineInstr *MI,
+ BitTracker::RegisterRef RD, const BitTracker::RegisterCell &RC,
+ const RegisterSet &AVs) {
+ if (!GenExtract)
+ return false;
+ if (MaxExtract.getNumOccurrences()) {
+ if (CountExtract >= MaxExtract)
+ return false;
+ CountExtract++;
+ }
+
+ unsigned W = RC.width();
+ unsigned RW = W;
+ unsigned Len;
+ bool Signed;
+
+ // The code is mostly class-independent, except for the part that generates
+ // the extract instruction, and establishes the source register (in case it
+ // needs to use a subregister).
+ const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI);
+ if (FRC != &Hexagon::IntRegsRegClass && FRC != &Hexagon::DoubleRegsRegClass)
+ return false;
+ assert(RD.Sub == 0);
+
+ // Observation:
+ // If the cell has a form of 00..0xx..x with k zeros and n remaining
+ // bits, this could be an extractu of the n bits, but it could also be
+ // an extractu of a longer field which happens to have 0s in the top
+ // bit positions.
+ // The same logic applies to sign-extended fields.
+ //
+ // Do not check for the extended extracts, since it would expand the
+ // search space quite a bit. The search may be expensive as it is.
+
+ const BitTracker::BitValue &TopV = RC[W-1];
+
+ // Eliminate candidates that have self-referential bits, since they
+ // cannot be extracts from other registers. Also, skip registers that
+ // have compile-time constant values.
+ bool IsConst = true;
+ for (unsigned I = 0; I != W; ++I) {
+ const BitTracker::BitValue &V = RC[I];
+ if (V.Type == BitTracker::BitValue::Ref && V.RefI.Reg == RD.Reg)
+ return false;
+ IsConst = IsConst && (V.is(0) || V.is(1));
+ }
+ if (IsConst)
+ return false;
+
+ if (TopV.is(0) || TopV.is(1)) {
+ bool S = TopV.is(1);
+ for (--W; W > 0 && RC[W-1].is(S); --W)
+ ;
+ Len = W;
+ Signed = S;
+ // The sign bit must be a part of the field being extended.
+ if (Signed)
+ ++Len;
+ } else {
+ // This could still be a sign-extended extract.
+ assert(TopV.Type == BitTracker::BitValue::Ref);
+ if (TopV.RefI.Reg == RD.Reg || TopV.RefI.Pos == W-1)
+ return false;
+ for (--W; W > 0 && RC[W-1] == TopV; --W)
+ ;
+ // The top bits of RC are copies of TopV. One occurrence of TopV will
+ // be a part of the field.
+ Len = W + 1;
+ Signed = true;
+ }
+
+ // This would be just a copy. It should be handled elsewhere.
+ if (Len == RW)
+ return false;
+
+ DEBUG({
+ dbgs() << __func__ << " on reg: " << PrintReg(RD.Reg, &HRI, RD.Sub)
+ << ", MI: " << *MI;
+ dbgs() << "Cell: " << RC << '\n';
+ dbgs() << "Expected bitfield size: " << Len << " bits, "
+ << (Signed ? "sign" : "zero") << "-extended\n";
+ });
+
+ bool Changed = false;
+
+ for (unsigned R = AVs.find_first(); R != 0; R = AVs.find_next(R)) {
+ if (!BT.has(R))
+ continue;
+ const BitTracker::RegisterCell &SC = BT.lookup(R);
+ unsigned SW = SC.width();
+
+ // The source can be longer than the destination, as long as its size is
+ // a multiple of the size of the destination. Also, we would need to be
+ // able to refer to the subregister in the source that would be of the
+ // same size as the destination, but only check the sizes here.
+ if (SW < RW || (SW % RW) != 0)
+ continue;
+
+ // The field can start at any offset in SC as long as it contains Len
+ // bits and does not cross subregister boundary (if the source register
+ // is longer than the destination).
+ unsigned Off = 0;
+ while (Off <= SW-Len) {
+ unsigned OE = (Off+Len)/RW;
+ if (OE != Off/RW) {
+ // The assumption here is that if the source (R) is longer than the
+ // destination, then the destination is a sequence of words of
+ // size RW, and each such word in R can be accessed via a subregister.
+ //
+ // If the beginning and the end of the field cross the subregister
+ // boundary, advance to the next subregister.
+ Off = OE*RW;
+ continue;
+ }
+ if (HBS::isEqual(RC, 0, SC, Off, Len))
+ break;
+ ++Off;
+ }
+
+ if (Off > SW-Len)
+ continue;
+
+ // Found match.
+ unsigned ExtOpc = 0;
+ if (Off == 0) {
+ if (Len == 8)
+ ExtOpc = Signed ? Hexagon::A2_sxtb : Hexagon::A2_zxtb;
+ else if (Len == 16)
+ ExtOpc = Signed ? Hexagon::A2_sxth : Hexagon::A2_zxth;
+ else if (Len < 10 && !Signed)
+ ExtOpc = Hexagon::A2_andir;
+ }
+ if (ExtOpc == 0) {
+ ExtOpc =
+ Signed ? (RW == 32 ? Hexagon::S4_extract : Hexagon::S4_extractp)
+ : (RW == 32 ? Hexagon::S2_extractu : Hexagon::S2_extractup);
+ }
+ unsigned SR = 0;
+ // This only recognizes isub_lo and isub_hi.
+ if (RW != SW && RW*2 != SW)
+ continue;
+ if (RW != SW)
+ SR = (Off/RW == 0) ? Hexagon::isub_lo : Hexagon::isub_hi;
+ Off = Off % RW;
+
+ if (!validateReg({R,SR}, ExtOpc, 1))
+ continue;
+
+ // Don't generate the same instruction as the one being optimized.
+ if (MI->getOpcode() == ExtOpc) {
+ // All possible ExtOpc's have the source in operand(1).
+ const MachineOperand &SrcOp = MI->getOperand(1);
+ if (SrcOp.getReg() == R)
+ continue;
+ }
+
+ DebugLoc DL = MI->getDebugLoc();
+ MachineBasicBlock &B = *MI->getParent();
+ unsigned NewR = MRI.createVirtualRegister(FRC);
+ auto At = MI->isPHI() ? B.getFirstNonPHI()
+ : MachineBasicBlock::iterator(MI);
+ auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR)
+ .addReg(R, 0, SR);
+ switch (ExtOpc) {
+ case Hexagon::A2_sxtb:
+ case Hexagon::A2_zxtb:
+ case Hexagon::A2_sxth:
+ case Hexagon::A2_zxth:
+ break;
+ case Hexagon::A2_andir:
+ MIB.addImm((1u << Len) - 1);
+ break;
+ case Hexagon::S4_extract:
+ case Hexagon::S2_extractu:
+ case Hexagon::S4_extractp:
+ case Hexagon::S2_extractup:
+ MIB.addImm(Len)
+ .addImm(Off);
+ break;
+ default:
+ llvm_unreachable("Unexpected opcode");
+ }
+
+ HBS::replaceReg(RD.Reg, NewR, MRI);
+ BT.put(BitTracker::RegisterRef(NewR), RC);
+ Changed = true;
+ break;
+ }
+
+ return Changed;
+}
+
bool BitSimplification::processBlock(MachineBasicBlock &B,
const RegisterSet &AVs) {
if (!BT.reached(&B))
@@ -2247,12 +2609,15 @@ bool BitSimplification::processBlock(MachineBasicBlock &B,
if (FRC->getID() == Hexagon::DoubleRegsRegClassID) {
bool T = genPackhl(MI, RD, RC);
+ T = T || simplifyExtractLow(MI, RD, RC, AVB);
Changed |= T;
continue;
}
if (FRC->getID() == Hexagon::IntRegsRegClassID) {
- bool T = genExtractHalf(MI, RD, RC);
+ bool T = genBitSplit(MI, RD, RC, AVB);
+ T = T || simplifyExtractLow(MI, RD, RC, AVB);
+ T = T || genExtractHalf(MI, RD, RC);
T = T || genCombineHalf(MI, RD, RC);
T = T || genExtractLow(MI, RD, RC);
Changed |= T;
@@ -2294,7 +2659,7 @@ bool HexagonBitSimplify::runOnMachineFunction(MachineFunction &MF) {
Changed |= visitBlock(Entry, ImmG, AIG);
RegisterSet ARE; // Available registers for RIE.
- RedundantInstrElimination RIE(BT, HII, MRI);
+ RedundantInstrElimination RIE(BT, HII, HRI, MRI);
bool Ried = visitBlock(Entry, RIE, ARE);
if (Ried) {
Changed = true;
@@ -2313,7 +2678,7 @@ bool HexagonBitSimplify::runOnMachineFunction(MachineFunction &MF) {
BT.run();
RegisterSet ABS; // Available registers for BS.
- BitSimplification BitS(BT, HII, HRI, MRI, MF);
+ BitSimplification BitS(BT, *MDT, HII, HRI, MRI, MF);
Changed |= visitBlock(Entry, BitS, ABS);
Changed = DeadCodeElimination(MF, *MDT).run() || Changed;
@@ -2599,7 +2964,7 @@ void HexagonLoopRescheduling::moveGroup(InstrGroup &G, MachineBasicBlock &LB,
for (unsigned j = 0, m = SI->getNumOperands(); j < m; ++j) {
const MachineOperand &Op = SI->getOperand(j);
if (!Op.isReg()) {
- MIB.addOperand(Op);
+ MIB.add(Op);
continue;
}
if (!Op.isUse())
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