diff options
| author | dim <dim@FreeBSD.org> | 2016-12-26 20:36:37 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2016-12-26 20:36:37 +0000 |
| commit | 06210ae42d418d50d8d9365d5c9419308ae9e7ee (patch) | |
| tree | ab60b4cdd6e430dda1f292a46a77ddb744723f31 /contrib/llvm/lib/CodeGen/MachineInstr.cpp | |
| parent | 2dd166267f53df1c3748b4325d294b9b839de74b (diff) | |
| download | FreeBSD-src-06210ae42d418d50d8d9365d5c9419308ae9e7ee.zip FreeBSD-src-06210ae42d418d50d8d9365d5c9419308ae9e7ee.tar.gz | |
MFC r309124:
Upgrade our copies of clang, llvm, lldb, compiler-rt and libc++ to 3.9.0
release, and add lld 3.9.0. Also completely revamp the build system for
clang, llvm, lldb and their related tools.
Please note that from 3.5.0 onwards, clang, llvm and lldb require C++11
support to build; see UPDATING for more information.
Release notes for llvm, clang and lld are available here:
<http://llvm.org/releases/3.9.0/docs/ReleaseNotes.html>
<http://llvm.org/releases/3.9.0/tools/clang/docs/ReleaseNotes.html>
<http://llvm.org/releases/3.9.0/tools/lld/docs/ReleaseNotes.html>
Thanks to Ed Maste, Bryan Drewery, Andrew Turner, Antoine Brodin and Jan
Beich for their help.
Relnotes: yes
MFC r309147:
Pull in r282174 from upstream llvm trunk (by Krzysztof Parzyszek):
[PPC] Set SP after loading data from stack frame, if no red zone is
present
Follow-up to r280705: Make sure that the SP is only restored after
all data is loaded from the stack frame, if there is no red zone.
This completes the fix for
https://llvm.org/bugs/show_bug.cgi?id=26519.
Differential Revision: https://reviews.llvm.org/D24466
Reported by: Mark Millard
PR: 214433
MFC r309149:
Pull in r283060 from upstream llvm trunk (by Hal Finkel):
[PowerPC] Refactor soft-float support, and enable PPC64 soft float
This change enables soft-float for PowerPC64, and also makes
soft-float disable all vector instruction sets for both 32-bit and
64-bit modes. This latter part is necessary because the PPC backend
canonicalizes many Altivec vector types to floating-point types, and
so soft-float breaks scalarization support for many operations. Both
for embedded targets and for operating-system kernels desiring
soft-float support, it seems reasonable that disabling hardware
floating-point also disables vector instructions (embedded targets
without hardware floating point support are unlikely to have Altivec,
etc. and operating system kernels desiring not to use floating-point
registers to lower syscall cost are unlikely to want to use vector
registers either). If someone needs this to work, we'll need to
change the fact that we promote many Altivec operations to act on
v4f32. To make it possible to disable Altivec when soft-float is
enabled, hardware floating-point support needs to be expressed as a
positive feature, like the others, and not a negative feature,
because target features cannot have dependencies on the disabling of
some other feature. So +soft-float has now become -hard-float.
Fixes PR26970.
Pull in r283061 from upstream clang trunk (by Hal Finkel):
[PowerPC] Enable soft-float for PPC64, and +soft-float -> -hard-float
Enable soft-float support on PPC64, as the backend now supports it.
Also, the backend now uses -hard-float instead of +soft-float, so set
the target features accordingly.
Fixes PR26970.
Reported by: Mark Millard
PR: 214433
MFC r309212:
Add a few missed clang 3.9.0 files to OptionalObsoleteFiles.
MFC r309262:
Fix packaging for clang, lldb and lld 3.9.0
During the upgrade of clang/llvm etc to 3.9.0 in r309124, the PACKAGE
directive in the usr.bin/clang/*.mk files got dropped accidentally.
Restore it, with a few minor changes and additions:
* Correct license in clang.ucl to NCSA
* Add PACKAGE=clang for clang and most of the "ll" tools
* Put lldb in its own package
* Put lld in its own package
Reviewed by: gjb, jmallett
Differential Revision: https://reviews.freebsd.org/D8666
MFC r309656:
During the bootstrap phase, when building the minimal llvm library on
PowerPC, add lib/Support/Atomic.cpp. This is needed because upstream
llvm revision r271821 disabled the use of std::call_once, which causes
some fallback functions from Atomic.cpp to be used instead.
Reported by: Mark Millard
PR: 214902
MFC r309835:
Tentatively apply https://reviews.llvm.org/D18730 to work around gcc PR
70528 (bogus error: constructor required before non-static data member).
This should fix buildworld with the external gcc package.
Reported by: https://jenkins.freebsd.org/job/FreeBSD_HEAD_amd64_gcc/
MFC r310194:
Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ to
3.9.1 release.
Please note that from 3.5.0 onwards, clang, llvm and lldb require C++11
support to build; see UPDATING for more information.
Release notes for llvm, clang and lld will be available here:
<http://releases.llvm.org/3.9.1/docs/ReleaseNotes.html>
<http://releases.llvm.org/3.9.1/tools/clang/docs/ReleaseNotes.html>
<http://releases.llvm.org/3.9.1/tools/lld/docs/ReleaseNotes.html>
Relnotes: yes
Diffstat (limited to 'contrib/llvm/lib/CodeGen/MachineInstr.cpp')
| -rw-r--r-- | contrib/llvm/lib/CodeGen/MachineInstr.cpp | 261 |
1 files changed, 205 insertions, 56 deletions
diff --git a/contrib/llvm/lib/CodeGen/MachineInstr.cpp b/contrib/llvm/lib/CodeGen/MachineInstr.cpp index 6dca74d..3cdf8d2 100644 --- a/contrib/llvm/lib/CodeGen/MachineInstr.cpp +++ b/contrib/llvm/lib/CodeGen/MachineInstr.cpp @@ -17,6 +17,7 @@ #include "llvm/Analysis/AliasAnalysis.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineMemOperand.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -372,10 +373,16 @@ void MachineOperand::print(raw_ostream &OS, ModuleSlotTracker &MST, getCImm()->getValue().print(OS, false); break; case MachineOperand::MO_FPImmediate: - if (getFPImm()->getType()->isFloatTy()) + if (getFPImm()->getType()->isFloatTy()) { OS << getFPImm()->getValueAPF().convertToFloat(); - else + } else if (getFPImm()->getType()->isHalfTy()) { + APFloat APF = getFPImm()->getValueAPF(); + bool Unused; + APF.convert(APFloat::IEEEsingle, APFloat::rmNearestTiesToEven, &Unused); + OS << "half " << APF.convertToFloat(); + } else { OS << getFPImm()->getValueAPF().convertToDouble(); + } break; case MachineOperand::MO_MachineBasicBlock: OS << "<BB#" << getMBB()->getNumber() << ">"; @@ -490,13 +497,12 @@ MachinePointerInfo MachinePointerInfo::getStack(MachineFunction &MF, return MachinePointerInfo(MF.getPSVManager().getStack(), Offset); } -MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, unsigned f, +MachineMemOperand::MachineMemOperand(MachinePointerInfo ptrinfo, Flags f, uint64_t s, unsigned int a, const AAMDNodes &AAInfo, const MDNode *Ranges) - : PtrInfo(ptrinfo), Size(s), - Flags((f & ((1 << MOMaxBits) - 1)) | ((Log2_32(a) + 1) << MOMaxBits)), - AAInfo(AAInfo), Ranges(Ranges) { + : PtrInfo(ptrinfo), Size(s), FlagVals(f), BaseAlignLog2(Log2_32(a) + 1), + AAInfo(AAInfo), Ranges(Ranges) { assert((PtrInfo.V.isNull() || PtrInfo.V.is<const PseudoSourceValue*>() || isa<PointerType>(PtrInfo.V.get<const Value*>()->getType())) && "invalid pointer value"); @@ -510,7 +516,8 @@ void MachineMemOperand::Profile(FoldingSetNodeID &ID) const { ID.AddInteger(getOffset()); ID.AddInteger(Size); ID.AddPointer(getOpaqueValue()); - ID.AddInteger(Flags); + ID.AddInteger(getFlags()); + ID.AddInteger(getBaseAlignment()); } void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { @@ -521,8 +528,7 @@ void MachineMemOperand::refineAlignment(const MachineMemOperand *MMO) { if (MMO->getBaseAlignment() >= getBaseAlignment()) { // Update the alignment value. - Flags = (Flags & ((1 << MOMaxBits) - 1)) | - ((Log2_32(MMO->getBaseAlignment()) + 1) << MOMaxBits); + BaseAlignLog2 = Log2_32(MMO->getBaseAlignment()) + 1; // Also update the base and offset, because the new alignment may // not be applicable with the old ones. PtrInfo = MMO->PtrInfo; @@ -647,7 +653,12 @@ MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid, DebugLoc dl, bool NoImp) : MCID(&tid), Parent(nullptr), Operands(nullptr), NumOperands(0), Flags(0), AsmPrinterFlags(0), NumMemRefs(0), MemRefs(nullptr), - debugLoc(std::move(dl)) { + debugLoc(std::move(dl)) +#ifdef LLVM_BUILD_GLOBAL_ISEL + , + Ty(nullptr) +#endif +{ assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor"); // Reserve space for the expected number of operands. @@ -664,10 +675,14 @@ MachineInstr::MachineInstr(MachineFunction &MF, const MCInstrDesc &tid, /// MachineInstr ctor - Copies MachineInstr arg exactly /// MachineInstr::MachineInstr(MachineFunction &MF, const MachineInstr &MI) - : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0), - Flags(0), AsmPrinterFlags(0), - NumMemRefs(MI.NumMemRefs), MemRefs(MI.MemRefs), - debugLoc(MI.getDebugLoc()) { + : MCID(&MI.getDesc()), Parent(nullptr), Operands(nullptr), NumOperands(0), + Flags(0), AsmPrinterFlags(0), NumMemRefs(MI.NumMemRefs), + MemRefs(MI.MemRefs), debugLoc(MI.getDebugLoc()) +#ifdef LLVM_BUILD_GLOBAL_ISEL + , + Ty(nullptr) +#endif +{ assert(debugLoc.hasTrivialDestructor() && "Expected trivial destructor"); CapOperands = OperandCapacity::get(MI.getNumOperands()); @@ -690,6 +705,25 @@ MachineRegisterInfo *MachineInstr::getRegInfo() { return nullptr; } +// Implement dummy setter and getter for type when +// global-isel is not built. +// The proper implementation is WIP and is tracked here: +// PR26576. +#ifndef LLVM_BUILD_GLOBAL_ISEL +void MachineInstr::setType(Type *Ty) {} + +Type *MachineInstr::getType() const { return nullptr; } + +#else +void MachineInstr::setType(Type *Ty) { + assert((!Ty || isPreISelGenericOpcode(getOpcode())) && + "Non generic instructions are not supposed to be typed"); + this->Ty = Ty; +} + +Type *MachineInstr::getType() const { return Ty; } +#endif // LLVM_BUILD_GLOBAL_ISEL + /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in /// this instruction from their respective use lists. This requires that the /// operands already be on their use lists. @@ -867,7 +901,7 @@ void MachineInstr::addMemOperand(MachineFunction &MF, } /// Check to see if the MMOs pointed to by the two MemRefs arrays are -/// identical. +/// identical. static bool hasIdenticalMMOs(const MachineInstr &MI1, const MachineInstr &MI2) { auto I1 = MI1.memoperands_begin(), E1 = MI1.memoperands_end(); auto I2 = MI2.memoperands_begin(), E2 = MI2.memoperands_end(); @@ -894,7 +928,7 @@ MachineInstr::mergeMemRefsWith(const MachineInstr& Other) { // cases in practice. if (hasIdenticalMMOs(*this, Other)) return std::make_pair(MemRefs, NumMemRefs); - + // TODO: consider uniquing elements within the operand lists to reduce // space usage and fall back to conservative information less often. size_t CombinedNumMemRefs = NumMemRefs + Other.NumMemRefs; @@ -913,7 +947,7 @@ MachineInstr::mergeMemRefsWith(const MachineInstr& Other) { MemEnd); assert(MemEnd - MemBegin == (ptrdiff_t)CombinedNumMemRefs && "missing memrefs"); - + return std::make_pair(MemBegin, CombinedNumMemRefs); } @@ -933,23 +967,23 @@ bool MachineInstr::hasPropertyInBundle(unsigned Mask, QueryType Type) const { } } -bool MachineInstr::isIdenticalTo(const MachineInstr *Other, +bool MachineInstr::isIdenticalTo(const MachineInstr &Other, MICheckType Check) const { // If opcodes or number of operands are not the same then the two // instructions are obviously not identical. - if (Other->getOpcode() != getOpcode() || - Other->getNumOperands() != getNumOperands()) + if (Other.getOpcode() != getOpcode() || + Other.getNumOperands() != getNumOperands()) return false; if (isBundle()) { // Both instructions are bundles, compare MIs inside the bundle. MachineBasicBlock::const_instr_iterator I1 = getIterator(); MachineBasicBlock::const_instr_iterator E1 = getParent()->instr_end(); - MachineBasicBlock::const_instr_iterator I2 = Other->getIterator(); - MachineBasicBlock::const_instr_iterator E2= Other->getParent()->instr_end(); + MachineBasicBlock::const_instr_iterator I2 = Other.getIterator(); + MachineBasicBlock::const_instr_iterator E2 = Other.getParent()->instr_end(); while (++I1 != E1 && I1->isInsideBundle()) { ++I2; - if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(&*I2, Check)) + if (I2 == E2 || !I2->isInsideBundle() || !I1->isIdenticalTo(*I2, Check)) return false; } } @@ -957,7 +991,7 @@ bool MachineInstr::isIdenticalTo(const MachineInstr *Other, // Check operands to make sure they match. for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { const MachineOperand &MO = getOperand(i); - const MachineOperand &OMO = Other->getOperand(i); + const MachineOperand &OMO = Other.getOperand(i); if (!MO.isReg()) { if (!MO.isIdenticalTo(OMO)) return false; @@ -990,8 +1024,8 @@ bool MachineInstr::isIdenticalTo(const MachineInstr *Other, } // If DebugLoc does not match then two dbg.values are not identical. if (isDebugValue()) - if (getDebugLoc() && Other->getDebugLoc() && - getDebugLoc() != Other->getDebugLoc()) + if (getDebugLoc() && Other.getDebugLoc() && + getDebugLoc() != Other.getDebugLoc()) return false; return true; } @@ -1130,6 +1164,16 @@ int MachineInstr::findInlineAsmFlagIdx(unsigned OpIdx, return -1; } +const DILocalVariable *MachineInstr::getDebugVariable() const { + assert(isDebugValue() && "not a DBG_VALUE"); + return cast<DILocalVariable>(getOperand(2).getMetadata()); +} + +const DIExpression *MachineInstr::getDebugExpression() const { + assert(isDebugValue() && "not a DBG_VALUE"); + return cast<DIExpression>(getOperand(3).getMetadata()); +} + const TargetRegisterClass* MachineInstr::getRegClassConstraint(unsigned OpIdx, const TargetInstrInfo *TII, @@ -1157,7 +1201,10 @@ MachineInstr::getRegClassConstraint(unsigned OpIdx, unsigned Flag = getOperand(FlagIdx).getImm(); unsigned RCID; - if (InlineAsm::hasRegClassConstraint(Flag, RCID)) + if ((InlineAsm::getKind(Flag) == InlineAsm::Kind_RegUse || + InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDef || + InlineAsm::getKind(Flag) == InlineAsm::Kind_RegDefEarlyClobber) && + InlineAsm::hasRegClassConstraint(Flag, RCID)) return TRI->getRegClass(RCID); // Assume that all registers in a memory operand are pointers. @@ -1173,7 +1220,7 @@ const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg( // Check every operands inside the bundle if we have // been asked to. if (ExploreBundle) - for (ConstMIBundleOperands OpndIt(this); OpndIt.isValid() && CurRC; + for (ConstMIBundleOperands OpndIt(*this); OpndIt.isValid() && CurRC; ++OpndIt) CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl( OpndIt.getOperandNo(), Reg, CurRC, TII, TRI); @@ -1219,11 +1266,24 @@ const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect( unsigned MachineInstr::getBundleSize() const { MachineBasicBlock::const_instr_iterator I = getIterator(); unsigned Size = 0; - while (I->isBundledWithSucc()) - ++Size, ++I; + while (I->isBundledWithSucc()) { + ++Size; + ++I; + } return Size; } +/// Returns true if the MachineInstr has an implicit-use operand of exactly +/// the given register (not considering sub/super-registers). +bool MachineInstr::hasRegisterImplicitUseOperand(unsigned Reg) const { + for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { + const MachineOperand &MO = getOperand(i); + if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg) + return true; + } + return false; +} + /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of /// the specific register or -1 if it is not found. It further tightens /// the search criteria to a use that kills the register if isKill is true. @@ -1498,12 +1558,10 @@ bool MachineInstr::hasOrderedMemoryRef() const { if (memoperands_empty()) return true; - // Check the memory reference information for ordered references. - for (mmo_iterator I = memoperands_begin(), E = memoperands_end(); I != E; ++I) - if (!(*I)->isUnordered()) - return true; - - return false; + // Check if any of our memory operands are ordered. + return any_of(memoperands(), [](const MachineMemOperand *MMO) { + return !MMO->isUnordered(); + }); } /// isInvariantLoad - Return true if this instruction is loading from a @@ -1523,23 +1581,21 @@ bool MachineInstr::isInvariantLoad(AliasAnalysis *AA) const { const MachineFrameInfo *MFI = getParent()->getParent()->getFrameInfo(); - for (mmo_iterator I = memoperands_begin(), - E = memoperands_end(); I != E; ++I) { - if ((*I)->isVolatile()) return false; - if ((*I)->isStore()) return false; - if ((*I)->isInvariant()) return true; - + for (MachineMemOperand *MMO : memoperands()) { + if (MMO->isVolatile()) return false; + if (MMO->isStore()) return false; + if (MMO->isInvariant()) continue; // A load from a constant PseudoSourceValue is invariant. - if (const PseudoSourceValue *PSV = (*I)->getPseudoValue()) + if (const PseudoSourceValue *PSV = MMO->getPseudoValue()) if (PSV->isConstant(MFI)) continue; - if (const Value *V = (*I)->getValue()) { + if (const Value *V = MMO->getValue()) { // If we have an AliasAnalysis, ask it whether the memory is constant. if (AA && AA->pointsToConstantMemory( - MemoryLocation(V, (*I)->getSize(), (*I)->getAAInfo()))) + MemoryLocation(V, MMO->getSize(), MMO->getAAInfo()))) continue; } @@ -1598,16 +1654,16 @@ bool MachineInstr::allDefsAreDead() const { /// copyImplicitOps - Copy implicit register operands from specified /// instruction to this instruction. void MachineInstr::copyImplicitOps(MachineFunction &MF, - const MachineInstr *MI) { - for (unsigned i = MI->getDesc().getNumOperands(), e = MI->getNumOperands(); + const MachineInstr &MI) { + for (unsigned i = MI.getDesc().getNumOperands(), e = MI.getNumOperands(); i != e; ++i) { - const MachineOperand &MO = MI->getOperand(i); + const MachineOperand &MO = MI.getOperand(i); if ((MO.isReg() && MO.isImplicit()) || MO.isRegMask()) addOperand(MF, MO); } } -void MachineInstr::dump() const { +LLVM_DUMP_METHOD void MachineInstr::dump() const { #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) dbgs() << " " << *this; #endif @@ -1651,8 +1707,12 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, if (StartOp != 0) OS << ", "; getOperand(StartOp).print(OS, MST, TRI); unsigned Reg = getOperand(StartOp).getReg(); - if (TargetRegisterInfo::isVirtualRegister(Reg)) + if (TargetRegisterInfo::isVirtualRegister(Reg)) { VirtRegs.push_back(Reg); + unsigned Size; + if (MRI && (Size = MRI->getSize(Reg))) + OS << '(' << Size << ')'; + } } if (StartOp != 0) @@ -1664,6 +1724,12 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, else OS << "UNKNOWN"; + if (getType()) { + OS << ' '; + getType()->print(OS, /*IsForDebug*/ false, /*NoDetails*/ true); + OS << ' '; + } + if (SkipOpers) return; @@ -1686,6 +1752,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, OS << " [mayload]"; if (ExtraInfo & InlineAsm::Extra_MayStore) OS << " [maystore]"; + if (ExtraInfo & InlineAsm::Extra_IsConvergent) + OS << " [isconvergent]"; if (ExtraInfo & InlineAsm::Extra_IsAlignStack) OS << " [alignstack]"; if (getInlineAsmDialect() == InlineAsm::AD_ATT) @@ -1761,13 +1829,41 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, } unsigned RCID = 0; - if (InlineAsm::hasRegClassConstraint(Flag, RCID)) { + if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) && + InlineAsm::hasRegClassConstraint(Flag, RCID)) { if (TRI) { OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID)); } else OS << ":RC" << RCID; } + if (InlineAsm::isMemKind(Flag)) { + unsigned MCID = InlineAsm::getMemoryConstraintID(Flag); + switch (MCID) { + case InlineAsm::Constraint_es: OS << ":es"; break; + case InlineAsm::Constraint_i: OS << ":i"; break; + case InlineAsm::Constraint_m: OS << ":m"; break; + case InlineAsm::Constraint_o: OS << ":o"; break; + case InlineAsm::Constraint_v: OS << ":v"; break; + case InlineAsm::Constraint_Q: OS << ":Q"; break; + case InlineAsm::Constraint_R: OS << ":R"; break; + case InlineAsm::Constraint_S: OS << ":S"; break; + case InlineAsm::Constraint_T: OS << ":T"; break; + case InlineAsm::Constraint_Um: OS << ":Um"; break; + case InlineAsm::Constraint_Un: OS << ":Un"; break; + case InlineAsm::Constraint_Uq: OS << ":Uq"; break; + case InlineAsm::Constraint_Us: OS << ":Us"; break; + case InlineAsm::Constraint_Ut: OS << ":Ut"; break; + case InlineAsm::Constraint_Uv: OS << ":Uv"; break; + case InlineAsm::Constraint_Uy: OS << ":Uy"; break; + case InlineAsm::Constraint_X: OS << ":X"; break; + case InlineAsm::Constraint_Z: OS << ":Z"; break; + case InlineAsm::Constraint_ZC: OS << ":ZC"; break; + case InlineAsm::Constraint_Zy: OS << ":Zy"; break; + default: OS << ":?"; break; + } + } + unsigned TiedTo = 0; if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo)) OS << " tiedto:$" << TiedTo; @@ -1824,11 +1920,18 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, HaveSemi = true; } for (unsigned i = 0; i != VirtRegs.size(); ++i) { - const TargetRegisterClass *RC = MRI->getRegClass(VirtRegs[i]); - OS << " " << TRI->getRegClassName(RC) - << ':' << PrintReg(VirtRegs[i]); + const RegClassOrRegBank &RC = MRI->getRegClassOrRegBank(VirtRegs[i]); + if (!RC) + continue; + // Generic virtual registers do not have register classes. + if (RC.is<const RegisterBank *>()) + OS << " " << RC.get<const RegisterBank *>()->getName(); + else + OS << " " + << TRI->getRegClassName(RC.get<const TargetRegisterClass *>()); + OS << ':' << PrintReg(VirtRegs[i]); for (unsigned j = i+1; j != VirtRegs.size();) { - if (MRI->getRegClass(VirtRegs[j]) != RC) { + if (MRI->getRegClassOrRegBank(VirtRegs[j]) != RC) { ++j; continue; } @@ -1877,6 +1980,13 @@ bool MachineInstr::addRegisterKilled(unsigned IncomingReg, MachineOperand &MO = getOperand(i); if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue; + + // DEBUG_VALUE nodes do not contribute to code generation and should + // always be ignored. Failure to do so may result in trying to modify + // KILL flags on DEBUG_VALUE nodes. + if (MO.isDebug()) + continue; + unsigned Reg = MO.getReg(); if (!Reg) continue; @@ -1932,7 +2042,7 @@ void MachineInstr::clearRegisterKills(unsigned Reg, if (!MO.isReg() || !MO.isUse() || !MO.isKill()) continue; unsigned OpReg = MO.getReg(); - if (OpReg == Reg || (RegInfo && RegInfo->isSuperRegister(Reg, OpReg))) + if ((RegInfo && RegInfo->regsOverlap(Reg, OpReg)) || Reg == OpReg) MO.setIsKill(false); } } @@ -2085,3 +2195,42 @@ void MachineInstr::emitError(StringRef Msg) const { return MF->getMMI().getModule()->getContext().emitError(LocCookie, Msg); report_fatal_error(Msg); } + +MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL, + const MCInstrDesc &MCID, bool IsIndirect, + unsigned Reg, unsigned Offset, + const MDNode *Variable, const MDNode *Expr) { + assert(isa<DILocalVariable>(Variable) && "not a variable"); + assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); + assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && + "Expected inlined-at fields to agree"); + if (IsIndirect) + return BuildMI(MF, DL, MCID) + .addReg(Reg, RegState::Debug) + .addImm(Offset) + .addMetadata(Variable) + .addMetadata(Expr); + else { + assert(Offset == 0 && "A direct address cannot have an offset."); + return BuildMI(MF, DL, MCID) + .addReg(Reg, RegState::Debug) + .addReg(0U, RegState::Debug) + .addMetadata(Variable) + .addMetadata(Expr); + } +} + +MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB, + MachineBasicBlock::iterator I, + const DebugLoc &DL, const MCInstrDesc &MCID, + bool IsIndirect, unsigned Reg, + unsigned Offset, const MDNode *Variable, + const MDNode *Expr) { + assert(isa<DILocalVariable>(Variable) && "not a variable"); + assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); + MachineFunction &MF = *BB.getParent(); + MachineInstr *MI = + BuildMI(MF, DL, MCID, IsIndirect, Reg, Offset, Variable, Expr); + BB.insert(I, MI); + return MachineInstrBuilder(MF, MI); +} |
