diff options
| author | dim <dim@FreeBSD.org> | 2016-12-26 20:36:37 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2016-12-26 20:36:37 +0000 |
| commit | 06210ae42d418d50d8d9365d5c9419308ae9e7ee (patch) | |
| tree | ab60b4cdd6e430dda1f292a46a77ddb744723f31 /contrib/llvm/lib/CodeGen/DFAPacketizer.cpp | |
| parent | 2dd166267f53df1c3748b4325d294b9b839de74b (diff) | |
| download | FreeBSD-src-06210ae42d418d50d8d9365d5c9419308ae9e7ee.zip FreeBSD-src-06210ae42d418d50d8d9365d5c9419308ae9e7ee.tar.gz | |
MFC r309124:
Upgrade our copies of clang, llvm, lldb, compiler-rt and libc++ to 3.9.0
release, and add lld 3.9.0. Also completely revamp the build system for
clang, llvm, lldb and their related tools.
Please note that from 3.5.0 onwards, clang, llvm and lldb require C++11
support to build; see UPDATING for more information.
Release notes for llvm, clang and lld are available here:
<http://llvm.org/releases/3.9.0/docs/ReleaseNotes.html>
<http://llvm.org/releases/3.9.0/tools/clang/docs/ReleaseNotes.html>
<http://llvm.org/releases/3.9.0/tools/lld/docs/ReleaseNotes.html>
Thanks to Ed Maste, Bryan Drewery, Andrew Turner, Antoine Brodin and Jan
Beich for their help.
Relnotes: yes
MFC r309147:
Pull in r282174 from upstream llvm trunk (by Krzysztof Parzyszek):
[PPC] Set SP after loading data from stack frame, if no red zone is
present
Follow-up to r280705: Make sure that the SP is only restored after
all data is loaded from the stack frame, if there is no red zone.
This completes the fix for
https://llvm.org/bugs/show_bug.cgi?id=26519.
Differential Revision: https://reviews.llvm.org/D24466
Reported by: Mark Millard
PR: 214433
MFC r309149:
Pull in r283060 from upstream llvm trunk (by Hal Finkel):
[PowerPC] Refactor soft-float support, and enable PPC64 soft float
This change enables soft-float for PowerPC64, and also makes
soft-float disable all vector instruction sets for both 32-bit and
64-bit modes. This latter part is necessary because the PPC backend
canonicalizes many Altivec vector types to floating-point types, and
so soft-float breaks scalarization support for many operations. Both
for embedded targets and for operating-system kernels desiring
soft-float support, it seems reasonable that disabling hardware
floating-point also disables vector instructions (embedded targets
without hardware floating point support are unlikely to have Altivec,
etc. and operating system kernels desiring not to use floating-point
registers to lower syscall cost are unlikely to want to use vector
registers either). If someone needs this to work, we'll need to
change the fact that we promote many Altivec operations to act on
v4f32. To make it possible to disable Altivec when soft-float is
enabled, hardware floating-point support needs to be expressed as a
positive feature, like the others, and not a negative feature,
because target features cannot have dependencies on the disabling of
some other feature. So +soft-float has now become -hard-float.
Fixes PR26970.
Pull in r283061 from upstream clang trunk (by Hal Finkel):
[PowerPC] Enable soft-float for PPC64, and +soft-float -> -hard-float
Enable soft-float support on PPC64, as the backend now supports it.
Also, the backend now uses -hard-float instead of +soft-float, so set
the target features accordingly.
Fixes PR26970.
Reported by: Mark Millard
PR: 214433
MFC r309212:
Add a few missed clang 3.9.0 files to OptionalObsoleteFiles.
MFC r309262:
Fix packaging for clang, lldb and lld 3.9.0
During the upgrade of clang/llvm etc to 3.9.0 in r309124, the PACKAGE
directive in the usr.bin/clang/*.mk files got dropped accidentally.
Restore it, with a few minor changes and additions:
* Correct license in clang.ucl to NCSA
* Add PACKAGE=clang for clang and most of the "ll" tools
* Put lldb in its own package
* Put lld in its own package
Reviewed by: gjb, jmallett
Differential Revision: https://reviews.freebsd.org/D8666
MFC r309656:
During the bootstrap phase, when building the minimal llvm library on
PowerPC, add lib/Support/Atomic.cpp. This is needed because upstream
llvm revision r271821 disabled the use of std::call_once, which causes
some fallback functions from Atomic.cpp to be used instead.
Reported by: Mark Millard
PR: 214902
MFC r309835:
Tentatively apply https://reviews.llvm.org/D18730 to work around gcc PR
70528 (bogus error: constructor required before non-static data member).
This should fix buildworld with the external gcc package.
Reported by: https://jenkins.freebsd.org/job/FreeBSD_HEAD_amd64_gcc/
MFC r310194:
Upgrade our copies of clang, llvm, lld, lldb, compiler-rt and libc++ to
3.9.1 release.
Please note that from 3.5.0 onwards, clang, llvm and lldb require C++11
support to build; see UPDATING for more information.
Release notes for llvm, clang and lld will be available here:
<http://releases.llvm.org/3.9.1/docs/ReleaseNotes.html>
<http://releases.llvm.org/3.9.1/tools/clang/docs/ReleaseNotes.html>
<http://releases.llvm.org/3.9.1/tools/lld/docs/ReleaseNotes.html>
Relnotes: yes
Diffstat (limited to 'contrib/llvm/lib/CodeGen/DFAPacketizer.cpp')
| -rw-r--r-- | contrib/llvm/lib/CodeGen/DFAPacketizer.cpp | 183 |
1 files changed, 117 insertions, 66 deletions
diff --git a/contrib/llvm/lib/CodeGen/DFAPacketizer.cpp b/contrib/llvm/lib/CodeGen/DFAPacketizer.cpp index af6b6a3..2386af9 100644 --- a/contrib/llvm/lib/CodeGen/DFAPacketizer.cpp +++ b/contrib/llvm/lib/CodeGen/DFAPacketizer.cpp @@ -23,12 +23,15 @@ // //===----------------------------------------------------------------------===// +#define DEBUG_TYPE "packets" + #include "llvm/CodeGen/DFAPacketizer.h" #include "llvm/CodeGen/MachineInstr.h" #include "llvm/CodeGen/MachineInstrBundle.h" #include "llvm/CodeGen/ScheduleDAGInstrs.h" #include "llvm/MC/MCInstrItineraries.h" #include "llvm/Target/TargetInstrInfo.h" + using namespace llvm; // -------------------------------------------------------------------- @@ -44,8 +47,8 @@ namespace { /// DFAPacketizerEmitter.cpp. DFAInput getDFAInsnInput(const std::vector<unsigned> &InsnClass) { DFAInput InsnInput = 0; - assert ((InsnClass.size() <= DFA_MAX_RESTERMS) && - "Exceeded maximum number of DFA terms"); + assert((InsnClass.size() <= DFA_MAX_RESTERMS) && + "Exceeded maximum number of DFA terms"); for (auto U : InsnClass) InsnInput = addDFAFuncUnits(InsnInput, U); return InsnInput; @@ -59,15 +62,16 @@ DFAPacketizer::DFAPacketizer(const InstrItineraryData *I, InstrItins(I), CurrentState(0), DFAStateInputTable(SIT), DFAStateEntryTable(SET) { // Make sure DFA types are large enough for the number of terms & resources. - assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAInput)) - && "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAInput"); - assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAStateInput)) - && "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput"); + static_assert((DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= + (8 * sizeof(DFAInput)), + "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAInput"); + static_assert( + (DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) <= (8 * sizeof(DFAStateInput)), + "(DFA_MAX_RESTERMS * DFA_MAX_RESOURCES) too big for DFAStateInput"); } -// -// ReadTable - Read the DFA transition table and update CachedTable. +// Read the DFA transition table and update CachedTable. // // Format of the transition tables: // DFAStateInputTable[][2] = pairs of <Input, Transition> for all valid @@ -80,8 +84,7 @@ void DFAPacketizer::ReadTable(unsigned int state) { unsigned NextStateInTable = DFAStateEntryTable[state+1]; // Early exit in case CachedTable has already contains this // state's transitions. - if (CachedTable.count(UnsignPair(state, - DFAStateInputTable[ThisState][0]))) + if (CachedTable.count(UnsignPair(state, DFAStateInputTable[ThisState][0]))) return; for (unsigned i = ThisState; i < NextStateInTable; i++) @@ -89,38 +92,41 @@ void DFAPacketizer::ReadTable(unsigned int state) { DFAStateInputTable[i][1]; } -// -// getInsnInput - Return the DFAInput for an instruction class. -// + +// Return the DFAInput for an instruction class. DFAInput DFAPacketizer::getInsnInput(unsigned InsnClass) { // Note: this logic must match that in DFAPacketizerDefs.h for input vectors. DFAInput InsnInput = 0; unsigned i = 0; + (void)i; for (const InstrStage *IS = InstrItins->beginStage(InsnClass), - *IE = InstrItins->endStage(InsnClass); IS != IE; ++IS, ++i) { + *IE = InstrItins->endStage(InsnClass); IS != IE; ++IS) { InsnInput = addDFAFuncUnits(InsnInput, IS->getUnits()); - assert ((i < DFA_MAX_RESTERMS) && "Exceeded maximum number of DFA inputs"); + assert((i++ < DFA_MAX_RESTERMS) && "Exceeded maximum number of DFA inputs"); } return InsnInput; } -// getInsnInput - Return the DFAInput for an instruction class input vector. + +// Return the DFAInput for an instruction class input vector. DFAInput DFAPacketizer::getInsnInput(const std::vector<unsigned> &InsnClass) { return getDFAInsnInput(InsnClass); } -// canReserveResources - Check if the resources occupied by a MCInstrDesc -// are available in the current state. + +// Check if the resources occupied by a MCInstrDesc are available in the +// current state. bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) { unsigned InsnClass = MID->getSchedClass(); DFAInput InsnInput = getInsnInput(InsnClass); UnsignPair StateTrans = UnsignPair(CurrentState, InsnInput); ReadTable(CurrentState); - return (CachedTable.count(StateTrans) != 0); + return CachedTable.count(StateTrans) != 0; } -// reserveResources - Reserve the resources occupied by a MCInstrDesc and -// change the current state to reflect that change. + +// Reserve the resources occupied by a MCInstrDesc and change the current +// state to reflect that change. void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) { unsigned InsnClass = MID->getSchedClass(); DFAInput InsnInput = getInsnInput(InsnClass); @@ -131,34 +137,46 @@ void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) { } -// canReserveResources - Check if the resources occupied by a machine -// instruction are available in the current state. -bool DFAPacketizer::canReserveResources(llvm::MachineInstr *MI) { - const llvm::MCInstrDesc &MID = MI->getDesc(); +// Check if the resources occupied by a machine instruction are available +// in the current state. +bool DFAPacketizer::canReserveResources(llvm::MachineInstr &MI) { + const llvm::MCInstrDesc &MID = MI.getDesc(); return canReserveResources(&MID); } -// reserveResources - Reserve the resources occupied by a machine -// instruction and change the current state to reflect that change. -void DFAPacketizer::reserveResources(llvm::MachineInstr *MI) { - const llvm::MCInstrDesc &MID = MI->getDesc(); + +// Reserve the resources occupied by a machine instruction and change the +// current state to reflect that change. +void DFAPacketizer::reserveResources(llvm::MachineInstr &MI) { + const llvm::MCInstrDesc &MID = MI.getDesc(); reserveResources(&MID); } + namespace llvm { -// DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides -// Schedule method to build the dependence graph. +// This class extends ScheduleDAGInstrs and overrides the schedule method +// to build the dependence graph. class DefaultVLIWScheduler : public ScheduleDAGInstrs { private: AliasAnalysis *AA; + /// Ordered list of DAG postprocessing steps. + std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations; public: DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA); - // Schedule - Actual scheduling work. + // Actual scheduling work. void schedule() override; + + /// DefaultVLIWScheduler takes ownership of the Mutation object. + void addMutation(std::unique_ptr<ScheduleDAGMutation> Mutation) { + Mutations.push_back(std::move(Mutation)); + } +protected: + void postprocessDAG(); }; } + DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI, AliasAnalysis *AA) @@ -166,42 +184,51 @@ DefaultVLIWScheduler::DefaultVLIWScheduler(MachineFunction &MF, CanHandleTerminators = true; } + +/// Apply each ScheduleDAGMutation step in order. +void DefaultVLIWScheduler::postprocessDAG() { + for (auto &M : Mutations) + M->apply(this); +} + + void DefaultVLIWScheduler::schedule() { // Build the scheduling graph. buildSchedGraph(AA); + postprocessDAG(); } -// VLIWPacketizerList Ctor -VLIWPacketizerList::VLIWPacketizerList(MachineFunction &MF, - MachineLoopInfo &MLI, AliasAnalysis *AA) - : MF(MF), AA(AA) { - TII = MF.getSubtarget().getInstrInfo(); + +VLIWPacketizerList::VLIWPacketizerList(MachineFunction &mf, + MachineLoopInfo &mli, AliasAnalysis *aa) + : MF(mf), TII(mf.getSubtarget().getInstrInfo()), AA(aa) { ResourceTracker = TII->CreateTargetScheduleState(MF.getSubtarget()); - VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, AA); + VLIWScheduler = new DefaultVLIWScheduler(MF, mli, AA); } -// VLIWPacketizerList Dtor + VLIWPacketizerList::~VLIWPacketizerList() { if (VLIWScheduler) delete VLIWScheduler; - if (ResourceTracker) delete ResourceTracker; } -// endPacket - End the current packet, bundle packet instructions and reset -// DFA state. + +// End the current packet, bundle packet instructions and reset DFA state. void VLIWPacketizerList::endPacket(MachineBasicBlock *MBB, - MachineInstr *MI) { + MachineBasicBlock::iterator MI) { if (CurrentPacketMIs.size() > 1) { - MachineInstr *MIFirst = CurrentPacketMIs.front(); - finalizeBundle(*MBB, MIFirst->getIterator(), MI->getIterator()); + MachineInstr &MIFirst = *CurrentPacketMIs.front(); + finalizeBundle(*MBB, MIFirst.getIterator(), MI.getInstrIterator()); } CurrentPacketMIs.clear(); ResourceTracker->clearResources(); + DEBUG(dbgs() << "End packet\n"); } -// PacketizeMIs - Bundle machine instructions into packets. + +// Bundle machine instructions into packets. void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB, MachineBasicBlock::iterator BeginItr, MachineBasicBlock::iterator EndItr) { @@ -211,64 +238,88 @@ void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB, std::distance(BeginItr, EndItr)); VLIWScheduler->schedule(); + DEBUG({ + dbgs() << "Scheduling DAG of the packetize region\n"; + for (SUnit &SU : VLIWScheduler->SUnits) + SU.dumpAll(VLIWScheduler); + }); + // Generate MI -> SU map. MIToSUnit.clear(); - for (unsigned i = 0, e = VLIWScheduler->SUnits.size(); i != e; ++i) { - SUnit *SU = &VLIWScheduler->SUnits[i]; - MIToSUnit[SU->getInstr()] = SU; - } + for (SUnit &SU : VLIWScheduler->SUnits) + MIToSUnit[SU.getInstr()] = &SU; // The main packetizer loop. for (; BeginItr != EndItr; ++BeginItr) { - MachineInstr *MI = BeginItr; - - this->initPacketizerState(); + MachineInstr &MI = *BeginItr; + initPacketizerState(); // End the current packet if needed. - if (this->isSoloInstruction(MI)) { + if (isSoloInstruction(MI)) { endPacket(MBB, MI); continue; } // Ignore pseudo instructions. - if (this->ignorePseudoInstruction(MI, MBB)) + if (ignorePseudoInstruction(MI, MBB)) continue; - SUnit *SUI = MIToSUnit[MI]; + SUnit *SUI = MIToSUnit[&MI]; assert(SUI && "Missing SUnit Info!"); // Ask DFA if machine resource is available for MI. + DEBUG(dbgs() << "Checking resources for adding MI to packet " << MI); + bool ResourceAvail = ResourceTracker->canReserveResources(MI); + DEBUG({ + if (ResourceAvail) + dbgs() << " Resources are available for adding MI to packet\n"; + else + dbgs() << " Resources NOT available\n"; + }); if (ResourceAvail && shouldAddToPacket(MI)) { // Dependency check for MI with instructions in CurrentPacketMIs. - for (std::vector<MachineInstr*>::iterator VI = CurrentPacketMIs.begin(), - VE = CurrentPacketMIs.end(); VI != VE; ++VI) { - MachineInstr *MJ = *VI; + for (auto MJ : CurrentPacketMIs) { SUnit *SUJ = MIToSUnit[MJ]; assert(SUJ && "Missing SUnit Info!"); + DEBUG(dbgs() << " Checking against MJ " << *MJ); // Is it legal to packetize SUI and SUJ together. - if (!this->isLegalToPacketizeTogether(SUI, SUJ)) { + if (!isLegalToPacketizeTogether(SUI, SUJ)) { + DEBUG(dbgs() << " Not legal to add MI, try to prune\n"); // Allow packetization if dependency can be pruned. - if (!this->isLegalToPruneDependencies(SUI, SUJ)) { + if (!isLegalToPruneDependencies(SUI, SUJ)) { // End the packet if dependency cannot be pruned. + DEBUG(dbgs() << " Could not prune dependencies for adding MI\n"); endPacket(MBB, MI); break; - } // !isLegalToPruneDependencies. - } // !isLegalToPacketizeTogether. - } // For all instructions in CurrentPacketMIs. + } + DEBUG(dbgs() << " Pruned dependence for adding MI\n"); + } + } } else { + DEBUG(if (ResourceAvail) + dbgs() << "Resources are available, but instruction should not be " + "added to packet\n " << MI); // End the packet if resource is not available, or if the instruction // shoud not be added to the current packet. endPacket(MBB, MI); } // Add MI to the current packet. - BeginItr = this->addToPacket(MI); - } // For all instructions in BB. + DEBUG(dbgs() << "* Adding MI to packet " << MI << '\n'); + BeginItr = addToPacket(MI); + } // For all instructions in the packetization range. // End any packet left behind. endPacket(MBB, EndItr); VLIWScheduler->exitRegion(); VLIWScheduler->finishBlock(); } + + +// Add a DAG mutation object to the ordered list. +void VLIWPacketizerList::addMutation( + std::unique_ptr<ScheduleDAGMutation> Mutation) { + VLIWScheduler->addMutation(std::move(Mutation)); +} |
