Gcc 3.2.1-prerelease from the FSF anoncvs repo gcc-3_2-branch on 1-Sep-2002 00:00:01 EDT.

38 files changed, 1857 insertions, 620 deletions

diff --git a/contrib/gcc/config/alpha/alpha.c b/contrib/gcc/config/alpha/alpha.c
index c91e68c..3bc8e4d 100644
--- a/contrib/gcc/config/alpha/alpha.c
+++ b/contrib/gcc/config/alpha/alpha.c
@@ -1664,7 +1664,11 @@ alpha_encode_section_info (decl)
       XSTR (XEXP (DECL_RTL (decl), 0), 0) = string;
     }
   else if (symbol_str[0] == '@')
-    abort ();
+    {
+      /* We're hosed.  This can happen when the user adds a weak
+	 attribute after rtl generation.  They should have gotten
+	 a warning about unspecified behaviour from varasm.c.  */
+    }
 }
 
 /* legitimate_address_p recognizes an RTL expression that is a valid
diff --git a/contrib/gcc/config/alpha/alpha.h b/contrib/gcc/config/alpha/alpha.h
index b2363bc..4410a86 100644
--- a/contrib/gcc/config/alpha/alpha.h
+++ b/contrib/gcc/config/alpha/alpha.h
@@ -1224,42 +1224,6 @@ extern struct alpha_compare alpha_compare;
 
 #define FUNCTION_PROFILER(FILE, LABELNO)
 
-/* Output assembler code to FILE to initialize this source file's
-   basic block profiling info, if that has not already been done.
-   This assumes that __bb_init_func doesn't garble a1-a5.  */
-
-#define FUNCTION_BLOCK_PROFILER(FILE, LABELNO)			\
-    do {							\
-	ASM_OUTPUT_REG_PUSH (FILE, 16);				\
-	fputs ("\tlda $16,$PBX32\n", (FILE));			\
-	fputs ("\tldq $26,0($16)\n", (FILE));			\
-	fputs ("\tbne $26,1f\n", (FILE));			\
-	fputs ("\tlda $27,__bb_init_func\n", (FILE));		\
-	fputs ("\tjsr $26,($27),__bb_init_func\n", (FILE));	\
-	fputs ("\tldgp $29,0($26)\n", (FILE));			\
-	fputs ("1:\n", (FILE));					\
-	ASM_OUTPUT_REG_POP (FILE, 16);				\
-    } while (0);
-
-/* Output assembler code to FILE to increment the entry-count for
-   the BLOCKNO'th basic block in this source file.  */
-
-#define BLOCK_PROFILER(FILE, BLOCKNO)				\
-    do {							\
-	int blockn = (BLOCKNO);					\
-	fputs ("\tsubq $30,16,$30\n", (FILE));			\
-	fputs ("\tstq $26,0($30)\n", (FILE));			\
-	fputs ("\tstq $27,8($30)\n", (FILE));			\
-	fputs ("\tlda $26,$PBX34\n", (FILE));			\
-	fprintf ((FILE), "\tldq $27,%d($26)\n", 8*blockn);	\
-	fputs ("\taddq $27,1,$27\n", (FILE));			\
-	fprintf ((FILE), "\tstq $27,%d($26)\n", 8*blockn);	\
-	fputs ("\tldq $26,0($30)\n", (FILE));			\
-	fputs ("\tldq $27,8($30)\n", (FILE));			\
-	fputs ("\taddq $30,16,$30\n", (FILE));			\
-    } while (0)
-
-
 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
    the stack pointer does not matter.  The value is tested only in
    functions that have frame pointers.
diff --git a/contrib/gcc/config/alpha/elf.h b/contrib/gcc/config/alpha/elf.h
index 05853c2..9f8d808 100644
--- a/contrib/gcc/config/alpha/elf.h
+++ b/contrib/gcc/config/alpha/elf.h
@@ -165,7 +165,7 @@ do {									\
     }									\
   ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT));	\
   ASM_OUTPUT_LABEL(FILE, NAME);						\
-  ASM_OUTPUT_SKIP((FILE), (SIZE));					\
+  ASM_OUTPUT_SKIP((FILE), (SIZE) ? (SIZE) : 1);				\
 } while (0)
 
 /* This says how to output assembler code to declare an
diff --git a/contrib/gcc/config/alpha/netbsd.h b/contrib/gcc/config/alpha/netbsd.h
index e5551da..9a54c3a 100644
--- a/contrib/gcc/config/alpha/netbsd.h
+++ b/contrib/gcc/config/alpha/netbsd.h
@@ -24,7 +24,7 @@ Boston, MA 02111-1307, USA.  */
 
 #undef CPP_PREDEFINES
 #define CPP_PREDEFINES							\
-  "-D__NetBSD__ -D__ELF__ -Asystem=unix -Asystem=NetBSD"
+  "-D__NetBSD__ -D__ELF__ -D_LP64 -Asystem=unix -Asystem=NetBSD"
 
 
 /* Show that we need a GP when profiling.  */
diff --git a/contrib/gcc/config/alpha/unicosmk.h b/contrib/gcc/config/alpha/unicosmk.h
index 65ab319..6dbe1a3 100644
--- a/contrib/gcc/config/alpha/unicosmk.h
+++ b/contrib/gcc/config/alpha/unicosmk.h
@@ -574,6 +574,30 @@ ssib_section ()			\
 #ifndef REAL_ARITHMETIC
 #define REAL_VALUE_ATOF(x,s) atof(x)
 #define REAL_VALUE_HTOF(x,s) atof(x)
+
+#define REAL_VALUE_TO_TARGET_SINGLE(IN, OUT)			\
+do {								\
+  union {							\
+    float f;							\
+    HOST_WIDE_INT l;						\
+  } u;								\
+								\
+  u.f = (IN);							\
+  (OUT) = (u.l >> 32) & 0xFFFFFFFF;				\
+} while (0) 
+
+#define REAL_VALUE_TO_TARGET_DOUBLE(IN, OUT)			\
+do {								\
+  union {							\
+    REAL_VALUE_TYPE f;						\
+    HOST_WIDE_INT l;						\
+  } u;								\
+								\
+  u.f = (IN);							\
+  (OUT)[0] = (u.l >> 32) & 0xFFFFFFFF;				\
+  (OUT)[1] = (u.l & 0xFFFFFFFF);				\
+} while (0)
+
 #endif
 
 #undef NM_FLAGS
diff --git a/contrib/gcc/config/arm/arm.c b/contrib/gcc/config/arm/arm.c
index 4ef7279..f07a281 100644
--- a/contrib/gcc/config/arm/arm.c
+++ b/contrib/gcc/config/arm/arm.c
@@ -4544,8 +4544,8 @@ arm_gen_movstrqi (operands)
 	  RTX_UNCHANGING_P (mem) = dst_unchanging_p;
 	  MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
 	  MEM_SCALAR_P (mem) = dst_scalar_p;
-	  emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));
-	  
+	  emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
+
 	  if (--last_bytes)
 	    {
 	      tmp = gen_reg_rtx (SImode);
@@ -4563,7 +4563,7 @@ arm_gen_movstrqi (operands)
 	  RTX_UNCHANGING_P (mem) = dst_unchanging_p;
 	  MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
 	  MEM_SCALAR_P (mem) = dst_scalar_p;
-	  emit_move_insn (mem, gen_rtx_SUBREG (HImode, part_bytes_reg, 0));
+	  emit_move_insn (mem, gen_lowpart (HImode, part_bytes_reg));
 	  last_bytes -= 2;
 	  if (last_bytes)
 	    {
@@ -4581,7 +4581,7 @@ arm_gen_movstrqi (operands)
 	  RTX_UNCHANGING_P (mem) = dst_unchanging_p;
 	  MEM_IN_STRUCT_P (mem) = dst_in_struct_p;
 	  MEM_SCALAR_P (mem) = dst_scalar_p;
-	  emit_move_insn (mem, gen_rtx_SUBREG (QImode, part_bytes_reg, 0));	  
+	  emit_move_insn (mem, gen_lowpart (QImode, part_bytes_reg));
 	}
     }
 
@@ -5119,23 +5119,23 @@ arm_reload_out_hi (operands)
     {
       emit_insn (gen_movqi (gen_rtx_MEM (QImode, 
 					 plus_constant (base, offset + 1)),
-			    gen_rtx_SUBREG (QImode, outval, 0)));
+			    gen_lowpart (QImode, outval)));
       emit_insn (gen_lshrsi3 (scratch,
 			      gen_rtx_SUBREG (SImode, outval, 0),
 			      GEN_INT (8)));
       emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
-			    gen_rtx_SUBREG (QImode, scratch, 0)));
+			    gen_lowpart (QImode, scratch)));
     }
   else
     {
       emit_insn (gen_movqi (gen_rtx_MEM (QImode, plus_constant (base, offset)),
-			    gen_rtx_SUBREG (QImode, outval, 0)));
+			    gen_lowpart (QImode, outval)));
       emit_insn (gen_lshrsi3 (scratch,
 			      gen_rtx_SUBREG (SImode, outval, 0),
 			      GEN_INT (8)));
       emit_insn (gen_movqi (gen_rtx_MEM (QImode,
 					 plus_constant (base, offset + 1)),
-			    gen_rtx_SUBREG (QImode, scratch, 0)));
+			    gen_lowpart (QImode, scratch)));
     }
 }
 
diff --git a/contrib/gcc/config/arm/arm.md b/contrib/gcc/config/arm/arm.md
index 91bbf61..b901504 100644
--- a/contrib/gcc/config/arm/arm.md
+++ b/contrib/gcc/config/arm/arm.md
@@ -3390,7 +3390,7 @@
   [(set (match_operand:SI 0 "s_register_operand" "")
 	(zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 0)))
    (clobber (match_operand:SI 2 "s_register_operand" ""))]
-  "TARGET_ARM && (GET_CODE (operands[1]) != MEM)"
+  "TARGET_ARM && (GET_CODE (operands[1]) != MEM) && ! BYTES_BIG_ENDIAN"
   [(set (match_dup 2) (match_dup 1))
    (set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
   ""
@@ -4288,7 +4288,7 @@
   [(set (match_dup 4) (match_dup 3))
    (set (match_dup 2)
 	(ashiftrt:SI (match_operand 0 "" "") (const_int 8)))
-   (set (match_operand 1 "" "")	(subreg:QI (match_dup 2) 0))]
+   (set (match_operand 1 "" "")	(subreg:QI (match_dup 2) 3))]
   "TARGET_ARM"
   "
   {
@@ -4312,7 +4312,7 @@
 (define_expand "storeinthi"
   [(set (match_operand 0 "" "")
 	(subreg:QI (match_operand 1 "" "") 0))
-   (set (match_dup 3) (subreg:QI (match_dup 2) 0))]
+   (set (match_dup 3) (match_dup 2))]
   "TARGET_ARM"
   "
   {
@@ -4351,6 +4351,7 @@
 
     operands[3] = adjust_address (op0, QImode, 1);
     operands[0] = adjust_address (operands[0], QImode, 0);
+    operands[2] = gen_lowpart (QImode, operands[2]);
   }"
 )
 
@@ -4413,7 +4414,7 @@
 	        }
 
 	      emit_insn (gen_movsi (reg, GEN_INT (val)));
-	      operands[1] = gen_rtx_SUBREG (HImode, reg, 0);
+	      operands[1] = gen_lowpart (HImode, reg);
 	    }
           else if (!arm_arch4)
 	    {
@@ -4810,7 +4811,7 @@
 	      rtx reg = gen_reg_rtx (SImode);
 
 	      emit_insn (gen_movsi (reg, operands[1]));
-	      operands[1] = gen_rtx_SUBREG (QImode, reg, 0);
+	      operands[1] = gen_lowpart (QImode, reg);
 	    }
          if (GET_CODE (operands[0]) == MEM)
 	   operands[1] = force_reg (QImode, operands[1]);
@@ -4853,7 +4854,7 @@
           if (GET_CODE (operands[0]) != REG)
 	    abort ();
 
-          operands[0] = gen_rtx (SUBREG, SImode, operands[0], 0);
+          operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
           emit_insn (gen_movsi (operands[0], operands[1]));
           DONE;
        }
diff --git a/contrib/gcc/config/i386/i386-protos.h b/contrib/gcc/config/i386/i386-protos.h
index 8321d47..03de4b1 100644
--- a/contrib/gcc/config/i386/i386-protos.h
+++ b/contrib/gcc/config/i386/i386-protos.h
@@ -33,9 +33,6 @@ extern HOST_WIDE_INT ix86_initial_elimination_offset PARAMS((int, int));
 extern void ix86_expand_prologue PARAMS ((void));
 extern void ix86_expand_epilogue PARAMS ((int));
 
-extern void ix86_output_function_block_profiler PARAMS ((FILE *, int));
-extern void ix86_output_block_profiler PARAMS ((FILE *, int));
-
 extern void ix86_output_addr_vec_elt PARAMS ((FILE *, int));
 extern void ix86_output_addr_diff_elt PARAMS ((FILE *, int, int));
 
@@ -197,4 +194,6 @@ extern tree ix86_handle_shared_attribute PARAMS ((tree *, tree, tree, int, bool
 extern unsigned int i386_pe_section_type_flags PARAMS ((tree, const char *,
 							int));
 extern void i386_pe_asm_named_section PARAMS ((const char *, unsigned int));
+extern void x86_output_mi_thunk PARAMS ((FILE *, int, tree));
+extern int x86_field_alignment PARAMS ((tree, int));
 #endif
diff --git a/contrib/gcc/config/i386/i386.c b/contrib/gcc/config/i386/i386.c
index bc3f456..f07ebad 100644
--- a/contrib/gcc/config/i386/i386.c
+++ b/contrib/gcc/config/i386/i386.c
@@ -457,7 +457,7 @@ static int const x86_64_int_return_registers[4] = {0 /*RAX*/, 1 /*RDI*/, 5, 4};
 int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
 {
   0, 1, 2, 3, 4, 5, 6, 7,		/* general regs */
-  33, 34, 35, 36, 37, 38, 39, 40	/* fp regs */
+  33, 34, 35, 36, 37, 38, 39, 40,	/* fp regs */
   -1, -1, -1, -1, -1,			/* arg, flags, fpsr, dir, frame */
   17, 18, 19, 20, 21, 22, 23, 24,	/* SSE */
   41, 42, 43, 44, 45, 46, 47, 48,       /* MMX */
@@ -1675,6 +1675,34 @@ classify_argument (mode, type, classes, bit_offset)
       /* Classify each field of record and merge classes.  */
       if (TREE_CODE (type) == RECORD_TYPE)
 	{
+	  /* For classes first merge in the field of the subclasses.  */
+	  if (TYPE_BINFO (type) != NULL && TYPE_BINFO_BASETYPES (type) != NULL)
+	    {
+	      tree bases = TYPE_BINFO_BASETYPES (type);
+	      int n_bases = TREE_VEC_LENGTH (bases);
+	      int i;
+
+	      for (i = 0; i < n_bases; ++i)
+		{
+		   tree binfo = TREE_VEC_ELT (bases, i);
+		   int num;
+		   int offset = tree_low_cst (BINFO_OFFSET (binfo), 0) * 8;
+		   tree type = BINFO_TYPE (binfo);
+
+		   num = classify_argument (TYPE_MODE (type),
+					    type, subclasses,
+					    (offset + bit_offset) % 256);
+		   if (!num)
+		     return 0;
+		   for (i = 0; i < num; i++)
+		     {
+		       int pos = (offset + bit_offset) / 8 / 8;
+		       classes[i + pos] =
+			 merge_classes (subclasses[i], classes[i + pos]);
+		     }
+		}
+	    }
+	  /* And now merge the fields of structure.   */
 	  for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
 	    {
 	      if (TREE_CODE (field) == FIELD_DECL)
@@ -1735,6 +1763,33 @@ classify_argument (mode, type, classes, bit_offset)
       else if (TREE_CODE (type) == UNION_TYPE
 	       || TREE_CODE (type) == QUAL_UNION_TYPE)
 	{
+	  /* For classes first merge in the field of the subclasses.  */
+	  if (TYPE_BINFO (type) != NULL && TYPE_BINFO_BASETYPES (type) != NULL)
+	    {
+	      tree bases = TYPE_BINFO_BASETYPES (type);
+	      int n_bases = TREE_VEC_LENGTH (bases);
+	      int i;
+
+	      for (i = 0; i < n_bases; ++i)
+		{
+		   tree binfo = TREE_VEC_ELT (bases, i);
+		   int num;
+		   int offset = tree_low_cst (BINFO_OFFSET (binfo), 0) * 8;
+		   tree type = BINFO_TYPE (binfo);
+
+		   num = classify_argument (TYPE_MODE (type),
+					    type, subclasses,
+					    (offset + bit_offset) % 256);
+		   if (!num)
+		     return 0;
+		   for (i = 0; i < num; i++)
+		     {
+		       int pos = (offset + bit_offset) / 8 / 8;
+		       classes[i + pos] =
+			 merge_classes (subclasses[i], classes[i + pos]);
+		     }
+		}
+	    }
 	  for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
 	    {
 	      if (TREE_CODE (field) == FIELD_DECL)
@@ -2841,6 +2896,18 @@ const_int_1_operand (op, mode)
   return (GET_CODE (op) == CONST_INT && INTVAL (op) == 1);
 }
 
+/* Return nonzero if OP is CONST_INT >= 1 and <= 31 (a valid operand
+   for shift & compare patterns, as shifting by 0 does not change flags),
+   else return zero.  */
+
+int
+const_int_1_31_operand (op, mode)
+     rtx op;
+     enum machine_mode mode ATTRIBUTE_UNUSED;
+{
+  return (GET_CODE (op) == CONST_INT && INTVAL (op) >= 1 && INTVAL (op) <= 31);
+}
+
 /* Returns 1 if OP is either a symbol reference or a sum of a symbol
    reference and a constant.  */
 
@@ -3863,9 +3930,6 @@ load_pic_register ()
 
   emit_insn (gen_prologue_get_pc (pic_offset_table_rtx, pclab));
 
-  if (! TARGET_DEEP_BRANCH_PREDICTION)
-    emit_insn (gen_popsi1 (pic_offset_table_rtx));
-
   emit_insn (gen_prologue_set_got (pic_offset_table_rtx, gotsym, pclab));
 }
 
@@ -4015,8 +4079,9 @@ ix86_compute_frame_layout (frame)
 
   offset += size;
 
-  /* Add outgoing arguments area.  */
-  if (ACCUMULATE_OUTGOING_ARGS)
+  /* Add outgoing arguments area.  Can be skipped if we eliminated
+     all the function calls as dead code.  */
+  if (ACCUMULATE_OUTGOING_ARGS && !current_function_is_leaf)
     {
       offset += current_function_outgoing_args_size;
       frame->outgoing_arguments_size = current_function_outgoing_args_size;
@@ -4024,9 +4089,13 @@ ix86_compute_frame_layout (frame)
   else
     frame->outgoing_arguments_size = 0;
 
-  /* Align stack boundary.  */
-  frame->padding2 = ((offset + preferred_alignment - 1)
-		     & -preferred_alignment) - offset;
+  /* Align stack boundary.  Only needed if we're calling another function
+     or using alloca.  */
+  if (!current_function_is_leaf || current_function_calls_alloca)
+    frame->padding2 = ((offset + preferred_alignment - 1)
+		       & -preferred_alignment) - offset;
+  else
+    frame->padding2 = 0;
 
   offset += frame->padding2;
 
@@ -7958,7 +8027,12 @@ ix86_expand_int_movcc (operands)
   if ((code == LEU || code == GTU)
       && GET_CODE (ix86_compare_op1) == CONST_INT
       && mode != HImode
-      && (unsigned int) INTVAL (ix86_compare_op1) != 0xffffffff
+      && INTVAL (ix86_compare_op1) != -1
+      /* For x86-64, the immediate field in the instruction is 32-bit
+	 signed, so we can't increment a DImode value above 0x7fffffff.  */
+      && (!TARGET_64BIT
+	  || GET_MODE (ix86_compare_op0) != DImode
+	  || INTVAL (ix86_compare_op1) != 0x7fffffff)
       && GET_CODE (operands[2]) == CONST_INT
       && GET_CODE (operands[3]) == CONST_INT)
     {
@@ -7966,7 +8040,8 @@ ix86_expand_int_movcc (operands)
 	code = LTU;
       else
 	code = GEU;
-      ix86_compare_op1 = GEN_INT (INTVAL (ix86_compare_op1) + 1);
+      ix86_compare_op1 = gen_int_mode (INTVAL (ix86_compare_op1) + 1,
+				       GET_MODE (ix86_compare_op0));
     }
 
   start_sequence ();
@@ -9130,6 +9205,9 @@ ix86_expand_movstr (dst, src, count_exp, align_exp)
     {
       rtx countreg2;
       rtx label = NULL;
+      int desired_alignment = (TARGET_PENTIUMPRO
+			       && (count == 0 || count >= (unsigned int) 260)
+			       ? 8 : UNITS_PER_WORD);
 
       /* In case we don't know anything about the alignment, default to
          library version, since it is usually equally fast and result in
@@ -9159,13 +9237,10 @@ ix86_expand_movstr (dst, src, count_exp, align_exp)
          This is quite costy.  Maybe we can revisit this decision later or
          add some customizability to this code.  */
 
-      if (count == 0
-	  && align < (TARGET_PENTIUMPRO && (count == 0
-					    || count >= (unsigned int) 260)
-		      ? 8 : UNITS_PER_WORD))
+      if (count == 0 && align < desired_alignment)
 	{
 	  label = gen_label_rtx ();
-	  emit_cmp_and_jump_insns (countreg, GEN_INT (UNITS_PER_WORD - 1),
+	  emit_cmp_and_jump_insns (countreg, GEN_INT (desired_alignment - 1),
 				   LEU, 0, counter_mode, 1, label);
 	}
       if (align <= 1)
@@ -9184,10 +9259,7 @@ ix86_expand_movstr (dst, src, count_exp, align_exp)
 	  emit_label (label);
 	  LABEL_NUSES (label) = 1;
 	}
-      if (align <= 4
-	  && ((TARGET_PENTIUMPRO && (count == 0
-				     || count >= (unsigned int) 260))
-	      || TARGET_64BIT))
+      if (align <= 4 && desired_alignment > 4)
 	{
 	  rtx label = ix86_expand_aligntest (destreg, 4);
 	  emit_insn (gen_strmovsi (destreg, srcreg));
@@ -9196,6 +9268,12 @@ ix86_expand_movstr (dst, src, count_exp, align_exp)
 	  LABEL_NUSES (label) = 1;
 	}
 
+      if (label && desired_alignment > 4 && !TARGET_64BIT)
+	{
+	  emit_label (label);
+	  LABEL_NUSES (label) = 1;
+	  label = NULL_RTX;
+	}
       if (!TARGET_SINGLE_STRINGOP)
 	emit_insn (gen_cld ());
       if (TARGET_64BIT)
@@ -9341,6 +9419,10 @@ ix86_expand_clrstr (src, count_exp, align_exp)
     {
       rtx countreg2;
       rtx label = NULL;
+      /* Compute desired alignment of the string operation.  */
+      int desired_alignment = (TARGET_PENTIUMPRO
+			       && (count == 0 || count >= (unsigned int) 260)
+			       ? 8 : UNITS_PER_WORD);
 
       /* In case we don't know anything about the alignment, default to
          library version, since it is usually equally fast and result in
@@ -9355,13 +9437,10 @@ ix86_expand_clrstr (src, count_exp, align_exp)
       countreg = copy_to_mode_reg (counter_mode, count_exp);
       zeroreg = copy_to_mode_reg (Pmode, const0_rtx);
 
-      if (count == 0
-	  && align < (TARGET_PENTIUMPRO && (count == 0
-					    || count >= (unsigned int) 260)
-		      ? 8 : UNITS_PER_WORD))
+      if (count == 0 && align < desired_alignment)
 	{
 	  label = gen_label_rtx ();
-	  emit_cmp_and_jump_insns (countreg, GEN_INT (UNITS_PER_WORD - 1),
+	  emit_cmp_and_jump_insns (countreg, GEN_INT (desired_alignment - 1),
 				   LEU, 0, counter_mode, 1, label);
 	}
       if (align <= 1)
@@ -9382,8 +9461,7 @@ ix86_expand_clrstr (src, count_exp, align_exp)
 	  emit_label (label);
 	  LABEL_NUSES (label) = 1;
 	}
-      if (align <= 4 && TARGET_PENTIUMPRO && (count == 0
-					      || count >= (unsigned int) 260))
+      if (align <= 4 && desired_alignment > 4)
 	{
 	  rtx label = ix86_expand_aligntest (destreg, 4);
 	  emit_insn (gen_strsetsi (destreg, (TARGET_64BIT
@@ -9394,6 +9472,13 @@ ix86_expand_clrstr (src, count_exp, align_exp)
 	  LABEL_NUSES (label) = 1;
 	}
 
+      if (label && desired_alignment > 4 && !TARGET_64BIT)
+	{
+	  emit_label (label);
+	  LABEL_NUSES (label) = 1;
+	  label = NULL_RTX;
+	}
+
       if (!TARGET_SINGLE_STRINGOP)
 	emit_insn (gen_cld ());
       if (TARGET_64BIT)
@@ -9409,18 +9494,18 @@ ix86_expand_clrstr (src, count_exp, align_exp)
 	  emit_insn (gen_rep_stossi (destreg, countreg2, zeroreg,
 				     destreg, countreg2));
 	}
-
       if (label)
 	{
 	  emit_label (label);
 	  LABEL_NUSES (label) = 1;
 	}
+
       if (TARGET_64BIT && align > 4 && count != 0 && (count & 4))
 	emit_insn (gen_strsetsi (destreg,
 				 gen_rtx_SUBREG (SImode, zeroreg, 0)));
       if (TARGET_64BIT && (align <= 4 || count == 0))
 	{
-	  rtx label = ix86_expand_aligntest (destreg, 2);
+	  rtx label = ix86_expand_aligntest (countreg, 4);
 	  emit_insn (gen_strsetsi (destreg,
 				   gen_rtx_SUBREG (SImode, zeroreg, 0)));
 	  emit_label (label);
@@ -9431,7 +9516,7 @@ ix86_expand_clrstr (src, count_exp, align_exp)
 				 gen_rtx_SUBREG (HImode, zeroreg, 0)));
       if (align <= 2 || count == 0)
 	{
-	  rtx label = ix86_expand_aligntest (destreg, 2);
+	  rtx label = ix86_expand_aligntest (countreg, 2);
 	  emit_insn (gen_strsethi (destreg,
 				   gen_rtx_SUBREG (HImode, zeroreg, 0)));
 	  emit_label (label);
@@ -9442,7 +9527,7 @@ ix86_expand_clrstr (src, count_exp, align_exp)
 				 gen_rtx_SUBREG (QImode, zeroreg, 0)));
       if (align <= 1 || count == 0)
 	{
-	  rtx label = ix86_expand_aligntest (destreg, 1);
+	  rtx label = ix86_expand_aligntest (countreg, 1);
 	  emit_insn (gen_strsetqi (destreg,
 				   gen_rtx_SUBREG (QImode, zeroreg, 0)));
 	  emit_label (label);
@@ -12473,3 +12558,97 @@ x86_order_regs_for_local_alloc ()
    while (pos < FIRST_PSEUDO_REGISTER)
      reg_alloc_order [pos++] = 0;
 }
+
+void
+x86_output_mi_thunk (file, delta, function)
+     FILE *file;
+     int delta;
+     tree function;
+{
+  tree parm;
+  rtx xops[3];
+
+  if (ix86_regparm > 0)
+    parm = TYPE_ARG_TYPES (TREE_TYPE (function));
+  else
+    parm = NULL_TREE;
+  for (; parm; parm = TREE_CHAIN (parm))
+    if (TREE_VALUE (parm) == void_type_node)
+      break;
+
+  xops[0] = GEN_INT (delta);
+  if (TARGET_64BIT)
+    {
+      int n = aggregate_value_p (TREE_TYPE (TREE_TYPE (function))) != 0;
+      xops[1] = gen_rtx_REG (DImode, x86_64_int_parameter_registers[n]);
+      output_asm_insn ("add{q} {%0, %1|%1, %0}", xops);
+      if (flag_pic)
+	{
+	  fprintf (file, "\tjmp *");
+	  assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
+	  fprintf (file, "@GOTPCREL(%%rip)\n");
+	}
+      else
+	{
+	  fprintf (file, "\tjmp ");
+	  assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
+	  fprintf (file, "\n");
+	}
+    }
+  else
+    {
+      if (parm)
+	xops[1] = gen_rtx_REG (SImode, 0);
+      else if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
+	xops[1] = gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 8));
+      else
+	xops[1] = gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 4));
+      output_asm_insn ("add{l} {%0, %1|%1, %0}", xops);
+
+      if (flag_pic)
+	{
+	  xops[0] = pic_offset_table_rtx;
+	  xops[1] = gen_label_rtx ();
+	  xops[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");
+
+	  if (ix86_regparm > 2)
+	    abort ();
+	  output_asm_insn ("push{l}\t%0", xops);
+	  output_asm_insn ("call\t%P1", xops);
+	  ASM_OUTPUT_INTERNAL_LABEL (file, "L", CODE_LABEL_NUMBER (xops[1]));
+	  output_asm_insn ("pop{l}\t%0", xops);
+	  output_asm_insn
+	    ("add{l}\t{%2+[.-%P1], %0|%0, OFFSET FLAT: %2+[.-%P1]}", xops);
+	  xops[0] = gen_rtx_MEM (SImode, XEXP (DECL_RTL (function), 0));
+	  output_asm_insn
+	    ("mov{l}\t{%0@GOT(%%ebx), %%ecx|%%ecx, %0@GOT[%%ebx]}", xops);
+	  asm_fprintf (file, "\tpop{l\t%%ebx|\t%%ebx}\n");
+	  asm_fprintf (file, "\tjmp\t{*%%ecx|%%ecx}\n");
+	}
+      else
+	{
+	  fprintf (file, "\tjmp ");
+	  assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
+	  fprintf (file, "\n");
+	}
+    }
+}
+
+int
+x86_field_alignment (field, computed)
+     tree field;
+     int computed;
+{
+  enum machine_mode mode;
+  tree type = TREE_TYPE (field);
+
+  if (TARGET_64BIT || TARGET_ALIGN_DOUBLE)
+    return computed;
+  mode = TYPE_MODE (TREE_CODE (type) == ARRAY_TYPE
+		    ? get_inner_array_type (type) : type);
+  if (mode == DFmode || mode == DCmode
+      || GET_MODE_CLASS (mode) == MODE_INT
+      || GET_MODE_CLASS (mode) == MODE_COMPLEX_INT)
+    return MIN (32, computed);
+  return computed;
+}
diff --git a/contrib/gcc/config/i386/i386.h b/contrib/gcc/config/i386/i386.h
index 2b9ad4b..07502a2 100644
--- a/contrib/gcc/config/i386/i386.h
+++ b/contrib/gcc/config/i386/i386.h
@@ -609,7 +609,7 @@ extern int ix86_arch;
 %{mcpu=athlon-4|mcpu=athlon-xp|mcpu=athlon-mp:\
 -D__tune_athlon_sse__ }\
 %{mcpu=pentium4:-D__tune_pentium4__ }\
-%{march=athlon-tbird|march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\
+%{march=athlon-xp|march=athlon-mp|march=pentium3|march=pentium4:\
 -D__SSE__ }\
 %{march=pentium-mmx|march=k6|march=k6-2|march=k6-3\
 |march=athlon|march=athlon-tbird|march=athlon-4|march=athlon-xp\
@@ -781,12 +781,15 @@ extern int ix86_arch;
 /* The published ABIs say that doubles should be aligned on word
    boundaries, so lower the aligment for structure fields unless
    -malign-double is set.  */
-/* BIGGEST_FIELD_ALIGNMENT is also used in libobjc, where it must be
-   constant.  Use the smaller value in that context.  */
-#ifndef IN_TARGET_LIBS
-#define BIGGEST_FIELD_ALIGNMENT (TARGET_64BIT ? 128 : (TARGET_ALIGN_DOUBLE ? 64 : 32))
-#else
+
+/* ??? Blah -- this macro is used directly by libobjc.  Since it
+   supports no vector modes, cut out the complexity and fall back
+   on BIGGEST_FIELD_ALIGNMENT.  */
+#ifdef IN_TARGET_LIBS
 #define BIGGEST_FIELD_ALIGNMENT 32
+#else
+#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \
+   x86_field_alignment (FIELD, COMPUTED)
 #endif
 
 /* If defined, a C expression to compute the alignment given to a
@@ -3026,6 +3029,7 @@ extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER];
 				       SYMBOL_REF, LABEL_REF}},		\
   {"shiftdi_operand", {SUBREG, REG, MEM}},				\
   {"const_int_1_operand", {CONST_INT}},					\
+  {"const_int_1_31_operand", {CONST_INT}},				\
   {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}},			\
   {"aligned_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF,	\
 		       LABEL_REF, SUBREG, REG, MEM}},			\
diff --git a/contrib/gcc/config/i386/i386.md b/contrib/gcc/config/i386/i386.md
index fefaca0..4275675 100644
--- a/contrib/gcc/config/i386/i386.md
+++ b/contrib/gcc/config/i386/i386.md
@@ -2014,7 +2014,7 @@
 ;; For 64BIT abi we always round up to 8 bytes.
 (define_insn "*pushqi2_rex64"
   [(set (match_operand:QI 0 "push_operand" "=X")
-	(match_operand:QI 1 "nonmemory_no_elim_operand" "ri"))]
+	(match_operand:QI 1 "nonmemory_no_elim_operand" "qi"))]
   "TARGET_64BIT"
   "push{q}\t%q1"
   [(set_attr "type" "push")
@@ -2555,17 +2555,16 @@
 ;; We fake an second form of instruction to force reload to load address
 ;; into register when rax is not available
 (define_insn "*movabsdi_1_rex64"
-  [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r,r"))
-	(match_operand:DI 1 "nonmemory_operand" "a,er,i"))]
+  [(set (mem:DI (match_operand:DI 0 "x86_64_movabs_operand" "i,r"))
+	(match_operand:DI 1 "nonmemory_operand" "a,er"))]
   "TARGET_64BIT"
   "@
    movabs{q}\t{%1, %P0|%P0, %1}
-   mov{q}\t{%1, %a0|%a0, %1}
-   movabs{q}\t{%1, %a0|%a0, %1}"
+   mov{q}\t{%1, %a0|%a0, %1}"
   [(set_attr "type" "imov")
-   (set_attr "modrm" "0,*,*")
-   (set_attr "length_address" "8,0,0")
-   (set_attr "length_immediate" "0,*,*")
+   (set_attr "modrm" "0,*")
+   (set_attr "length_address" "8,0")
+   (set_attr "length_immediate" "0,*")
    (set_attr "memory" "store")
    (set_attr "mode" "DI")])
 
@@ -10951,7 +10950,7 @@
   [(set (reg 17)
 	(compare
 	  (ashift:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-		     (match_operand:QI 2 "immediate_operand" "I"))
+		     (match_operand:QI 2 "const_int_1_31_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
 	(ashift:SI (match_dup 1) (match_dup 2)))]
@@ -10990,7 +10989,7 @@
   [(set (reg 17)
 	(compare
 	  (ashift:SI (match_operand:SI 1 "register_operand" "0")
-		     (match_operand:QI 2 "immediate_operand" "I"))
+		     (match_operand:QI 2 "const_int_1_31_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (ashift:SI (match_dup 1) (match_dup 2))))]
@@ -11115,7 +11114,7 @@
   [(set (reg 17)
 	(compare
 	  (ashift:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-		     (match_operand:QI 2 "immediate_operand" "I"))
+		     (match_operand:QI 2 "const_int_1_31_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
 	(ashift:HI (match_dup 1) (match_dup 2)))]
@@ -11279,7 +11278,7 @@
   [(set (reg 17)
 	(compare
 	  (ashift:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-		     (match_operand:QI 2 "immediate_operand" "I"))
+		     (match_operand:QI 2 "const_int_1_31_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
 	(ashift:QI (match_dup 1) (match_dup 2)))]
@@ -11629,7 +11628,7 @@
   [(set (reg 17)
 	(compare
 	  (ashiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-		       (match_operand:QI 2 "immediate_operand" "I"))
+		       (match_operand:QI 2 "const_int_1_31_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
 	(ashiftrt:SI (match_dup 1) (match_dup 2)))]
@@ -11643,7 +11642,7 @@
   [(set (reg 17)
 	(compare
 	  (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		       (match_operand:QI 2 "immediate_operand" "I"))
+		       (match_operand:QI 2 "const_int_1_31_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (ashiftrt:SI (match_dup 1) (match_dup 2))))]
@@ -11715,7 +11714,7 @@
   [(set (reg 17)
 	(compare
 	  (ashiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-		       (match_operand:QI 2 "immediate_operand" "I"))
+		       (match_operand:QI 2 "const_int_1_31_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
 	(ashiftrt:HI (match_dup 1) (match_dup 2)))]
@@ -11768,7 +11767,7 @@
 	  (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
 		       (match_operand:QI 2 "const_int_1_operand" "I"))
 	  (const_int 0)))
-   (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
+   (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
 	(ashiftrt:QI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
    && (TARGET_PENTIUM || TARGET_PENTIUMPRO)
@@ -11787,9 +11786,9 @@
   [(set (reg 17)
 	(compare
 	  (ashiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-		       (match_operand:QI 2 "immediate_operand" "I"))
+		       (match_operand:QI 2 "const_int_1_31_operand" "I"))
 	  (const_int 0)))
-   (set (match_operand:QI 0 "nonimmediate_operand" "=rm")
+   (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
 	(ashiftrt:QI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
    && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
@@ -12020,7 +12019,7 @@
   [(set (reg 17)
 	(compare
 	  (lshiftrt:SI (match_operand:SI 1 "nonimmediate_operand" "0")
-		       (match_operand:QI 2 "immediate_operand" "I"))
+		       (match_operand:QI 2 "const_int_1_31_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=rm")
 	(lshiftrt:SI (match_dup 1) (match_dup 2)))]
@@ -12034,7 +12033,7 @@
   [(set (reg 17)
 	(compare
 	  (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		       (match_operand:QI 2 "immediate_operand" "I"))
+		       (match_operand:QI 2 "const_int_1_31_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(lshiftrt:DI (zero_extend:DI (match_dup 1)) (match_dup 2)))]
@@ -12106,7 +12105,7 @@
   [(set (reg 17)
 	(compare
 	  (lshiftrt:HI (match_operand:HI 1 "nonimmediate_operand" "0")
-		       (match_operand:QI 2 "immediate_operand" "I"))
+		       (match_operand:QI 2 "const_int_1_31_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=rm")
 	(lshiftrt:HI (match_dup 1) (match_dup 2)))]
@@ -12178,7 +12177,7 @@
   [(set (reg 17)
 	(compare
 	  (lshiftrt:QI (match_operand:QI 1 "nonimmediate_operand" "0")
-		       (match_operand:QI 2 "immediate_operand" "I"))
+		       (match_operand:QI 2 "const_int_1_31_operand" "I"))
 	  (const_int 0)))
    (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
 	(lshiftrt:QI (match_dup 1) (match_dup 2)))]
@@ -13816,6 +13815,7 @@
     {
       ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "L",
 				 CODE_LABEL_NUMBER (operands[1]));
+      return "pop{l}\t%0";
     }
   RET;
 }
@@ -16576,12 +16576,12 @@
   "#")
 
 (define_insn "sse_movdfcc"
-  [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?f#xr,?f#xr,?r#xf,?r#xf,?r#xf,?r#xf")
+  [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?f#Yr,?f#Yr,?r#Yf,?r#Yf,?r#Yf,?r#Yf")
 	(if_then_else:DF (match_operator 1 "sse_comparison_operator"
-			[(match_operand:DF 4 "nonimmediate_operand" "0#fx,x#fx,f#x,f#x,xm#f,xm#f,f#x,f#x,xm#f,xm#f")
-			 (match_operand:DF 5 "nonimmediate_operand" "xm#f,xm#f,f#x,f#x,x#f,x#f,f#x,f#x,x#f,x#f")])
-		      (match_operand:DF 2 "nonimmediate_operand" "x#fr,0#fr,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx,0#rx")
-		      (match_operand:DF 3 "nonimmediate_operand" "x#fr,x#fr,0#fx,f#fx,0#fx,f#fx,0#fx,rm#rx,0#rx,rm#rx")))
+			[(match_operand:DF 4 "nonimmediate_operand" "0#fY,Y#fY,f#Y,f#Y,Ym#f,Ym#f,f#Y,f#Y,Ym#f,Ym#f")
+			 (match_operand:DF 5 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,f#Y,Y#f,Y#f,f#Y,f#Y,Y#f,Y#f")])
+		      (match_operand:DF 2 "nonimmediate_operand" "Y#fr,0#fr,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY,0#rY")
+		      (match_operand:DF 3 "nonimmediate_operand" "Y#fr,Y#fr,0#fY,f#fY,0#fY,f#fY,0#fY,rm#rY,0#rY,rm#rY")))
    (clobber (match_scratch:DF 6 "=2,&4,X,X,X,X,X,X,X,X"))
    (clobber (reg:CC 17))]
   "TARGET_SSE2
@@ -16591,11 +16591,11 @@
   "#")
 
 (define_insn "sse_movdfcc_eq"
-  [(set (match_operand:DF 0 "register_operand" "=&x#rf,x#rf,?f#xr,?f#xr,?r#xf,?r#xf")
-	(if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fx,x#fx,f#x,xm#f,f#x,xm#f")
-			     (match_operand:DF 4 "nonimmediate_operand" "xm#f,xm#f,f#x,x#f,f#x,x#f"))
-		      (match_operand:DF 1 "nonimmediate_operand" "x#fr,0#fr,0#fx,0#fx,0#rx,0#rx")
-		      (match_operand:DF 2 "nonimmediate_operand" "x#fr,x#fr,f#fx,f#fx,rm#rx,rm#rx")))
+  [(set (match_operand:DF 0 "register_operand" "=&Y#rf,Y#rf,?f#Yr,?f#Yr,?r#Yf,?r#Yf")
+	(if_then_else:DF (eq (match_operand:DF 3 "nonimmediate_operand" "%0#fY,Y#fY,f#Y,Ym#f,f#Y,Ym#f")
+			     (match_operand:DF 4 "nonimmediate_operand" "Ym#f,Ym#f,f#Y,Y#f,f#Y,Y#f"))
+		      (match_operand:DF 1 "nonimmediate_operand" "Y#fr,0#fr,0#fY,0#fY,0#rY,0#rY")
+		      (match_operand:DF 2 "nonimmediate_operand" "Y#fr,Y#fr,f#fY,f#fY,rm#rY,rm#rY")))
    (clobber (match_scratch:DF 5 "=1,&3,X,X,X,X"))
    (clobber (reg:CC 17))]
   "TARGET_SSE
@@ -16647,6 +16647,10 @@
    (set (subreg:TI (match_dup 0) 0) (ior:TI (subreg:TI (match_dup 6) 0)
 					    (subreg:TI (match_dup 7) 0)))]
 {
+  /* If op2 == op3, op3 will be clobbered before it is used.
+     This should be optimized out though.  */
+  if (operands_match_p (operands[2], operands[3]))
+    abort ();
   PUT_MODE (operands[1], GET_MODE (operands[0]));
   if (operands_match_p (operands[0], operands[4]))
     operands[6] = operands[4], operands[7] = operands[2];
@@ -16658,7 +16662,7 @@
 ;; Do not brother with the integer/floating point case, since these are
 ;; bot considerably slower, unlike in the generic case.
 (define_insn "*sse_movsfcc_const0_1"
-  [(set (match_operand:SF 0 "register_operand" "=x")
+  [(set (match_operand:SF 0 "register_operand" "=&x")
 	(if_then_else:SF (match_operator 1 "sse_comparison_operator"
 			[(match_operand:SF 4 "register_operand" "0")
 			 (match_operand:SF 5 "nonimmediate_operand" "xm")])
@@ -16668,7 +16672,7 @@
   "#")
 
 (define_insn "*sse_movsfcc_const0_2"
-  [(set (match_operand:SF 0 "register_operand" "=x")
+  [(set (match_operand:SF 0 "register_operand" "=&x")
 	(if_then_else:SF (match_operator 1 "sse_comparison_operator"
 			[(match_operand:SF 4 "register_operand" "0")
 			 (match_operand:SF 5 "nonimmediate_operand" "xm")])
@@ -16678,7 +16682,7 @@
   "#")
 
 (define_insn "*sse_movsfcc_const0_3"
-  [(set (match_operand:SF 0 "register_operand" "=x")
+  [(set (match_operand:SF 0 "register_operand" "=&x")
 	(if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
 			[(match_operand:SF 4 "nonimmediate_operand" "xm")
 			 (match_operand:SF 5 "register_operand" "0")])
@@ -16688,7 +16692,7 @@
   "#")
 
 (define_insn "*sse_movsfcc_const0_4"
-  [(set (match_operand:SF 0 "register_operand" "=x")
+  [(set (match_operand:SF 0 "register_operand" "=&x")
 	(if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
 			[(match_operand:SF 4 "nonimmediate_operand" "xm")
 			 (match_operand:SF 5 "register_operand" "0")])
@@ -16698,42 +16702,42 @@
   "#")
 
 (define_insn "*sse_movdfcc_const0_1"
-  [(set (match_operand:SF 0 "register_operand" "=x")
-	(if_then_else:SF (match_operator 1 "sse_comparison_operator"
-			[(match_operand:SF 4 "register_operand" "0")
-			 (match_operand:SF 5 "nonimmediate_operand" "xm")])
-		      (match_operand:SF 2 "register_operand" "x")
-		      (match_operand:SF 3 "const0_operand" "X")))]
+  [(set (match_operand:DF 0 "register_operand" "=&Y")
+	(if_then_else:DF (match_operator 1 "sse_comparison_operator"
+			[(match_operand:DF 4 "register_operand" "0")
+			 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
+		      (match_operand:DF 2 "register_operand" "Y")
+		      (match_operand:DF 3 "const0_operand" "X")))]
   "TARGET_SSE2"
   "#")
 
 (define_insn "*sse_movdfcc_const0_2"
-  [(set (match_operand:SF 0 "register_operand" "=x")
-	(if_then_else:SF (match_operator 1 "sse_comparison_operator"
-			[(match_operand:SF 4 "register_operand" "0")
-			 (match_operand:SF 5 "nonimmediate_operand" "xm")])
-		      (match_operand:SF 2 "const0_operand" "X")
-		      (match_operand:SF 3 "register_operand" "x")))]
+  [(set (match_operand:DF 0 "register_operand" "=&Y")
+	(if_then_else:DF (match_operator 1 "sse_comparison_operator"
+			[(match_operand:DF 4 "register_operand" "0")
+			 (match_operand:DF 5 "nonimmediate_operand" "Ym")])
+		      (match_operand:DF 2 "const0_operand" "X")
+		      (match_operand:DF 3 "register_operand" "Y")))]
   "TARGET_SSE2"
   "#")
 
 (define_insn "*sse_movdfcc_const0_3"
-  [(set (match_operand:SF 0 "register_operand" "=x")
-	(if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
-			[(match_operand:SF 4 "nonimmediate_operand" "xm")
-			 (match_operand:SF 5 "register_operand" "0")])
-		      (match_operand:SF 2 "register_operand" "x")
-		      (match_operand:SF 3 "const0_operand" "X")))]
+  [(set (match_operand:DF 0 "register_operand" "=&Y")
+	(if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
+			[(match_operand:DF 4 "nonimmediate_operand" "Ym")
+			 (match_operand:DF 5 "register_operand" "0")])
+		      (match_operand:DF 2 "register_operand" "Y")
+		      (match_operand:DF 3 "const0_operand" "X")))]
   "TARGET_SSE2"
   "#")
 
 (define_insn "*sse_movdfcc_const0_4"
-  [(set (match_operand:SF 0 "register_operand" "=x")
-	(if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
-			[(match_operand:SF 4 "nonimmediate_operand" "xm")
-			 (match_operand:SF 5 "register_operand" "0")])
-		      (match_operand:SF 2 "const0_operand" "X")
-		      (match_operand:SF 3 "register_operand" "x")))]
+  [(set (match_operand:DF 0 "register_operand" "=&Y")
+	(if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
+			[(match_operand:DF 4 "nonimmediate_operand" "Ym")
+			 (match_operand:DF 5 "register_operand" "0")])
+		      (match_operand:DF 2 "const0_operand" "X")
+		      (match_operand:DF 3 "register_operand" "Y")))]
   "TARGET_SSE2"
   "#")
 
@@ -19779,7 +19783,7 @@
   [(set_attr "type" "mmx")])
 
 (define_expand "prefetch"
-  [(prefetch (match_operand:SI 0 "address_operand" "")
+  [(prefetch (match_operand 0 "address_operand" "")
 	     (match_operand:SI 1 "const_int_operand" "")
 	     (match_operand:SI 2 "const_int_operand" ""))]
   "TARGET_PREFETCH_SSE || TARGET_3DNOW"
@@ -19791,6 +19795,8 @@
     abort ();
   if (locality < 0 || locality > 3)
     abort ();
+  if (GET_MODE (operands[0]) != Pmode && GET_MODE (operands[0]) != VOIDmode)
+    abort ();
 
   /* Use 3dNOW prefetch in case we are asking for write prefetch not
      suported by SSE counterpart or the SSE prefetch is not available
@@ -19806,7 +19812,26 @@
   [(prefetch (match_operand:SI 0 "address_operand" "p")
 	     (const_int 0)
 	     (match_operand:SI 1 "const_int_operand" ""))]
-  "TARGET_PREFETCH_SSE"
+  "TARGET_PREFETCH_SSE && !TARGET_64BIT"
+{
+  static const char * const patterns[4] = {
+   "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
+  };
+
+  int locality = INTVAL (operands[1]);
+  if (locality < 0 || locality > 3)
+    abort ();
+
+  return patterns[locality];  
+}
+  [(set_attr "type" "sse")
+   (set_attr "memory" "none")])
+
+(define_insn "*prefetch_sse_rex"
+  [(prefetch (match_operand:DI 0 "address_operand" "p")
+	     (const_int 0)
+	     (match_operand:SI 1 "const_int_operand" ""))]
+  "TARGET_PREFETCH_SSE && TARGET_64BIT"
 {
   static const char * const patterns[4] = {
    "prefetchnta\t%a0", "prefetcht2\t%a0", "prefetcht1\t%a0", "prefetcht0\t%a0"
@@ -19824,7 +19849,21 @@
   [(prefetch (match_operand:SI 0 "address_operand" "p")
 	     (match_operand:SI 1 "const_int_operand" "n")
 	     (const_int 3))]
-  "TARGET_3DNOW"
+  "TARGET_3DNOW && !TARGET_64BIT"
+{
+  if (INTVAL (operands[1]) == 0)
+    return "prefetch\t%a0";
+  else
+    return "prefetchw\t%a0";
+}
+  [(set_attr "type" "mmx")
+   (set_attr "memory" "none")])
+
+(define_insn "*prefetch_3dnow_rex"
+  [(prefetch (match_operand:DI 0 "address_operand" "p")
+	     (match_operand:SI 1 "const_int_operand" "n")
+	     (const_int 3))]
+  "TARGET_3DNOW && TARGET_64BIT"
 {
   if (INTVAL (operands[1]) == 0)
     return "prefetch\t%a0";
diff --git a/contrib/gcc/config/i386/linux64.h b/contrib/gcc/config/i386/linux64.h
index 4926999..6158431 100644
--- a/contrib/gcc/config/i386/linux64.h
+++ b/contrib/gcc/config/i386/linux64.h
@@ -69,13 +69,16 @@ Boston, MA 02111-1307, USA.  */
 #define MULTILIB_DEFAULTS { "m64" }
 
 /* Do code reading to identify a signal frame, and set the frame
-   state data appropriately.  See unwind-dw2.c for the structs.  */
+   state data appropriately.  See unwind-dw2.c for the structs.  
+   Don't use this at all if inhibit_libc is used.  */
 
+#ifndef inhibit_libc
 #ifdef IN_LIBGCC2
 #include <signal.h>
 #include <sys/ucontext.h>
 #endif
 
+#ifdef __x86_64__
 #define MD_FALLBACK_FRAME_STATE_FOR(CONTEXT, FS, SUCCESS)		\
   do {									\
     unsigned char *pc_ = (CONTEXT)->ra;					\
@@ -132,3 +135,59 @@ Boston, MA 02111-1307, USA.  */
     (FS)->retaddr_column = 16;						\
     goto SUCCESS;							\
   } while (0)
+#else /* ifdef __x86_64__  */
+#define MD_FALLBACK_FRAME_STATE_FOR(CONTEXT, FS, SUCCESS)		\
+  do {									\
+    unsigned char *pc_ = (CONTEXT)->ra;					\
+    struct sigcontext *sc_;						\
+    long new_cfa_;							\
+									\
+    /* popl %eax ; movl $__NR_sigreturn,%eax ; int $0x80  */		\
+    if (*(unsigned short *)(pc_+0) == 0xb858				\
+	&& *(unsigned int *)(pc_+2) == 119				\
+	&& *(unsigned short *)(pc_+6) == 0x80cd)			\
+      sc_ = (CONTEXT)->cfa + 4;						\
+    /* movl $__NR_rt_sigreturn,%eax ; int $0x80  */			\
+    else if (*(unsigned char *)(pc_+0) == 0xb8				\
+	     && *(unsigned int *)(pc_+1) == 173				\
+	     && *(unsigned short *)(pc_+5) == 0x80cd)			\
+      {									\
+	struct rt_sigframe {						\
+	  int sig;							\
+	  struct siginfo *pinfo;					\
+	  void *puc;							\
+	  struct siginfo info;						\
+	  struct ucontext uc;						\
+	} *rt_ = (CONTEXT)->cfa;					\
+	sc_ = (struct sigcontext *) &rt_->uc.uc_mcontext;		\
+      }									\
+    else								\
+      break;								\
+									\
+    new_cfa_ = sc_->esp;						\
+    (FS)->cfa_how = CFA_REG_OFFSET;					\
+    (FS)->cfa_reg = 4;							\
+    (FS)->cfa_offset = new_cfa_ - (long) (CONTEXT)->cfa;		\
+									\
+    /* The SVR4 register numbering macros aren't usable in libgcc.  */	\
+    (FS)->regs.reg[0].how = REG_SAVED_OFFSET;				\
+    (FS)->regs.reg[0].loc.offset = (long)&sc_->eax - new_cfa_;		\
+    (FS)->regs.reg[3].how = REG_SAVED_OFFSET;				\
+    (FS)->regs.reg[3].loc.offset = (long)&sc_->ebx - new_cfa_;		\
+    (FS)->regs.reg[1].how = REG_SAVED_OFFSET;				\
+    (FS)->regs.reg[1].loc.offset = (long)&sc_->ecx - new_cfa_;		\
+    (FS)->regs.reg[2].how = REG_SAVED_OFFSET;				\
+    (FS)->regs.reg[2].loc.offset = (long)&sc_->edx - new_cfa_;		\
+    (FS)->regs.reg[6].how = REG_SAVED_OFFSET;				\
+    (FS)->regs.reg[6].loc.offset = (long)&sc_->esi - new_cfa_;		\
+    (FS)->regs.reg[7].how = REG_SAVED_OFFSET;				\
+    (FS)->regs.reg[7].loc.offset = (long)&sc_->edi - new_cfa_;		\
+    (FS)->regs.reg[5].how = REG_SAVED_OFFSET;				\
+    (FS)->regs.reg[5].loc.offset = (long)&sc_->ebp - new_cfa_;		\
+    (FS)->regs.reg[8].how = REG_SAVED_OFFSET;				\
+    (FS)->regs.reg[8].loc.offset = (long)&sc_->eip - new_cfa_;		\
+    (FS)->retaddr_column = 8;						\
+    goto SUCCESS;							\
+  } while (0)
+#endif /* ifdef __x86_64__  */
+#endif /* ifdef inhibit_libc  */
diff --git a/contrib/gcc/config/i386/mmintrin.h b/contrib/gcc/config/i386/mmintrin.h
index 41dc4be..88e384f 100644
--- a/contrib/gcc/config/i386/mmintrin.h
+++ b/contrib/gcc/config/i386/mmintrin.h
@@ -31,7 +31,7 @@
 #define _MMINTRIN_H_INCLUDED
 
 /* The data type intended for user use.  */
-typedef unsigned long long __m64;
+typedef unsigned long long __m64 __attribute__ ((__aligned__ (8)));
 
 /* Internal data types for implementing the intrinsics.  */
 typedef int __v2si __attribute__ ((__mode__ (__V2SI__)));
diff --git a/contrib/gcc/config/i386/netbsd64.h b/contrib/gcc/config/i386/netbsd64.h
index 74862af..051f33b 100644
--- a/contrib/gcc/config/i386/netbsd64.h
+++ b/contrib/gcc/config/i386/netbsd64.h
@@ -48,6 +48,24 @@ Boston, MA 02111-1307, USA.  */
   "-D__NetBSD__ -D__ELF__ -Asystem=unix -Asystem=NetBSD"
 
 
+/* Provide some extra CPP specs needed by NetBSD/x86_64.  */
+#define CPP_LP64_SPEC "%{!m32:-D_LP64}"
+
+#define CPP_SUBTARGET_SPEC "%(cpp_lp64)"
+
+#undef SUBTARGET_EXTRA_SPECS
+#define SUBTARGET_EXTRA_SPECS						\
+  { "cpp_lp64", CPP_LP64_SPEC },					\
+  { "cpp_subtarget", CPP_SUBTARGET_SPEC },
+
+
+/* Provide a CPP_SPEC appropriate for NetBSD.  Currently we deal with
+   our subtarget specs and the GCC option `-posix'.  */
+
+#undef CPP_SPEC
+#define CPP_SPEC "%(cpp_cpu) %(cpp_subtarget) %{posix:-D_POSIX_SOURCE}"
+
+
 /* Output assembler code to FILE to call the profiler.  */
 
 #undef FUNCTION_PROFILER
diff --git a/contrib/gcc/config/i386/openbsd.h b/contrib/gcc/config/i386/openbsd.h
index a07ee15..5015b9d 100644
--- a/contrib/gcc/config/i386/openbsd.h
+++ b/contrib/gcc/config/i386/openbsd.h
@@ -95,26 +95,11 @@ Boston, MA 02111-1307, USA.  */
 
 #undef ASM_PREFERRED_EH_DATA_FORMAT
 
-/* Assembler format: alignment output.  */
-
-/* A C statement to output to the stdio stream FILE an assembler
-   command to advance the location counter to a multiple of 1<<LOG
-   bytes if it is within MAX_SKIP bytes.
-
-   This will be used to align code labels according to Intel 
-   recommendations, in prevision of binutils upgrade.  */
-#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN
-#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE,LOG,MAX_SKIP)			\
-  do {									\
-    if ((LOG) != 0) {							\
-      if ((MAX_SKIP) == 0) fprintf ((FILE), "\t.p2align %d\n", (LOG));	\
-      else fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP));	\
-    }									\
-  } while (0)
-#endif
 
 /* Note that we pick up ASM_OUTPUT_MI_THUNK from unix.h.  */
 
 #undef ASM_COMMENT_START
 #define ASM_COMMENT_START ";#"
 
+/* OpenBSD gas currently does not support quad, so do not use it.  */
+#undef ASM_QUAD
diff --git a/contrib/gcc/config/i386/unix.h b/contrib/gcc/config/i386/unix.h
index 15a0701..f7e38b4 100644
--- a/contrib/gcc/config/i386/unix.h
+++ b/contrib/gcc/config/i386/unix.h
@@ -79,57 +79,5 @@ Boston, MA 02111-1307, USA.  */
 
 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
    Used for C++ multiple inheritance.  */
-#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION)	    \
-do {									    \
-  tree parm;								    \
-  rtx xops[3];								    \
-									    \
-  if (ix86_regparm > 0)							    \
-    parm = TYPE_ARG_TYPES (TREE_TYPE (function));			    \
-  else									    \
-    parm = NULL_TREE;							    \
-  for (; parm; parm = TREE_CHAIN (parm))				    \
-    if (TREE_VALUE (parm) == void_type_node)				    \
-      break;								    \
-									    \
-  xops[0] = GEN_INT (DELTA);						    \
-  if (parm)								    \
-    xops[1] = gen_rtx_REG (SImode, 0);					    \
-  else if (aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))))	    \
-    xops[1] = gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 8));   \
-  else									    \
-    xops[1] = gen_rtx_MEM (SImode, plus_constant (stack_pointer_rtx, 4));   \
-  output_asm_insn ("add{l} {%0, %1|%1, %0}", xops);			    \
-									    \
-  if (flag_pic && !TARGET_64BIT)					    \
-    {									    \
-      xops[0] = pic_offset_table_rtx;					    \
-      xops[1] = gen_label_rtx ();					    \
-      xops[2] = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_");        \
-									    \
-      if (ix86_regparm > 2)						    \
-	abort ();							    \
-      output_asm_insn ("push{l}\t%0", xops);				    \
-      output_asm_insn ("call\t%P1", xops);				    \
-      ASM_OUTPUT_INTERNAL_LABEL (FILE, "L", CODE_LABEL_NUMBER (xops[1]));   \
-      output_asm_insn ("pop{l}\t%0", xops);				    \
-      output_asm_insn ("add{l}\t{%2+[.-%P1], %0|%0, OFFSET FLAT: %2+[.-%P1]}", xops); \
-      xops[0] = gen_rtx_MEM (SImode, XEXP (DECL_RTL (FUNCTION), 0));	    \
-      output_asm_insn ("mov{l}\t{%0@GOT(%%ebx), %%ecx|%%ecx, %0@GOT[%%ebx]}",\
-	               xops);						    \
-      asm_fprintf (FILE, "\tpop{l\t%%ebx|\t%%ebx}\n");			    \
-      asm_fprintf (FILE, "\tjmp\t{*%%ecx|%%ecx}\n");			    \
-    }									    \
-  else if (flag_pic && TARGET_64BIT)					    \
-    {									    \
-      fprintf (FILE, "\tjmp *");					    \
-      assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0));	    \
-      fprintf (FILE, "@GOTPCREL(%%rip)\n");				    \
-    }									    \
-  else									    \
-    {									    \
-      fprintf (FILE, "\tjmp ");						    \
-      assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0));	    \
-      fprintf (FILE, "\n");						    \
-    }									    \
-} while (0)
+#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
+    x86_output_mi_thunk (FILE, DELTA, FUNCTION);
diff --git a/contrib/gcc/config/ia64/linux.h b/contrib/gcc/config/ia64/linux.h
index 3091852..07882cd 100644
--- a/contrib/gcc/config/ia64/linux.h
+++ b/contrib/gcc/config/ia64/linux.h
@@ -58,7 +58,7 @@
 #include <sys/ucontext.h>
 
 #define IA64_GATE_AREA_START 0xa000000000000100LL
-#define IA64_GATE_AREA_END   0xa000000000010000LL
+#define IA64_GATE_AREA_END   0xa000000000020000LL
 
 #define MD_FALLBACK_FRAME_STATE_FOR(CONTEXT, FS, SUCCESS)		\
   if ((CONTEXT)->rp >= IA64_GATE_AREA_START				\
diff --git a/contrib/gcc/config/ia64/sysv4.h b/contrib/gcc/config/ia64/sysv4.h
index c53a1dc..840ebdd 100644
--- a/contrib/gcc/config/ia64/sysv4.h
+++ b/contrib/gcc/config/ia64/sysv4.h
@@ -140,45 +140,136 @@ do {									\
   emit_safe_across_calls (STREAM);					\
 } while (0)
 
+/* A C statement or statements to switch to the appropriate
+   section for output of DECL.  DECL is either a `VAR_DECL' node
+   or a constant of some sort.  RELOC indicates whether forming
+   the initial value of DECL requires link-time relocations.
+
+   Set SECNUM to:
+	0	.text
+	1	.rodata
+	2	.data
+	3	.sdata
+	4	.bss
+	5	.sbss
+*/
+#define DO_SELECT_SECTION(SECNUM, DECL, RELOC)				\
+  do									\
+    {									\
+      if (TREE_CODE (DECL) == FUNCTION_DECL)				\
+	SECNUM = 0;							\
+      else if (TREE_CODE (DECL) == STRING_CST)				\
+	{								\
+	  if (! flag_writable_strings)					\
+	    SECNUM = 0x101;						\
+	  else								\
+	    SECNUM = 2;							\
+	}								\
+      else if (TREE_CODE (DECL) == VAR_DECL)				\
+	{								\
+	  if (XSTR (XEXP (DECL_RTL (DECL), 0), 0)[0]			\
+	      == SDATA_NAME_FLAG_CHAR)					\
+	    SECNUM = 3;							\
+	  /* ??? We need the extra RELOC check, because the default	\
+	     is to only check RELOC if flag_pic is set, and we don't	\
+	     set flag_pic (yet?).  */					\
+	  else if (!DECL_READONLY_SECTION (DECL, RELOC) || (RELOC))	\
+	    SECNUM = 2;							\
+	  else if (flag_merge_constants < 2)				\
+	    /* C and C++ don't allow different variables to share	\
+	       the same location.  -fmerge-all-constants allows		\
+	       even that (at the expense of not conforming).  */	\
+	    SECNUM = 1;							\
+	  else if (TREE_CODE (DECL_INITIAL (DECL)) == STRING_CST)	\
+	    SECNUM = 0x201;						\
+	  else								\
+	    SECNUM = 0x301;						\
+	}								\
+      /* This could be a CONSTRUCTOR containing ADDR_EXPR of a VAR_DECL, \
+	 in which case we can't put it in a shared library rodata.  */	\
+      else if (flag_pic && (RELOC))					\
+	SECNUM = 3;							\
+      else								\
+	SECNUM = 2;							\
+    }									\
+  while (0)
+
 /* We override svr4.h so that we can support the sdata section.  */
 
 #undef SELECT_SECTION
 #define SELECT_SECTION(DECL,RELOC,ALIGN)				\
-{									\
-  if (TREE_CODE (DECL) == STRING_CST)					\
+  do									\
     {									\
-      if (! flag_writable_strings)					\
-	mergeable_string_section ((DECL), (ALIGN), 0);			\
-      else								\
-	data_section ();						\
+      typedef void (*sec_fn) PARAMS ((void));				\
+      static sec_fn const sec_functions[6] =				\
+      {									\
+	text_section,							\
+	const_section,							\
+	data_section,							\
+	sdata_section,							\
+	bss_section,							\
+	sbss_section							\
+      };								\
+									\
+      int sec;								\
+									\
+      DO_SELECT_SECTION (sec, DECL, RELOC);				\
+									\
+      switch (sec)							\
+	{								\
+	case 0x101:							\
+	  mergeable_string_section (DECL, ALIGN, 0);			\
+	  break;							\
+	case 0x201:							\
+	  mergeable_string_section (DECL_INITIAL (DECL),		\
+				    ALIGN, 0);				\
+	  break;							\
+	case 0x301:							\
+	  mergeable_constant_section (DECL_MODE (DECL),			\
+				      ALIGN, 0);			\
+	  break;							\
+	default:							\
+	  (*sec_functions[sec]) ();					\
+	  break;							\
+	}								\
     }									\
-  else if (TREE_CODE (DECL) == VAR_DECL)				\
+  while (0)
+
+#undef  UNIQUE_SECTION
+#define UNIQUE_SECTION(DECL, RELOC)					\
+  do									\
     {									\
-      if (XSTR (XEXP (DECL_RTL (DECL), 0), 0)[0]			\
-	  == SDATA_NAME_FLAG_CHAR)					\
-        sdata_section ();						\
-      /* ??? We need the extra RELOC check, because the default is to	\
-	 only check RELOC if flag_pic is set, and we don't set flag_pic \
-	 (yet?).  */							\
-      else if (!DECL_READONLY_SECTION (DECL, RELOC) || (RELOC))		\
-	data_section ();						\
-      else if (flag_merge_constants < 2)				\
-	/* C and C++ don't allow different variables to share		\
-	   the same location.  -fmerge-all-constants allows		\
-	   even that (at the expense of not conforming).  */		\
-	const_section ();						\
-      else if (TREE_CODE (DECL_INITIAL (DECL)) == STRING_CST)		\
-	mergeable_string_section (DECL_INITIAL (DECL), (ALIGN), 0);	\
-      else								\
-	mergeable_constant_section (DECL_MODE (DECL), (ALIGN), 0);	\
+      static const char * const prefixes[6][2] =			\
+      {									\
+	{ ".text.",   ".gnu.linkonce.t." },				\
+	{ ".rodata.", ".gnu.linkonce.r." },				\
+	{ ".data.",   ".gnu.linkonce.d." },				\
+	{ ".sdata.",  ".gnu.linkonce.s." },				\
+	{ ".bss.",    ".gnu.linkonce.b." },				\
+	{ ".sbss.",   ".gnu.linkonce.sb." }				\
+      };								\
+									\
+      int nlen, plen, sec;						\
+      const char *name, *prefix;					\
+      char *string;							\
+									\
+      DO_SELECT_SECTION (sec, DECL, RELOC);				\
+									\
+      name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (DECL));		\
+      STRIP_NAME_ENCODING (name, name);					\
+      nlen = strlen (name);						\
+									\
+      prefix = prefixes[sec & 0xff][DECL_ONE_ONLY(DECL)];		\
+      plen = strlen (prefix);						\
+									\
+      string = alloca (nlen + plen + 1);				\
+									\
+      memcpy (string, prefix, plen);					\
+      memcpy (string + plen, name, nlen + 1);				\
+									\
+      DECL_SECTION_NAME (DECL) = build_string (nlen + plen, string);	\
     }									\
-  /* This could be a CONSTRUCTOR containing ADDR_EXPR of a VAR_DECL,	\
-     in which case we can't put it in a shared library rodata.  */	\
-  else if (flag_pic && (RELOC))						\
-    data_section ();							\
-  else									\
-    const_section ();							\
-}
+  while (0)
 
 /* Similarly for constant pool data.  */
 
diff --git a/contrib/gcc/config/rs6000/aix43.h b/contrib/gcc/config/rs6000/aix43.h
index 7aa8707..8fe9859 100644
--- a/contrib/gcc/config/rs6000/aix43.h
+++ b/contrib/gcc/config/rs6000/aix43.h
@@ -186,18 +186,15 @@ do {									\
 #undef LINK_SPEC
 #define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro} -bnodelcsect\
    %{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\
-   %{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}"
+   %{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\
+   %{mpe:-binitfini:poe_remote_main}"
 
 #undef STARTFILE_SPEC
 #define STARTFILE_SPEC "%{!shared:\
-   %{mpe:%{pg:/usr/lpp/ppe.poe/lib/gcrt0.o}\
-         %{!pg:%{p:/usr/lpp/ppe.poe/lib/mcrt0.o}\
-               %{!p:/usr/lpp/ppe.poe/lib/crt0.o}}}\
-   %{!mpe:\
-     %{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
-     %{!maix64:\
-       %{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
-       %{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}}"
+   %{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
+   %{!maix64:\
+     %{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
+     %{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}"
 
 /* AIX 4.3 typedefs ptrdiff_t as "long" while earlier releases used "int".  */
 
diff --git a/contrib/gcc/config/rs6000/aix51.h b/contrib/gcc/config/rs6000/aix51.h
index 121c7ba..4051dd0 100644
--- a/contrib/gcc/config/rs6000/aix51.h
+++ b/contrib/gcc/config/rs6000/aix51.h
@@ -189,18 +189,15 @@ do {									\
 #undef LINK_SPEC
 #define LINK_SPEC "-bpT:0x10000000 -bpD:0x20000000 %{!r:-btextro} -bnodelcsect\
    %{static:-bnso %(link_syscalls) } %{shared:-bM:SRE %{!e:-bnoentry}}\
-   %{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}"
+   %{!maix64:%{!shared:%{g*: %(link_libg) }}} %{maix64:-b64}\
+   %{mpe:-binitfini:poe_remote_main}"
 
 #undef STARTFILE_SPEC
 #define STARTFILE_SPEC "%{!shared:\
-   %{mpe:%{pg:/usr/lpp/ppe.poe/lib/gcrt0.o}\
-         %{!pg:%{p:/usr/lpp/ppe.poe/lib/mcrt0.o}\
-               %{!p:/usr/lpp/ppe.poe/lib/crt0.o}}}\
-   %{!mpe:\
-     %{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
-     %{!maix64:\
-       %{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
-       %{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}}"
+   %{maix64:%{pg:gcrt0_64%O%s}%{!pg:%{p:mcrt0_64%O%s}%{!p:crt0_64%O%s}}}\
+   %{!maix64:\
+     %{pthread:%{pg:gcrt0_r%O%s}%{!pg:%{p:mcrt0_r%O%s}%{!p:crt0_r%O%s}}}\
+     %{!pthread:%{pg:gcrt0%O%s}%{!pg:%{p:mcrt0%O%s}%{!p:crt0%O%s}}}}}"
 
 /* AIX V5 typedefs ptrdiff_t as "long" while earlier releases used "int".  */
 
diff --git a/contrib/gcc/config/rs6000/altivec.h b/contrib/gcc/config/rs6000/altivec.h
index 85869dc..f1387c0 100644
--- a/contrib/gcc/config/rs6000/altivec.h
+++ b/contrib/gcc/config/rs6000/altivec.h
@@ -45,8 +45,8 @@ Boston, MA 02111-1307, USA.  */
 #define vector __vector
 
 #define bool signed
-#define pixel short
-#define __pixel short
+#define pixel unsigned short
+#define __pixel unsigned short
 
 /* Dummy prototype.  */
 extern int __altivec_link_error_invalid_argument ();
@@ -122,13 +122,80 @@ extern int __altivec_link_error_invalid_argument ();
    inlined.  */
 inline vector float vec_ctf (vector unsigned int, const char) __attribute__ ((always_inline));
 inline vector float vec_ctf (vector signed int, const char) __attribute__ ((always_inline));
+inline vector float vec_vcfsx (vector signed int a1, const char a2) __attribute__ ((always_inline));
+inline vector float vec_vcfux (vector unsigned int a1, const char a2) __attribute__ ((always_inline));
 inline vector signed int vec_cts (vector float, const char) __attribute__ ((always_inline));
 inline vector unsigned int vec_ctu (vector float, const char) __attribute__ ((always_inline));
 inline void vec_dss (const char) __attribute__ ((always_inline));
-inline void vec_dst (void *, int, const char) __attribute__ ((always_inline));
-inline void vec_dstst (void *, int, const char) __attribute__ ((always_inline));
-inline void vec_dststt (void *, int, const char) __attribute__ ((always_inline));
-inline void vec_dstt (void *, int, const char) __attribute__ ((always_inline));
+
+inline void vec_dst (vector unsigned char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (vector signed char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (vector unsigned short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (vector signed short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (vector unsigned int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (vector signed int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (vector float *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (unsigned char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (signed char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (unsigned short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (signed short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (unsigned int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (signed int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (unsigned long *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (signed long *, int, const char) __attribute__ ((always_inline));
+inline void vec_dst (float *, int, const char) __attribute__ ((always_inline));
+
+inline void vec_dstst (vector unsigned char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (vector signed char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (vector unsigned short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (vector signed short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (vector unsigned int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (vector signed int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (vector float *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (unsigned char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (signed char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (unsigned short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (signed short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (unsigned int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (signed int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (unsigned long *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (signed long *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstst (float *, int, const char) __attribute__ ((always_inline));
+
+inline void vec_dststt (vector unsigned char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (vector signed char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (vector unsigned short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (vector signed short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (vector unsigned int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (vector signed int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (vector float *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (unsigned char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (signed char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (unsigned short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (signed short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (unsigned int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (signed int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (unsigned long *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (signed long *, int, const char) __attribute__ ((always_inline));
+inline void vec_dststt (float *, int, const char) __attribute__ ((always_inline));
+
+inline void vec_dstt (vector unsigned char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (vector signed char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (vector unsigned short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (vector signed short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (vector unsigned int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (vector signed int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (vector float *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (unsigned char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (signed char *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (unsigned short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (signed short *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (unsigned int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (signed int *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (unsigned long *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (signed long *, int, const char) __attribute__ ((always_inline));
+inline void vec_dstt (float *, int, const char) __attribute__ ((always_inline));
+
 inline vector float vec_sld (vector float, vector float, const char) __attribute__ ((always_inline));
 inline vector signed int vec_sld (vector signed int, vector signed int, const char) __attribute__ ((always_inline));
 inline vector unsigned int vec_sld (vector unsigned int, vector unsigned int, const char) __attribute__ ((always_inline));
@@ -149,6 +216,13 @@ inline vector signed int vec_splat_s32 (const char) __attribute__ ((always_inlin
 inline vector unsigned char vec_splat_u8 (const char) __attribute__ ((always_inline));
 inline vector unsigned short vec_splat_u16 (const char) __attribute__ ((always_inline));
 inline vector unsigned int vec_splat_u32 (const char) __attribute__ ((always_inline));
+inline vector float vec_vspltw (vector float a1, const char a2) __attribute__ ((always_inline));
+inline vector signed int vec_vspltw (vector signed int a1, const char a2) __attribute__ ((always_inline));
+inline vector unsigned int vec_vspltw (vector unsigned int a1, const char a2) __attribute__ ((always_inline));
+inline vector signed short vec_vsplth (vector signed short a1, const char a2) __attribute__ ((always_inline));
+inline vector unsigned short vec_vsplth (vector unsigned short a1, const char a2) __attribute__ ((always_inline));
+inline vector signed char vec_vspltb (vector signed char a1, const char a2) __attribute__ ((always_inline));
+inline vector unsigned char vec_vspltb (vector unsigned char a1, const char a2) __attribute__ ((always_inline));
 
 /* vec_abs */
 
@@ -1132,7 +1206,97 @@ vec_dssall ()
 /* vec_dst */
 
 inline void
-vec_dst (void *a1, int a2, const char a3)
+vec_dst (vector unsigned char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (vector signed char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (vector unsigned short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (vector signed short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (vector unsigned int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (vector signed int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (vector float *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (unsigned char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (signed char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (unsigned short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (signed short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (unsigned int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (signed int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (unsigned long *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (signed long *a1, int a2, const char a3)
+{
+  __builtin_altivec_dst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dst (float *a1, int a2, const char a3)
 {
   __builtin_altivec_dst ((void *) a1, a2, a3);
 }
@@ -1140,7 +1304,97 @@ vec_dst (void *a1, int a2, const char a3)
 /* vec_dstst */
 
 inline void
-vec_dstst (void *a1, int a2, const char a3)
+vec_dstst (vector unsigned char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (vector signed char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (vector unsigned short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (vector signed short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (vector unsigned int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (vector signed int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (vector float *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (unsigned char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (signed char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (unsigned short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (signed short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (unsigned int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (signed int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (unsigned long *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (signed long *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstst ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstst (float *a1, int a2, const char a3)
 {
   __builtin_altivec_dstst ((void *) a1, a2, a3);
 }
@@ -1148,7 +1402,97 @@ vec_dstst (void *a1, int a2, const char a3)
 /* vec_dststt */
 
 inline void
-vec_dststt (void *a1, int a2, const char a3)
+vec_dststt (vector unsigned char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (vector signed char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (vector unsigned short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (vector signed short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (vector unsigned int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (vector signed int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (vector float *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (unsigned char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (signed char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (unsigned short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (signed short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (unsigned int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (signed int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (unsigned long *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (signed long *a1, int a2, const char a3)
+{
+  __builtin_altivec_dststt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dststt (float *a1, int a2, const char a3)
 {
   __builtin_altivec_dststt ((void *) a1, a2, a3);
 }
@@ -1156,7 +1500,97 @@ vec_dststt (void *a1, int a2, const char a3)
 /* vec_dstt */
 
 inline void
-vec_dstt (void *a1, int a2, const char a3)
+vec_dstt (vector unsigned char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (vector signed char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (vector unsigned short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (vector signed short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (vector unsigned int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (vector signed int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (vector float *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (unsigned char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (signed char *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (unsigned short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (signed short *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (unsigned int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (signed int *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (unsigned long *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (signed long *a1, int a2, const char a3)
+{
+  __builtin_altivec_dstt ((void *) a1, a2, a3);
+}
+
+inline void
+vec_dstt (float *a1, int a2, const char a3)
 {
   __builtin_altivec_dstt ((void *) a1, a2, a3);
 }
@@ -1203,6 +1637,12 @@ vec_ld (int a1, signed int *a2)
   return (vector signed int) __builtin_altivec_lvx (a1, (void *) a2);
 }
 
+inline vector signed int
+vec_ld (int a1, signed long *a2)
+{
+  return (vector signed int) __builtin_altivec_lvx (a1, (void *) a2);
+}
+
 inline vector unsigned int
 vec_ld (int a1, vector unsigned int *a2)
 {
@@ -1215,6 +1655,12 @@ vec_ld (int a1, unsigned int *a2)
   return (vector unsigned int) __builtin_altivec_lvx (a1, (void *) a2);
 }
 
+inline vector unsigned int
+vec_ld (int a1, unsigned long *a2)
+{
+  return (vector unsigned int) __builtin_altivec_lvx (a1, (void *) a2);
+}
+
 inline vector signed short
 vec_ld (int a1, vector signed short *a2)
 {
@@ -1307,6 +1753,18 @@ vec_lde (int a1, unsigned int *a2)
   return (vector unsigned int) __builtin_altivec_lvewx (a1, (void *) a2);
 }
 
+inline vector signed int
+vec_lde (int a1, signed long *a2)
+{
+  return (vector signed int) __builtin_altivec_lvewx (a1, (void *) a2);
+}
+
+inline vector unsigned int
+vec_lde (int a1, unsigned long *a2)
+{
+  return (vector unsigned int) __builtin_altivec_lvewx (a1, (void *) a2);
+}
+
 /* vec_lvewx */
 
 inline vector float
@@ -1327,6 +1785,18 @@ vec_lvewx (int a1, unsigned int *a2)
   return (vector unsigned int) __builtin_altivec_lvewx (a1, (void *) a2);
 }
 
+inline vector signed int
+vec_lvewx (int a1, signed long *a2)
+{
+  return (vector signed int) __builtin_altivec_lvewx (a1, (void *) a2);
+}
+
+inline vector unsigned int
+vec_lvewx (int a1, unsigned long *a2)
+{
+  return (vector unsigned int) __builtin_altivec_lvewx (a1, (void *) a2);
+}
+
 /* vec_lvehx */
 
 inline vector signed short
@@ -1381,6 +1851,12 @@ vec_ldl (int a1, signed int *a2)
   return (vector signed int) __builtin_altivec_lvxl (a1, (void *) a2);
 }
 
+inline vector signed int
+vec_ldl (int a1, signed long *a2)
+{
+  return (vector signed int) __builtin_altivec_lvxl (a1, (void *) a2);
+}
+
 inline vector unsigned int
 vec_ldl (int a1, vector unsigned int *a2)
 {
@@ -1393,6 +1869,12 @@ vec_ldl (int a1, unsigned int *a2)
   return (vector unsigned int) __builtin_altivec_lvxl (a1, (void *) a2);
 }
 
+inline vector unsigned int
+vec_ldl (int a1, unsigned long *a2)
+{
+  return (vector unsigned int) __builtin_altivec_lvxl (a1, (void *) a2);
+}
+
 inline vector signed short
 vec_ldl (int a1, vector signed short *a2)
 {
@@ -1488,6 +1970,18 @@ vec_lvsl (int a1, signed int *a2)
 }
 
 inline vector unsigned char
+vec_lvsl (int a1, unsigned long *a2)
+{
+  return (vector unsigned char) __builtin_altivec_lvsl (a1, (void *) a2);
+}
+
+inline vector unsigned char
+vec_lvsl (int a1, signed long *a2)
+{
+  return (vector unsigned char) __builtin_altivec_lvsl (a1, (void *) a2);
+}
+
+inline vector unsigned char
 vec_lvsl (int a1, float *a2)
 {
   return (vector unsigned char) __builtin_altivec_lvsl (a1, (void *) a2);
@@ -1532,6 +2026,18 @@ vec_lvsr (int a1, signed int *a2)
 }
 
 inline vector unsigned char
+vec_lvsr (int a1, unsigned long *a2)
+{
+  return (vector unsigned char) __builtin_altivec_lvsr (a1, (void *) a2);
+}
+
+inline vector unsigned char
+vec_lvsr (int a1, signed long *a2)
+{
+  return (vector unsigned char) __builtin_altivec_lvsr (a1, (void *) a2);
+}
+
+inline vector unsigned char
 vec_lvsr (int a1, float *a2)
 {
   return (vector unsigned char) __builtin_altivec_lvsr (a1, (void *) a2);
@@ -2557,10 +3063,10 @@ vec_vpkuhum (vector unsigned short a1, vector unsigned short a2)
 
 /* vec_packpx */
 
-inline vector signed short
+inline vector unsigned short
 vec_packpx (vector unsigned int a1, vector unsigned int a2)
 {
-  return (vector signed short) __builtin_altivec_vpkpx ((vector signed int) a1, (vector signed int) a2);
+  return (vector unsigned short) __builtin_altivec_vpkpx ((vector signed int) a1, (vector signed int) a2);
 }
 
 /* vec_packs */
@@ -4321,6 +4827,12 @@ vec_unpackh (vector signed short a1)
   return (vector signed int) __builtin_altivec_vupkhsh ((vector signed short) a1);
 }
 
+inline vector unsigned int
+vec_unpackh (vector unsigned short a1)
+{
+  return (vector unsigned int) __builtin_altivec_vupkhpx ((vector signed short) a1);
+}
+
 /* vec_vupkhsh */
 
 inline vector signed int
@@ -4332,7 +4844,7 @@ vec_vupkhsh (vector signed short a1)
 /* vec_vupkhpx */
 
 inline vector unsigned int
-vec_vupkhpx (vector signed short a1)
+vec_vupkhpx (vector unsigned short a1)
 {
   return (vector unsigned int) __builtin_altivec_vupkhpx ((vector signed short) a1);
 }
@@ -4354,7 +4866,7 @@ vec_unpackl (vector signed char a1)
 }
 
 inline vector unsigned int
-vec_vupklpx (vector signed short a1)
+vec_unpackl (vector unsigned short a1)
 {
   return (vector unsigned int) __builtin_altivec_vupklpx ((vector signed short) a1);
 }
@@ -4365,6 +4877,14 @@ vec_unpackl (vector signed short a1)
   return (vector signed int) __builtin_altivec_vupklsh ((vector signed short) a1);
 }
 
+/* vec_vupklpx */
+
+inline vector unsigned int
+vec_vupklpx (vector unsigned short a1)
+{
+  return (vector unsigned int) __builtin_altivec_vupklpx ((vector signed short) a1);
+}
+
 /* vec_upklsh */
 
 inline vector signed int
@@ -4630,7 +5150,7 @@ vec_all_ge (vector signed int a1, vector signed int a2)
 inline int
 vec_all_ge (vector float a1, vector float a2)
 {
-  return __builtin_altivec_vcmpgefp_p (__CR6_EQ, a1, a2);
+  return __builtin_altivec_vcmpgefp_p (__CR6_LT, a1, a2);
 }
 
 /* vec_all_gt */
@@ -5326,7 +5846,7 @@ vec_any_le (vector signed int a1, vector signed int a2)
 inline int
 vec_any_le (vector float a1, vector float a2)
 {
-  return __builtin_altivec_vcmpgefp_p (__CR6_LT_REV, a2, a1);
+  return __builtin_altivec_vcmpgefp_p (__CR6_EQ_REV, a2, a1);
 }
 
 /* vec_any_lt */
@@ -5595,7 +6115,7 @@ struct __vec_step_help<vector float>
   static const int _S_elem = 4;
 };
 
-#define vec_step(t)  __vec_step_help<t>::_S_elem
+#define vec_step(t)  __vec_step_help<typeof(t)>::_S_elem
 
 #else /* not C++ */
 
@@ -5623,13 +6143,13 @@ struct __vec_step_help<vector float>
   __altivec_link_error_invalid_argument ())))
 
 #define vec_step(t) \
-  __ch (__builtin_types_compatible_p (t, vector signed int), 4,		\
-  __ch (__builtin_types_compatible_p (t, vector unsigned int), 4,	\
-  __ch (__builtin_types_compatible_p (t, vector signed short), 8,	\
-  __ch (__builtin_types_compatible_p (t, vector unsigned short), 8,	\
-  __ch (__builtin_types_compatible_p (t, vector signed char), 16,	\
-  __ch (__builtin_types_compatible_p (t, vector unsigned char), 16,	\
-  __ch (__builtin_types_compatible_p (t, vector float), 4,		\
+  __ch (__builtin_types_compatible_p (typeof (t), vector signed int), 4,      \
+  __ch (__builtin_types_compatible_p (typeof (t), vector unsigned int), 4,    \
+  __ch (__builtin_types_compatible_p (typeof (t), vector signed short), 8,    \
+  __ch (__builtin_types_compatible_p (typeof (t), vector unsigned short), 8,  \
+  __ch (__builtin_types_compatible_p (typeof (t), vector signed char), 16,    \
+  __ch (__builtin_types_compatible_p (typeof (t), vector unsigned char), 16,  \
+  __ch (__builtin_types_compatible_p (typeof (t), vector float), 4,           \
   __altivec_link_error_invalid_argument ())))))))
 
 #define vec_vaddubm(a1, a2) \
@@ -5813,8 +6333,10 @@ __ch (__bin_args_eq (vector float, (a1), vector unsigned int, (a2)), \
       ((vector float) __builtin_altivec_vandc ((vector signed int) (a1), (vector signed int) (a2))), \
 __ch (__bin_args_eq (vector unsigned int, (a1), vector float, (a2)), \
       ((vector float) __builtin_altivec_vandc ((vector signed int) (a1), (vector signed int) (a2))), \
-__ch (__bin_args_eq (vector unsigned int, (a1), vector unsigned int, (a2)), \
-      ((vector unsigned int) __builtin_altivec_vandc ((vector signed int) (a1), (vector signed int) (a2))), \
+__ch (__bin_args_eq (vector signed int, (a1), vector float, (a2)), \
+      ((vector float) __builtin_altivec_vandc ((vector signed int) (a1), (vector signed int) (a2))), \
+__ch (__bin_args_eq (vector float, (a1), vector signed int, (a2)), \
+      ((vector float) __builtin_altivec_vandc ((vector signed int) (a1), (vector signed int) (a2))), \
 __ch (__bin_args_eq (vector signed int, (a1), vector unsigned int, (a2)), \
       ((vector unsigned int) __builtin_altivec_vandc ((vector signed int) (a1), (vector signed int) (a2))), \
 __ch (__bin_args_eq (vector signed int, (a1), vector signed int, (a2)), \
@@ -5826,9 +6348,9 @@ __ch (__bin_args_eq (vector unsigned int, (a1), vector unsigned int, (a2)), \
 __ch (__bin_args_eq (vector unsigned short, (a1), vector unsigned short, (a2)), \
       ((vector unsigned short) __builtin_altivec_vandc ((vector signed int) (a1), (vector signed int) (a2))), \
 __ch (__bin_args_eq (vector signed short, (a1), vector unsigned short, (a2)), \
-      ((vector signed short) __builtin_altivec_vandc ((vector signed int) (a1), (vector signed int) (a2))), \
+      ((vector unsigned short) __builtin_altivec_vandc ((vector signed int) (a1), (vector signed int) (a2))), \
 __ch (__bin_args_eq (vector unsigned short, (a1), vector signed short, (a2)), \
-      ((vector signed short) __builtin_altivec_vandc ((vector signed int) (a1), (vector signed int) (a2))), \
+      ((vector unsigned short) __builtin_altivec_vandc ((vector signed int) (a1), (vector signed int) (a2))), \
 __ch (__bin_args_eq (vector unsigned short, (a1), vector unsigned short, (a2)), \
       ((vector signed short) __builtin_altivec_vandc ((vector signed int) (a1), (vector signed int) (a2))), \
 __ch (__bin_args_eq (vector signed short, (a1), vector signed short, (a2)), \
@@ -5851,7 +6373,7 @@ __ch (__bin_args_eq (vector signed char, (a1), vector signed char, (a2)), \
       ((vector signed char) __builtin_altivec_vandc ((vector signed int) (a1), (vector signed int) (a2))), \
 __ch (__bin_args_eq (vector unsigned char, (a1), vector signed char, (a2)), \
       ((vector signed char) __builtin_altivec_vandc ((vector signed int) (a1), (vector signed int) (a2))), \
-    __altivec_link_error_invalid_argument ()))))))))))))))))))))))
+    __altivec_link_error_invalid_argument ())))))))))))))))))))))))
 
 #define vec_avg(a1, a2) \
 __ch (__bin_args_eq (vector unsigned char, (a1), vector unsigned char, (a2)), \
@@ -6023,17 +6545,25 @@ __ch (__bin_args_eq (vector unsigned int, (a1), int, (a2)), \
       ((vector float) __builtin_altivec_vcfux ((vector signed int) (a1), (const char) (a2))), \
 __ch (__bin_args_eq (vector signed int, (a1), int, (a2)), \
       ((vector float) __builtin_altivec_vcfsx ((vector signed int) (a1), (const char) (a2))), \
-    __altivec_link_error_invalid_argument ()))
+__ch (__bin_args_eq (vector unsigned int, (a1), unsigned int, (a2)), \
+      ((vector float) __builtin_altivec_vcfux ((vector signed int) (a1), (const char) (a2))), \
+__ch (__bin_args_eq (vector signed int, (a1), unsigned int, (a2)), \
+      ((vector float) __builtin_altivec_vcfsx ((vector signed int) (a1), (const char) (a2))), \
+    __altivec_link_error_invalid_argument ()))))
 
 #define vec_vcfsx(a1, a2) \
 __ch (__bin_args_eq (vector signed int, (a1), int, (a2)), \
       ((vector float) __builtin_altivec_vcfsx ((vector signed int) (a1), (const char) (a2))), \
-  __altivec_link_error_invalid_argument ())
+__ch (__bin_args_eq (vector signed int, (a1), unsigned int, (a2)), \
+      ((vector float) __builtin_altivec_vcfsx ((vector signed int) (a1), (const char) (a2))), \
+  __altivec_link_error_invalid_argument ()))
 
 #define vec_vcfux(a1, a2) \
 __ch (__bin_args_eq (vector unsigned int, (a1), int, (a2)), \
       ((vector float) __builtin_altivec_vcfux ((vector signed int) (a1), (const char) (a2))), \
-  __altivec_link_error_invalid_argument ())
+__ch (__bin_args_eq (vector unsigned int, (a1), unsigned int, (a2)), \
+      ((vector float) __builtin_altivec_vcfux ((vector signed int) (a1), (const char) (a2))), \
+  __altivec_link_error_invalid_argument ()))
 
 #define vec_cts(a1, a2) __builtin_altivec_vctsxs ((a1), (a2))
 
@@ -6043,209 +6573,311 @@ __ch (__bin_args_eq (vector unsigned int, (a1), int, (a2)), \
 
 #define vec_dssall() __builtin_altivec_dssall ()
 
-#define vec_dst(a1, a2, a3) __builtin_altivec_dst ((a1), (a2), (a3))
-
-#define vec_dstst(a1, a2, a3) __builtin_altivec_dstst ((a1), (a2), (a3))
-
-#define vec_dststt(a1, a2, a3) __builtin_altivec_dststt ((a1), (a2), (a3))
-
-#define vec_dstt(a1, a2, a3) __builtin_altivec_dstt ((a1), (a2), (a3))
+#define vec_dst(a1, a2, a3) \
+__ch (__un_args_eq (vector unsigned char, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector signed char, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector unsigned short, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector signed short, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector unsigned int, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector signed int, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector float, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned char, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed char, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned short, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed short, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned int, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed int, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned long, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed long, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (float, *(a1)), \
+      __builtin_altivec_dst ((void *) (a1), (a2), (a3)), \
+  __altivec_link_error_invalid_argument ()))))))))))))))))
+
+#define vec_dstst(a1, a2, a3) \
+__ch (__un_args_eq (vector unsigned char, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector signed char, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector unsigned short, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector signed short, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector unsigned int, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector signed int, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector float, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned char, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed char, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned short, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed short, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned int, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed int, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned long, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed long, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (float, *(a1)), \
+      __builtin_altivec_dstst ((void *) (a1), (a2), (a3)), \
+  __altivec_link_error_invalid_argument ()))))))))))))))))
+
+#define vec_dststt(a1, a2, a3) \
+__ch (__un_args_eq (vector unsigned char, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector signed char, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector unsigned short, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector signed short, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector unsigned int, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector signed int, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector float, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned char, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed char, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned short, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed short, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned int, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed int, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned long, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed long, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (float, *(a1)), \
+      __builtin_altivec_dststt ((void *) (a1), (a2), (a3)), \
+  __altivec_link_error_invalid_argument ()))))))))))))))))
+
+#define vec_dstt(a1, a2, a3) \
+__ch (__un_args_eq (vector unsigned char, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector signed char, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector unsigned short, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector signed short, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector unsigned int, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector signed int, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (vector float, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned char, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed char, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned short, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed short, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned int, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed int, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (unsigned long, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (signed long, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+__ch (__un_args_eq (float, *(a1)), \
+      __builtin_altivec_dstt ((void *) (a1), (a2), (a3)), \
+  __altivec_link_error_invalid_argument ()))))))))))))))))
 
 #define vec_expte(a1) __builtin_altivec_vexptefp ((a1))
 
 #define vec_floor(a1) __builtin_altivec_vrfim (a1)
 
 #define vec_ld(a, b) \
-__ch (__un_args_eq (vector unsigned char *, (b)), \
-      ((vector unsigned char) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (vector unsigned char [], (b)), \
+__ch (__un_args_eq (vector unsigned char, *(b)), \
       ((vector unsigned char) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (unsigned char *, (b)), \
+__ch (__un_args_eq (unsigned char, *(b)), \
       ((vector unsigned char) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (unsigned char [], (b)), \
-      ((vector unsigned char) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (vector signed char *, (b)), \
-      ((vector signed char) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (vector signed char [], (b)), \
-      ((vector signed char) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (signed char *, (b)), \
+__ch (__un_args_eq (vector signed char, *(b)), \
       ((vector signed char) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (signed char [], (b)), \
+__ch (__un_args_eq (signed char, *(b)), \
       ((vector signed char) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (vector unsigned short *, (b)), \
+__ch (__un_args_eq (vector unsigned short, *(b)), \
       ((vector unsigned short) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (vector unsigned short [], (b)), \
+__ch (__un_args_eq (unsigned short, *(b)), \
       ((vector unsigned short) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (unsigned short *, (b)), \
-      ((vector unsigned short) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (unsigned short [], (b)), \
-      ((vector unsigned short) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (vector signed short *, (b)), \
-      ((vector signed short) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (vector signed short [], (b)), \
-      ((vector signed short) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (signed short *, (b)), \
+__ch (__un_args_eq (vector signed short, *(b)), \
       ((vector signed short) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (signed short [], (b)), \
+__ch (__un_args_eq (signed short, *(b)), \
       ((vector signed short) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (vector unsigned int *, (b)), \
+__ch (__un_args_eq (vector unsigned int, *(b)), \
       ((vector unsigned int) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (vector unsigned int [], (b)), \
+__ch (__un_args_eq (unsigned int, *(b)), \
       ((vector unsigned int) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (unsigned int *, (b)), \
+__ch (__un_args_eq (unsigned long, *(b)), \
       ((vector unsigned int) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (unsigned int [], (b)), \
-      ((vector unsigned int) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (vector signed int *, (b)), \
-      ((vector signed int) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (vector signed int [], (b)), \
+__ch (__un_args_eq (vector signed int, *(b)), \
       ((vector signed int) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (signed int *, (b)), \
+__ch (__un_args_eq (signed int, *(b)), \
       ((vector signed int) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (signed int [], (b)), \
+__ch (__un_args_eq (signed long, *(b)), \
       ((vector signed int) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (vector float *, (b)), \
-      ((vector float) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (vector float [], (b)), \
-      ((vector float) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (float *, (b)), \
+__ch (__un_args_eq (vector float, *(b)), \
       ((vector float) __builtin_altivec_lvx ((a), (b))), \
-__ch (__un_args_eq (float [], (b)), \
+__ch (__un_args_eq (float, *(b)), \
       ((vector float) __builtin_altivec_lvx ((a), (b))), \
-__altivec_link_error_invalid_argument ()))))))))))))))))))))))))))))
+__altivec_link_error_invalid_argument ()))))))))))))))))
 
 #define vec_lde(a, b) \
-__ch (__un_args_eq (unsigned char *, (b)), \
+__ch (__un_args_eq (unsigned char, *(b)), \
       ((vector unsigned char) __builtin_altivec_lvebx ((a), (b))), \
-__ch (__un_args_eq (unsigned char [], (b)), \
-      ((vector unsigned char) __builtin_altivec_lvebx ((a), (b))), \
-__ch (__un_args_eq (signed char *, (b)), \
-      ((vector signed char) __builtin_altivec_lvebx ((a), (b))), \
-__ch (__un_args_eq (signed char [], (b)), \
+__ch (__un_args_eq (signed char, *(b)), \
       ((vector signed char) __builtin_altivec_lvebx ((a), (b))), \
-__ch (__un_args_eq (unsigned short *, (b)), \
+__ch (__un_args_eq (unsigned short, *(b)), \
       ((vector unsigned short) __builtin_altivec_lvehx ((a), (b))), \
-__ch (__un_args_eq (unsigned short [], (b)), \
-      ((vector unsigned short) __builtin_altivec_lvehx ((a), (b))), \
-__ch (__un_args_eq (signed short *, (b)), \
-      ((vector signed short) __builtin_altivec_lvehx ((a), (b))), \
-__ch (__un_args_eq (signed short [], (b)), \
+__ch (__un_args_eq (signed short, *(b)), \
       ((vector signed short) __builtin_altivec_lvehx ((a), (b))), \
-__ch (__un_args_eq (unsigned int *, (b)), \
+__ch (__un_args_eq (unsigned long, *(b)), \
       ((vector unsigned int) __builtin_altivec_lvewx ((a), (b))), \
-__ch (__un_args_eq (unsigned int [], (b)), \
-      ((vector unsigned int) __builtin_altivec_lvewx ((a), (b))), \
-__ch (__un_args_eq (signed int *, (b)), \
+__ch (__un_args_eq (signed long, *(b)), \
       ((vector signed int) __builtin_altivec_lvewx ((a), (b))), \
-__ch (__un_args_eq (signed int [], (b)), \
+__ch (__un_args_eq (unsigned int, *(b)), \
+      ((vector unsigned int) __builtin_altivec_lvewx ((a), (b))), \
+__ch (__un_args_eq (signed int, *(b)), \
       ((vector signed int) __builtin_altivec_lvewx ((a), (b))), \
-__ch (__un_args_eq (float *, (b)), \
+__ch (__un_args_eq (float, *(b)), \
       ((vector float) __builtin_altivec_lvewx ((a), (b))), \
-__ch (__un_args_eq (float [], (b)), \
-      ((vector float) __builtin_altivec_lvewx ((a), (b))), \
-__altivec_link_error_invalid_argument ()))))))))))))))
+__altivec_link_error_invalid_argument ())))))))))
 
 #define vec_lvewx(a, b) \
-__ch (__un_args_eq (unsigned int *, (b)), \
-      ((vector unsigned int) __builtin_altivec_lvewx ((a), (b))), \
-__ch (__un_args_eq (unsigned int [], (b)), \
+__ch (__un_args_eq (unsigned int, *(b)), \
       ((vector unsigned int) __builtin_altivec_lvewx ((a), (b))), \
-__ch (__un_args_eq (signed int *, (b)), \
+__ch (__un_args_eq (signed int, *(b)), \
       ((vector signed int) __builtin_altivec_lvewx ((a), (b))), \
-__ch (__un_args_eq (signed int [], (b)), \
+__ch (__un_args_eq (unsigned long, *(b)), \
+      ((vector unsigned int) __builtin_altivec_lvewx ((a), (b))), \
+__ch (__un_args_eq (signed long, *(b)), \
       ((vector signed int) __builtin_altivec_lvewx ((a), (b))), \
-__ch (__un_args_eq (float *, (b)), \
-      ((vector float) __builtin_altivec_lvewx ((a), (b))), \
-__ch (__un_args_eq (float [], (b)), \
+__ch (__un_args_eq (float, *(b)), \
       ((vector float) __builtin_altivec_lvewx ((a), (b))), \
-__altivec_link_error_invalid_argument ()))))))
+__altivec_link_error_invalid_argument ())))))
 
 #define vec_lvehx(a, b) \
-__ch (__un_args_eq (unsigned short *, (b)), \
-      ((vector unsigned short) __builtin_altivec_lvehx ((a), (b))), \
-__ch (__un_args_eq (unsigned short [], (b)), \
+__ch (__un_args_eq (unsigned short, *(b)), \
       ((vector unsigned short) __builtin_altivec_lvehx ((a), (b))), \
-__ch (__un_args_eq (signed short *, (b)), \
+__ch (__un_args_eq (signed short, *(b)), \
       ((vector signed short) __builtin_altivec_lvehx ((a), (b))), \
-__ch (__un_args_eq (signed short [], (b)), \
-      ((vector signed short) __builtin_altivec_lvehx ((a), (b))), \
-__altivec_link_error_invalid_argument ()))))
+__altivec_link_error_invalid_argument ()))
 
 #define vec_lvebx(a, b) \
-__ch (__un_args_eq (unsigned char *, (b)), \
-      ((vector unsigned char) __builtin_altivec_lvebx ((a), (b))), \
-__ch (__un_args_eq (unsigned char [], (b)), \
+__ch (__un_args_eq (unsigned char, *(b)), \
       ((vector unsigned char) __builtin_altivec_lvebx ((a), (b))), \
-__ch (__un_args_eq (signed char *, (b)), \
+__ch (__un_args_eq (signed char, *(b)), \
       ((vector signed char) __builtin_altivec_lvebx ((a), (b))), \
-__ch (__un_args_eq (signed char [], (b)), \
-      ((vector signed char) __builtin_altivec_lvebx ((a), (b))), \
-__altivec_link_error_invalid_argument ()))))
+__altivec_link_error_invalid_argument ()))
 
 #define vec_ldl(a, b) \
-__ch (__un_args_eq (vector unsigned char *, (b)), \
-      ((vector unsigned char) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (vector unsigned char [], (b)), \
+__ch (__un_args_eq (vector unsigned char, *(b)), \
       ((vector unsigned char) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (unsigned char *, (b)), \
+__ch (__un_args_eq (unsigned char, *(b)), \
       ((vector unsigned char) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (unsigned char [], (b)), \
-      ((vector unsigned char) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (vector signed char *, (b)), \
-      ((vector signed char) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (vector signed char [], (b)), \
-      ((vector signed char) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (signed char *, (b)), \
+__ch (__un_args_eq (vector signed char, *(b)), \
       ((vector signed char) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (signed char [], (b)), \
+__ch (__un_args_eq (signed char, *(b)), \
       ((vector signed char) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (vector unsigned short *, (b)), \
+__ch (__un_args_eq (vector unsigned short, *(b)), \
       ((vector unsigned short) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (vector unsigned short [], (b)), \
+__ch (__un_args_eq (unsigned short, *(b)), \
       ((vector unsigned short) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (unsigned short *, (b)), \
-      ((vector unsigned short) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (unsigned short [], (b)), \
-      ((vector unsigned short) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (vector signed short *, (b)), \
-      ((vector signed short) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (vector signed short [], (b)), \
-      ((vector signed short) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (signed short *, (b)), \
+__ch (__un_args_eq (vector signed short, *(b)), \
       ((vector signed short) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (signed short [], (b)), \
+__ch (__un_args_eq (signed short, *(b)), \
       ((vector signed short) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (vector unsigned int *, (b)), \
+__ch (__un_args_eq (vector unsigned int, *(b)), \
       ((vector unsigned int) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (vector unsigned int [], (b)), \
+__ch (__un_args_eq (unsigned int, *(b)), \
       ((vector unsigned int) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (unsigned int *, (b)), \
+__ch (__un_args_eq (unsigned long, *(b)), \
       ((vector unsigned int) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (unsigned int [], (b)), \
-      ((vector unsigned int) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (vector signed int *, (b)), \
-      ((vector signed int) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (vector signed int [], (b)), \
+__ch (__un_args_eq (vector signed int, *(b)), \
       ((vector signed int) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (signed int *, (b)), \
+__ch (__un_args_eq (signed int, *(b)), \
       ((vector signed int) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (signed int [], (b)), \
+__ch (__un_args_eq (signed long, *(b)), \
       ((vector signed int) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (vector float *, (b)), \
-      ((vector float) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (vector float [], (b)), \
-      ((vector float) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (float *, (b)), \
+__ch (__un_args_eq (vector float, *(b)), \
       ((vector float) __builtin_altivec_lvxl ((a), (b))), \
-__ch (__un_args_eq (float [], (b)), \
+__ch (__un_args_eq (float, *(b)), \
       ((vector float) __builtin_altivec_lvxl ((a), (b))), \
-__altivec_link_error_invalid_argument ()))))))))))))))))))))))))))))
+__altivec_link_error_invalid_argument ()))))))))))))))))
 
 #define vec_loge(a1) __builtin_altivec_vlogefp ((a1))
 
-#define vec_lvsl(a1, a2) ((vector unsigned char) __builtin_altivec_lvsl ((a1), (a2)))
-
-#define vec_lvsr(a1, a2) ((vector unsigned char) __builtin_altivec_lvsr ((a1), (a2)))
+#define vec_lvsl(a1, a2) \
+__ch (__un_args_eq (unsigned char, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsl ((a1), (void *) (a2))), \
+__ch (__un_args_eq (signed char, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsl ((a1), (void *) (a2))), \
+__ch (__un_args_eq (unsigned short, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsl ((a1), (void *) (a2))), \
+__ch (__un_args_eq (signed short, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsl ((a1), (void *) (a2))), \
+__ch (__un_args_eq (unsigned int, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsl ((a1), (void *) (a2))), \
+__ch (__un_args_eq (signed int, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsl ((a1), (void *) (a2))), \
+__ch (__un_args_eq (unsigned long, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsl ((a1), (void *) (a2))), \
+__ch (__un_args_eq (signed long, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsl ((a1), (void *) (a2))), \
+__ch (__un_args_eq (float, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsl ((a1), (void *) (a2))), \
+__altivec_link_error_invalid_argument ())))))))))
+
+#define vec_lvsr(a1, a2) \
+__ch (__un_args_eq (unsigned char, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsr ((a1), (void *) (a2))), \
+__ch (__un_args_eq (signed char, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsr ((a1), (void *) (a2))), \
+__ch (__un_args_eq (unsigned short, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsr ((a1), (void *) (a2))), \
+__ch (__un_args_eq (signed short, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsr ((a1), (void *) (a2))), \
+__ch (__un_args_eq (unsigned int, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsr ((a1), (void *) (a2))), \
+__ch (__un_args_eq (signed int, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsr ((a1), (void *) (a2))), \
+__ch (__un_args_eq (unsigned long, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsr ((a1), (void *) (a2))), \
+__ch (__un_args_eq (signed long, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsr ((a1), (void *) (a2))), \
+__ch (__un_args_eq (float, *(a2)), \
+      ((vector unsigned char) __builtin_altivec_lvsr ((a1), (void *) (a2))), \
+__altivec_link_error_invalid_argument ())))))))))
 
 #define vec_madd(a1, a2, a3) (__builtin_altivec_vmaddfp ((a1), (a2), (a3)))
 
@@ -6524,7 +7156,7 @@ __ch (__tern_args_eq (vector signed char, (a1), vector unsigned char, (a2), vect
       ((vector signed int) __builtin_altivec_vmsummbm ((vector signed char) (a1), (vector signed char) (a2), (vector signed int) (a3))), \
 __altivec_link_error_invalid_argument ())
 
-#define vec_msumubm(a1, a2, a3) \
+#define vec_vmsumubm(a1, a2, a3) \
 __ch (__tern_args_eq (vector unsigned char, (a1), vector unsigned char, (a2), vector unsigned int, (a3)), \
       ((vector unsigned int) __builtin_altivec_vmsumubm ((vector signed char) (a1), (vector signed char) (a2), (vector signed int) (a3))), \
 __altivec_link_error_invalid_argument ())
@@ -6613,7 +7245,7 @@ __ch (__bin_args_eq (vector unsigned short, (a1), vector unsigned short, (a2)),
       ((vector unsigned int) __builtin_altivec_vmulouh ((vector signed short) (a1), (vector signed short) (a2))), \
 __altivec_link_error_invalid_argument ())
 
-#define vec_mulosb(a1, a2) \
+#define vec_vmulosb(a1, a2) \
 __ch (__bin_args_eq (vector signed char, (a1), vector signed char, (a2)), \
       ((vector signed short) __builtin_altivec_vmulosb ((vector signed char) (a1), (vector signed char) (a2))), \
 __altivec_link_error_invalid_argument ())
@@ -6703,7 +7335,10 @@ __ch (__bin_args_eq (vector unsigned short, (a1), vector unsigned short, (a2)),
       ((vector unsigned char) __builtin_altivec_vpkuhum ((vector signed short) (a1), (vector signed short) (a2))), \
 __altivec_link_error_invalid_argument ()))
 
-#define vec_packpx(a1, a2) __builtin_altivec_vpkpx ((a1), (a2))
+#define vec_packpx(a1, a2) \
+__ch (__bin_args_eq (vector unsigned int, (a1), vector unsigned int, (a2)), \
+  (vector unsigned short) __builtin_altivec_vpkpx ((vector signed int) (a1), (vector signed int) (a2)), \
+__altivec_link_error_invalid_argument ())
 
 #define vec_packs(a1, a2) \
 __ch (__bin_args_eq (vector unsigned short, (a1), vector unsigned short, (a2)), \
@@ -6886,19 +7521,33 @@ __altivec_link_error_invalid_argument ()))
 #define vec_sld(a1, a2, a3) \
 __ch (__tern_args_eq (vector float, (a1), vector float, (a2), int, (a3)), \
       ((vector float) __builtin_altivec_vsldoi_4si ((vector signed int) (a1), (vector signed int) (a2), (const char) (a3))), \
+__ch (__tern_args_eq (vector float, (a1), vector float, (a2), unsigned int, (a3)), \
+      ((vector float) __builtin_altivec_vsldoi_4si ((vector signed int) (a1), (vector signed int) (a2), (const char) (a3))), \
 __ch (__tern_args_eq (vector signed int, (a1), vector signed int, (a2), int, (a3)), \
       ((vector signed int) __builtin_altivec_vsldoi_4si ((vector signed int) (a1), (vector signed int) (a2), (const char) (a3))), \
+__ch (__tern_args_eq (vector signed int, (a1), vector signed int, (a2), unsigned int, (a3)), \
+      ((vector signed int) __builtin_altivec_vsldoi_4si ((vector signed int) (a1), (vector signed int) (a2), (const char) (a3))), \
 __ch (__tern_args_eq (vector unsigned int, (a1), vector unsigned int, (a2), int, (a3)), \
       ((vector unsigned int) __builtin_altivec_vsldoi_4si ((vector signed int) (a1), (vector signed int) (a2), (const char) (a3))), \
+__ch (__tern_args_eq (vector unsigned int, (a1), vector unsigned int, (a2), unsigned int, (a3)), \
+      ((vector unsigned int) __builtin_altivec_vsldoi_4si ((vector signed int) (a1), (vector signed int) (a2), (const char) (a3))), \
 __ch (__tern_args_eq (vector signed short, (a1), vector signed short, (a2), int, (a3)), \
       ((vector signed short) __builtin_altivec_vsldoi_4si ((vector signed int) (a1), (vector signed int) (a2), (const char) (a3))), \
+__ch (__tern_args_eq (vector signed short, (a1), vector signed short, (a2), unsigned int, (a3)), \
+      ((vector signed short) __builtin_altivec_vsldoi_4si ((vector signed int) (a1), (vector signed int) (a2), (const char) (a3))), \
 __ch (__tern_args_eq (vector unsigned short, (a1), vector unsigned short, (a2), int, (a3)), \
       ((vector unsigned short) __builtin_altivec_vsldoi_4si ((vector signed int) (a1), (vector signed int) (a2), (const char) (a3))), \
+__ch (__tern_args_eq (vector unsigned short, (a1), vector unsigned short, (a2), unsigned int, (a3)), \
+      ((vector unsigned short) __builtin_altivec_vsldoi_4si ((vector signed int) (a1), (vector signed int) (a2), (const char) (a3))), \
 __ch (__tern_args_eq (vector signed char, (a1), vector signed char, (a2), int, (a3)), \
       ((vector signed char) __builtin_altivec_vsldoi_4si ((vector signed int) (a1), (vector signed int) (a2), (const char) (a3))), \
+__ch (__tern_args_eq (vector signed char, (a1), vector signed char, (a2), unsigned int, (a3)), \
+      ((vector signed char) __builtin_altivec_vsldoi_4si ((vector signed int) (a1), (vector signed int) (a2), (const char) (a3))), \
 __ch (__tern_args_eq (vector unsigned char, (a1), vector unsigned char, (a2), int, (a3)), \
       ((vector unsigned char) __builtin_altivec_vsldoi_4si ((vector signed int) (a1), (vector signed int) (a2), (const char) (a3))), \
-    __altivec_link_error_invalid_argument ())))))))
+__ch (__tern_args_eq (vector unsigned char, (a1), vector unsigned char, (a2), unsigned int, (a3)), \
+      ((vector unsigned char) __builtin_altivec_vsldoi_4si ((vector signed int) (a1), (vector signed int) (a2), (const char) (a3))), \
+    __altivec_link_error_invalid_argument ()))))))))))))))
 
 #define vec_sll(a1, a2) \
 __ch (__bin_args_eq (vector signed int, (a1), vector unsigned int, (a2)), \
@@ -6973,42 +7622,70 @@ __ch (__bin_args_eq (vector unsigned char, (a1), vector unsigned char, (a2)), \
 #define vec_splat(a1, a2) \
 __ch (__bin_args_eq (vector signed char, ((a1)), int, ((a2))), \
       ((vector signed char) __builtin_altivec_vspltb ((vector signed char) ((a1)), (const char) ((a2)))), \
+__ch (__bin_args_eq (vector signed char, ((a1)), unsigned int, ((a2))), \
+      ((vector signed char) __builtin_altivec_vspltb ((vector signed char) ((a1)), (const char) ((a2)))), \
 __ch (__bin_args_eq (vector unsigned char, ((a1)), int, ((a2))), \
       ((vector unsigned char) __builtin_altivec_vspltb ((vector signed char) ((a1)), (const char) ((a2)))), \
+__ch (__bin_args_eq (vector unsigned char, ((a1)), unsigned int, ((a2))), \
+      ((vector unsigned char) __builtin_altivec_vspltb ((vector signed char) ((a1)), (const char) ((a2)))), \
 __ch (__bin_args_eq (vector signed short, ((a1)), int, ((a2))), \
       ((vector signed short) __builtin_altivec_vsplth ((vector signed short) ((a1)), (const char) ((a2)))), \
+__ch (__bin_args_eq (vector signed short, ((a1)), unsigned int, ((a2))), \
+      ((vector signed short) __builtin_altivec_vsplth ((vector signed short) ((a1)), (const char) ((a2)))), \
 __ch (__bin_args_eq (vector unsigned short, ((a1)), int, ((a2))), \
       ((vector unsigned short) __builtin_altivec_vsplth ((vector signed short) ((a1)), (const char) ((a2)))), \
+__ch (__bin_args_eq (vector unsigned short, ((a1)), unsigned int, ((a2))), \
+      ((vector unsigned short) __builtin_altivec_vsplth ((vector signed short) ((a1)), (const char) ((a2)))), \
 __ch (__bin_args_eq (vector float, ((a1)), int, ((a2))), \
       ((vector float) __builtin_altivec_vspltw ((vector signed int) ((a1)), (const char) ((a2)))), \
+__ch (__bin_args_eq (vector float, ((a1)), unsigned int, ((a2))), \
+      ((vector float) __builtin_altivec_vspltw ((vector signed int) ((a1)), (const char) ((a2)))), \
 __ch (__bin_args_eq (vector signed int, ((a1)), int, ((a2))), \
       ((vector signed int) __builtin_altivec_vspltw ((vector signed int) ((a1)), (const char) ((a2)))), \
+__ch (__bin_args_eq (vector signed int, ((a1)), unsigned int, ((a2))), \
+      ((vector signed int) __builtin_altivec_vspltw ((vector signed int) ((a1)), (const char) ((a2)))), \
 __ch (__bin_args_eq (vector unsigned int, ((a1)), int, ((a2))), \
       ((vector unsigned int) __builtin_altivec_vspltw ((vector signed int) (a1), (const char) ((a2)))), \
-    __altivec_link_error_invalid_argument ())))))))
+__ch (__bin_args_eq (vector unsigned int, ((a1)), unsigned int, ((a2))), \
+      ((vector unsigned int) __builtin_altivec_vspltw ((vector signed int) (a1), (const char) ((a2)))), \
+    __altivec_link_error_invalid_argument ()))))))))))))))
 
 #define vec_vspltw(a1, a2) \
 __ch (__bin_args_eq (vector float, ((a1)), int, ((a2))), \
       ((vector float) __builtin_altivec_vspltw ((vector signed int) ((a1)), (const char) ((a2)))), \
+__ch (__bin_args_eq (vector float, ((a1)), unsigned int, ((a2))), \
+      ((vector float) __builtin_altivec_vspltw ((vector signed int) ((a1)), (const char) ((a2)))), \
 __ch (__bin_args_eq (vector signed int, ((a1)), int, ((a2))), \
       ((vector signed int) __builtin_altivec_vspltw ((vector signed int) ((a1)), (const char) ((a2)))), \
+__ch (__bin_args_eq (vector signed int, ((a1)), unsigned int, ((a2))), \
+      ((vector signed int) __builtin_altivec_vspltw ((vector signed int) ((a1)), (const char) ((a2)))), \
 __ch (__bin_args_eq (vector unsigned int, ((a1)), int, ((a2))), \
       ((vector unsigned int) __builtin_altivec_vspltw ((vector signed int) (a1), (const char) ((a2)))), \
-__altivec_link_error_invalid_argument ())))
+__ch (__bin_args_eq (vector unsigned int, ((a1)), unsigned int, ((a2))), \
+      ((vector unsigned int) __builtin_altivec_vspltw ((vector signed int) (a1), (const char) ((a2)))), \
+__altivec_link_error_invalid_argument ()))))))
 
 #define vec_vsplth(a1, a2) \
 __ch (__bin_args_eq (vector signed short, ((a1)), int, ((a2))), \
       ((vector signed short) __builtin_altivec_vsplth ((vector signed short) ((a1)), (const char) ((a2)))), \
+__ch (__bin_args_eq (vector signed short, ((a1)), unsigned int, ((a2))), \
+      ((vector signed short) __builtin_altivec_vsplth ((vector signed short) ((a1)), (const char) ((a2)))), \
 __ch (__bin_args_eq (vector unsigned short, ((a1)), int, ((a2))), \
       ((vector unsigned short) __builtin_altivec_vsplth ((vector signed short) ((a1)), (const char) ((a2)))), \
-__altivec_link_error_invalid_argument ()))
+__ch (__bin_args_eq (vector unsigned short, ((a1)), unsigned int, ((a2))), \
+      ((vector unsigned short) __builtin_altivec_vsplth ((vector signed short) ((a1)), (const char) ((a2)))), \
+__altivec_link_error_invalid_argument ()))))
 
 #define vec_vspltb(a1, a2) \
 __ch (__bin_args_eq (vector signed char, ((a1)), int, ((a2))), \
       ((vector signed char) __builtin_altivec_vspltb ((vector signed char) ((a1)), (const char) ((a2)))), \
+__ch (__bin_args_eq (vector signed char, ((a1)), unsigned int, ((a2))), \
+      ((vector signed char) __builtin_altivec_vspltb ((vector signed char) ((a1)), (const char) ((a2)))), \
 __ch (__bin_args_eq (vector unsigned char, ((a1)), int, ((a2))), \
       ((vector unsigned char) __builtin_altivec_vspltb ((vector signed char) ((a1)), (const char) ((a2)))), \
-__altivec_link_error_invalid_argument ()))
+__ch (__bin_args_eq (vector unsigned char, ((a1)), unsigned int, ((a2))), \
+      ((vector unsigned char) __builtin_altivec_vspltb ((vector signed char) ((a1)), (const char) ((a2)))), \
+__altivec_link_error_invalid_argument ()))))
 
 #define vec_splat_s8(a1) __builtin_altivec_vspltisb ((a1))
 
@@ -7277,7 +7954,10 @@ __ch (__bin_args_eq (vector unsigned char, (a1), vector unsigned char, (a2)), \
       ((vector unsigned char) __builtin_altivec_vsububm ((vector signed char) (a1), (vector signed char) (a2))), \
 __altivec_link_error_invalid_argument ()))))
 
-#define vec_subc(a1, a2) ((vector unsigned int) __builtin_altivec_vsubcuw ((vector unsigned int) (a1), (vector unsigned int) (a2)))
+#define vec_subc(a1, a2) \
+__ch (__bin_args_eq (vector unsigned int, (a1), vector unsigned int, (a2)), \
+  ((vector unsigned int) __builtin_altivec_vsubcuw ((vector signed int) (a1), (vector signed int) (a2))), \
+__altivec_link_error_invalid_argument ())
 
 #define vec_subs(a1, a2) \
 __ch (__bin_args_eq (vector signed char, (a1), vector unsigned char, (a2)), \
@@ -7381,7 +8061,7 @@ __altivec_link_error_invalid_argument ())
 #define vec_unpackh(a1) \
 __ch (__un_args_eq (vector signed char, (a1)), \
       ((vector signed short) __builtin_altivec_vupkhsb ((vector signed char) (a1))), \
-__ch (__un_args_eq (vector signed short, (a1)), \
+__ch (__un_args_eq (vector unsigned short, (a1)), \
       ((vector unsigned int) __builtin_altivec_vupkhpx ((vector signed short) (a1))), \
 __ch (__un_args_eq (vector signed short, (a1)), \
       ((vector signed int) __builtin_altivec_vupkhsh ((vector signed short) (a1))), \
@@ -7393,7 +8073,7 @@ __ch (__un_args_eq (vector signed short, (a1)), \
 __altivec_link_error_invalid_argument ())
 
 #define vec_vupkhpx(a1) \
-__ch (__un_args_eq (vector signed short, (a1)), \
+__ch (__un_args_eq (vector unsigned short, (a1)), \
       ((vector unsigned int) __builtin_altivec_vupkhpx ((vector signed short) (a1))), \
 __altivec_link_error_invalid_argument ())
 
@@ -7405,7 +8085,7 @@ __altivec_link_error_invalid_argument ())
 #define vec_unpackl(a1) \
 __ch (__un_args_eq (vector signed char, (a1)), \
       ((vector signed short) __builtin_altivec_vupklsb ((vector signed char) (a1))), \
-__ch (__un_args_eq (vector signed short, (a1)), \
+__ch (__un_args_eq (vector unsigned short, (a1)), \
       ((vector unsigned int) __builtin_altivec_vupklpx ((vector signed short) (a1))), \
 __ch (__un_args_eq (vector signed short, (a1)), \
       ((vector signed int) __builtin_altivec_vupklsh ((vector signed short) (a1))), \
@@ -7417,7 +8097,7 @@ __ch (__un_args_eq (vector signed short, (a1)), \
 __altivec_link_error_invalid_argument ())
 
 #define vec_vupklpx(a1) \
-__ch (__un_args_eq (vector signed short, (a1)), \
+__ch (__un_args_eq (vector unsigned short, (a1)), \
       ((vector unsigned int) __builtin_altivec_vupklpx ((vector signed short) (a1))), \
 __altivec_link_error_invalid_argument ())
 
@@ -7433,10 +8113,12 @@ __ch (__bin_args_eq (vector float, ((a1)), vector unsigned int, ((a2))), \
       ((vector float) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
 __ch (__bin_args_eq (vector unsigned int, ((a1)), vector float, ((a2))), \
       ((vector float) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
+__ch (__bin_args_eq (vector signed int, ((a1)), vector float, ((a2))), \
+      ((vector float) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
+__ch (__bin_args_eq (vector float, ((a1)), vector signed int, ((a2))), \
+      ((vector float) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
 __ch (__bin_args_eq (vector signed int, ((a1)), vector signed int, ((a2))), \
       ((vector signed int) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
-__ch (__bin_args_eq (vector unsigned int, ((a1)), vector unsigned int, ((a2))), \
-      ((vector unsigned int) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
 __ch (__bin_args_eq (vector signed int, ((a1)), vector unsigned int, ((a2))), \
       ((vector unsigned int) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
 __ch (__bin_args_eq (vector unsigned int, ((a1)), vector signed int, ((a2))), \
@@ -7446,9 +8128,9 @@ __ch (__bin_args_eq (vector unsigned int, ((a1)), vector unsigned int, ((a2))),
 __ch (__bin_args_eq (vector unsigned short, ((a1)), vector unsigned short, ((a2))), \
       ((vector unsigned short) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
 __ch (__bin_args_eq (vector signed short, ((a1)), vector unsigned short, ((a2))), \
-      ((vector signed short) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
+      ((vector unsigned short) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
 __ch (__bin_args_eq (vector unsigned short, ((a1)), vector signed short, ((a2))), \
-      ((vector signed short) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
+      ((vector unsigned short) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
 __ch (__bin_args_eq (vector unsigned short, ((a1)), vector unsigned short, ((a2))), \
       ((vector signed short) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
 __ch (__bin_args_eq (vector signed short, ((a1)), vector signed short, ((a2))), \
@@ -7470,8 +8152,8 @@ __ch (__bin_args_eq (vector unsigned char, ((a1)), vector unsigned char, ((a2)))
 __ch (__bin_args_eq (vector signed char, ((a1)), vector unsigned char, ((a2))), \
       ((vector signed char) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
 __ch (__bin_args_eq (vector unsigned char, ((a1)), vector signed char, ((a2))), \
-      ((vector signed char) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
-    __altivec_link_error_invalid_argument ()))))))))))))))))))))))
+      ((vector unsigned char) __builtin_altivec_vxor ((vector signed int) ((a1)), (vector signed int) ((a2)))), \
+    __altivec_link_error_invalid_argument ())))))))))))))))))))))))
 
 /* Predicates.  */
 
@@ -7530,7 +8212,7 @@ __ch (__bin_args_eq (vector unsigned int, (a1), vector unsigned int, (a2)), \
 __ch (__bin_args_eq (vector signed int, (a1), vector signed int, (a2)), \
       __builtin_altivec_vcmpgtsw_p (__CR6_EQ, (vector signed int) (a2), (vector signed int) (a1)), \
 __ch (__bin_args_eq (vector float, (a1), vector float, (a2)), \
-      __builtin_altivec_vcmpgefp_p (__CR6_EQ, (vector float) (a1), (vector float) (a2)), \
+      __builtin_altivec_vcmpgefp_p (__CR6_LT, (vector float) (a1), (vector float) (a2)), \
     __altivec_link_error_invalid_argument ())))))))))))))
 
 #define vec_all_gt(a1, a2) \
diff --git a/contrib/gcc/config/rs6000/linux64.h b/contrib/gcc/config/rs6000/linux64.h
index 40b64dc..f84e1e3 100644
--- a/contrib/gcc/config/rs6000/linux64.h
+++ b/contrib/gcc/config/rs6000/linux64.h
@@ -308,3 +308,22 @@ do {						\
 	       || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT		\
 		   && ! TARGET_NO_FP_IN_TOC)))))
 
+/* This is the same as the dbxelf.h version, except that we need to
+   use the function code label, not the function descriptor.  */
+#undef	ASM_OUTPUT_SOURCE_LINE
+#define	ASM_OUTPUT_SOURCE_LINE(FILE, LINE)				\
+do									\
+  {									\
+    static int sym_lineno = 1;						\
+    char temp[256];							\
+    ASM_GENERATE_INTERNAL_LABEL (temp, "LM", sym_lineno);		\
+    fprintf (FILE, "\t.stabn 68,0,%d,", LINE);				\
+    assemble_name (FILE, temp);						\
+    fputs ("-.", FILE);							\
+    assemble_name (FILE,						\
+		   XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0));\
+    putc ('\n', FILE);							\
+    ASM_OUTPUT_INTERNAL_LABEL (FILE, "LM", sym_lineno);			\
+    sym_lineno += 1;							\
+  }									\
+while (0)
diff --git a/contrib/gcc/config/rs6000/netbsd.h b/contrib/gcc/config/rs6000/netbsd.h
index 95f6542..d41e576 100644
--- a/contrib/gcc/config/rs6000/netbsd.h
+++ b/contrib/gcc/config/rs6000/netbsd.h
@@ -60,11 +60,6 @@ Boston, MA 02111-1307, USA.  */
 #undef TARGET_VERSION
 #define TARGET_VERSION fprintf (stderr, " (PowerPC NetBSD/ELF)");
 
-/* For backward compatibility, we must continue to use the AIX
-   structure return convention.  */
-#undef DRAFT_V4_STRUCT_RET
-#define DRAFT_V4_STRUCT_RET 1
-
 /* Use STABS debugging information by default.  DWARF2 makes a mess of
    the 1.5.2 linker.  */
 #undef  PREFERRED_DEBUGGING_TYPE
diff --git a/contrib/gcc/config/rs6000/rs6000.c b/contrib/gcc/config/rs6000/rs6000.c
index 45d6fdf..92b1d64 100644
--- a/contrib/gcc/config/rs6000/rs6000.c
+++ b/contrib/gcc/config/rs6000/rs6000.c
@@ -9735,23 +9735,22 @@ output_mi_thunk (file, thunk_fndecl, delta, function)
 	fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta);
     }
 
+  /* 64-bit constants.  If "int" is 32 bits, we'll never hit this abort.  */
+  else if (TARGET_64BIT && (delta < -2147483647 - 1 || delta > 2147483647))
+    abort ();
+
   /* Large constants that can be done by one addis instruction.  */
-  else if ((delta & 0xffff) == 0 && num_insns_constant_wide (delta) == 1)
+  else if ((delta & 0xffff) == 0)
     asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg,
 		 delta >> 16);
 
   /* 32-bit constants that can be done by an add and addis instruction.  */
-  else if (TARGET_32BIT || num_insns_constant_wide (delta) == 1)
+  else
     {
       /* Break into two pieces, propagating the sign bit from the low
 	 word to the upper word.  */
-      int delta_high = delta >> 16;
-      int delta_low  = delta & 0xffff;
-      if ((delta_low & 0x8000) != 0)
-	{
-	  delta_high++;
-	  delta_low = (delta_low ^ 0x8000) - 0x8000;	/* sign extend */
-	}
+      int delta_low  = ((delta & 0xffff) ^ 0x8000) - 0x8000;
+      int delta_high = (delta - delta_low) >> 16;
 
       asm_fprintf (file, "\t{cau|addis} %s,%s,%d\n", this_reg, this_reg,
 		   delta_high);
@@ -9762,10 +9761,6 @@ output_mi_thunk (file, thunk_fndecl, delta, function)
 	fprintf (file, "\taddi %s,%s,%d\n", this_reg, this_reg, delta_low);
     }
 
-  /* 64-bit constants, fixme */
-  else
-    abort ();
-
   /* Get the prefix in front of the names.  */
   switch (DEFAULT_ABI)
     {
@@ -9821,7 +9816,10 @@ output_mi_thunk (file, thunk_fndecl, delta, function)
 	    }
 	  assemble_name (file, fname);
 	  putc ('\n', file);
-	  text_section ();
+	  if (TARGET_ELF)
+	    function_section (current_function_decl);
+	  else
+	    text_section ();
 	  if (TARGET_MINIMAL_TOC)
 	    asm_fprintf (file, (TARGET_32BIT)
 			 ? "\t{l|lwz} %s,%s(%s)\n" : "\tld %s,%s(%s)\n", r12,
@@ -10157,8 +10155,10 @@ output_toc (file, x, labelno, mode)
 	  if (TARGET_MINIMAL_TOC)
 	    fputs (DOUBLE_INT_ASM_OP, file);
 	  else
-	    fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]);
-	  fprintf (file, "0x%lx%08lx\n", k[0], k[1]);
+	    fprintf (file, "\t.tc FD_%lx_%lx[TC],",
+		     k[0] & 0xffffffff, k[1] & 0xffffffff);
+	  fprintf (file, "0x%lx%08lx\n",
+		   k[0] & 0xffffffff, k[1] & 0xffffffff);
 	  return;
 	}
       else
@@ -10166,8 +10166,10 @@ output_toc (file, x, labelno, mode)
 	  if (TARGET_MINIMAL_TOC)
 	    fputs ("\t.long ", file);
 	  else
-	    fprintf (file, "\t.tc FD_%lx_%lx[TC],", k[0], k[1]);
-	  fprintf (file, "0x%lx,0x%lx\n", k[0], k[1]);
+	    fprintf (file, "\t.tc FD_%lx_%lx[TC],",
+		     k[0] & 0xffffffff, k[1] & 0xffffffff);
+	  fprintf (file, "0x%lx,0x%lx\n",
+		   k[0] & 0xffffffff, k[1] & 0xffffffff);
 	  return;
 	}
     }
@@ -10184,8 +10186,8 @@ output_toc (file, x, labelno, mode)
 	  if (TARGET_MINIMAL_TOC)
 	    fputs (DOUBLE_INT_ASM_OP, file);
 	  else
-	    fprintf (file, "\t.tc FS_%lx[TC],", l);
-	  fprintf (file, "0x%lx00000000\n", l);
+	    fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
+	  fprintf (file, "0x%lx00000000\n", l & 0xffffffff);
 	  return;
 	}
       else
@@ -10193,8 +10195,8 @@ output_toc (file, x, labelno, mode)
 	  if (TARGET_MINIMAL_TOC)
 	    fputs ("\t.long ", file);
 	  else
-	    fprintf (file, "\t.tc FS_%lx[TC],", l);
-	  fprintf (file, "0x%lx\n", l);
+	    fprintf (file, "\t.tc FS_%lx[TC],", l & 0xffffffff);
+	  fprintf (file, "0x%lx\n", l & 0xffffffff);
 	  return;
 	}
     }
@@ -10244,8 +10246,10 @@ output_toc (file, x, labelno, mode)
 	  if (TARGET_MINIMAL_TOC)
 	    fputs (DOUBLE_INT_ASM_OP, file);
 	  else
-	    fprintf (file, "\t.tc ID_%lx_%lx[TC],", (long) high, (long) low);
-	  fprintf (file, "0x%lx%08lx\n", (long) high, (long) low);
+	    fprintf (file, "\t.tc ID_%lx_%lx[TC],",
+		     (long) high & 0xffffffff, (long) low & 0xffffffff);
+	  fprintf (file, "0x%lx%08lx\n",
+		   (long) high & 0xffffffff, (long) low & 0xffffffff);
 	  return;
 	}
       else
@@ -10256,16 +10260,17 @@ output_toc (file, x, labelno, mode)
 		fputs ("\t.long ", file);
 	      else
 		fprintf (file, "\t.tc ID_%lx_%lx[TC],",
-			 (long) high, (long) low);
-	      fprintf (file, "0x%lx,0x%lx\n", (long) high, (long) low);
+			 (long) high & 0xffffffff, (long) low & 0xffffffff);
+	      fprintf (file, "0x%lx,0x%lx\n",
+		       (long) high & 0xffffffff, (long) low & 0xffffffff);
 	    }
 	  else
 	    {
 	      if (TARGET_MINIMAL_TOC)
 		fputs ("\t.long ", file);
 	      else
-		fprintf (file, "\t.tc IS_%lx[TC],", (long) low);
-	      fprintf (file, "0x%lx\n", (long) low);
+		fprintf (file, "\t.tc IS_%lx[TC],", (long) low & 0xffffffff);
+	      fprintf (file, "0x%lx\n", (long) low & 0xffffffff);
 	    }
 	  return;
 	}
@@ -10879,18 +10884,19 @@ rs6000_select_section (decl, reloc)
   if (TREE_CODE (decl) == STRING_CST)
     readonly = ! flag_writable_strings;
   else if (TREE_CODE (decl) == VAR_DECL)
-    readonly = (! (flag_pic && reloc)
+    readonly = (! ((flag_pic || DEFAULT_ABI == ABI_AIX) && reloc)
 		&& TREE_READONLY (decl)
 		&& ! TREE_SIDE_EFFECTS (decl)
 		&& DECL_INITIAL (decl)
 		&& DECL_INITIAL (decl) != error_mark_node
 		&& TREE_CONSTANT (DECL_INITIAL (decl)));
   else if (TREE_CODE (decl) == CONSTRUCTOR)
-    readonly = (! (flag_pic && reloc)
+    readonly = (! ((flag_pic || DEFAULT_ABI == ABI_AIX) && reloc)
 		&& ! TREE_SIDE_EFFECTS (decl)
 		&& TREE_CONSTANT (decl));
   else
-    readonly = 1;
+    readonly = ! ((flag_pic || DEFAULT_ABI == ABI_AIX) && reloc);
+
   if (needs_sdata && rs6000_sdata != SDATA_EABI)
     readonly = 0;
   
@@ -10935,14 +10941,15 @@ rs6000_unique_section (decl, reloc)
       int needs_sdata;
       int size;
 
-      readonly = 1;
       if (TREE_CODE (decl) == STRING_CST)
 	readonly = ! flag_writable_strings;
       else if (TREE_CODE (decl) == VAR_DECL)
-	readonly = (! (flag_pic && reloc)
+	readonly = (! ((flag_pic || DEFAULT_ABI == ABI_AIX) && reloc)
 		    && TREE_READONLY (decl)
 		    && ! TREE_SIDE_EFFECTS (decl)
 		    && TREE_CONSTANT (DECL_INITIAL (decl)));
+      else
+	readonly = ! ((flag_pic || DEFAULT_ABI == ABI_AIX) && reloc);
 
       size = int_size_in_bytes (TREE_TYPE (decl));
       needs_sdata = (size > 0 
diff --git a/contrib/gcc/config/rs6000/rs6000.h b/contrib/gcc/config/rs6000/rs6000.h
index 3e4c5f2..8c77dd5 100644
--- a/contrib/gcc/config/rs6000/rs6000.h
+++ b/contrib/gcc/config/rs6000/rs6000.h
@@ -105,8 +105,8 @@ Boston, MA 02111-1307, USA.  */
 %{mcpu=rsc: -mpwr} \
 %{mcpu=rsc1: -mpwr} \
 %{mcpu=401: -mppc} \
-%{mcpu=403: -mppc} \
-%{mcpu=405: -mppc} \
+%{mcpu=403: -m403} \
+%{mcpu=405: -m405} \
 %{mcpu=505: -mppc} \
 %{mcpu=601: -m601} \
 %{mcpu=602: -mppc} \
@@ -2439,12 +2439,14 @@ extern int toc_initialized;
   do									\
     {									\
       fputs ("\t.weak\t", (FILE));					\
-      assemble_name ((FILE), (NAME)); 					\
+      RS6000_OUTPUT_BASENAME ((FILE), (NAME)); 			\
       if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL			\
 	  && DEFAULT_ABI == ABI_AIX)					\
 	{								\
+	  if (TARGET_XCOFF)						\
+	    fputs ("[DS]", (FILE));					\
 	  fputs ("\n\t.weak\t.", (FILE));				\
-	  assemble_name ((FILE), (NAME)); 				\
+	  RS6000_OUTPUT_BASENAME ((FILE), (NAME)); 			\
 	}								\
       fputc ('\n', (FILE));						\
       if (VAL)								\
@@ -2454,9 +2456,9 @@ extern int toc_initialized;
 	      && DEFAULT_ABI == ABI_AIX)				\
 	    {								\
 	      fputs ("\t.set\t.", (FILE));				\
-	      assemble_name ((FILE), (NAME));				\
+	      RS6000_OUTPUT_BASENAME ((FILE), (NAME));			\
 	      fputs (",.", (FILE));					\
-	      assemble_name ((FILE), (VAL));				\
+	      RS6000_OUTPUT_BASENAME ((FILE), (VAL));			\
 	      fputc ('\n', (FILE));					\
 	    }								\
 	}								\
@@ -2479,20 +2481,20 @@ extern int toc_initialized;
 	      if (!RS6000_WEAK || !DECL_WEAK (DECL))			\
 		{							\
 		  fputs ("\t.globl\t.", FILE);				\
-		  assemble_name (FILE, alias);				\
+		  RS6000_OUTPUT_BASENAME (FILE, alias);			\
 		  putc ('\n', FILE);					\
 		}							\
 	    }								\
 	  else if (TARGET_XCOFF)					\
 	    {								\
 	      fputs ("\t.lglobl\t.", FILE);				\
-	      assemble_name (FILE, alias);				\
+	      RS6000_OUTPUT_BASENAME (FILE, alias);			\
 	      putc ('\n', FILE);					\
 	    }								\
 	  fputs ("\t.set\t.", FILE);					\
-	  assemble_name (FILE, alias);					\
+	  RS6000_OUTPUT_BASENAME (FILE, alias);				\
 	  fputs (",.", FILE);						\
-	  assemble_name (FILE, name);					\
+	  RS6000_OUTPUT_BASENAME (FILE, name);				\
 	  fputc ('\n', FILE);						\
 	}								\
       ASM_OUTPUT_DEF (FILE, alias, name);				\
diff --git a/contrib/gcc/config/rs6000/rs6000.md b/contrib/gcc/config/rs6000/rs6000.md
index 93c6fc3..5188ce5 100644
--- a/contrib/gcc/config/rs6000/rs6000.md
+++ b/contrib/gcc/config/rs6000/rs6000.md
@@ -5271,9 +5271,18 @@
 	      (clobber (match_dup 4))
 	      (clobber (match_dup 5))
 	      (clobber (match_dup 6))])]
-  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT"
   "
 {
+  if (TARGET_POWERPC64)
+    {
+      rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
+      rtx t1 = gen_reg_rtx (DImode);
+      rtx t2 = gen_reg_rtx (DImode);
+      emit_insn (gen_floatsidf_ppc64 (operands[0], operands[1], mem, t1, t2));
+      DONE;
+    }
+
   operands[2] = force_reg (SImode, GEN_INT (0x43300000));
   operands[3] = force_reg (DFmode, rs6000_float_const (\"4503601774854144\", DFmode));
   operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
@@ -5338,9 +5347,19 @@
 	      (use (match_dup 3))
 	      (clobber (match_dup 4))
 	      (clobber (match_dup 5))])]
-  "! TARGET_POWERPC64 && TARGET_HARD_FLOAT"
+  "TARGET_HARD_FLOAT"
   "
 {
+  if (TARGET_POWERPC64)
+    {
+      rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
+      rtx t1 = gen_reg_rtx (DImode);
+      rtx t2 = gen_reg_rtx (DImode);
+      emit_insn (gen_floatunssidf_ppc64 (operands[0], operands[1], mem,
+					 t1, t2));
+      DONE;
+    }
+
   operands[2] = force_reg (SImode, GEN_INT (0x43300000));
   operands[3] = force_reg (DFmode, rs6000_float_const (\"4503599627370496\", DFmode));
   operands[4] = assign_stack_temp (DFmode, GET_MODE_SIZE (DFmode), 0);
@@ -5407,7 +5426,7 @@
 (define_insn "*fix_truncdfsi2_internal"
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f")))
-   (clobber (match_operand:DI 2 "gpc_reg_operand" "=f"))
+   (clobber (match_operand:DI 2 "gpc_reg_operand" "=*f"))
    (clobber (match_operand:DI 3 "memory_operand" "=o"))]
   "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
   "#"
@@ -5443,7 +5462,7 @@
 ; because the first makes it clear that operand 0 is not live
 ; before the instruction.
 (define_insn "fctiwz"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
 	(unspec:DI [(fix:SI (match_operand:DF 1 "gpc_reg_operand" "f"))] 10))]
   "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT"
   "{fcirz|fctiwz} %0,%1"
@@ -5451,13 +5470,43 @@
 
 (define_insn "floatdidf2"
   [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
-	(float:DF (match_operand:DI 1 "gpc_reg_operand" "f")))]
+	(float:DF (match_operand:DI 1 "gpc_reg_operand" "*f")))]
   "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
   "fcfid %0,%1"
   [(set_attr "type" "fp")])
 
+(define_insn_and_split "floatsidf_ppc64"
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
+   (clobber (match_operand:DI 2 "memory_operand" "=o"))
+   (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
+   (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
+  "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
+  "#"
+  ""
+  [(set (match_dup 3) (sign_extend:DI (match_dup 1)))
+   (set (match_dup 2) (match_dup 3))
+   (set (match_dup 4) (match_dup 2))
+   (set (match_dup 0) (float:DF (match_dup 4)))]
+  "")
+
+(define_insn_and_split "floatunssidf_ppc64"
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))
+   (clobber (match_operand:DI 2 "memory_operand" "=o"))
+   (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
+   (clobber (match_operand:DI 4 "gpc_reg_operand" "=f"))]
+  "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
+  "#"
+  ""
+  [(set (match_dup 3) (zero_extend:DI (match_dup 1)))
+   (set (match_dup 2) (match_dup 3))
+   (set (match_dup 4) (match_dup 2))
+   (set (match_dup 0) (float:DF (match_dup 4)))]
+  "")
+
 (define_insn "fix_truncdfdi2"
-  [(set (match_operand:DI 0 "gpc_reg_operand" "=f")
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=*f")
 	(fix:DI (match_operand:DF 1 "gpc_reg_operand" "f")))]
   "TARGET_POWERPC64 && TARGET_HARD_FLOAT"
   "fctidz %0,%1"
@@ -13255,15 +13304,15 @@
 
 (define_insn "*ctrdi_internal1"
   [(set (pc)
-	(if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
+	(if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
 			  (const_int 1))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))
-   (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
+   (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
 	(plus:DI (match_dup 1)
 		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
-   (clobber (match_scratch:DI 4 "=X,X,r,r"))]
+   (clobber (match_scratch:CC 3 "=X,&x,&x"))
+   (clobber (match_scratch:DI 4 "=X,X,r"))]
   "TARGET_POWERPC64"
   "*
 {
@@ -13275,19 +13324,19 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16,24")])
+   (set_attr "length" "*,12,16")])
 
 (define_insn "*ctrdi_internal2"
   [(set (pc)
-	(if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
+	(if_then_else (ne (match_operand:DI 1 "register_operand" "c,*r,*r")
 			  (const_int 1))
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))
-   (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
+   (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
 	(plus:DI (match_dup 1)
 		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
-   (clobber (match_scratch:DI 4 "=X,X,r,r"))]
+   (clobber (match_scratch:CC 3 "=X,&x,&x"))
+   (clobber (match_scratch:DI 4 "=X,X,r"))]
   "TARGET_POWERPC64"
   "*
 {
@@ -13299,7 +13348,7 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16,24")])
+   (set_attr "length" "*,12,16")])
 
 ;; Similar, but we can use GE since we have a REG_NONNEG.
 
@@ -13353,15 +13402,15 @@
 
 (define_insn "*ctrdi_internal3"
   [(set (pc)
-	(if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
+	(if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
 			  (const_int 0))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))
-   (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
+   (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
 	(plus:DI (match_dup 1)
 		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
-   (clobber (match_scratch:DI 4 "=X,X,r,r"))]
+   (clobber (match_scratch:CC 3 "=X,&x,&x"))
+   (clobber (match_scratch:DI 4 "=X,X,r"))]
   "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
   "*
 {
@@ -13373,19 +13422,19 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16,24")])
+   (set_attr "length" "*,12,16")])
 
 (define_insn "*ctrdi_internal4"
   [(set (pc)
-	(if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
+	(if_then_else (ge (match_operand:DI 1 "register_operand" "c,*r,*r")
 			  (const_int 0))
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))
-   (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
+   (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
 	(plus:DI (match_dup 1)
 		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
-   (clobber (match_scratch:DI 4 "=X,X,r,r"))]
+   (clobber (match_scratch:CC 3 "=X,&x,&x"))
+   (clobber (match_scratch:DI 4 "=X,X,r"))]
   "TARGET_POWERPC64 && find_reg_note (insn, REG_NONNEG, 0)"
   "*
 {
@@ -13397,7 +13446,7 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16,24")])
+   (set_attr "length" "*,12,16")])
 
 ;; Similar but use EQ
 
@@ -13451,15 +13500,15 @@
 
 (define_insn "*ctrdi_internal5"
   [(set (pc)
-	(if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
+	(if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
 			  (const_int 1))
 		      (label_ref (match_operand 0 "" ""))
 		      (pc)))
-   (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
+   (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
 	(plus:DI (match_dup 1)
 		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
-   (clobber (match_scratch:DI 4 "=X,X,r,r"))]
+   (clobber (match_scratch:CC 3 "=X,&x,&x"))
+   (clobber (match_scratch:DI 4 "=X,X,r"))]
   "TARGET_POWERPC64"
   "*
 {
@@ -13471,19 +13520,19 @@
     return \"{bdn|bdnz} $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16,24")])
+   (set_attr "length" "*,12,16")])
 
 (define_insn "*ctrdi_internal6"
   [(set (pc)
-	(if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r,!*f")
+	(if_then_else (eq (match_operand:DI 1 "register_operand" "c,*r,*r")
 			  (const_int 1))
 		      (pc)
 		      (label_ref (match_operand 0 "" ""))))
-   (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l,!*f")
+   (set (match_operand:DI 2 "register_operand" "=1,*r,m*c*l")
 	(plus:DI (match_dup 1)
 		 (const_int -1)))
-   (clobber (match_scratch:CC 3 "=X,&x,&x,&x"))
-   (clobber (match_scratch:DI 4 "=X,X,r,r"))]
+   (clobber (match_scratch:CC 3 "=X,&x,&x"))
+   (clobber (match_scratch:DI 4 "=X,X,r"))]
   "TARGET_POWERPC64"
   "*
 {
@@ -13495,7 +13544,7 @@
     return \"bdz $+8\;b %l0\";
 }"
   [(set_attr "type" "branch")
-   (set_attr "length" "*,12,16,24")])
+   (set_attr "length" "*,12,16")])
 
 ;; Now the splitters if we could not allocate the CTR register
 
@@ -13566,7 +13615,7 @@
 		 (const_int -1)))
    (clobber (match_scratch:CC 3 ""))
    (clobber (match_scratch:DI 4 ""))]
-  "TARGET_POWERPC64 && reload_completed && INT_REGNO_P (REGNO (operands[0]))"
+  "TARGET_POWERPC64 && reload_completed"
   [(parallel [(set (match_dup 3)
 		   (compare:CC (plus:DI (match_dup 1)
 					(const_int -1))
@@ -13610,44 +13659,6 @@
 { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
 			 const0_rtx); }")
 
-(define_split
-  [(set (pc)
-       (if_then_else (match_operator 2 "comparison_operator"
-				     [(match_operand:DI 1 "gpc_reg_operand" "")
-				      (const_int 1)])
-		     (match_operand 5 "" "")
-		     (match_operand 6 "" "")))
-   (set (match_operand:DI 0 "gpc_reg_operand" "")
-       (plus:DI (match_dup 1)
-		(const_int -1)))
-   (clobber (match_scratch:CC 3 ""))
-   (clobber (match_scratch:DI 4 ""))]
-  "TARGET_POWERPC64 && reload_completed && FP_REGNO_P (REGNO (operands[0]))"
-  [(set (match_dup 8)
-	(match_dup 1))
-   (set (match_dup 4)
-	(match_dup 8))
-   (parallel [(set (match_dup 3)
-		   (compare:CC (plus:DI (match_dup 4)
-					(const_int -1))
-			       (const_int 0)))
-	      (set (match_dup 4)
-		   (plus:DI (match_dup 4)
-			    (const_int -1)))])
-   (set (match_dup 8)
-	(match_dup 4))
-   (set (match_dup 0)
-	(match_dup 8))
-   (set (pc) (if_then_else (match_dup 7)
-			   (match_dup 5)
-			   (match_dup 6)))]
-  "
-{
-  operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
-			 const0_rtx);
-  operands[8] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
-}")
-
 
 (define_insn "trap"
   [(trap_if (const_int 1) (const_int 0))]
diff --git a/contrib/gcc/config/rs6000/sysv4.h b/contrib/gcc/config/rs6000/sysv4.h
index b807bb7..9274d8f 100644
--- a/contrib/gcc/config/rs6000/sysv4.h
+++ b/contrib/gcc/config/rs6000/sysv4.h
@@ -403,7 +403,6 @@ do {									\
          : MAX (COMPUTED, SPECIFIED))
 
 #undef  BIGGEST_FIELD_ALIGNMENT
-#undef  ADJUST_FIELD_ALIGN
 
 /* Use ELF style section commands.  */
 
diff --git a/contrib/gcc/config/rs6000/xcoff.h b/contrib/gcc/config/rs6000/xcoff.h
index 4a51b04..a61061a 100644
--- a/contrib/gcc/config/rs6000/xcoff.h
+++ b/contrib/gcc/config/rs6000/xcoff.h
@@ -457,6 +457,15 @@ toc_section ()						\
 /* This is how we tell the assembler that two symbols have the same value.  */
 #define SET_ASM_OP "\t.set "
 
+/* This is how we tell the assembler to equate two values.  */
+#define ASM_OUTPUT_DEF(FILE,LABEL1,LABEL2)				\
+ do {	fprintf ((FILE), "%s", SET_ASM_OP);				\
+	RS6000_OUTPUT_BASENAME (FILE, LABEL1);				\
+	fprintf (FILE, ",");						\
+	RS6000_OUTPUT_BASENAME (FILE, LABEL2);				\
+	fprintf (FILE, "\n");						\
+  } while (0)
+
 /* Used by rs6000_assemble_integer, among others.  */
 #define DOUBLE_INT_ASM_OP "\t.llong\t"
 
diff --git a/contrib/gcc/config/sparc/netbsd-elf.h b/contrib/gcc/config/sparc/netbsd-elf.h
index b4bbf71..f141f89 100644
--- a/contrib/gcc/config/sparc/netbsd-elf.h
+++ b/contrib/gcc/config/sparc/netbsd-elf.h
@@ -31,12 +31,28 @@ Boston, MA 02111-1307, USA.  */
 /* CPP defines used for 64 bit code.  */
 #undef CPP_SUBTARGET_SPEC64
 #define CPP_SUBTARGET_SPEC64 \
-  "-D__sparc64__ -D__arch64__ -D__sparc_v9__ %{posix:-D_POSIX_SOURCE}"
+  "-D__sparc64__ -D__sparc_v9__ -D_LP64 %{posix:-D_POSIX_SOURCE}"
 
 /* CPP defines used for 32 bit code.  */
 #undef CPP_SUBTARGET_SPEC32
 #define CPP_SUBTARGET_SPEC32 "-D__sparc %{posix:-D_POSIX_SOURCE}"
 
+/* CPP_ARCH32_SPEC and CPP_ARCH64_SPEC are wrong from sparc/sparc.h; we
+   always want the non-SPARC_BI_ARCH versions, since the SPARC_BI_ARCH
+   versions define __SIZE_TYPE__ and __PTRDIFF_TYPE__ incorrectly for
+   NetBSD.  */
+#undef CPP_ARCH32_SPEC
+#define CPP_ARCH32_SPEC "-D__GCC_NEW_VARARGS__ -Acpu=sparc -Amachine=sparc"
+
+#undef CPP_ARCH64_SPEC
+#define CPP_ARCH64_SPEC "-D__arch64__ -Acpu=sparc64 -Amachine=sparc64"
+
+/* sparc/sparc.h defines NO_BUILTIN_SIZE_TYPE and NO_BUILTIN_PTRDIFF_TYPE
+   if SPARC_BI_ARCH is defined.  This is wrong for NetBSD; size_t and
+   ptrdiff_t do not change for 32-bit vs. 64-bit.  */
+#undef NO_BUILTIN_PTRDIFF_TYPE
+#undef NO_BUILTIN_SIZE_TYPE
+
 /* SIZE_TYPE and PTRDIFF_TYPE are wrong from sparc/sparc.h.  */
 #undef SIZE_TYPE
 #define SIZE_TYPE "long unsigned int"
@@ -99,9 +115,6 @@ Boston, MA 02111-1307, USA.  */
  * Clean up afterwards generic SPARC ELF configuration.
  */
 
-#undef TRANSFER_FROM_TRAMPOLINE
-#define TRANSFER_FROM_TRAMPOLINE
-
 /* FIXME: Aren't these supposed to be available for SPARC ELF?  */
 #undef MULDI3_LIBCALL
 #undef DIVDI3_LIBCALL
diff --git a/contrib/gcc/config/sparc/openbsd1-64.h b/contrib/gcc/config/sparc/openbsd1-64.h
new file mode 100644
index 0000000..1310538
--- /dev/null
+++ b/contrib/gcc/config/sparc/openbsd1-64.h
@@ -0,0 +1,24 @@
+/* Configuration file for sparc64 OpenBSD target.
+   Copyright (C) 1999 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#define OBSD_HAS_DECLARE_FUNCTION_NAME
+#define OBSD_HAS_DECLARE_FUNCTION_SIZE
+#define OBSD_HAS_DECLARE_OBJECT
+
diff --git a/contrib/gcc/config/sparc/openbsd64.h b/contrib/gcc/config/sparc/openbsd64.h
new file mode 100644
index 0000000..4dfe381
--- /dev/null
+++ b/contrib/gcc/config/sparc/openbsd64.h
@@ -0,0 +1,75 @@
+/* Configuration file for sparc64 OpenBSD target.
+   Copyright (C) 1999 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+#undef TARGET_VERSION
+#define TARGET_VERSION fprintf (stderr, " (sparc64 OpenBSD ELF)")
+
+/* XXX - do we really want HARD_QUAD? */
+#undef TARGET_DEFAULT
+#define TARGET_DEFAULT \
+(MASK_V9 + MASK_PTR64 + MASK_64BIT + MASK_HARD_QUAD \
+ + MASK_APP_REGS + MASK_FPU + MASK_STACK_BIAS + MASK_LONG_DOUBLE_128)
+
+#undef SPARC_DEFAULT_CMODEL
+#define SPARC_DEFAULT_CMODEL CM_MEDMID
+
+/* Run-time target specifications.  */
+#undef CPP_PREDEFINES
+#define CPP_PREDEFINES "-D__unix__ -D__sparc__ -D__sparc64__ -D__sparcv9__ -D__sparc_v9__ -D__arch64__ -D__ELF__ -D__OpenBSD__ -Asystem(unix) -Asystem(OpenBSD) -Acpu(sparc) -Amachine(sparc)"
+
+#undef CPP_SUBTARGET_SPEC
+#define CPP_SUBTARGET_SPEC ""
+
+#undef MD_EXEC_PREFIX
+#undef MD_STARTFILE_PREFIX
+
+#undef ASM_SPEC
+#define ASM_SPEC "\
+%{v:-V} -s %{fpic:-K PIC} %{fPIC:-K PIC} \
+%{mlittle-endian:-EL} \
+%(asm_cpu) %(asm_arch) \
+"
+
+/* Layout of source language data types.  */
+#undef WCHAR_TYPE
+#define WCHAR_TYPE "int"
+
+#undef WCHAR_TYPE_SIZE
+#define WCHAR_TYPE_SIZE 32
+
+#undef LONG_DOUBLE_TYPE_SIZE
+#define LONG_DOUBLE_TYPE_SIZE 128
+
+#undef LINK_SPEC
+#define LINK_SPEC \
+  "%{!shared:%{!nostdlib:%{!r*:%{!e*:-e __start}}}} \
+   %{shared:-shared} %{R*} \
+   %{static:-Bstatic} \
+   %{!static:-Bdynamic} \
+   %{assert*} \
+   %{!dynamic-linker:-dynamic-linker /usr/libexec/ld.so}"
+
+/* As an elf system, we need crtbegin/crtend stuff.  */
+#undef STARTFILE_SPEC
+#define STARTFILE_SPEC "\
+        %{!shared: %{pg:gcrt0%O%s} %{!pg:%{p:gcrt0%O%s} %{!p:crt0%O%s}} \
+        crtbegin%O%s} %{shared:crtbeginS%O%s}"
+#undef ENDFILE_SPEC
+#define ENDFILE_SPEC "%{!shared:crtend%O%s} %{shared:crtendS%O%s}"
diff --git a/contrib/gcc/config/sparc/sol2.h b/contrib/gcc/config/sparc/sol2.h
index 67e064d..56bfbb7 100644
--- a/contrib/gcc/config/sparc/sol2.h
+++ b/contrib/gcc/config/sparc/sol2.h
@@ -71,17 +71,21 @@ Boston, MA 02111-1307, USA.  */
 
 /* This is here rather than in sparc.h because it's not known what
    other assemblers will accept.  */
+
 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9
 #undef ASM_CPU_DEFAULT_SPEC
 #define ASM_CPU_DEFAULT_SPEC "-xarch=v8plus"
 #endif
+
 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc
 #undef ASM_CPU_DEFAULT_SPEC
 #define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusa"
 #endif
+
 #undef ASM_CPU_SPEC
 #define ASM_CPU_SPEC "\
 %{mcpu=v8plus:-xarch=v8plus} \
+%{mcpu=v9:-xarch=v8plus} \
 %{mcpu=ultrasparc:-xarch=v8plusa} \
 %{!mcpu*:%(asm_cpu_default)} \
 "
@@ -227,6 +231,12 @@ Boston, MA 02111-1307, USA.  */
 #define MODDI3_LIBCALL "__rem64"
 #define UMODDI3_LIBCALL "__urem64"
 
+/* Solaris's _Qp_* library routine implementation clobbers the output
+   memory before the inputs are fully consumed.  */
+
+#undef TARGET_BUGGY_QP_LIB
+#define TARGET_BUGGY_QP_LIB	1
+
 #undef INIT_SUBTARGET_OPTABS
 #define INIT_SUBTARGET_OPTABS						\
   fixsfdi_libfunc							\
diff --git a/contrib/gcc/config/sparc/sparc-protos.h b/contrib/gcc/config/sparc/sparc-protos.h
index fd372de..7de8940 100644
--- a/contrib/gcc/config/sparc/sparc-protos.h
+++ b/contrib/gcc/config/sparc/sparc-protos.h
@@ -123,4 +123,6 @@ extern rtx gen_df_reg PARAMS ((rtx, int));
 extern int sparc_extra_constraint_check PARAMS ((rtx, int, int));
 #endif /* RTX_CODE */
 
+extern void sparc_output_mi_thunk PARAMS ((FILE *, tree, HOST_WIDE_INT, tree));
+
 #endif /* __SPARC_PROTOS_H__ */
diff --git a/contrib/gcc/config/sparc/sparc.c b/contrib/gcc/config/sparc/sparc.c
index 28bbcec..6ef28141c 100644
--- a/contrib/gcc/config/sparc/sparc.c
+++ b/contrib/gcc/config/sparc/sparc.c
@@ -2489,9 +2489,17 @@ emit_soft_tfmode_libcall (func_name, nargs, operands)
       /* TFmode arguments and return values are passed by reference.  */
       if (GET_MODE (this_arg) == TFmode)
 	{
-	  if (GET_CODE (this_arg) == MEM)
+	  int force_stack_temp;
+
+	  force_stack_temp = 0;
+	  if (TARGET_BUGGY_QP_LIB && i == 0)
+	    force_stack_temp = 1;
+
+	  if (GET_CODE (this_arg) == MEM
+	      && ! force_stack_temp)
 	    this_arg = XEXP (this_arg, 0);
-	  else if (CONSTANT_P (this_arg))
+	  else if (CONSTANT_P (this_arg)
+		   && ! force_stack_temp)
 	    {
 	      this_slot = force_const_mem (TFmode, this_arg);
 	      this_arg = XEXP (this_slot, 0);
@@ -8993,3 +9001,70 @@ sparc_extra_constraint_check (op, c, strict)
 
   return reload_ok_mem;
 }
+
+/* Output code to add DELTA to the first argument, and then jump to FUNCTION.
+   Used for C++ multiple inheritance.  */
+
+void
+sparc_output_mi_thunk (file, thunk_fndecl, delta, function)
+     FILE *file;
+     tree thunk_fndecl ATTRIBUTE_UNUSED;
+     HOST_WIDE_INT delta;
+     tree function;
+{
+  rtx this, insn, funexp, delta_rtx, tmp;
+
+  reload_completed = 1;
+  no_new_pseudos = 1;
+  current_function_uses_only_leaf_regs = 1;
+
+  emit_note (NULL, NOTE_INSN_PROLOGUE_END);
+
+  /* Find the "this" pointer.  Normally in %o0, but in ARCH64 if the function
+     returns a structure, the structure return pointer is there instead.  */
+  if (TARGET_ARCH64 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function))))
+    this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST + 1);
+  else
+    this = gen_rtx_REG (Pmode, SPARC_INCOMING_INT_ARG_FIRST);
+
+  /* Add DELTA.  When possible use a plain add, otherwise load it into
+     a register first.  */
+  delta_rtx = GEN_INT (delta);
+  if (!SPARC_SIMM13_P (delta))
+    {
+      rtx scratch = gen_rtx_REG (Pmode, 1);
+      if (TARGET_ARCH64)
+	sparc_emit_set_const64 (scratch, delta_rtx);
+      else
+	sparc_emit_set_const32 (scratch, delta_rtx);
+      delta_rtx = scratch;
+    }
+
+  tmp = gen_rtx_PLUS (Pmode, this, delta_rtx);
+  emit_insn (gen_rtx_SET (VOIDmode, this, tmp));
+
+  /* Generate a tail call to the target function.  */
+  if (! TREE_USED (function))
+    {
+      assemble_external (function);
+      TREE_USED (function) = 1;
+    }
+  funexp = XEXP (DECL_RTL (function), 0);
+  funexp = gen_rtx_MEM (FUNCTION_MODE, funexp);
+  insn = emit_call_insn (gen_sibcall (funexp));
+  SIBLING_CALL_P (insn) = 1;
+  emit_barrier ();
+
+  /* Run just enough of rest_of_compilation to get the insns emitted.
+     There's not really enough bulk here to make other passes such as
+     instruction scheduling worth while.  Note that use_thunk calls
+     assemble_start_function and assemble_end_function.  */
+  insn = get_insns ();
+  shorten_branches (insn);
+  final_start_function (insn, file, 1);
+  final (insn, file, 1, 0);
+  final_end_function ();
+
+  reload_completed = 0;
+  no_new_pseudos = 0;
+}
diff --git a/contrib/gcc/config/sparc/sparc.h b/contrib/gcc/config/sparc/sparc.h
index 3f21578..2902f06 100644
--- a/contrib/gcc/config/sparc/sparc.h
+++ b/contrib/gcc/config/sparc/sparc.h
@@ -1414,6 +1414,8 @@ extern char leaf_reg_remap[];
 #define PREFERRED_RELOAD_CLASS(X,CLASS)			\
   (CONSTANT_P (X)					\
    ? ((FP_REG_CLASS_P (CLASS)				\
+       || (CLASS) == GENERAL_OR_FP_REGS			\
+       || (CLASS) == GENERAL_OR_EXTRA_FP_REGS		\
        || (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT	\
 	   && ! TARGET_FPU)				\
        || (GET_MODE (X) == TFmode			\
@@ -1958,7 +1960,8 @@ do {									\
    return an rtx for the address of the word in the frame
    that holds the dynamic chain--the previous frame's address.
    ??? -mflat support? */
-#define DYNAMIC_CHAIN_ADDRESS(frame) plus_constant (frame, 14 * UNITS_PER_WORD)
+#define DYNAMIC_CHAIN_ADDRESS(frame)	\
+  plus_constant (frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS)
 
 /* The return address isn't on the stack, it is in a register, so we can't
    access it from the current frame pointer.  We can access it from the
@@ -2568,6 +2571,11 @@ do {                                                                    \
 #define LTTF2_LIBCALL "_Q_flt"
 #define LETF2_LIBCALL "_Q_fle"
 
+/* Assume by default that the _Qp_* 64-bit libcalls are implemented such
+   that the inputs are fully consumed before the output memory is clobbered.  */
+
+#define TARGET_BUGGY_QP_LIB	0
+
 /* We can define the TFmode sqrt optab only if TARGET_FPU.  This is because
    with soft-float, the SFmode and DFmode sqrt instructions will be absent,
    and the compiler will notice and try to use the TFmode sqrt instruction
@@ -2604,6 +2612,17 @@ do {                                                                    \
 	  sqrt_optab->handlers[(int) TFmode].libfunc			\
 	    = init_one_libfunc ("_Q_sqrt");				\
       }									\
+    if (TARGET_ARCH64)							\
+      {									\
+        /* In the SPARC 64bit ABI, these libfuncs do not exist in the	\
+           library.  Make sure the compiler does not emit calls to them	\
+	   by accident.  */						\
+	sdiv_optab->handlers[(int) SImode].libfunc = NULL;		\
+	udiv_optab->handlers[(int) SImode].libfunc = NULL;		\
+	smod_optab->handlers[(int) SImode].libfunc = NULL;		\
+	umod_optab->handlers[(int) SImode].libfunc = NULL;		\
+        smul_optab->handlers[(int) SImode].libfunc = NULL;		\
+      }									\
     INIT_SUBTARGET_OPTABS;						\
   } while (0)
 
@@ -2903,24 +2922,8 @@ do {									\
 
 /* Output code to add DELTA to the first argument, and then jump to FUNCTION.
    Used for C++ multiple inheritance.  */
-#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION)	\
-do {									\
-  int reg = 0;								\
-									\
-  if (TARGET_ARCH64							\
-      && aggregate_value_p (TREE_TYPE (TREE_TYPE (FUNCTION))))		\
-    reg = 1;								\
-  if ((DELTA) >= 4096 || (DELTA) < -4096)				\
-    fprintf (FILE, "\tset\t%d, %%g1\n\tadd\t%%o%d, %%g1, %%o%d\n",	\
-	     (int)(DELTA), reg, reg);					\
-  else									\
-    fprintf (FILE, "\tadd\t%%o%d, %d, %%o%d\n", reg, (int)(DELTA), reg);\
-  fprintf (FILE, "\tor\t%%o7, %%g0, %%g1\n");				\
-  fprintf (FILE, "\tcall\t");						\
-  assemble_name (FILE, XSTR (XEXP (DECL_RTL (FUNCTION), 0), 0));	\
-  fprintf (FILE, ", 0\n");						\
-  fprintf (FILE, "\t or\t%%g1, %%g0, %%o7\n");				\
-} while (0)
+#define ASM_OUTPUT_MI_THUNK(FILE, THUNK_FNDECL, DELTA, FUNCTION) \
+  sparc_output_mi_thunk (FILE, THUNK_FNDECL, DELTA, FUNCTION)
 
 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \
   ((CHAR) == '#' || (CHAR) == '*' || (CHAR) == '^' || (CHAR) == '(' || (CHAR) == '_')
diff --git a/contrib/gcc/config/sparc/t-crtfm b/contrib/gcc/config/sparc/t-crtfm
index 744537d..e0adb97 100644
--- a/contrib/gcc/config/sparc/t-crtfm
+++ b/contrib/gcc/config/sparc/t-crtfm
@@ -1,4 +1,4 @@
 EXTRA_PARTS += crtfastmath.o
 
-crtfastmath.o: $(srcdir)/config/sparc/crtfastmath.c $(GCC_PASSES)
-	$(GCC_FOR_TARGET) $(LIBGCC2_CFLAGS) -c -o crtfastmath.o $(srcdir)/config/sparc/crtfastmath.c
+$(T)crtfastmath.o: $(srcdir)/config/sparc/crtfastmath.c $(GCC_PASSES)
+	$(GCC_FOR_TARGET) $(MULTILIB_CFLAGS) $(LIBGCC2_CFLAGS) -c -o $(T)crtfastmath.o $(srcdir)/config/sparc/crtfastmath.c
diff --git a/contrib/gcc/config/sparc/t-linux64 b/contrib/gcc/config/sparc/t-linux64
index c93ff25..a648626 100644
--- a/contrib/gcc/config/sparc/t-linux64
+++ b/contrib/gcc/config/sparc/t-linux64
@@ -7,7 +7,8 @@ MULTILIB_EXCLUSIONS = m32/!m64/mno-app-regs m32/!m64/mcmodel=medany
 LIBGCC = stmp-multilib
 INSTALL_LIBGCC = install-multilib
 
-EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o
+EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o crtbeginS.o crtendS.o crtbeginT.o \
+	crtfastmath.o
 
 SHLIB_SLIBDIR_SUFFIXES = 64:64 32:
 
diff --git a/contrib/gcc/config/sparc/t-sol2-64 b/contrib/gcc/config/sparc/t-sol2-64
index ef7dee7..39204d7 100644
--- a/contrib/gcc/config/sparc/t-sol2-64
+++ b/contrib/gcc/config/sparc/t-sol2-64
@@ -5,6 +5,7 @@ MULTILIB_MATCHES =
 LIBGCC = stmp-multilib
 INSTALL_LIBGCC = install-multilib
 
-EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o gmon.o crt1.o crti.o crtn.o gcrt1.o
+EXTRA_MULTILIB_PARTS=crtbegin.o crtend.o gmon.o crt1.o crti.o crtn.o gcrt1.o \
+	crtfastmath.o
 
 SHLIB_SLIBDIR_SUFFIXES = sparcv9:/sparcv9 sparcv7: