MFC r258428, r258445

gcc: another round of merges from the gcc pre-43 branch.

Bring The following revisions from the gcc43 branch[1]:

118360, 118361, 118363, 118576, 119820,
123906, 125246, and 125721.

They all have in common that the were merged long ago
into Apple's gcc and should help improve the general
quality of the compiler and make it easier to bring
new features from Apple's gcc42.

For details please review the additions to the files:
gcc/ChangeLog.gcc43
gcc/cp/ChangeLog.gcc43 (new, adds previous revisions)

Fix crosscompilation (r258445 by andreast)
Reference:
[1] http://gcc.gnu.org/viewcvs/gcc/trunk/?pathrev=126700

Obtained from:	gcc pre4.3 (GPLv2) branch
MFC after:	3 weeks

6 files changed, 295 insertions, 273 deletions

diff --git a/contrib/gcc/config/i386/beos-elf.h b/contrib/gcc/config/i386/beos-elf.h
index f1e2cf8..3acc830 100644
--- a/contrib/gcc/config/i386/beos-elf.h
+++ b/contrib/gcc/config/i386/beos-elf.h
@@ -135,7 +135,7 @@ Boston, MA 02110-1301, USA.  */
    for the BeOS include files relative to TOOL_INCLUDE_DIR.  Yes, we
    use ANSI string concatenation here (FIXME) */
 
-#ifndef CROSS_COMPILE
+#ifndef CROSS_DIRECTORY_STRUCTURE
 #undef INCLUDE_DEFAULTS
 #define INCLUDE_DEFAULTS \
     { \
@@ -177,7 +177,7 @@ Boston, MA 02110-1301, USA.  */
     { "/boot/develop/headers", 0, 0, 0 }, \
     { 0, 0, 0, 0 } \
     }
-#else /* CROSS_COMPILE */
+#else /* CROSS_DIRECTORY_STRUCTURE */
 #undef	INCLUDE_DEFAULTS
 #define INCLUDE_DEFAULTS				\
     { \
diff --git a/contrib/gcc/config/i386/cygwin.h b/contrib/gcc/config/i386/cygwin.h
index a7d5e47..fe85a6d 100644
--- a/contrib/gcc/config/i386/cygwin.h
+++ b/contrib/gcc/config/i386/cygwin.h
@@ -146,7 +146,7 @@ char cygwin_tool_include_dir[sizeof (TOOL_INCLUDE_DIR) + 1
 #undef TOOL_INCLUDE_DIR
 #define TOOL_INCLUDE_DIR ((const char *) cygwin_tool_include_dir)
 
-#ifndef CROSS_COMPILE
+#ifndef CROSS_DIRECTORY_STRUCTURE
 #undef STANDARD_INCLUDE_DIR
 #define STANDARD_INCLUDE_DIR "/usr/include"
 char cygwin_standard_include_dir[sizeof (STANDARD_INCLUDE_DIR) + 1
diff --git a/contrib/gcc/config/i386/i386.c b/contrib/gcc/config/i386/i386.c
index 1598ae9..51bd93c 100644
--- a/contrib/gcc/config/i386/i386.c
+++ b/contrib/gcc/config/i386/i386.c
@@ -1089,6 +1089,8 @@ const int x86_cmpxchg = ~m_386;
 const int x86_cmpxchg8b = ~(m_386 | m_486);
 /* Exchange and add was added for 80486.  */
 const int x86_xadd = ~m_386;
+/* Byteswap was added for 80486.  */
+const int x86_bswap = ~m_386;
 const int x86_pad_returns = m_ATHLON_K8_AMDFAM10 | m_CORE2 | m_GENERIC;
 
 /* In case the average insn count for single function invocation is
diff --git a/contrib/gcc/config/i386/i386.h b/contrib/gcc/config/i386/i386.h
index 1394fba..4a303f6 100644
--- a/contrib/gcc/config/i386/i386.h
+++ b/contrib/gcc/config/i386/i386.h
@@ -168,6 +168,7 @@ extern const int x86_use_bt;
 extern const int x86_cmpxchg, x86_cmpxchg8b, x86_xadd;
 extern const int x86_use_incdec;
 extern const int x86_pad_returns;
+extern const int x86_bswap;
 extern const int x86_partial_flag_reg_stall;
 extern int x86_prefetch_sse, x86_cmpxchg16b;
 
@@ -243,6 +244,7 @@ extern int x86_prefetch_sse, x86_cmpxchg16b;
 #define TARGET_CMPXCHG8B (x86_cmpxchg8b & (1 << ix86_arch))
 #define TARGET_CMPXCHG16B (x86_cmpxchg16b)
 #define TARGET_XADD (x86_xadd & (1 << ix86_arch))
+#define TARGET_BSWAP (x86_bswap & (1 << ix86_arch))
 
 #ifndef TARGET_64BIT_DEFAULT
 #define TARGET_64BIT_DEFAULT 0
diff --git a/contrib/gcc/config/i386/i386.md b/contrib/gcc/config/i386/i386.md
index 21b9cb3..f009cbb 100644
--- a/contrib/gcc/config/i386/i386.md
+++ b/contrib/gcc/config/i386/i386.md
@@ -284,14 +284,14 @@
     (const_int 0)))
 
 ;; Set when string REP prefix is used.
-(define_attr "prefix_rep" "" 
+(define_attr "prefix_rep" ""
   (if_then_else (and (eq_attr "unit" "sse") (eq_attr "mode" "SF,DF"))
     (const_int 1)
     (const_int 0)))
 
 ;; Set when 0f opcode prefix is used.
 (define_attr "prefix_0f" ""
-  (if_then_else 
+  (if_then_else
     (ior (eq_attr "type" "imovx,setcc,icmov,bitmanip")
 	 (eq_attr "unit" "sse,mmx"))
     (const_int 1)
@@ -466,7 +466,7 @@
 
 ;; All x87 floating point modes
 (define_mode_macro X87MODEF [SF DF XF])
- 
+
 ;; All integer modes handled by x87 fisttp operator.
 (define_mode_macro X87MODEI [HI SI DI])
 
@@ -475,7 +475,7 @@
 
 ;; All SSE floating point modes
 (define_mode_macro SSEMODEF [SF DF])
- 
+
 ;; All integer modes handled by SSE cvtts?2si* operators.
 (define_mode_macro SSEMODEI24 [SI DI])
 
@@ -1098,7 +1098,7 @@
 ;; Push/pop instructions.  They are separate since autoinc/dec is not a
 ;; general_operand.
 ;;
-;; %%% We don't use a post-inc memory reference because x86 is not a 
+;; %%% We don't use a post-inc memory reference because x86 is not a
 ;; general AUTO_INC_DEC host, which impacts how it is treated in flow.
 ;; Changing this impacts compiler performance on other non-AUTO_INC_DEC
 ;; targets without our curiosities, and it is just as easy to represent
@@ -1160,7 +1160,7 @@
   [(set_attr "type" "alu1")
    (set_attr "mode" "SI")
    (set_attr "length_immediate" "0")])
- 
+
 (define_insn "*movsi_or"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(match_operand:SI 1 "immediate_operand" "i"))
@@ -2308,7 +2308,7 @@
    && (reload_in_progress || reload_completed
        || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
        || GET_CODE (operands[1]) != CONST_DOUBLE
-       || memory_operand (operands[0], SFmode))" 
+       || memory_operand (operands[0], SFmode))"
 {
   switch (which_alternative)
     {
@@ -2368,7 +2368,7 @@
 		   (const_string "V4SF"))
 	       /* For architectures resolving dependencies on
 		  whole SSE registers use APS move to break dependency
-		  chains, otherwise use short move to avoid extra work. 
+		  chains, otherwise use short move to avoid extra work.
 
 		  Do the same for architectures resolving dependencies on
 		  the parts.  While in DF mode it is better to always handle
@@ -2476,7 +2476,7 @@
    && (reload_in_progress || reload_completed
        || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
        || GET_CODE (operands[1]) != CONST_DOUBLE
-       || memory_operand (operands[0], DFmode))" 
+       || memory_operand (operands[0], DFmode))"
 {
   switch (which_alternative)
     {
@@ -2596,7 +2596,7 @@
    && (reload_in_progress || reload_completed
        || (ix86_cmodel == CM_MEDIUM || ix86_cmodel == CM_LARGE)
        || GET_CODE (operands[1]) != CONST_DOUBLE
-       || memory_operand (operands[0], DFmode))" 
+       || memory_operand (operands[0], DFmode))"
 {
   switch (which_alternative)
     {
@@ -2712,10 +2712,10 @@
 	(match_operand:DF 1 "general_operand" ""))]
   "reload_completed
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
-   && ! (ANY_FP_REG_P (operands[0]) || 
+   && ! (ANY_FP_REG_P (operands[0]) ||
 	 (GET_CODE (operands[0]) == SUBREG
 	  && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
-   && ! (ANY_FP_REG_P (operands[1]) || 
+   && ! (ANY_FP_REG_P (operands[1]) ||
 	 (GET_CODE (operands[1]) == SUBREG
 	  && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
   [(const_int 0)]
@@ -2807,7 +2807,7 @@
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
    && (reload_in_progress || reload_completed
        || GET_CODE (operands[1]) != CONST_DOUBLE
-       || memory_operand (operands[0], XFmode))" 
+       || memory_operand (operands[0], XFmode))"
 {
   switch (which_alternative)
     {
@@ -2841,7 +2841,7 @@
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
    && (reload_in_progress || reload_completed
        || GET_CODE (operands[1]) != CONST_DOUBLE
-       || memory_operand (operands[0], XFmode))" 
+       || memory_operand (operands[0], XFmode))"
 {
   switch (which_alternative)
     {
@@ -2875,10 +2875,10 @@
   "reload_completed
    && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
    && GET_MODE (operands[0]) == XFmode
-   && ! (ANY_FP_REG_P (operands[0]) || 
+   && ! (ANY_FP_REG_P (operands[0]) ||
 	 (GET_CODE (operands[0]) == SUBREG
 	  && ANY_FP_REG_P (SUBREG_REG (operands[0]))))
-   && ! (ANY_FP_REG_P (operands[1]) || 
+   && ! (ANY_FP_REG_P (operands[1]) ||
 	 (GET_CODE (operands[1]) == SUBREG
 	  && ANY_FP_REG_P (SUBREG_REG (operands[1]))))"
   [(const_int 0)]
@@ -3073,7 +3073,7 @@
   [(set (match_operand:HI 0 "register_operand" "")
 	(zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))
    (clobber (reg:CC FLAGS_REG))]
-  "reload_completed 
+  "reload_completed
    && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
    && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
   [(set (match_operand:HI 0 "register_operand" "")
@@ -3143,7 +3143,7 @@
   [(set (match_operand:SI 0 "register_operand" "")
 	(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))
    (clobber (reg:CC FLAGS_REG))]
-  "reload_completed 
+  "reload_completed
    && (!TARGET_ZERO_EXTEND_WITH_AND || optimize_size)
    && (!REG_P (operands[1]) || ANY_QI_REG_P (operands[1]))"
   [(set (match_dup 0)
@@ -3220,7 +3220,7 @@
   [(set (match_dup 4) (const_int 0))]
   "split_di (&operands[0], 1, &operands[3], &operands[4]);")
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "register_operand" "")
 	(zero_extend:DI (match_operand:SI 1 "register_operand" "")))
    (clobber (reg:CC FLAGS_REG))]
@@ -3229,7 +3229,7 @@
   [(set (match_dup 4) (const_int 0))]
   "split_di (&operands[0], 1, &operands[3], &operands[4]);")
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "nonimmediate_operand" "")
 	(zero_extend:DI (match_operand:SI 1 "general_operand" "")))
    (clobber (reg:CC FLAGS_REG))]
@@ -3308,7 +3308,7 @@
     (set_attr "mode" "DI")])
 
 ;; Extend to memory case when source register does die.
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "memory_operand" "")
 	(sign_extend:DI (match_operand:SI 1 "register_operand" "")))
    (clobber (reg:CC FLAGS_REG))
@@ -3323,7 +3323,7 @@
   "split_di (&operands[0], 1, &operands[3], &operands[4]);")
 
 ;; Extend to memory case when source register does not die.
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "memory_operand" "")
 	(sign_extend:DI (match_operand:SI 1 "register_operand" "")))
    (clobber (reg:CC FLAGS_REG))
@@ -3353,7 +3353,7 @@
 
 ;; Extend to register case.  Optimize case where source and destination
 ;; registers match and cases where we can use cltd.
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "register_operand" "")
 	(sign_extend:DI (match_operand:SI 1 "register_operand" "")))
    (clobber (reg:CC FLAGS_REG))
@@ -3482,7 +3482,7 @@
 ;; These are all no-ops in the model used for the 80387.  So just
 ;; emit moves.
 
-;; %%% Kill these when call knows how to work out a DFmode push earlier. 
+;; %%% Kill these when call knows how to work out a DFmode push earlier.
 (define_insn "*dummy_extendsfdf2"
   [(set (match_operand:DF 0 "push_operand" "=<")
 	(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fY")))]
@@ -4365,7 +4365,7 @@
    (set_attr "i387_cw" "trunc")
    (set_attr "mode" "DI")])
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "register_operand" "")
 	(fix:DI (match_operand 1 "register_operand" "")))
    (use (match_operand:HI 2 "memory_operand" ""))
@@ -4380,7 +4380,7 @@
    (set (match_dup 0) (match_dup 4))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "memory_operand" "")
 	(fix:DI (match_operand 1 "register_operand" "")))
    (use (match_operand:HI 2 "memory_operand" ""))
@@ -4421,7 +4421,7 @@
    (set_attr "i387_cw" "trunc")
    (set_attr "mode" "<MODE>")])
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "register_operand" "")
 	(fix:X87MODEI12 (match_operand 1 "register_operand" "")))
    (use (match_operand:HI 2 "memory_operand" ""))
@@ -4434,7 +4434,7 @@
    (set (match_dup 0) (match_dup 4))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "memory_operand" "")
 	(fix:X87MODEI12 (match_operand 1 "register_operand" "")))
    (use (match_operand:HI 2 "memory_operand" ""))
@@ -4913,7 +4913,7 @@
 
 (define_insn "*addsi3_carry_zext"
   [(set (match_operand:DI 0 "register_operand" "=r")
-	  (zero_extend:DI 
+	  (zero_extend:DI
 	    (plus:SI (plus:SI (match_operand:SI 3 "ix86_carry_flag_operator" "")
 			      (match_operand:SI 1 "nonimmediate_operand" "%0"))
 		     (match_operand:SI 2 "general_operand" "rim"))))
@@ -5222,7 +5222,7 @@
 	(compare
 	  (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0")
 		   (match_operand:DI 2 "x86_64_general_operand" "rme,re"))
-	  (const_int 0)))			
+	  (const_int 0)))
    (set (match_operand:DI 0 "nonimmediate_operand" "=r,rm")
 	(plus:DI (match_dup 1) (match_dup 2)))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
@@ -5369,7 +5369,7 @@
 	(compare
 	  (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0")
 		   (match_operand:DI 2 "x86_64_general_operand" "rme"))
-	  (const_int 0)))			
+	  (const_int 0)))
    (clobber (match_scratch:DI 0 "=r"))]
   "TARGET_64BIT
    && ix86_match_ccmode (insn, CCGOCmode)
@@ -5568,7 +5568,7 @@
 	(compare
 	  (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0")
 		   (match_operand:SI 2 "general_operand" "rmni,rni"))
-	  (const_int 0)))			
+	  (const_int 0)))
    (set (match_operand:SI 0 "nonimmediate_operand" "=r,rm")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
@@ -5616,7 +5616,7 @@
 	(compare
 	  (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
 		   (match_operand:SI 2 "general_operand" "rmni"))
-	  (const_int 0)))			
+	  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCGOCmode)
@@ -5794,7 +5794,7 @@
 	(compare
 	  (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
 		   (match_operand:SI 2 "general_operand" "rmni"))
-	  (const_int 0)))			
+	  (const_int 0)))
    (clobber (match_scratch:SI 0 "=r"))]
   "ix86_match_ccmode (insn, CCGOCmode)
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)
@@ -5934,7 +5934,7 @@
 	(compare
 	  (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0")
 		   (match_operand:HI 2 "general_operand" "rmni,rni"))
-	  (const_int 0)))			
+	  (const_int 0)))
    (set (match_operand:HI 0 "nonimmediate_operand" "=r,rm")
 	(plus:HI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCGOCmode)
@@ -6054,7 +6054,7 @@
 	(compare
 	  (plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0")
 		   (match_operand:HI 2 "general_operand" "rmni"))
-	  (const_int 0)))			
+	  (const_int 0)))
    (clobber (match_scratch:HI 0 "=r"))]
   "ix86_match_ccmode (insn, CCGOCmode)
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
@@ -7483,7 +7483,7 @@
  		(match_operand:DF 2 "nonimmediate_operand" "")))]
    "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
    "")
- 
+
 (define_expand "divsf3"
   [(set (match_operand:SF 0 "register_operand" "")
 	(div:SF (match_operand:SF 1 "register_operand" "")
@@ -8161,7 +8161,7 @@
 	    gcc_assert (INTVAL (operands[2]) == 0xffff);
 	    mode = HImode;
 	  }
-	
+
 	operands[1] = gen_lowpart (mode, operands[1]);
 	if (mode == QImode)
 	  return "movz{bq|x}\t{%1,%0|%0, %1}";
@@ -8226,7 +8226,7 @@
 	    gcc_assert (INTVAL (operands[2]) == 0xffff);
 	    mode = HImode;
 	  }
-	
+
 	operands[1] = gen_lowpart (mode, operands[1]);
 	if (mode == QImode)
 	  return "movz{bl|x}\t{%1,%0|%0, %1}";
@@ -8270,7 +8270,7 @@
   [(parallel [(set (zero_extract:SI (match_dup 0)
 				    (const_int 8)
 				    (const_int 8))
-		   (xor:SI 
+		   (xor:SI
 		     (zero_extract:SI (match_dup 0)
 				      (const_int 8)
 				      (const_int 8))
@@ -8458,7 +8458,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
-	(and:SI 
+	(and:SI
 	  (zero_extract:SI
 	    (match_operand 1 "ext_register_operand" "0")
 	    (const_int 8)
@@ -8487,7 +8487,7 @@
    (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
-	(and:SI 
+	(and:SI
 	  (zero_extract:SI
 	    (match_dup 1)
 	    (const_int 8)
@@ -8503,7 +8503,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
-	(and:SI 
+	(and:SI
 	  (zero_extract:SI
 	    (match_operand 1 "ext_register_operand" "0")
 	    (const_int 8)
@@ -8521,7 +8521,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
-	(and:SI 
+	(and:SI
 	  (zero_extract:SI
 	    (match_operand 1 "ext_register_operand" "0")
 	    (const_int 8)
@@ -8864,7 +8864,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
-	(ior:SI 
+	(ior:SI
 	  (zero_extract:SI
 	    (match_operand 1 "ext_register_operand" "0")
 	    (const_int 8)
@@ -8881,7 +8881,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
-	(ior:SI 
+	(ior:SI
 	  (zero_extract:SI
 	    (match_operand 1 "ext_register_operand" "0")
 	    (const_int 8)
@@ -8900,7 +8900,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
-	(ior:SI 
+	(ior:SI
 	  (zero_extract:SI
 	    (match_operand 1 "ext_register_operand" "0")
 	    (const_int 8)
@@ -8919,7 +8919,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
-	(ior:SI 
+	(ior:SI
 	  (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
 	  		   (const_int 8)
 			   (const_int 8))
@@ -9202,7 +9202,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
-	(xor:SI 
+	(xor:SI
 	  (zero_extract:SI
 	    (match_operand 1 "ext_register_operand" "0")
 	    (const_int 8)
@@ -9219,7 +9219,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
-	(xor:SI 
+	(xor:SI
 	  (zero_extract:SI
 	    (match_operand 1 "ext_register_operand" "0")
 	    (const_int 8)
@@ -9238,7 +9238,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
-	(xor:SI 
+	(xor:SI
 	  (zero_extract:SI
 	    (match_operand 1 "ext_register_operand" "0")
 	    (const_int 8)
@@ -9257,7 +9257,7 @@
   [(set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
-	(xor:SI 
+	(xor:SI
 	  (zero_extract:SI (match_operand 1 "ext_register_operand" "0")
 	  		   (const_int 8)
 			   (const_int 8))
@@ -9325,7 +9325,7 @@
    (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=q")
 			 (const_int 8)
 			 (const_int 8))
-	(xor:SI 
+	(xor:SI
 	  (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
 	  (match_dup 2)))]
   "!TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
@@ -9346,7 +9346,7 @@
    (set (zero_extract:SI (match_operand 0 "ext_register_operand" "=Q")
 			 (const_int 8)
 			 (const_int 8))
-	(xor:SI 
+	(xor:SI
 	  (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
 	  (match_dup 2)))]
   "TARGET_64BIT && ix86_match_ccmode (insn, CCNOmode)"
@@ -9368,7 +9368,7 @@
      (set (zero_extract:SI (match_operand 0 "ext_register_operand" "")
 			   (const_int 8)
 			   (const_int 8))
-	  (xor:SI 
+	  (xor:SI
 	    (zero_extract:SI (match_dup 1) (const_int 8) (const_int 8))
 	    (match_dup 2)))])]
   ""
@@ -9867,7 +9867,7 @@
   enum machine_mode mode = GET_MODE (operands[0]);
   enum machine_mode vmode = GET_MODE (operands[2]);
   rtx tmp;
-  
+
   operands[0] = simplify_gen_subreg (vmode, operands[0], mode, 0);
   operands[1] = simplify_gen_subreg (vmode, operands[1], mode, 0);
   if (operands_match_p (operands[0], operands[2]))
@@ -9891,7 +9891,7 @@
   "reload_completed"
   [(parallel [(set (match_dup 0) (match_dup 1))
 	      (clobber (reg:CC FLAGS_REG))])]
-{ 
+{
   rtx tmp;
   operands[0] = gen_lowpart (SImode, operands[0]);
   if (GET_CODE (operands[1]) == ABS)
@@ -9998,7 +9998,7 @@
   operands[1] = tmp;
 })
 
-;; Conditionalize these after reload. If they match before reload, we 
+;; Conditionalize these after reload. If they match before reload, we
 ;; lose the clobber and ability to use integer instructions.
 
 (define_insn "*negsf2_1"
@@ -11415,8 +11415,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "sar{q}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:DI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:DI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -11448,8 +11448,8 @@
    && ix86_binary_operator_ok (ASHIFTRT, DImode, operands)"
   "sar{q}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:DI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:DI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -11628,8 +11628,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "sar{l}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -11684,8 +11684,8 @@
    && ix86_binary_operator_ok (ASHIFTRT, SImode, operands)"
   "sar{l}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -11785,8 +11785,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "sar{w}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -11818,8 +11818,8 @@
    && ix86_binary_operator_ok (ASHIFTRT, HImode, operands)"
   "sar{w}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -11888,8 +11888,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "sar{b}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -11903,8 +11903,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "sar{b}\t%0"
   [(set_attr "type" "ishift1")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -11949,8 +11949,8 @@
    && ix86_binary_operator_ok (ASHIFTRT, QImode, operands)"
   "sar{b}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12042,7 +12042,7 @@
   "#"
   [(set_attr "type" "multi")])
 
-(define_split 
+(define_split
   [(set (match_operand:TI 0 "register_operand" "")
 	(lshiftrt:TI (match_operand:TI 1 "register_operand" "")
 		     (match_operand:QI 2 "register_operand" "")))
@@ -12052,7 +12052,7 @@
   [(const_int 0)]
   "ix86_split_lshr (operands, operands[3], TImode); DONE;")
 
-(define_split 
+(define_split
   [(set (match_operand:TI 0 "register_operand" "")
 	(lshiftrt:TI (match_operand:TI 1 "register_operand" "")
 		     (match_operand:QI 2 "immediate_operand" "")))
@@ -12077,8 +12077,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "shr{q}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:DI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:DI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12110,8 +12110,8 @@
    && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
   "shr{q}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:DI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:DI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12186,7 +12186,7 @@
   [(const_int 0)]
   "ix86_split_lshr (operands, operands[3], DImode); DONE;")
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "register_operand" "")
 	(lshiftrt:DI (match_operand:DI 1 "register_operand" "")
 		     (match_operand:QI 2 "nonmemory_operand" "")))
@@ -12213,8 +12213,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "shr{l}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12270,8 +12270,8 @@
    && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
   "shr{l}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12371,8 +12371,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "shr{w}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12404,8 +12404,8 @@
    && ix86_binary_operator_ok (LSHIFTRT, HImode, operands)"
   "shr{w}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12474,8 +12474,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "shr{b}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12488,8 +12488,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "shr{b}\t%0"
   [(set_attr "type" "ishift1")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12534,8 +12534,8 @@
    && ix86_binary_operator_ok (LSHIFTRT, QImode, operands)"
   "shr{b}\t%0"
   [(set_attr "type" "ishift")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12608,7 +12608,7 @@
 })
 
 ;; Implement rotation using two double-precision shift instructions
-;; and a scratch register.   
+;; and a scratch register.
 (define_insn_and_split "ix86_rotldi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (rotate:DI (match_operand:DI 1 "register_operand" "0")
@@ -12616,7 +12616,7 @@
   (clobber (reg:CC FLAGS_REG))
   (clobber (match_scratch:SI 3 "=&r"))]
  "!TARGET_64BIT"
- "" 
+ ""
  "&& reload_completed"
  [(set (match_dup 3) (match_dup 4))
   (parallel
@@ -12632,7 +12632,7 @@
                               (minus:QI (const_int 32) (match_dup 2)))))
     (clobber (reg:CC FLAGS_REG))])]
  "split_di (operands, 1, operands + 4, operands + 5);")
- 
+
 (define_insn "*rotlsi3_1_one_bit_rex64"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
 	(rotate:DI (match_operand:DI 1 "nonimmediate_operand" "0")
@@ -12642,8 +12642,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "rol{q}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand:DI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:DI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12676,8 +12676,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "rol{l}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12735,8 +12735,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "rol{w}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12769,8 +12769,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "rol{b}\t%0"
   [(set_attr "type" "rotate1")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12783,8 +12783,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "rol{b}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12830,9 +12830,9 @@
   emit_insn (gen_ix86_rotrdi3 (operands[0], operands[1], operands[2]));
   DONE;
 })
-  
+
 ;; Implement rotation using two double-precision shift instructions
-;; and a scratch register.   
+;; and a scratch register.
 (define_insn_and_split "ix86_rotrdi3"
  [(set (match_operand:DI 0 "register_operand" "=r")
        (rotatert:DI (match_operand:DI 1 "register_operand" "0")
@@ -12866,8 +12866,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "ror{q}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand:DI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:DI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12900,8 +12900,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "ror{l}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12915,8 +12915,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "ror{l}\t%k0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand:SI 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand:SI 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12962,8 +12962,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "ror{w}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -12996,8 +12996,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "ror{b}\t%0"
   [(set_attr "type" "rotate")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -13010,8 +13010,8 @@
    && (TARGET_SHIFT1 || optimize_size)"
   "ror{b}\t%0"
   [(set_attr "type" "rotate1")
-   (set (attr "length") 
-     (if_then_else (match_operand 0 "register_operand" "") 
+   (set (attr "length")
+     (if_then_else (match_operand 0 "register_operand" "")
 	(const_string "2")
 	(const_string "*")))])
 
@@ -13378,14 +13378,14 @@
    (set_attr "mode" "QI")])
 
 ;; In general it is not safe to assume too much about CCmode registers,
-;; so simplify-rtx stops when it sees a second one.  Under certain 
+;; so simplify-rtx stops when it sees a second one.  Under certain
 ;; conditions this is safe on x86, so help combine not create
 ;;
 ;;	seta	%al
 ;;	testb	%al, %al
 ;;	sete	%al
 
-(define_split 
+(define_split
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
 	(ne:QI (match_operator 1 "ix86_comparison_operator"
 	         [(reg FLAGS_REG) (const_int 0)])
@@ -13396,7 +13396,7 @@
   PUT_MODE (operands[1], QImode);
 })
 
-(define_split 
+(define_split
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
 	(ne:QI (match_operator 1 "ix86_comparison_operator"
 	         [(reg FLAGS_REG) (const_int 0)])
@@ -13407,7 +13407,7 @@
   PUT_MODE (operands[1], QImode);
 })
 
-(define_split 
+(define_split
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
 	(eq:QI (match_operator 1 "ix86_comparison_operator"
 	         [(reg FLAGS_REG) (const_int 0)])
@@ -13427,7 +13427,7 @@
     FAIL;
 })
 
-(define_split 
+(define_split
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
 	(eq:QI (match_operator 1 "ix86_comparison_operator"
 	         [(reg FLAGS_REG) (const_int 0)])
@@ -13659,14 +13659,14 @@
 	     (const_int 6)))])
 
 ;; In general it is not safe to assume too much about CCmode registers,
-;; so simplify-rtx stops when it sees a second one.  Under certain 
+;; so simplify-rtx stops when it sees a second one.  Under certain
 ;; conditions this is safe on x86, so help combine not create
 ;;
 ;;	seta	%al
 ;;	testb	%al, %al
 ;;	je	Lfoo
 
-(define_split 
+(define_split
   [(set (pc)
 	(if_then_else (ne (match_operator 0 "ix86_comparison_operator"
 				      [(reg FLAGS_REG) (const_int 0)])
@@ -13681,8 +13681,8 @@
 {
   PUT_MODE (operands[0], VOIDmode);
 })
-  
-(define_split 
+
+(define_split
   [(set (pc)
 	(if_then_else (eq (match_operator 0 "ix86_comparison_operator"
 				      [(reg FLAGS_REG) (const_int 0)])
@@ -14157,7 +14157,7 @@
     return "call\t%P0";
 }
   [(set_attr "type" "call")])
-  
+
 (define_insn "*call_pop_1"
   [(call (mem:QI (match_operand:SI 0 "call_insn_operand" "rsm"))
 	 (match_operand:SI 1 "" ""))
@@ -14493,7 +14493,7 @@
 })
 
 (define_insn_and_split "eh_return_si"
-  [(set (pc) 
+  [(set (pc)
         (unspec [(match_operand:SI 0 "register_operand" "c")]
 	         UNSPEC_EH_RETURN))]
   "!TARGET_64BIT"
@@ -14503,7 +14503,7 @@
   "ix86_expand_epilogue (2); DONE;")
 
 (define_insn_and_split "eh_return_di"
-  [(set (pc) 
+  [(set (pc)
         (unspec [(match_operand:DI 0 "register_operand" "c")]
 	         UNSPEC_EH_RETURN))]
   "TARGET_64BIT"
@@ -14530,7 +14530,7 @@
 
 (define_expand "ffssi2"
   [(parallel
-     [(set (match_operand:SI 0 "register_operand" "") 
+     [(set (match_operand:SI 0 "register_operand" "")
 	   (ffs:SI (match_operand:SI 1 "nonimmediate_operand" "")))
       (clobber (match_scratch:SI 2 ""))
       (clobber (reg:CC FLAGS_REG))])]
@@ -14538,7 +14538,7 @@
   "")
 
 (define_insn_and_split "*ffs_cmove"
-  [(set (match_operand:SI 0 "register_operand" "=r") 
+  [(set (match_operand:SI 0 "register_operand" "=r")
 	(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
    (clobber (match_scratch:SI 2 "=&r"))
    (clobber (reg:CC FLAGS_REG))]
@@ -14557,7 +14557,7 @@
   "")
 
 (define_insn_and_split "*ffs_no_cmove"
-  [(set (match_operand:SI 0 "nonimmediate_operand" "=r") 
+  [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
 	(ffs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))
    (clobber (match_scratch:SI 2 "=&q"))
    (clobber (reg:CC FLAGS_REG))]
@@ -14591,7 +14591,7 @@
 
 (define_expand "ffsdi2"
   [(parallel
-     [(set (match_operand:DI 0 "register_operand" "") 
+     [(set (match_operand:DI 0 "register_operand" "")
 	   (ffs:DI (match_operand:DI 1 "nonimmediate_operand" "")))
       (clobber (match_scratch:DI 2 ""))
       (clobber (reg:CC FLAGS_REG))])]
@@ -14599,7 +14599,7 @@
   "")
 
 (define_insn_and_split "*ffs_rex64"
-  [(set (match_operand:DI 0 "register_operand" "=r") 
+  [(set (match_operand:DI 0 "register_operand" "=r")
 	(ffs:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))
    (clobber (match_scratch:DI 2 "=&r"))
    (clobber (reg:CC FLAGS_REG))]
@@ -14718,6 +14718,24 @@
    (set_attr "type" "bitmanip")
    (set_attr "mode" "SI")])
 
+(define_insn "bswapsi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(bswap:SI (match_operand:SI 1 "register_operand" "0")))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_BSWAP"
+  "bswap\t%k0"
+  [(set_attr "prefix_0f" "1")
+   (set_attr "length" "2")])
+
+(define_insn "bswapdi2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(bswap:DI (match_operand:DI 1 "register_operand" "0")))
+   (clobber (reg:CC FLAGS_REG))]
+  "TARGET_64BIT && TARGET_BSWAP"
+  "bswap\t%0"
+  [(set_attr "prefix_0f" "1")
+   (set_attr "length" "3")])
+
 (define_expand "clzdi2"
   [(parallel
      [(set (match_operand:DI 0 "register_operand" "")
@@ -15231,12 +15249,12 @@
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
+  [(set (attr "type")
 	(if_then_else (eq_attr "alternative" "1")
-	   (if_then_else (match_operand:SF 3 "mult_operator" "") 
+	   (if_then_else (match_operand:SF 3 "mult_operator" "")
 	      (const_string "ssemul")
 	      (const_string "sseadd"))
-	   (if_then_else (match_operand:SF 3 "mult_operator" "") 
+	   (if_then_else (match_operand:SF 3 "mult_operator" "")
 	      (const_string "fmul")
 	      (const_string "fop"))))
    (set_attr "mode" "SF")])
@@ -15250,8 +15268,8 @@
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (if_then_else (match_operand:SF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (if_then_else (match_operand:SF 3 "mult_operator" "")
 	   (const_string "ssemul")
 	   (const_string "sseadd")))
    (set_attr "mode" "SF")])
@@ -15265,8 +15283,8 @@
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-	(if_then_else (match_operand:SF 3 "mult_operator" "") 
+  [(set (attr "type")
+	(if_then_else (match_operand:SF 3 "mult_operator" "")
 	   (const_string "fmul")
 	   (const_string "fop")))
    (set_attr "mode" "SF")])
@@ -15280,7 +15298,7 @@
    && !COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
+  [(set (attr "type")
         (cond [(and (eq_attr "alternative" "2")
 	            (match_operand:SF 3 "mult_operator" ""))
                  (const_string "ssemul")
@@ -15289,9 +15307,9 @@
                  (const_string "ssediv")
 	       (eq_attr "alternative" "2")
                  (const_string "sseadd")
-	       (match_operand:SF 3 "mult_operator" "") 
+	       (match_operand:SF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:SF 3 "div_operator" "") 
+               (match_operand:SF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15305,7 +15323,7 @@
   "TARGET_SSE_MATH
    && !COMMUTATIVE_ARITH_P (operands[3])"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
+  [(set (attr "type")
         (cond [(match_operand:SF 3 "mult_operator" "")
                  (const_string "ssemul")
 	       (match_operand:SF 3 "div_operator" "")
@@ -15324,10 +15342,10 @@
    && !COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:SF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:SF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:SF 3 "div_operator" "") 
+               (match_operand:SF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15341,10 +15359,10 @@
 	   (match_operand:SF 2 "register_operand" "0,0")]))]
   "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP && !TARGET_SSE_MATH"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:SF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:SF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:SF 3 "div_operator" "") 
+               (match_operand:SF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15358,10 +15376,10 @@
 	   (float:SF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
   "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP && !TARGET_SSE_MATH"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:SF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:SF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:SF 3 "div_operator" "") 
+               (match_operand:SF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15377,12 +15395,12 @@
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
+  [(set (attr "type")
 	(if_then_else (eq_attr "alternative" "1")
-	   (if_then_else (match_operand:DF 3 "mult_operator" "") 
+	   (if_then_else (match_operand:DF 3 "mult_operator" "")
 	      (const_string "ssemul")
 	      (const_string "sseadd"))
-	   (if_then_else (match_operand:DF 3 "mult_operator" "") 
+	   (if_then_else (match_operand:DF 3 "mult_operator" "")
 	      (const_string "fmul")
 	      (const_string "fop"))))
    (set_attr "mode" "DF")])
@@ -15396,8 +15414,8 @@
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (if_then_else (match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (if_then_else (match_operand:DF 3 "mult_operator" "")
 	   (const_string "ssemul")
 	   (const_string "sseadd")))
    (set_attr "mode" "DF")])
@@ -15411,8 +15429,8 @@
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-	(if_then_else (match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+	(if_then_else (match_operand:DF 3 "mult_operator" "")
 	   (const_string "fmul")
 	   (const_string "fop")))
    (set_attr "mode" "DF")])
@@ -15426,7 +15444,7 @@
    && !COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
+  [(set (attr "type")
         (cond [(and (eq_attr "alternative" "2")
 	            (match_operand:DF 3 "mult_operator" ""))
                  (const_string "ssemul")
@@ -15435,9 +15453,9 @@
                  (const_string "ssediv")
 	       (eq_attr "alternative" "2")
                  (const_string "sseadd")
-	       (match_operand:DF 3 "mult_operator" "") 
+	       (match_operand:DF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:DF 3 "div_operator" "") 
+               (match_operand:DF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15452,7 +15470,7 @@
    && !COMMUTATIVE_ARITH_P (operands[3])"
   "* return output_387_binary_op (insn, operands);"
   [(set_attr "mode" "DF")
-   (set (attr "type") 
+   (set (attr "type")
         (cond [(match_operand:DF 3 "mult_operator" "")
                  (const_string "ssemul")
 	       (match_operand:DF 3 "div_operator" "")
@@ -15470,8 +15488,8 @@
    && !COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:DF 3 "mult_operator" "")
                  (const_string "fmul")
                (match_operand:DF 3 "div_operator" "")
                  (const_string "fdiv")
@@ -15488,10 +15506,10 @@
   "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
    && !(TARGET_SSE2 && TARGET_SSE_MATH)"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:DF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:DF 3 "div_operator" "") 
+               (match_operand:DF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15506,10 +15524,10 @@
   "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP
    && !(TARGET_SSE2 && TARGET_SSE_MATH)"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:DF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:DF 3 "div_operator" "") 
+               (match_operand:DF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15524,10 +15542,10 @@
   "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:DF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:DF 3 "div_operator" "") 
+               (match_operand:DF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15541,10 +15559,10 @@
 	    (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
   "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:DF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:DF 3 "div_operator" "") 
+               (match_operand:DF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15559,10 +15577,10 @@
 	    (match_operand:SF 2 "nonimmediate_operand" "fm,0"))]))]
   "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:DF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:DF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:DF 3 "div_operator" "") 
+               (match_operand:DF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15576,8 +15594,8 @@
   "TARGET_80387
    && COMMUTATIVE_ARITH_P (operands[3])"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (if_then_else (match_operand:XF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (if_then_else (match_operand:XF 3 "mult_operator" "")
            (const_string "fmul")
            (const_string "fop")))
    (set_attr "mode" "XF")])
@@ -15590,10 +15608,10 @@
   "TARGET_80387
    && !COMMUTATIVE_ARITH_P (operands[3])"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:XF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:XF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:XF 3 "div_operator" "") 
+               (match_operand:XF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15606,10 +15624,10 @@
 	    (match_operand:XF 2 "register_operand" "0,0")]))]
   "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:XF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:XF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:XF 3 "div_operator" "") 
+               (match_operand:XF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15623,10 +15641,10 @@
 	   (float:XF (match_operand:X87MODEI12 2 "nonimmediate_operand" "m,?r"))]))]
   "TARGET_80387 && TARGET_USE_<MODE>MODE_FIOP"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:XF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:XF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:XF 3 "div_operator" "") 
+               (match_operand:XF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15640,10 +15658,10 @@
 	    (match_operand:XF 2 "register_operand" "0,f")]))]
   "TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:XF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:XF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:XF 3 "div_operator" "") 
+               (match_operand:XF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15657,10 +15675,10 @@
 	    (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
   "TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:XF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:XF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:XF 3 "div_operator" "") 
+               (match_operand:XF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15675,10 +15693,10 @@
 	    (match_operand 2 "nonimmediate_operand" "fm,0"))]))]
   "TARGET_80387"
   "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:XF 3 "mult_operator" "") 
+  [(set (attr "type")
+        (cond [(match_operand:XF 3 "mult_operator" "")
                  (const_string "fmul")
-               (match_operand:XF 3 "div_operator" "") 
+               (match_operand:XF 3 "div_operator" "")
                  (const_string "fdiv")
               ]
               (const_string "fop")))
@@ -15692,7 +15710,7 @@
   "TARGET_80387 && reload_completed
    && FLOAT_MODE_P (GET_MODE (operands[0]))"
   [(const_int 0)]
-{ 
+{
   operands[4] = ix86_force_to_memory (GET_MODE (operands[1]), operands[1]);
   operands[4] = gen_rtx_FLOAT (GET_MODE (operands[0]), operands[4]);
   emit_insn (gen_rtx_SET (VOIDmode, operands[0],
@@ -16105,7 +16123,7 @@
    (set_attr "mode" "XF")])
 
 ;; With sincos pattern defined, sin and cos builtin function will be
-;; expanded to sincos pattern with one of its outputs left unused. 
+;; expanded to sincos pattern with one of its outputs left unused.
 ;; Cse pass  will detected, if two sincos patterns can be combined,
 ;; otherwise sincos pattern will be split back to sin or cos pattern,
 ;; depending on the unused output.
@@ -17507,7 +17525,7 @@
   [(set_attr "type" "fpspc")
    (set_attr "mode" "DI")])
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "register_operand" "")
 	(unspec:DI [(match_operand:XF 1 "register_operand" "")]
 	 UNSPEC_FIST))
@@ -17519,7 +17537,7 @@
    (set (match_dup 0) (match_dup 2))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "memory_operand" "")
 	(unspec:DI [(match_operand:XF 1 "register_operand" "")]
 	 UNSPEC_FIST))
@@ -17570,7 +17588,7 @@
   [(set_attr "type" "fpspc")
    (set_attr "mode" "<MODE>")])
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "register_operand" "")
 	(unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
 	 UNSPEC_FIST))
@@ -17581,7 +17599,7 @@
    (set (match_dup 0) (match_dup 2))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "memory_operand" "")
 	(unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
 	 UNSPEC_FIST))
@@ -17744,7 +17762,7 @@
    (set_attr "i387_cw" "floor")
    (set_attr "mode" "DI")])
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "register_operand" "")
 	(unspec:DI [(match_operand:XF 1 "register_operand" "")]
 	 UNSPEC_FIST_FLOOR))
@@ -17760,7 +17778,7 @@
    (set (match_dup 0) (match_dup 4))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "memory_operand" "")
 	(unspec:DI [(match_operand:XF 1 "register_operand" "")]
 	 UNSPEC_FIST_FLOOR))
@@ -17802,7 +17820,7 @@
    (set_attr "i387_cw" "floor")
    (set_attr "mode" "<MODE>")])
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "register_operand" "")
 	(unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
 	 UNSPEC_FIST_FLOOR))
@@ -17817,7 +17835,7 @@
    (set (match_dup 0) (match_dup 4))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "memory_operand" "")
 	(unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
 	 UNSPEC_FIST_FLOOR))
@@ -17985,7 +18003,7 @@
    (set_attr "i387_cw" "ceil")
    (set_attr "mode" "DI")])
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "register_operand" "")
 	(unspec:DI [(match_operand:XF 1 "register_operand" "")]
 	 UNSPEC_FIST_CEIL))
@@ -18001,7 +18019,7 @@
    (set (match_dup 0) (match_dup 4))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:DI 0 "memory_operand" "")
 	(unspec:DI [(match_operand:XF 1 "register_operand" "")]
 	 UNSPEC_FIST_CEIL))
@@ -18043,7 +18061,7 @@
    (set_attr "i387_cw" "ceil")
    (set_attr "mode" "<MODE>")])
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "register_operand" "")
 	(unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
 	 UNSPEC_FIST_CEIL))
@@ -18058,7 +18076,7 @@
    (set (match_dup 0) (match_dup 4))]
   "")
 
-(define_split 
+(define_split
   [(set (match_operand:X87MODEI12 0 "memory_operand" "")
 	(unspec:X87MODEI12 [(match_operand:XF 1 "register_operand" "")]
 	 UNSPEC_FIST_CEIL))
@@ -18452,11 +18470,11 @@
 
 (define_insn "*rep_movdi_rex64"
   [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
-   (set (match_operand:DI 0 "register_operand" "=D") 
+   (set (match_operand:DI 0 "register_operand" "=D")
         (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
 			    (const_int 3))
 		 (match_operand:DI 3 "register_operand" "0")))
-   (set (match_operand:DI 1 "register_operand" "=S") 
+   (set (match_operand:DI 1 "register_operand" "=S")
         (plus:DI (ashift:DI (match_dup 5) (const_int 3))
 		 (match_operand:DI 4 "register_operand" "1")))
    (set (mem:BLK (match_dup 3))
@@ -18472,11 +18490,11 @@
 
 (define_insn "*rep_movsi"
   [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
-   (set (match_operand:SI 0 "register_operand" "=D") 
+   (set (match_operand:SI 0 "register_operand" "=D")
         (plus:SI (ashift:SI (match_operand:SI 5 "register_operand" "2")
 			    (const_int 2))
 		 (match_operand:SI 3 "register_operand" "0")))
-   (set (match_operand:SI 1 "register_operand" "=S") 
+   (set (match_operand:SI 1 "register_operand" "=S")
         (plus:SI (ashift:SI (match_dup 5) (const_int 2))
 		 (match_operand:SI 4 "register_operand" "1")))
    (set (mem:BLK (match_dup 3))
@@ -18492,11 +18510,11 @@
 
 (define_insn "*rep_movsi_rex64"
   [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
-   (set (match_operand:DI 0 "register_operand" "=D") 
+   (set (match_operand:DI 0 "register_operand" "=D")
         (plus:DI (ashift:DI (match_operand:DI 5 "register_operand" "2")
 			    (const_int 2))
 		 (match_operand:DI 3 "register_operand" "0")))
-   (set (match_operand:DI 1 "register_operand" "=S") 
+   (set (match_operand:DI 1 "register_operand" "=S")
         (plus:DI (ashift:DI (match_dup 5) (const_int 2))
 		 (match_operand:DI 4 "register_operand" "1")))
    (set (mem:BLK (match_dup 3))
@@ -18512,10 +18530,10 @@
 
 (define_insn "*rep_movqi"
   [(set (match_operand:SI 2 "register_operand" "=c") (const_int 0))
-   (set (match_operand:SI 0 "register_operand" "=D") 
+   (set (match_operand:SI 0 "register_operand" "=D")
         (plus:SI (match_operand:SI 3 "register_operand" "0")
 		 (match_operand:SI 5 "register_operand" "2")))
-   (set (match_operand:SI 1 "register_operand" "=S") 
+   (set (match_operand:SI 1 "register_operand" "=S")
         (plus:SI (match_operand:SI 4 "register_operand" "1") (match_dup 5)))
    (set (mem:BLK (match_dup 3))
 	(mem:BLK (match_dup 4)))
@@ -18530,10 +18548,10 @@
 
 (define_insn "*rep_movqi_rex64"
   [(set (match_operand:DI 2 "register_operand" "=c") (const_int 0))
-   (set (match_operand:DI 0 "register_operand" "=D") 
+   (set (match_operand:DI 0 "register_operand" "=D")
         (plus:DI (match_operand:DI 3 "register_operand" "0")
 		 (match_operand:DI 5 "register_operand" "2")))
-   (set (match_operand:DI 1 "register_operand" "=S") 
+   (set (match_operand:DI 1 "register_operand" "=S")
         (plus:DI (match_operand:DI 4 "register_operand" "1") (match_dup 5)))
    (set (mem:BLK (match_dup 3))
 	(mem:BLK (match_dup 4)))
@@ -18720,7 +18738,7 @@
 
 (define_insn "*rep_stosdi_rex64"
   [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
-   (set (match_operand:DI 0 "register_operand" "=D") 
+   (set (match_operand:DI 0 "register_operand" "=D")
         (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
 			    (const_int 3))
 		 (match_operand:DI 3 "register_operand" "0")))
@@ -18738,7 +18756,7 @@
 
 (define_insn "*rep_stossi"
   [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
-   (set (match_operand:SI 0 "register_operand" "=D") 
+   (set (match_operand:SI 0 "register_operand" "=D")
         (plus:SI (ashift:SI (match_operand:SI 4 "register_operand" "1")
 			    (const_int 2))
 		 (match_operand:SI 3 "register_operand" "0")))
@@ -18756,7 +18774,7 @@
 
 (define_insn "*rep_stossi_rex64"
   [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
-   (set (match_operand:DI 0 "register_operand" "=D") 
+   (set (match_operand:DI 0 "register_operand" "=D")
         (plus:DI (ashift:DI (match_operand:DI 4 "register_operand" "1")
 			    (const_int 2))
 		 (match_operand:DI 3 "register_operand" "0")))
@@ -18774,7 +18792,7 @@
 
 (define_insn "*rep_stosqi"
   [(set (match_operand:SI 1 "register_operand" "=c") (const_int 0))
-   (set (match_operand:SI 0 "register_operand" "=D") 
+   (set (match_operand:SI 0 "register_operand" "=D")
         (plus:SI (match_operand:SI 3 "register_operand" "0")
 		 (match_operand:SI 4 "register_operand" "1")))
    (set (mem:BLK (match_dup 3))
@@ -18791,7 +18809,7 @@
 
 (define_insn "*rep_stosqi_rex64"
   [(set (match_operand:DI 1 "register_operand" "=c") (const_int 0))
-   (set (match_operand:DI 0 "register_operand" "=D") 
+   (set (match_operand:DI 0 "register_operand" "=D")
         (plus:DI (match_operand:DI 3 "register_operand" "0")
 		 (match_operand:DI 4 "register_operand" "1")))
    (set (mem:BLK (match_dup 3))
@@ -19167,7 +19185,7 @@
 
 (define_insn "*movdicc_c_rex64"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
-	(if_then_else:DI (match_operator 1 "ix86_comparison_operator" 
+	(if_then_else:DI (match_operator 1 "ix86_comparison_operator"
 				[(reg FLAGS_REG) (const_int 0)])
 		      (match_operand:DI 2 "nonimmediate_operand" "rm,0")
 		      (match_operand:DI 3 "nonimmediate_operand" "0,rm")))]
@@ -19210,7 +19228,7 @@
 
 (define_insn "*movsicc_noc"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(if_then_else:SI (match_operator 1 "ix86_comparison_operator" 
+	(if_then_else:SI (match_operator 1 "ix86_comparison_operator"
 				[(reg FLAGS_REG) (const_int 0)])
 		      (match_operand:SI 2 "nonimmediate_operand" "rm,0")
 		      (match_operand:SI 3 "nonimmediate_operand" "0,rm")))]
@@ -19232,7 +19250,7 @@
 
 (define_insn "*movhicc_noc"
   [(set (match_operand:HI 0 "register_operand" "=r,r")
-	(if_then_else:HI (match_operator 1 "ix86_comparison_operator" 
+	(if_then_else:HI (match_operator 1 "ix86_comparison_operator"
 				[(reg FLAGS_REG) (const_int 0)])
 		      (match_operand:HI 2 "nonimmediate_operand" "rm,0")
 		      (match_operand:HI 3 "nonimmediate_operand" "0,rm")))]
@@ -19254,7 +19272,7 @@
 
 (define_insn_and_split "*movqicc_noc"
   [(set (match_operand:QI 0 "register_operand" "=r,r")
-	(if_then_else:QI (match_operator 1 "ix86_comparison_operator" 
+	(if_then_else:QI (match_operator 1 "ix86_comparison_operator"
 				[(match_operand 4 "flags_reg_operand" "")
 				 (const_int 0)])
 		      (match_operand:QI 2 "register_operand" "r,0")
@@ -19282,7 +19300,7 @@
 
 (define_insn "*movsfcc_1_387"
   [(set (match_operand:SF 0 "register_operand" "=f,f,r,r")
-	(if_then_else:SF (match_operator 1 "fcmov_comparison_operator" 
+	(if_then_else:SF (match_operator 1 "fcmov_comparison_operator"
 				[(reg FLAGS_REG) (const_int 0)])
 		      (match_operand:SF 2 "nonimmediate_operand" "f,0,rm,0")
 		      (match_operand:SF 3 "nonimmediate_operand" "0,f,0,rm")))]
@@ -19306,7 +19324,7 @@
 
 (define_insn "*movdfcc_1"
   [(set (match_operand:DF 0 "register_operand" "=f,f,&r,&r")
-	(if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 
+	(if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
 				[(reg FLAGS_REG) (const_int 0)])
 		      (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
 		      (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
@@ -19322,7 +19340,7 @@
 
 (define_insn "*movdfcc_1_rex64"
   [(set (match_operand:DF 0 "register_operand" "=f,f,r,r")
-	(if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 
+	(if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
 				[(reg FLAGS_REG) (const_int 0)])
 		      (match_operand:DF 2 "nonimmediate_operand" "f,0,rm,0")
 		      (match_operand:DF 3 "nonimmediate_operand" "0,f,0,rm")))]
@@ -19338,7 +19356,7 @@
 
 (define_split
   [(set (match_operand:DF 0 "register_and_not_any_fp_reg_operand" "")
-	(if_then_else:DF (match_operator 1 "fcmov_comparison_operator" 
+	(if_then_else:DF (match_operator 1 "fcmov_comparison_operator"
 				[(match_operand 4 "flags_reg_operand" "")
 				 (const_int 0)])
 		      (match_operand:DF 2 "nonimmediate_operand" "")
@@ -19366,7 +19384,7 @@
 
 (define_insn "*movxfcc_1"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
-	(if_then_else:XF (match_operator 1 "fcmov_comparison_operator" 
+	(if_then_else:XF (match_operator 1 "fcmov_comparison_operator"
 				[(reg FLAGS_REG) (const_int 0)])
 		      (match_operand:XF 2 "register_operand" "f,0")
 		      (match_operand:XF 3 "register_operand" "0,f")))]
@@ -19528,7 +19546,7 @@
 
 ;; This pattern exists to put a dependency on all ebp-based memory accesses.
 ;; Otherwise there will be nothing to keep
-;; 
+;;
 ;; [(set (reg ebp) (reg esp))]
 ;; [(set (reg esp) (plus (reg esp) (const_int -160000)))
 ;;  (clobber (eflags)]
@@ -19720,7 +19738,7 @@
       && INTVAL (operands[1]) < CHECK_STACK_LIMIT)
     emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
 			   operands[1]));
-  else 
+  else
 #endif
     emit_insn (gen_allocate_stack_worker (copy_to_mode_reg (SImode,
 							    operands[1])));
@@ -19760,12 +19778,12 @@
 	    (match_operand 2 "aligned_operand" "")]))
    (clobber (reg:CC FLAGS_REG))]
   "! TARGET_PARTIAL_REG_STALL && reload_completed
-   && ((GET_MODE (operands[0]) == HImode 
+   && ((GET_MODE (operands[0]) == HImode
 	&& ((!optimize_size && !TARGET_FAST_PREFIX)
             /* ??? next two lines just !satisfies_constraint_K (...) */
 	    || GET_CODE (operands[2]) != CONST_INT
 	    || satisfies_constraint_K (operands[2])))
-       || (GET_MODE (operands[0]) == QImode 
+       || (GET_MODE (operands[0]) == QImode
 	   && (TARGET_PROMOTE_QImode || optimize_size)))"
   [(parallel [(set (match_dup 0)
 		   (match_op_dup 3 [(match_dup 1) (match_dup 2)]))
@@ -19838,7 +19856,7 @@
    (clobber (reg:CC FLAGS_REG))]
   "! TARGET_PARTIAL_REG_STALL && reload_completed
    && (GET_MODE (operands[0]) == HImode
-       || (GET_MODE (operands[0]) == QImode 
+       || (GET_MODE (operands[0]) == QImode
 	   && (TARGET_PROMOTE_QImode || optimize_size)))"
   [(parallel [(set (match_dup 0)
 		   (neg:SI (match_dup 1)))
@@ -19851,29 +19869,29 @@
 	(not (match_operand 1 "register_operand" "")))]
   "! TARGET_PARTIAL_REG_STALL && reload_completed
    && (GET_MODE (operands[0]) == HImode
-       || (GET_MODE (operands[0]) == QImode 
+       || (GET_MODE (operands[0]) == QImode
 	   && (TARGET_PROMOTE_QImode || optimize_size)))"
   [(set (match_dup 0)
 	(not:SI (match_dup 1)))]
   "operands[0] = gen_lowpart (SImode, operands[0]);
    operands[1] = gen_lowpart (SImode, operands[1]);")
 
-(define_split 
+(define_split
   [(set (match_operand 0 "register_operand" "")
-	(if_then_else (match_operator 1 "comparison_operator" 
+	(if_then_else (match_operator 1 "comparison_operator"
 				[(reg FLAGS_REG) (const_int 0)])
 		      (match_operand 2 "register_operand" "")
 		      (match_operand 3 "register_operand" "")))]
   "! TARGET_PARTIAL_REG_STALL && TARGET_CMOVE
    && (GET_MODE (operands[0]) == HImode
-       || (GET_MODE (operands[0]) == QImode 
+       || (GET_MODE (operands[0]) == QImode
 	   && (TARGET_PROMOTE_QImode || optimize_size)))"
   [(set (match_dup 0)
 	(if_then_else:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
   "operands[0] = gen_lowpart (SImode, operands[0]);
    operands[2] = gen_lowpart (SImode, operands[2]);
    operands[3] = gen_lowpart (SImode, operands[3]);")
-			
+
 
 ;; RTL Peephole optimizations, run before sched2.  These primarily look to
 ;; transform a complex memory operation into two memory to register operations.
@@ -20018,7 +20036,7 @@
    (set (match_dup 0) (match_op_dup 1 [(match_dup 3) (const_int 0)]))]
   "")
 
-;; NOT is not pairable on Pentium, while XOR is, but one byte longer. 
+;; NOT is not pairable on Pentium, while XOR is, but one byte longer.
 ;; Don't split NOTs with a displacement operand, because resulting XOR
 ;; will not be pairable anyway.
 ;;
@@ -20034,7 +20052,7 @@
 	(not:SI (match_operand:SI 1 "nonimmediate_operand" "")))]
   "!optimize_size
    && peep2_regno_dead_p (0, FLAGS_REG)
-   && ((TARGET_PENTIUM 
+   && ((TARGET_PENTIUM
         && (GET_CODE (operands[0]) != MEM
             || !memory_displacement_operand (operands[0], SImode)))
        || (TARGET_K6 && long_memory_operand (operands[0], SImode)))"
@@ -20048,7 +20066,7 @@
 	(not:HI (match_operand:HI 1 "nonimmediate_operand" "")))]
   "!optimize_size
    && peep2_regno_dead_p (0, FLAGS_REG)
-   && ((TARGET_PENTIUM 
+   && ((TARGET_PENTIUM
         && (GET_CODE (operands[0]) != MEM
             || !memory_displacement_operand (operands[0], HImode)))
        || (TARGET_K6 && long_memory_operand (operands[0], HImode)))"
@@ -20062,7 +20080,7 @@
 	(not:QI (match_operand:QI 1 "nonimmediate_operand" "")))]
   "!optimize_size
    && peep2_regno_dead_p (0, FLAGS_REG)
-   && ((TARGET_PENTIUM 
+   && ((TARGET_PENTIUM
         && (GET_CODE (operands[0]) != MEM
             || !memory_displacement_operand (operands[0], QImode)))
        || (TARGET_K6 && long_memory_operand (operands[0], QImode)))"
@@ -20143,7 +20161,7 @@
 	      (set (zero_extract:SI (match_dup 2)
 				    (const_int 8)
 				    (const_int 8))
-		   (and:SI 
+		   (and:SI
 		     (zero_extract:SI
 		       (match_dup 2)
 		       (const_int 8)
@@ -20245,7 +20263,7 @@
   [(set (match_operand 0 "register_operand" "")
 	(const_int -1))]
   "(GET_MODE (operands[0]) == HImode
-    || GET_MODE (operands[0]) == SImode 
+    || GET_MODE (operands[0]) == SImode
     || (GET_MODE (operands[0]) == DImode && TARGET_64BIT))
    && (optimize_size || TARGET_PENTIUM)
    && peep2_regno_dead_p (0, FLAGS_REG)"
@@ -20601,7 +20619,7 @@
           (mult:SI (match_operand:SI 1 "nonimmediate_operand" "")
                    (match_operand:SI 2 "const_int_operand" "")))
      (clobber (reg:CC FLAGS_REG))])]
-  "!optimize_size 
+  "!optimize_size
    && (INTVAL (operands[2]) == 3
        || INTVAL (operands[2]) == 5
        || INTVAL (operands[2]) == 9)"
@@ -20633,7 +20651,7 @@
                    (match_operand:DI 2 "const_int_operand" "")))
      (clobber (reg:CC FLAGS_REG))])]
   "TARGET_64BIT
-   && !optimize_size 
+   && !optimize_size
    && (INTVAL (operands[2]) == 3
        || INTVAL (operands[2]) == 5
        || INTVAL (operands[2]) == 9)"
@@ -20764,7 +20782,7 @@
    && ((!TARGET_PARTIAL_REG_STALL
 	&& (GET_MODE (operands[0]) == QImode
 	    || GET_MODE (operands[0]) == HImode))
-       || GET_MODE (operands[0]) == SImode 
+       || GET_MODE (operands[0]) == SImode
        || (TARGET_64BIT && GET_MODE (operands[0]) == DImode))
    /* We reorder load and the shift.  */
    && !rtx_equal_p (operands[1], operands[3])
@@ -20913,7 +20931,7 @@
   [(set_attr "type" "callv")])
 
 ;; We used to use "int $5", in honor of #BR which maps to interrupt vector 5.
-;; That, however, is usually mapped by the OS to SIGSEGV, which is often 
+;; That, however, is usually mapped by the OS to SIGSEGV, which is often
 ;; caught for use by garbage collectors and the like.  Using an insn that
 ;; maps to SIGILL makes it more likely the program will rightfully die.
 ;; Keeping with tradition, "6" is in honor of #UD.
@@ -21021,7 +21039,7 @@
   int locality = INTVAL (operands[1]);
   gcc_assert (locality >= 0 && locality <= 3);
 
-  return patterns[locality];  
+  return patterns[locality];
 }
   [(set_attr "type" "sse")
    (set_attr "memory" "none")])
@@ -21039,7 +21057,7 @@
   int locality = INTVAL (operands[1]);
   gcc_assert (locality >= 0 && locality <= 3);
 
-  return patterns[locality];  
+  return patterns[locality];
 }
   [(set_attr "type" "sse")
    (set_attr "memory" "none")])
diff --git a/contrib/gcc/config/i386/nto.h b/contrib/gcc/config/i386/nto.h
index 1095a63..42ae556 100644
--- a/contrib/gcc/config/i386/nto.h
+++ b/contrib/gcc/config/i386/nto.h
@@ -43,7 +43,7 @@ Boston, MA 02110-1301, USA.  */
 #undef THREAD_MODEL_SPEC
 #define THREAD_MODEL_SPEC "posix"
 
-#ifdef CROSS_COMPILE
+#ifdef CROSS_DIRECTORY_STRUCTURE
 #define SYSROOT_SUFFIX_SPEC "x86"
 #endif