Revert r236962 - Experimental amdfam10/barcelona support.

The patches are unexpectedly causing gcc to fail while
building ports/graphics/ImageMagick even when the cpu
flags are not used.

Reported by:	Andreas Tobler

1 files changed, 52 insertions, 308 deletions

diff --git a/contrib/gcc/config/i386/i386.md b/contrib/gcc/config/i386/i386.md
index e0b0d0c..bd81c4a 100644
--- a/contrib/gcc/config/i386/i386.md
+++ b/contrib/gcc/config/i386/i386.md
@@ -104,7 +104,7 @@
    (UNSPEC_MFENCE		44)
    (UNSPEC_LFENCE		45)
    (UNSPEC_PSADBW		46)
-   (UNSPEC_LDDQU		47)
+   (UNSPEC_LDQQU		47)
 
    ; Generic math support
    (UNSPEC_COPYSIGN		50)
@@ -153,12 +153,6 @@
    (UNSPEC_PSHUFB		120)
    (UNSPEC_PSIGN		121)
    (UNSPEC_PALIGNR		122)
-
-   ; For SSE4A support
-   (UNSPEC_EXTRQI               130)
-   (UNSPEC_EXTRQ                131)   
-   (UNSPEC_INSERTQI             132)
-   (UNSPEC_INSERTQ              133)
   ])
 
 (define_constants
@@ -184,9 +178,7 @@
    (SP_REG			 7)
    (FLAGS_REG			17)
    (FPSR_REG			18)
-   (FPCR_REG			19)
-   (DIRFLAG_REG			20)
-   (R11_REG			41)
+   (DIRFLAG_REG			19)
   ])
 
 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
@@ -200,8 +192,7 @@
 
 ;; Processor type.  This attribute must exactly match the processor_type
 ;; enumeration in i386.h.
-(define_attr "cpu" "i386,i486,pentium,pentiumpro,geode,k6,athlon,pentium4,k8,
-                    nocona,core2,generic32,generic64,amdfam10"
+(define_attr "cpu" "i386,i486,pentium,pentiumpro,geode,k6,athlon,pentium4,k8,nocona,core2,generic32,generic64"
   (const (symbol_ref "ix86_tune")))
 
 ;; A basic instruction type.  Refinements due to arguments to be
@@ -212,10 +203,10 @@
    incdec,ishift,ishift1,rotate,rotate1,imul,idiv,
    icmp,test,ibr,setcc,icmov,
    push,pop,call,callv,leave,
-   str,,bitmanip,cld,
+   str,cld,
    fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint,
    sselog,sselog1,sseiadd,sseishft,sseimul,
-   sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,sseins,
+   sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,
    mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft"
   (const_string "other"))
 
@@ -229,7 +220,7 @@
   (cond [(eq_attr "type" "fmov,fop,fsgn,fmul,fdiv,fpspc,fcmov,fcmp,fxch,fistp,fisttp,frndint")
 	   (const_string "i387")
 	 (eq_attr "type" "sselog,sselog1,sseiadd,sseishft,sseimul,
-			  sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv,sseins")
+			  sse,ssemov,sseadd,ssemul,ssecmp,ssecomi,ssecvt,sseicvt,ssediv")
 	   (const_string "sse")
 	 (eq_attr "type" "mmx,mmxmov,mmxadd,mmxmul,mmxcmp,mmxcvt,mmxshft")
 	   (const_string "mmx")
@@ -239,8 +230,7 @@
 
 ;; The (bounding maximum) length of an instruction immediate.
 (define_attr "length_immediate" ""
-  (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave,
-                          bitmanip")
+  (cond [(eq_attr "type" "incdec,setcc,icmov,str,cld,lea,other,multi,idiv,leave")
 	   (const_int 0)
 	 (eq_attr "unit" "i387,sse,mmx")
 	   (const_int 0)
@@ -294,7 +284,7 @@
 ;; Set when 0f opcode prefix is used.
 (define_attr "prefix_0f" ""
   (if_then_else 
-    (ior (eq_attr "type" "imovx,setcc,icmov,bitmanip")
+    (ior (eq_attr "type" "imovx,setcc,icmov")
 	 (eq_attr "unit" "sse,mmx"))
     (const_int 1)
     (const_int 0)))
@@ -423,7 +413,7 @@
 	   (const_string "load")
 	 (and (eq_attr "type"
 		 "!alu1,negnot,ishift1,
-		   imov,imovx,icmp,test,bitmanip,
+		   imov,imovx,icmp,test,
 		   fmov,fcmp,fsgn,
 		   sse,ssemov,ssecmp,ssecomi,ssecvt,sseicvt,sselog1,
 		   mmx,mmxmov,mmxcmp,mmxcvt")
@@ -978,11 +968,10 @@
   "sahf"
   [(set_attr "length" "1")
    (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "direct")
    (set_attr "mode" "SI")])
 
 ;; Pentium Pro can do steps 1 through 3 in one go.
-;; comi*, ucomi*, fcomi*, ficomi*,fucomi* (i387 instructions set condition codes) 
+
 (define_insn "*cmpfp_i_mixed"
   [(set (reg:CCFP FLAGS_REG)
 	(compare:CCFP (match_operand 0 "register_operand" "f,x")
@@ -996,8 +985,7 @@
      (if_then_else (match_operand:SF 1 "" "")
         (const_string "SF")
         (const_string "DF")))
-   (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "direct")])
+   (set_attr "athlon_decode" "vector")])
 
 (define_insn "*cmpfp_i_sse"
   [(set (reg:CCFP FLAGS_REG)
@@ -1012,8 +1000,7 @@
      (if_then_else (match_operand:SF 1 "" "")
         (const_string "SF")
         (const_string "DF")))
-   (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "direct")])
+   (set_attr "athlon_decode" "vector")])
 
 (define_insn "*cmpfp_i_i387"
   [(set (reg:CCFP FLAGS_REG)
@@ -1032,8 +1019,7 @@
 	      (const_string "DF")
 	   ]
 	   (const_string "XF")))
-   (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "direct")])
+   (set_attr "athlon_decode" "vector")])
 
 (define_insn "*cmpfp_iu_mixed"
   [(set (reg:CCFPU FLAGS_REG)
@@ -1048,8 +1034,7 @@
      (if_then_else (match_operand:SF 1 "" "")
         (const_string "SF")
         (const_string "DF")))
-   (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "direct")])
+   (set_attr "athlon_decode" "vector")])
 
 (define_insn "*cmpfp_iu_sse"
   [(set (reg:CCFPU FLAGS_REG)
@@ -1064,8 +1049,7 @@
      (if_then_else (match_operand:SF 1 "" "")
         (const_string "SF")
         (const_string "DF")))
-   (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "direct")])
+   (set_attr "athlon_decode" "vector")])
 
 (define_insn "*cmpfp_iu_387"
   [(set (reg:CCFPU FLAGS_REG)
@@ -1084,8 +1068,7 @@
 	      (const_string "DF")
 	   ]
 	   (const_string "XF")))
-   (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "direct")])
+   (set_attr "athlon_decode" "vector")])
 
 ;; Move instructions.
 
@@ -1291,8 +1274,7 @@
   [(set_attr "type" "imov")
    (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
-   (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "double")])   
+   (set_attr "athlon_decode" "vector")])
 
 (define_expand "movhi"
   [(set (match_operand:HI 0 "nonimmediate_operand" "")
@@ -1409,10 +1391,8 @@
   [(set_attr "type" "imov")
    (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
-   (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "double")])   
+   (set_attr "athlon_decode" "vector")])
 
-;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10
 (define_insn "*swaphi_2"
   [(set (match_operand:HI 0 "register_operand" "+r")
 	(match_operand:HI 1 "register_operand" "+r"))
@@ -1585,10 +1565,8 @@
   [(set_attr "type" "imov")
    (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
-   (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "athlon_decode" "vector")])
 
-;; Not added amdfam10_decode since TARGET_PARTIAL_REG_STALL is disabled for AMDFAM10
 (define_insn "*swapqi_2"
   [(set (match_operand:QI 0 "register_operand" "+q")
 	(match_operand:QI 1 "register_operand" "+q"))
@@ -2142,8 +2120,7 @@
   [(set_attr "type" "imov")
    (set_attr "mode" "DI")
    (set_attr "pent_pair" "np")
-   (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "double")])   
+   (set_attr "athlon_decode" "vector")])
 
 (define_expand "movti"
   [(set (match_operand:TI 0 "nonimmediate_operand" "")
@@ -4173,8 +4150,7 @@
   "cvttss2si{q}\t{%1, %0|%0, %1}"
   [(set_attr "type" "sseicvt")
    (set_attr "mode" "SF")
-   (set_attr "athlon_decode" "double,vector")
-   (set_attr "amdfam10_decode" "double,double")])
+   (set_attr "athlon_decode" "double,vector")])
 
 (define_insn "fix_truncdfdi_sse"
   [(set (match_operand:DI 0 "register_operand" "=r,r")
@@ -4183,8 +4159,7 @@
   "cvttsd2si{q}\t{%1, %0|%0, %1}"
   [(set_attr "type" "sseicvt")
    (set_attr "mode" "DF")
-   (set_attr "athlon_decode" "double,vector")
-   (set_attr "amdfam10_decode" "double,double")])
+   (set_attr "athlon_decode" "double,vector")])
 
 (define_insn "fix_truncsfsi_sse"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -4193,8 +4168,7 @@
   "cvttss2si\t{%1, %0|%0, %1}"
   [(set_attr "type" "sseicvt")
    (set_attr "mode" "DF")
-   (set_attr "athlon_decode" "double,vector")
-   (set_attr "amdfam10_decode" "double,double")])
+   (set_attr "athlon_decode" "double,vector")])
 
 (define_insn "fix_truncdfsi_sse"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -4203,8 +4177,7 @@
   "cvttsd2si\t{%1, %0|%0, %1}"
   [(set_attr "type" "sseicvt")
    (set_attr "mode" "DF")
-   (set_attr "athlon_decode" "double,vector")
-   (set_attr "amdfam10_decode" "double,double")])
+   (set_attr "athlon_decode" "double,vector")])
 
 ;; Avoid vector decoded forms of the instruction.
 (define_peephole2
@@ -4450,7 +4423,7 @@
 
 (define_insn "x86_fnstcw_1"
   [(set (match_operand:HI 0 "memory_operand" "=m")
-	(unspec:HI [(reg:HI FPCR_REG)] UNSPEC_FSTCW))]
+	(unspec:HI [(reg:HI FPSR_REG)] UNSPEC_FSTCW))]
   "TARGET_80387"
   "fnstcw\t%0"
   [(set_attr "length" "2")
@@ -4458,15 +4431,14 @@
    (set_attr "unit" "i387")])
 
 (define_insn "x86_fldcw_1"
-  [(set (reg:HI FPCR_REG)
+  [(set (reg:HI FPSR_REG)
 	(unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
   "TARGET_80387"
   "fldcw\t%0"
   [(set_attr "length" "2")
    (set_attr "mode" "HI")
    (set_attr "unit" "i387")
-   (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "athlon_decode" "vector")])
 
 ;; Conversion between fixed point and floating point.
 
@@ -4517,7 +4489,6 @@
    (set_attr "mode" "SF")
    (set_attr "unit" "*,i387,*,*")
    (set_attr "athlon_decode" "*,*,vector,double")
-   (set_attr "amdfam10_decode" "*,*,vector,double")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "*floatsisf2_sse"
@@ -4528,7 +4499,6 @@
   [(set_attr "type" "sseicvt")
    (set_attr "mode" "SF")
    (set_attr "athlon_decode" "vector,double")
-   (set_attr "amdfam10_decode" "vector,double")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "*floatsisf2_i387"
@@ -4562,7 +4532,6 @@
    (set_attr "mode" "SF")
    (set_attr "unit" "*,i387,*,*")
    (set_attr "athlon_decode" "*,*,vector,double")
-   (set_attr "amdfam10_decode" "*,*,vector,double")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "*floatdisf2_sse"
@@ -4573,7 +4542,6 @@
   [(set_attr "type" "sseicvt")
    (set_attr "mode" "SF")
    (set_attr "athlon_decode" "vector,double")
-   (set_attr "amdfam10_decode" "vector,double")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "*floatdisf2_i387"
@@ -4632,7 +4600,6 @@
    (set_attr "mode" "DF")
    (set_attr "unit" "*,i387,*,*")
    (set_attr "athlon_decode" "*,*,double,direct")
-   (set_attr "amdfam10_decode" "*,*,vector,double")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "*floatsidf2_sse"
@@ -4643,7 +4610,6 @@
   [(set_attr "type" "sseicvt")
    (set_attr "mode" "DF")
    (set_attr "athlon_decode" "double,direct")
-   (set_attr "amdfam10_decode" "vector,double")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "*floatsidf2_i387"
@@ -4677,7 +4643,6 @@
    (set_attr "mode" "DF")
    (set_attr "unit" "*,i387,*,*")
    (set_attr "athlon_decode" "*,*,double,direct")
-   (set_attr "amdfam10_decode" "*,*,vector,double")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "*floatdidf2_sse"
@@ -4688,7 +4653,6 @@
   [(set_attr "type" "sseicvt")
    (set_attr "mode" "DF")
    (set_attr "athlon_decode" "double,direct")
-   (set_attr "amdfam10_decode" "vector,double")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "*floatdidf2_i387"
@@ -6896,14 +6860,6 @@
   "TARGET_64BIT"
   "")
 
-;; On AMDFAM10 
-;; IMUL reg64, reg64, imm8 	Direct
-;; IMUL reg64, mem64, imm8 	VectorPath
-;; IMUL reg64, reg64, imm32 	Direct
-;; IMUL reg64, mem64, imm32 	VectorPath 
-;; IMUL reg64, reg64 		Direct
-;; IMUL reg64, mem64 		Direct
-
 (define_insn "*muldi3_1_rex64"
   [(set (match_operand:DI 0 "register_operand" "=r,r,r")
 	(mult:DI (match_operand:DI 1 "nonimmediate_operand" "%rm,rm,0")
@@ -6926,11 +6882,6 @@
 		    (match_operand 1 "memory_operand" ""))
 		  (const_string "vector")]
 	      (const_string "direct")))
-   (set (attr "amdfam10_decode")
-	(cond [(and (eq_attr "alternative" "0,1")
-		    (match_operand 1 "memory_operand" ""))
-		  (const_string "vector")]
-	      (const_string "direct")))	      
    (set_attr "mode" "DI")])
 
 (define_expand "mulsi3"
@@ -6941,14 +6892,6 @@
   ""
   "")
 
-;; On AMDFAM10 
-;; IMUL reg32, reg32, imm8 	Direct
-;; IMUL reg32, mem32, imm8 	VectorPath
-;; IMUL reg32, reg32, imm32 	Direct
-;; IMUL reg32, mem32, imm32 	VectorPath
-;; IMUL reg32, reg32 		Direct
-;; IMUL reg32, mem32 		Direct
-
 (define_insn "*mulsi3_1"
   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
 	(mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
@@ -6970,11 +6913,6 @@
 		    (match_operand 1 "memory_operand" ""))
 		  (const_string "vector")]
 	      (const_string "direct")))
-   (set (attr "amdfam10_decode")
-	(cond [(and (eq_attr "alternative" "0,1")
-		    (match_operand 1 "memory_operand" ""))
-		  (const_string "vector")]
-	      (const_string "direct")))	      
    (set_attr "mode" "SI")])
 
 (define_insn "*mulsi3_1_zext"
@@ -7000,11 +6938,6 @@
 		    (match_operand 1 "memory_operand" ""))
 		  (const_string "vector")]
 	      (const_string "direct")))
-   (set (attr "amdfam10_decode")
-	(cond [(and (eq_attr "alternative" "0,1")
-		    (match_operand 1 "memory_operand" ""))
-		  (const_string "vector")]
-	      (const_string "direct")))	      
    (set_attr "mode" "SI")])
 
 (define_expand "mulhi3"
@@ -7015,13 +6948,6 @@
   "TARGET_HIMODE_MATH"
   "")
 
-;; On AMDFAM10
-;; IMUL reg16, reg16, imm8 	VectorPath
-;; IMUL reg16, mem16, imm8 	VectorPath
-;; IMUL reg16, reg16, imm16 	VectorPath
-;; IMUL reg16, mem16, imm16 	VectorPath
-;; IMUL reg16, reg16 		Direct
-;; IMUL reg16, mem16 		Direct
 (define_insn "*mulhi3_1"
   [(set (match_operand:HI 0 "register_operand" "=r,r,r")
 	(mult:HI (match_operand:HI 1 "nonimmediate_operand" "%rm,rm,0")
@@ -7040,10 +6966,6 @@
 	       (eq_attr "alternative" "1,2")
 		  (const_string "vector")]
 	      (const_string "direct")))
-   (set (attr "amdfam10_decode")
-	(cond [(eq_attr "alternative" "0,1")
-		  (const_string "vector")]
-	      (const_string "direct")))
    (set_attr "mode" "HI")])
 
 (define_expand "mulqi3"
@@ -7054,10 +6976,6 @@
   "TARGET_QIMODE_MATH"
   "")
 
-;;On AMDFAM10
-;; MUL reg8 	Direct
-;; MUL mem8 	Direct
-
 (define_insn "*mulqi3_1"
   [(set (match_operand:QI 0 "register_operand" "=a")
 	(mult:QI (match_operand:QI 1 "nonimmediate_operand" "%0")
@@ -7072,7 +6990,6 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "direct")))
-   (set_attr "amdfam10_decode" "direct")        
    (set_attr "mode" "QI")])
 
 (define_expand "umulqihi3"
@@ -7099,7 +7016,6 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "direct")))
-   (set_attr "amdfam10_decode" "direct")        
    (set_attr "mode" "QI")])
 
 (define_expand "mulqihi3"
@@ -7124,7 +7040,6 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "direct")))
-   (set_attr "amdfam10_decode" "direct")        
    (set_attr "mode" "QI")])
 
 (define_expand "umulditi3"
@@ -7151,7 +7066,6 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")        
    (set_attr "mode" "DI")])
 
 ;; We can't use this pattern in 64bit mode, since it results in two separate 32bit registers
@@ -7179,7 +7093,6 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")        
    (set_attr "mode" "SI")])
 
 (define_expand "mulditi3"
@@ -7206,7 +7119,6 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")
    (set_attr "mode" "DI")])
 
 (define_expand "mulsidi3"
@@ -7233,7 +7145,6 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")        
    (set_attr "mode" "SI")])
 
 (define_expand "umuldi3_highpart"
@@ -7270,7 +7181,6 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")        
    (set_attr "mode" "DI")])
 
 (define_expand "umulsi3_highpart"
@@ -7306,7 +7216,6 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")
    (set_attr "mode" "SI")])
 
 (define_insn "*umulsi3_highpart_zext"
@@ -7329,7 +7238,6 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")
    (set_attr "mode" "SI")])
 
 (define_expand "smuldi3_highpart"
@@ -7365,7 +7273,6 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")
    (set_attr "mode" "DI")])
 
 (define_expand "smulsi3_highpart"
@@ -7400,7 +7307,6 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")
    (set_attr "mode" "SI")])
 
 (define_insn "*smulsi3_highpart_zext"
@@ -7422,7 +7328,6 @@
      (if_then_else (eq_attr "cpu" "athlon")
         (const_string "vector")
         (const_string "double")))
-   (set_attr "amdfam10_decode" "double")
    (set_attr "mode" "SI")])
 
 ;; The patterns that match these are at the end of this file.
@@ -10404,8 +10309,7 @@
   [(set_attr "type" "ishift")
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "DI")
-   (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "athlon_decode" "vector")])
 
 (define_expand "x86_64_shift_adj"
   [(set (reg:CCZ FLAGS_REG)
@@ -10620,8 +10524,7 @@
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "SI")
    (set_attr "pent_pair" "np")
-   (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "athlon_decode" "vector")])
 
 (define_expand "x86_shift_adj_1"
   [(set (reg:CCZ FLAGS_REG)
@@ -11381,8 +11284,7 @@
   [(set_attr "type" "ishift")
    (set_attr "prefix_0f" "1")
    (set_attr "mode" "DI")
-   (set_attr "athlon_decode" "vector")
-   (set_attr "amdfam10_decode" "vector")])   
+   (set_attr "athlon_decode" "vector")])
 
 (define_expand "ashrdi3"
   [(set (match_operand:DI 0 "shiftdi_operand" "")
@@ -14254,7 +14156,7 @@
   [(set_attr "type" "call")])
 
 (define_insn "*sibcall_1_rex64_v"
-  [(call (mem:QI (reg:DI R11_REG))
+  [(call (mem:QI (reg:DI 40))
 	 (match_operand 0 "" ""))]
   "SIBLING_CALL_P (insn) && TARGET_64BIT"
   "jmp\t*%%r11"
@@ -14656,23 +14558,7 @@
      [(set (match_dup 0) (xor:SI (match_dup 0) (const_int 31)))
       (clobber (reg:CC FLAGS_REG))])]
   ""
-{
-  if (TARGET_ABM)
-    {
-      emit_insn (gen_clzsi2_abm (operands[0], operands[1]));
-      DONE;
-    }
-})
-
-(define_insn "clzsi2_abm"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-        (clz:SI (match_operand:SI 1 "nonimmediate_operand" "")))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_ABM"
-  "lzcnt{l}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_rep" "1")
-   (set_attr "type" "bitmanip")
-   (set_attr "mode" "SI")])
+  "")
 
 (define_insn "*bsr"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -14681,44 +14567,7 @@
    (clobber (reg:CC FLAGS_REG))]
   ""
   "bsr{l}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_0f" "1")
-   (set_attr "mode" "SI")])
-
-(define_insn "popcountsi2"
-  [(set (match_operand:SI 0 "register_operand" "=r")
-	(popcount:SI (match_operand:SI 1 "nonimmediate_operand" "")))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_POPCNT"
-  "popcnt{l}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_rep" "1")
-   (set_attr "type" "bitmanip")
-   (set_attr "mode" "SI")])
-
-(define_insn "*popcountsi2_cmp"
-  [(set (reg FLAGS_REG)
-	(compare
-	  (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))
-	  (const_int 0)))
-   (set (match_operand:SI 0 "register_operand" "=r")
-	(popcount:SI (match_dup 1)))]
-  "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
-  "popcnt{l}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_rep" "1")
-   (set_attr "type" "bitmanip")
-   (set_attr "mode" "SI")])
-
-(define_insn "*popcountsi2_cmp_zext"
-  [(set (reg FLAGS_REG)
-        (compare
-          (popcount:SI (match_operand:SI 1 "nonimmediate_operand" "rm"))
-          (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-        (zero_extend:DI(popcount:SI (match_dup 1))))]
-  "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
-  "popcnt{l}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_rep" "1")
-   (set_attr "type" "bitmanip")
-   (set_attr "mode" "SI")])
+  [(set_attr "prefix_0f" "1")])
 
 (define_expand "clzdi2"
   [(parallel
@@ -14730,23 +14579,7 @@
      [(set (match_dup 0) (xor:DI (match_dup 0) (const_int 63)))
       (clobber (reg:CC FLAGS_REG))])]
   "TARGET_64BIT"
-{
-  if (TARGET_ABM)
-    {
-      emit_insn (gen_clzdi2_abm (operands[0], operands[1]));
-      DONE;
-    }
-})
-
-(define_insn "clzdi2_abm"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(clz:DI (match_operand:DI 1 "nonimmediate_operand" "")))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && TARGET_ABM"
-  "lzcnt{q}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_rep" "1")
-   (set_attr "type" "bitmanip")
-   (set_attr "mode" "DI")])
+  "")
 
 (define_insn "*bsr_rex64"
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -14755,92 +14588,7 @@
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT"
   "bsr{q}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_0f" "1")
-   (set_attr "mode" "DI")])
-
-(define_insn "popcountdi2"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-	(popcount:DI (match_operand:DI 1 "nonimmediate_operand" "")))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_64BIT && TARGET_POPCNT"
-  "popcnt{q}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_rep" "1")
-   (set_attr "type" "bitmanip")
-   (set_attr "mode" "DI")])
-
-(define_insn "*popcountdi2_cmp"
-  [(set (reg FLAGS_REG)
-	(compare
-	  (popcount:DI (match_operand:DI 1 "nonimmediate_operand" "rm"))
-	  (const_int 0)))
-   (set (match_operand:DI 0 "register_operand" "=r")
-	(popcount:DI (match_dup 1)))]
-  "TARGET_64BIT && TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
-  "popcnt{q}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_rep" "1")
-   (set_attr "type" "bitmanip")
-   (set_attr "mode" "DI")])
-
-(define_expand "clzhi2"
-  [(parallel
-     [(set (match_operand:HI 0 "register_operand" "")
-	   (minus:HI (const_int 15)
-		     (clz:HI (match_operand:HI 1 "nonimmediate_operand" ""))))
-      (clobber (reg:CC FLAGS_REG))])
-   (parallel
-     [(set (match_dup 0) (xor:HI (match_dup 0) (const_int 15)))
-      (clobber (reg:CC FLAGS_REG))])]
-  ""
-{
-  if (TARGET_ABM)
-    {
-      emit_insn (gen_clzhi2_abm (operands[0], operands[1]));
-      DONE;
-    }
-})
-
-(define_insn "clzhi2_abm"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(clz:HI (match_operand:HI 1 "nonimmediate_operand" "")))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_ABM"
-  "lzcnt{w}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_rep" "1")
-   (set_attr "type" "bitmanip")
-   (set_attr "mode" "HI")])
-
-(define_insn "*bsrhi"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(minus:HI (const_int 15)
-		  (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))))
-   (clobber (reg:CC FLAGS_REG))]
-  ""
-  "bsr{w}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_0f" "1")
-   (set_attr "mode" "HI")])
-
-(define_insn "popcounthi2"
-  [(set (match_operand:HI 0 "register_operand" "=r")
-	(popcount:HI (match_operand:HI 1 "nonimmediate_operand" "")))
-   (clobber (reg:CC FLAGS_REG))]
-  "TARGET_POPCNT"
-  "popcnt{w}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_rep" "1")
-   (set_attr "type" "bitmanip")
-   (set_attr "mode" "HI")])
-
-(define_insn "*popcounthi2_cmp"
-  [(set (reg FLAGS_REG)
-        (compare
-          (popcount:HI (match_operand:HI 1 "nonimmediate_operand" "rm"))
-          (const_int 0)))
-   (set (match_operand:HI 0 "register_operand" "=r")
-        (popcount:HI (match_dup 1)))]
-  "TARGET_POPCNT && ix86_match_ccmode (insn, CCZmode)"
-  "popcnt{w}\t{%1, %0|%0, %1}"
-  [(set_attr "prefix_rep" "1")
-   (set_attr "type" "bitmanip")
-   (set_attr "mode" "HI")])
+  [(set_attr "prefix_0f" "1")])
 
 ;; Thread-local storage patterns for ELF.
 ;;
@@ -15755,8 +15503,7 @@
   "sqrtss\t{%1, %0|%0, %1}"
   [(set_attr "type" "sse")
    (set_attr "mode" "SF")
-   (set_attr "athlon_decode" "*")
-   (set_attr "amdfam10_decode" "*")])
+   (set_attr "athlon_decode" "*")])
 
 (define_insn "*sqrtsf2_i387"
   [(set (match_operand:SF 0 "register_operand" "=f")
@@ -15794,8 +15541,7 @@
   "sqrtsd\t{%1, %0|%0, %1}"
   [(set_attr "type" "sse")
    (set_attr "mode" "DF")
-   (set_attr "athlon_decode" "*")
-   (set_attr "amdfam10_decode" "*")])
+   (set_attr "athlon_decode" "*")])
 
 (define_insn "*sqrtdf2_i387"
   [(set (match_operand:DF 0 "register_operand" "=f")
@@ -15824,8 +15570,7 @@
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")
-   (set_attr "athlon_decode" "direct")
-   (set_attr "amdfam10_decode" "direct")])
+   (set_attr "athlon_decode" "direct")])
 
 (define_insn "*sqrtextendsfxf2_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
@@ -15845,8 +15590,7 @@
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")
-   (set_attr "athlon_decode" "direct")   
-   (set_attr "amdfam10_decode" "direct")])
+   (set_attr "athlon_decode" "direct")])
 
 (define_insn "fpremxf4"
   [(set (match_operand:XF 0 "register_operand" "=f")
@@ -20647,7 +20391,7 @@
 		   (mult:DI (match_operand:DI 1 "memory_operand" "")
 			    (match_operand:DI 2 "immediate_operand" "")))
 	      (clobber (reg:CC FLAGS_REG))])]
-  "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
+  "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
    && !satisfies_constraint_K (operands[2])"
   [(set (match_dup 3) (match_dup 1))
    (parallel [(set (match_dup 0) (mult:DI (match_dup 3) (match_dup 2)))
@@ -20660,7 +20404,7 @@
 		   (mult:SI (match_operand:SI 1 "memory_operand" "")
 			    (match_operand:SI 2 "immediate_operand" "")))
 	      (clobber (reg:CC FLAGS_REG))])]
-  "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
+  "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
    && !satisfies_constraint_K (operands[2])"
   [(set (match_dup 3) (match_dup 1))
    (parallel [(set (match_dup 0) (mult:SI (match_dup 3) (match_dup 2)))
@@ -20674,7 +20418,7 @@
 		     (mult:SI (match_operand:SI 1 "memory_operand" "")
 			      (match_operand:SI 2 "immediate_operand" ""))))
 	      (clobber (reg:CC FLAGS_REG))])]
-  "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
+  "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
    && !satisfies_constraint_K (operands[2])"
   [(set (match_dup 3) (match_dup 1))
    (parallel [(set (match_dup 0) (zero_extend:DI (mult:SI (match_dup 3) (match_dup 2))))
@@ -20691,7 +20435,7 @@
 			    (match_operand:DI 2 "const_int_operand" "")))
 	      (clobber (reg:CC FLAGS_REG))])
    (match_scratch:DI 3 "r")]
-  "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
+  "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
    && satisfies_constraint_K (operands[2])"
   [(set (match_dup 3) (match_dup 2))
    (parallel [(set (match_dup 0) (mult:DI (match_dup 0) (match_dup 3)))
@@ -20707,7 +20451,7 @@
 			    (match_operand:SI 2 "const_int_operand" "")))
 	      (clobber (reg:CC FLAGS_REG))])
    (match_scratch:SI 3 "r")]
-  "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size
+  "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size
    && satisfies_constraint_K (operands[2])"
   [(set (match_dup 3) (match_dup 2))
    (parallel [(set (match_dup 0) (mult:SI (match_dup 0) (match_dup 3)))
@@ -20723,7 +20467,7 @@
 			    (match_operand:HI 2 "immediate_operand" "")))
 	      (clobber (reg:CC FLAGS_REG))])
    (match_scratch:HI 3 "r")]
-  "(TARGET_K8 || TARGET_GENERIC64 || TARGET_AMDFAM10) && !optimize_size"
+  "(TARGET_K8 || TARGET_GENERIC64) && !optimize_size"
   [(set (match_dup 3) (match_dup 2))
    (parallel [(set (match_dup 0) (mult:HI (match_dup 0) (match_dup 3)))
 	      (clobber (reg:CC FLAGS_REG))])]
@@ -20902,7 +20646,7 @@
 
 (define_insn "*sibcall_value_1_rex64_v"
   [(set (match_operand 0 "" "")
-	(call (mem:QI (reg:DI R11_REG))
+	(call (mem:QI (reg:DI 40))
 	      (match_operand:DI 1 "" "")))]
   "SIBLING_CALL_P (insn) && TARGET_64BIT"
   "jmp\t*%%r11"
@@ -20921,14 +20665,14 @@
 
 (define_expand "sse_prologue_save"
   [(parallel [(set (match_operand:BLK 0 "" "")
-		   (unspec:BLK [(reg:DI 22)
+		   (unspec:BLK [(reg:DI 21)
+				(reg:DI 22)
 				(reg:DI 23)
 				(reg:DI 24)
 				(reg:DI 25)
 				(reg:DI 26)
 				(reg:DI 27)
-				(reg:DI 28)
-				(reg:DI 29)] UNSPEC_SSE_PROLOGUE_SAVE))
+				(reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
 	      (use (match_operand:DI 1 "register_operand" ""))
 	      (use (match_operand:DI 2 "immediate_operand" ""))
 	      (use (label_ref:DI (match_operand 3 "" "")))])]
@@ -20938,14 +20682,14 @@
 (define_insn "*sse_prologue_save_insn"
   [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
 			  (match_operand:DI 4 "const_int_operand" "n")))
-	(unspec:BLK [(reg:DI 22)
+	(unspec:BLK [(reg:DI 21)
+		     (reg:DI 22)
 		     (reg:DI 23)
 		     (reg:DI 24)
 		     (reg:DI 25)
 		     (reg:DI 26)
 		     (reg:DI 27)
-		     (reg:DI 28)
-		     (reg:DI 29)] UNSPEC_SSE_PROLOGUE_SAVE))
+		     (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
    (use (match_operand:DI 1 "register_operand" "r"))
    (use (match_operand:DI 2 "const_int_operand" "i"))
    (use (label_ref:DI (match_operand 3 "" "X")))]