diff options
| author | obrien <obrien@FreeBSD.org> | 2004-06-16 05:45:41 +0000 |
|---|---|---|
| committer | obrien <obrien@FreeBSD.org> | 2004-06-16 05:45:41 +0000 |
| commit | abfa7c9435b930b7b0628c3d5aecb3d2bd2939ae (patch) | |
| tree | 1b1eca723e1299baef96baf728843d50abdf24a8 /contrib/binutils/opcodes | |
| parent | ed2b7f732a9e0add59e9276fb35caeac694ca2c7 (diff) | |
| parent | 2504df11e1275f63f4c53377bf91eee996360cb5 (diff) | |
| download | FreeBSD-src-abfa7c9435b930b7b0628c3d5aecb3d2bd2939ae.zip FreeBSD-src-abfa7c9435b930b7b0628c3d5aecb3d2bd2939ae.tar.gz | |
This commit was generated by cvs2svn to compensate for changes in r130561,
which included commits to RCS files with non-trunk default branches.
Diffstat (limited to 'contrib/binutils/opcodes')
53 files changed, 18524 insertions, 14497 deletions
diff --git a/contrib/binutils/opcodes/ChangeLog b/contrib/binutils/opcodes/ChangeLog index 3c9dfc3..88c6b3e 100644 --- a/contrib/binutils/opcodes/ChangeLog +++ b/contrib/binutils/opcodes/ChangeLog @@ -1,2934 +1,187 @@ -2002-10-30 Daniel Jacobowitz <drow@mvista.com> +2004-05-13 Nick Clifton <nickc@redhat.com> - * po/opcodes.pot: Regenerated. - -2002-10-28 Daniel Jacobowitz <drow@mvista.com> - - Merge from mainline: - 2002-10-07 Nathan Tallent <eraxxon@alumni.rice.edu> - * sparc-opc.c (sparc_opcodes) <fb, fba, fbe, fbz, fbg, fbge, - fbl, fble, fblg, fbn, fbne, fbnz, fbo, fbu, fbue, fbug, fbuge, - fbul, fbule>: Add conditional/unconditional branch - classification. - - 2002-09-24 Nick Clifton <nickc@redhat.com> - * po/de.po: Updated Danish translation file. - -2002-09-04 Nick Clifton <nickc@redhat.com> - Daniel Jacobowitz <drow@mvista.com> - - * disassemble.c (disassembler_usage): Add invocation of - print_ppc_disassembler_options. - * ppc-dis.c (print_ppc_disassembler_options): New function. - -2002-09-23 Daniel Jacobowitz <drow@mvista.com> - - Merge from mainline: - 2002-09-11 Nick Clifton <nickc@redhat.com> - * po/da.po: Updated Danish translation file. - - 2002-09-04 Nick Clifton <nickc@redhat.com> - * ppc-opc.c: The BookE implementations of the TLBWE and TLBRE - instructions do not take any arguments. - - 2002-09-04 Nick Clifton <nickc@redhat.com> - * ppc-opc.c (extsw, extsw.): Do not allow for the BookE32. - - 2002-08-09 Nick Clifton <nickc@redhat.com> - * po/sv.po: Updated Swedish translation. - -2002-08-20 Maciej W. Rozycki <macro@ds2.pg.gda.pl> - - * mips-opc.c (mips_builtin_opcodes): Remove "dla" and "la" as - aliases to "daddiu" and "addiu". - -2002-07-30 Daniel Jacobowitz <drow@mvista.com> - - Merge from mainline: - 2002-07-30 Nick Clifton <nickc@redhat.com> - * po/sv.po: Updated Swedish translation. - -2002-07-25 Nick Clifton <nickc@redhat.com> - - * po/sv.po: Updated Swedish translation. - * po/es.po: Updated Spanish translation. - * po/pr_BR.po: Updated Brazilian Portuguese translation. - * po/tr.po: Updated Turkish translation. * po/fr.po: Updated French translation. -2002-07-24 Nick Clifton <nickc@redhat.com> - - * po/sv.po: Updated Swedish translation. - * po/es.po: Updated Spanish translation. - * po/pr_BR.po: Updated Brazilian Portuguese translation. - -2002-07-23 Daniel Jacobowitz <drow@mvista.com> - - * po/opcodes.pot: Regenerated. - -2002-07-23 Nick Clifton <nickc@redhat.com> - - * po/fr.po: Updated French translation. - * po/pr_BR.po: New Brazilian Portuguese translation. - * po/id.po: Updated Indonesian translation. - * configure.in (LINGUAS): Add pr_BR. - * configure: Regenerate. - -2002-07-17 David Mosberger <davidm@hpl.hp.com> - - * ia64-opc-b.c (bWhc): New macro. - (mWhc): Ditto. - (OpPaWhcD): Ditto. - (ia64_opcodes_b): Correct patterns for indirect call - instructions to use 3-bit "wh" field. - * ia64-asmtab.c: Regnerate. - -2002-07-09 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-dis.c (mips_isa_type): Add MIPS16 insn handling. - * mips-opc.c (I16): New define. - (mips_builtin_opcodes): Make jalx an I16 insn. - -2002-06-18 Dave Brolley <brolley@redhat.com> - - * po/POTFILES.in: Add frv-*.[ch]. - * disassemble.c (ARCH_frv): New macro. - (disassembler): Handle bfd_arch_frv. - * configure.in: Support frv_bfd_arch. - * Makefile.am (HFILES): Add frv-*.h. - (CFILES): Add frv-*.c - (ALL_MACHINES): Add frv-*.lo. - (CLEANFILES): Add stamp-frv. - (FRV_DEPS): New variable. - (stamp-frv): New target. - (frv-asm.lo): New target. - (frv-desc.lo): New target. - (frv-dis.lo): New target. - (frv-ibld.lo): New target. - (frv-opc.lo): New target. - (frv-*.[ch]): New files. - -2002-06-18 Ben Elliston <bje@redhat.com> - - * Makefile.am (CGENDEPS): Remove unnecessary stamp-cgen. - * Makefile.in: Regenerate. - -2002-06-08 Alan Modra <amodra@bigpond.net.au> - - * a29k-dis.c: Replace CONST with const. - * h8300-dis.c: Likewise. - * m68k-dis.c: Likewise. - * or32-dis.c: Likewise. - * sparc-dis.c: Likewise. - -2002-06-04 Jason Thorpe <thorpej@wasabisystems.com> - - * configure.in: Add "sh5*-*" to list of targets which include - sh64 support. - * configure: Regenerate. - -2002-05-31 Chris G. Demetriou <cgd@broadcom.com> - - * mips-opc.c: Clean up a few whitespace issues, and sort a - few entries understanding that 'x' follows 'w' in the alphabet. - -2002-05-31 Chris G. Demetriou <cgd@broadcom.com> - Ed Satterthwaite <ehs@broadcom.com> - - * mips-opc.c: Add support for SB-1 MDMX subset and extensions. - -2002-05-31 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - * po/POTFILES.in: Regenerate. - -2002-05-30 Chris G. Demetriou <cgd@broadcom.com> - Ed Satterthwaite <ehs@broadcom.com> - - * mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y', - and 'Z' formats, for MDMX. - (mips_isa_type): Add MDMX instructions to the ISA - bit mask for bfd_mach_mipsisa64. - * mips-opc.c: Add support for MDMX instructions. - (MX): New definition. - - * mips-dis.c: Update copyright years to include 2002. - -2002-05-30 Diego Novillo <dnovillo@redhat.com> - - * d10v-opc.c (d10v_opcodes): `btsti' does not modify its - arguments. - -2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net> - - * configure.in: Add DLX configuraton support. - * configure: Regenerate. - * Makefile.am: Add DLX configuraton support. - * Makefile.in: Regenerate. - * disassemble.c: Add DLX support. - * dlx-dis.c: New file. - -2002-05-25 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am (sh-dis.lo): Don't put make commands in deps. - * Makefile.in: Regenerate. - * arc-dis.c: Use #include "" instead of <> for local header files. - * m68k-dis.c: Likewise. - -Wed May 22 20:11:51 2002 J"orn Rennecke <joern.rennecke@superh.com> - - * Makefile.am (sh-dis.lo): Compile with @archdefs@. - * Makefile.in: regenerate. - - * sh-dis.c (print_insn_sh): If coff and bfd_mach_sh, use arch_sh4 - for disassembly. - -2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros. - -Fri May 17 14:26:44 2002 J"orn Rennecke <joern.rennecke@superh.com> - - * disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh. - * sh-dis.c (LITTLE_BIT): Delete. - (print_insn_sh, print_insn_shl): Deleted. - (print_insn_shx): Renamed to - (print_insn_sh). No longer static. Handle SHmedia instructions. - Use info->endian to determine endianness. - * sh64-dis.c (print_insn_sh64, print_insn_sh64l): Delete. - (print_insn_sh64x): No longer static. Renamed to - (print_insn_sh64). Removed pfun_compact and endian arguments. - If we got an uneven address to indicate SHmedia, adjust it. - Return -2 for SHcompact instructions. - -2002-05-17 Alan Modra <amodra@bigpond.net.au> - - * acinclude.m4 (AM_INSTALL_LIBBFD): Fake to fool autotools. - * configure.in: Invoke AM_INSTALL_LIBBFD. - * Makefile.am (install-data-local): Move to.. - (install_libopcodes): .. New target. - (uninstall_libopcodes): Likewise. - (install-bfdlibLTLIBRARIES): Likewise. - (uninstall-bfdlibLTLIBRARIES): Likewise. - (bfdlibdir): New. - (bfdincludedir): New. - (lib_LTLIBRARIES): Rename to bfdlib_LTLIBRARIES. - * aclocal.m4: Regenerate. - * configure: Regenerate. - * Makefile.in: Regenerate. - -2002-05-15 Nick Clifton <nickc@cambridge.redhat.com> - - * fr30-asm.c: Regenerate. - * fr30-desc.c: Regenerate. - * fr30-dis.c: Regenerate. - * m32r-asm.c: Regenerate. - * m32r-desc.c: Regenerate. - * m32r-dis.c: Regenerate. - * openrisc-asm.c: Regenerate. - * openrisc-desc.c: Regenerate. - * openrisc-dis.c: Regenerate. - * xstormy16-asm.c: Regenerate. - * xstormy16-desc.c: Regenerate. - * xstormy16-dis.c: Regenerate. - -2002-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-dis.c (is_newabi): EABI is not a NewABI. - -2002-05-13 Jason Thorpe <thorpej@wasabisystems.com> - - * configure.in (shle-*-*elf*): Include sh64 support. - * configure: Regenerate. - -2002-04-28 Jason Thorpe <thorpej@wasabisystems.com> - - * vax-dis.c (print_insn_arg): Pass the insn info to print_insn_mode. - (print_insn_mode): Print some basic info about floating point values. - -2002-05-09 Anton Blanchard <anton@samba.org> - - * ppc-opc.c: Add "tlbiel" for POWER4. - -2002-05-07 Graydon Hoare <graydon@redhat.com> - - * cgen-dis.in: (print_insn_@arch@): Cache list of opened CPUs rather - than just most-recently-opened. - -2002-05-01 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c: Add "tlbsx." and "tlbsxe." for booke. - -2002-04-24 Christian Groessler <chris@groessler.org> - - * z8k-dis.c (print_insn_z8k): Set disassemble_info to 2 - bytes_per_chunk, 6 bytes_per_line for nicer display of the hex - codes. - (z8k_lookup_instr): CLASS_IGNORE case added. - (output_instr): Don't print hex codes, they are already - printed. - (unpack_instr): ARG_NIM4 case added. ARG_NIM8 case - fixed. Support CLASS_BIT_1OR2 and CLASS_IGNORE cases. - (unparse_instr): Fix base and indexed addressing disassembly: - The index is inside the brackets. - * z8kgen.c (gas): Add ARG_NIM4 and CLASS_IGNORE defines. - (opt): Fix shift left/right arithmetic/logical byte defines: - The high byte of the immediate word is ignored by the - processor. - Fix n parameter of ldm opcodes: The opcode contains (n-1). - (args): Fix "n" entry. - (toks): Add "nim4" and "iiii" entries. - * z8k-opc.h: Regenerated with new z8kgen.c. - -2002-04-24 Nick Clifton <nickc@cambridge.redhat.com> - - * po/id.po: New Indonesian translation. - * configure.in (ALL_LIGUAS): Add id.po - * configure: Regenerate. - -2002-04-17 matthew green <mrg@redhat.com> - - * ppc-opc.c (powerpc_opcode): Fix dssall operand list. - -2002-04-04 Alan Modra <amodra@bigpond.net.au> - - * dep-in.sed: Cope with absolute paths. - * Makefile.am (dep.sed): Subst TOPDIR. - Run "make dep-am". - * Makefile.in: Regenerate. - * ppc-opc.c: Whitespace. - * s390-dis.c: Fix copyright date. - -2002-03-23 matthew green <mrg@redhat.com> - - * ppc-opc.c (vmaddfp): Fix operand order. - -2002-03-21 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - -2002-03-21 Anton Blanchard <anton@samba.org> - - * ppc-opc.c: Add optional field to mtmsrd. - (MTMSRD_L, XRLARB_MASK): Define. - -Mon Mar 18 21:10:43 CET 2002 Jan Hubicka <jh@suse.cz> - - * i386-dis.c (prefix_name): Fix handling of 32bit address prefix - in 64bit mode. - (print_insn) Likewise. - (putop): Fix handling of 'E' - (OP_E, OP_OFF): handle 32bit addressing mode in 64bit. - (ptr_reg): Likewise. - -2002-03-18 Nick Clifton <nickc@cambridge.redhat.com> - - * po/fr.po: Updated version. - -2002-03-16 Chris Demetriou <cgd@broadcom.com> - - * mips-opc.c (M3D): Tweak comment. - (mips_builtin_op): Add comment indicating that opcodes of the - same name must be placed together in the table, and sort - the "recip.fmt", "recip1.fmt", "recip2.fmt", "rsqrt.fmt", - "rsqrt1.fmt", and "rsqrt2.fmt" opcodes by name. - -2002-03-16 Nick Clifton <nickc@cambridge.redhat.com> - - * Makefile.am: Tidy up sh64 rules. - * Makefile.in: Regenerate. - -2002-03-15 Chris G. Demetriou <cgd@broadcom.com> - - * mips-dis.c: Update copyright years. - -2002-03-15 Chris G. Demetriou <cgd@broadcom.com> - - * mips-dis.c (mips_isa_type): Add MIPS3D instructions to the ISA - bit masks for bfd_mach_mips_sb1 and bfd_mach_mipsisa64. Add - comments for bfd_mach_mipsisa32 and bfd_mach_mipsisa64 that - indicate that they should dissassemble all applicable - MIPS-specified ASEs. - * mips-opc.c: Add support for MIPS-3D instructions. - (M3D): New definition. - - * mips-opc.c: Update copyright years. - -2002-03-15 Chris G. Demetriou <cgd@broadcom.com> - - * mips-opc.c (mips_builtin_opcodes): Sort bc<N> opcodes by name. - -2002-03-15 Chris Demetriou <cgd@broadcom.com> - - * mips-dis.c (is_newabi): Fix ABI decoding. - -2002-03-14 Chris G. Demetriou <cgd@broadcom.com> - - * mips-dis.c (mips_isa_type): Fix formatting of bfd_mach_mipsisa32 - and bfd_mach_mipsisa64 cases to match the rest. - -2002-03-13 Nick Clifton <nickc@cambridge.redhat.com> - - * po/fr.po: Updated version. - -2002-03-13 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c: Add optional `L' field to tlbie. - (XRTLRA_MASK): Define. - -2002-03-06 Chris Demetriou <cgd@broadcom.com> - - * mips-opc.c (mips_builtin_opcodes): Mark "pref" as being - present on I4. - - * mips-opc.c (mips_builtin_opcodes): Add "movn.ps" and "movz.ps". - -2002-03-05 Paul Koning <pkoning@equallogic.com> - - * pdp11-opc.c: Fix "mark" operand type. Fix operand types - for float opcodes that take float operands. Add alternate - names (xxxD vs. xxxF) for float opcodes. - * pdp11-dis.c (print_operand): Clean up formatting for mode 67. - (print_foperand): New function to handle float opcode operands. - (print_insn_pdp11): Use print_foperand to disassemble float ops. - -2002-02-27 Nick Clifton <nickc@cambridge.redhat.com> - - * po/de.po: Updated. - -2002-02-26 Brian Gaeke <brg@dgate.org> - - * Makefile.am (install-data-local): Install dis-asm.h. - -2002-02-26 Nick Clifton <nickc@cambridge.redhat.com> - - * configure.in (LINGUAS): Add de.po. - * configure: Regenerate. - * po/de.po: New file. - -2002-02-25 Alan Modra <amodra@bigpond.net.au> - - * ppc-dis.c (powerpc_dialect): Handle power4 option. - * ppc-opc.c (insert_bdm): Correct description of "at" branch - hints. Test PPC_OPCODE_POWER4 to determine branch hint flavour. - (extract_bdm, insert_bdp, extract_bdp, valid_bo): Likewise. - (BOFM64, BOFP64, BOTM64, BOFP64): Rename to BOFM4, BOFP4 etc. - (BODNZM64, BODNZP64, BODZM64, BODZP64): Likewise. - (PPCCOM32, PPCCOM64): Delete. - (NOPOWER4, POWER4): Define. - (powerpc_opcodes): Replace occurences of PPCCOM32 with NOPOWER4, - and PPCCOM4 with POWER4 so that "at" style branch hint opcodes - are enabled for power4 rather than ppc64. - -2002-02-20 Tom Rix <trix@redhat.com> - - * ppc-opc.c (powerpc_operands): Add WS field. Use for tlbre, tlbwe. - -2002-02-19 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390-dis.c (init_disasm): Use renamed architecture defines. - -2002-02-19 matthew green <mrg@redhat.com> - - * ppc-opc.c (powerpc_dialect): Fix comment; BookE is not Motorola - specific. - -2002-02-18 Nick Clifton <nickc@cambridge.redhat.com> - - * po/tr.po: Updated translation. - -2002-02-15 Richard Henderson <rth@redhat.com> - - * alpha-opc.c (alpha_opcodes): Fix thinko in ret pseudo - disassembly mask. - -2002-02-15 Richard Henderson <rth@redhat.com> - - * alpha-opc.c (alpha_opcodes): Add simple pseudos for - lda, ldah, jmp, ret. - -2002-02-14 Nick Clifton <nickc@cambridge.redhat.com> - - * po/da.po: Updated translation. - -2002-02-12 Graydon Hoare <graydon@redhat.com> - - * cgen-asm.in (parse_insn_normal): Change call from - @arch@_cgen_parse_operand to cd->parse_operand, to - facilitate CGEN_ASM_INIT_HOOK doing useful work. - -2002-02-11 Alexandre Oliva <aoliva@redhat.com> - - * sparc-dis.c (print_insn_sparc): Make sure 0xFFFFFFFF is not - sign-extended. - -2002-02-11 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: "make dep-am". - * Makefile.in: Regenerate. - * aclocal.m4: Regenerate. - * config.in: Regenerate. - * configure: Regenerate. - -2002-02-10 Hans-Peter Nilsson <hp@bitrange.com> - - * configure.in <bfd_sh_arc>: For sh-* and shl-*, enable sh64 - support only for sh-*-*elf*, shl-*-*elf*, sh-*-linux* and - shl-*-linux*. - * configure: Regenerate. - -2002-02-10 Daniel Jacobowitz <drow@mvista.com> - - * cgen-dis.c: Add prototypes for count_decodable_bits - and add_insn_to_hash_chain. - -2002-02-08 Alexandre Oliva <aoliva@redhat.com> - - * configure.in <bfd_sh_arc>: Enable sh64 support on sh-*. - * configure: Rebuilt. - -2002-02-08 Ivan Guzvinec <ivang@opencores.org> - - * or32-opc.c: Fix compile time warning messages. - * or32-dis.c: Fix compile time warning messages. - -2002-02-08 Alexandre Oliva <aoliva@redhat.com> - - Contribute sh64-elf. - 2001-10-08 Nick Clifton <nickc@cambridge.redhat.com> - * sh64-opc.c: Regenerate. - 2001-03-13 DJ Delorie <dj@redhat.com> - * sh64-opc.h: Rename A_RESV_Fx to A_REUSE_PREV so that its - purpose is more obvious. - * sh64-opc.c (shmedia_table): Ditto. - * sh64-dis.c (initialize_shmedia_opcode_mask_table): Ditto. - (print_insn_shmedia): Ditto. - 2001-03-12 DJ Delorie <dj@redhat.com> - * sh64-opc.c: Adjust comments to reflect reality: replace bits - 3:0 with zeros (not "reserved"), replace "rrrrrr" with - "gggggg" for two-operand floating point opcodes. Remove - "fsina". - 2001-01-08 Hans-Peter Nilsson <hpn@cygnus.com> - * sh64-dis.c (print_insn_shmedia) <failing read_memory_func>: - Correct printing of .byte:s. Return number of printed bytes or - -1; never 0. - (print_insn_sh64x) <not CRT_SH5_ISA16>: Ditto. Print as .byte:s - to next four-byte-alignment if insn or data is not aligned. - 2001-01-06 Hans-Peter Nilsson <hpn@cygnus.com> - * sh64-dis.c: Update comments and fix comment formatting. - (initialize_shmedia_opcode_mask_table) <case A_IMMM>: - Abort instead of setting length to 0. - (crange_qsort_cmpb, crange_qsort_cmpl, crange_bsearch_cmpb, - crange_bsearch_cmpl, sh64_get_contents_type, - sh64_address_in_cranges): Move to bfd/elf32-sh64.c. - 2001-01-05 Hans-Peter Nilsson <hpn@cygnus.com> - * sh64-opc.c: Remove #if 0:d entries for instructions not found in - SH-5/ST50-023-04: fcosa.s, fsrra.s and prefo. - 2000-12-30 Hans-Peter Nilsson <hpn@cygnus.com> - * sh64-dis.c (print_insn_shmedia): Display MOVI/SHORI-formed - address with same prefix as SHcompact. - In the disassembler, use a .cranges section for linked executables. - * sh64-dis.c (SAVED_MOVI_R, SAVED_MOVI_IMM): Move to head of file - and update for using structure in info->private_data. - (struct sh64_disassemble_info): New. - (is_shmedia_p): Delete. - (crange_qsort_cmpb): New function. - (crange_qsort_cmpl, crange_bsearch_cmpb): New functions. - (crange_bsearch_cmpl, sh64_address_in_cranges): New functions. - (init_sh64_disasm_info, sh64_get_contents_type_disasm): New functions. - (sh64_get_contents_type, sh64_address_is_shmedia): New functions. - (print_insn_shmedia): Correct displaying of address after MOVI/SHORI - pair. Display addresses for linked executables only. - (print_insn_sh64x_media): Initialize info->private_data by calling - init_sh64_disasm_info. - (print_insn_sh64x): Ditto. Find out type of contents by calling - sh64_contents_type_disasm. Display data regions using ".long" and - ".byte" similar to unrecognized opcodes. - 2000-12-19 Hans-Peter Nilsson <hpn@cygnus.com> - * sh64-dis.c (is_shmedia_p): Check info->section and look for ISA - information in section flags before considering symbols. Don't - assume an info->mach setting of bfd_mach_sh5 means SHmedia code. - * configure.in (bfd_sh_arch): Check presence of sh64 insns by - matching $target $canon_targets instead of looking at the - now-removed -DINCLUDE_SHMEDIA in $targ_cflags. - * configure: Regenerate. - 2000-11-25 Hans-Peter Nilsson <hpn@cygnus.com> - * sh64-opc.c (shmedia_creg_table): New. - * sh64-opc.h (shmedia_creg_info): New type. - (shmedia_creg_table): Declare. - * sh64-dis.c (creg_name): New function. - (print_insn_shmedia): Use it. - * disassemble.c (disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map - bfd_mach_sh5 to print_insn_sh64 if big-endian and to - print_insn_sh64l if little-endian. - * sh64-dis.c (print_insn_shmedia): Make r unsigned. - (print_insn_sh64l): New. - (print_insn_sh64x): New. - (print_insn_sh64x_media): New. - (print_insn_sh64): Break out code to print_insn_sh64x and - print_insn_sh64x_media. - 2000-11-24 Hans-Peter Nilsson <hpn@cygnus.com> - * sh64-opc.h: New file - * sh64-opc.c: New file - * sh64-dis.c: New file - * Makefile.am: Add sh64 targets. - (HFILES): Add sh64-opc.h. - (CFILES): Add sh64-opc.c and sh64-dis.c. - (ALL_MACHINES): Add sh64 files. - * Makefile.in: Regenerate. - * configure.in: Add support for sh64 to bfd_sh_arch. - * configure: Regenerate. - * disassemble.c [ARCH_all] (INCLUDE_SHMEDIA): Define. - (disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map bfd_mach_sh5 to - print_insn_sh64. - * sh-dis.c (print_insn_shx): Handle bfd_mach_sh5 as arch_sh4. - * po/POTFILES.in: Regenerate. - * po/opcodes.pot: Regenerate. - -2002-02-04 Frank Ch. Eigler <fche@redhat.com> - - * cgen-dis.in (print_insn_@arch@): Support disassemble_info.insn_sets. - -2002-02-04 Alexandre Oliva <aoliva@redhat.com> - - * sh-opc.h (sh_arg_type): Added A_DISP_PC_ABS. - -2002-02-01 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am" - * Makefile.in: Regenerate. - -2002-01-31 Ivan Guzvinec <ivang@opencores.org> - - * or32-dis.c: New file. - * or32-opc.c: New file. - * configure.in: Add support for or32. - * configure: Regenerate. - * Makefile.am: Add support for or32. - * Makefile.in: Regenerate. - * disassemble.c: Add support for or32. - * po/POTFILES.in: Regenerate. - * po/opcodes.pot: Regenerate. - -2002-01-27 Daniel Jacobowitz <drow@mvista.com> - - * configure: Regenerated. - -2002-01-26 Nick Clifton <nickc@cambridge.redhat.com> - - * po/fr.po: Updated version. - -2002-01-25 Nick Clifton <nickc@cambridge.redhat.com> - - * po/es.po: Updated version. - -2002-01-24 Nick Clifton <nickc@cambridge.redhat.com> - - * po/da.po: New version. - -2002-01-23 Nick Clifton <nickc@cambridge.redhat.com> - - * po/da.po: New file: Spanish translation. - * configure.in (ALL_LINGUAS): Add da. - * configure: Regenerate. - -2002-01-22 Graydon Hoare <graydon@redhat.com> - - * fr30-asm.c: Regenerate. - * fr30-desc.c: Likewise. - * fr30-desc.h: Likewise. - * fr30-dis.c: Likewise. - * fr30-ibld.c: Likewise. - * fr30-opc.c: Likewise. - * fr30-opc.h: Likewise. - * m32r-asm.c: Likewise. - * m32r-desc.c: Likewise. - * m32r-desc.h: Likewise. - * m32r-dis.c: Likewise. - * m32r-ibld.c: Likewise. - * m32r-opc.c: Likewise. - * m32r-opc.h: Likewise. - * m32r-opinst.c: Likewise. - * openrisc-asm.c: Likewise. - * openrisc-desc.c: Likewise. - * openrisc-desc.h: Likewise. - * openrisc-dis.c: Likewise. - * openrisc-ibld.c: Likewise. - * openrisc-opc.c: Likewise. - * openrisc-opc.h: Likewise. - * xstormy16-desc.c: Likewise. - -2002-01-22 Richard Henderson <rth@redhat.com> - - * alpha-dis.c (print_insn_alpha): Also mask the base opcode for - comparison. - -2002-01-22 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - * opcodes/po/POTFILES.in: Regenerate. - -2002-01-19 Richard Earnshaw <rearnsha@arm.com> - - * arm-opc.h (arm_opcodes): Use generic rule %5?hb instead of %h. - * arm-dis.c (print_insn_arm): Don't handle 'h' case. - -2002-01-18 Keith Walker <keith.walker@arm.com> +2004-05-05 Alan Modra <amodra@bigpond.net.au> - * arm-opc.h (arm_opcodes): Add bxj instruction. + PR 146. + * ppc-opc.c (PPCVEC): Remove PPC_OPCODE_PPC. -2002-01-17 Nick Clifton <nickc@cambridge.redhat.com> +2004-04-09 Daniel Jacobowitz <drow@mvista.com> - * po/opcodes.pot: Regenerate. - * po/fr.po: Regenerate. - * po/sv.po: Regenerate. - * po/tr.po: Regenerate. - -2002-01-16 Nick Clifton <nickc@cambridge.redhat.com> - - * po/tr.po: Import new version. - -2002-01-15 Richard Earnshaw <rearnsha@arm.com> - - * arm-opc.h (arm_opcodes): Add patterns for VFP instructions. - * arm-dis.c (print_insn_arm): Support new disassembly qualifiers for - VFP bitfields. - -2002-01-10 matthew green <mrg@redhat.com> - - * xstormy16-asm.c: Regenerate. - * xstormy16-desc.c: Likewise. - * xstormy16-desc.h: Likewise. - * xstormy16-dis.c: Likewise. - * xstormy16-opc.c: Likewise. - * xstormy16-opc.h: Likewise. - -2002-01-07 Nick Clifton <nickc@cambridge.redhat.com> - - * po/es.po: New file: Spanish translation. - * configure.in (ALL_LINGUAS): Add es. - * configure: Regenerate. - -2001-12-31 Jeffrey A Law (law@redhat.com) - - * hppa-dis.c (print_insn_hppa): Handle new 'c' mode completers, - 'X', 'M', and 'A'. No longer emit a space after 'x' or 's'. - Always emit a space after 'H'. - -2001-12-18 matthew green <mrg@redhat.com> - - * ppc-opc.c (PPCVEC): Include PPC_OPCODE_ANY. - -2001-12-17 Richard Henderson <rth@redhat.com> - - * alpha-opc.c (unop): Encode with RB as $sp. - -2001-12-07 Geoffrey Keating <geoffk@redhat.com> - - * Makefile.am: Add support for xstormy16. - * Makefile.in: Regenerate. - * configure.in: Add support for xstormy16. - * configure: Regenerate. - * disassemble.c: Add support for xstormy16. - * xstormy16-asm.c: New generated file. - * xstormy16-desc.c: New generated file. - * xstormy16-desc.h: New generated file. - * xstormy16-dis.c: New generated file. - * xstormy16-ibld.c: New generated file. - * xstormy16-opc.c: New generated file. - * xstormy16-opc.h: New generated file. - -2001-12-06 Richard Henderson <rth@redhat.com> - - * alpha-opc.c (alpha_opcodes): Add wh64en. - -2001-12-04 Alexandre Oliva <aoliva@redhat.com> - - * d10v-opc.c (d10v_predefined_registers): Remove warnings - introduced in Nov 29's patch. - - * d10v-dis.c (print_operand): Apply REGISTER_MASK to `num' of - unmatched register. - - * d10v-dis.c (print_operand): Disregard OPERAND_SP in register - predefined value. - - * d10v-opc.c (RSRC_NOSP): New macro. - (d10v_operands): Add it. - (d10v_opcodes): Use RSRC_NOSP in post-decrement "st" and "st2w". - -2001-11-29 Alexandre Oliva <aoliva@redhat.com> - - * d10v-opc.c (d10v_predefined_registers): Mark `sp' as OPERAND_SP. - (RSRC_SP): New macro. - (d10v_operands): Add it. - (d10v_opcodes): Adjust "st" and "st2w" to use RSRC_SP. - -2001-11-23 Lars Brinkhoff <lars@nocrew.org> - - * pdp11-dis.c (print_insn_pdp11): Handle illegal instructions. - Also, break out of the loop as soon as an instruction has been - printed. - -2001-11-17 matthew green <mrg@redhat.com> - - * ppc-opc.c (mfvrsave, mtvrsave): New instructions. - -2001-11-15 Alan Modra <amodra@bigpond.net.au> - - * po/POTFILES.in: Regenerate. - - * ppc-opc.c (PPC64): Revert 2001-10-12. Do include PPC_OPCODE_PPC. - (insert_bat, extract_bat, insert_bba, extract_bba, - insert_bd, extract_bd, insert_bdm, extract_bdm, - insert_bdp, extract_bdp, valid_bo, - insert_bo, extract_bo, insert_boe, extract_boe, - insert_ds, extract_ds, insert_de, extract_de, - insert_des, extract_des, insert_li, extract_li, - insert_mbe, extract_mbe, insert_mb6, extract_mb6, - insert_nb, extract_nb, insert_nsi, extract_nsi, - insert_ral, insert_ram, insert_ras, - insert_rbs, extract_rbs, insert_sh6, extract_sh6, - insert_spr, extract_spr, insert_tbr, extract_tbr): Add dialect param. - (extract_bd, extract_bdm, extract_bdp, - extract_ds, extract_des, - extract_li, extract_nsi): Implement sign extension without conditional. - (insert_bdm, extract_bdm, - insert_bdp, extract_bdp, valid_bo): Handle 64 bit branch hints. - (extract_bdm, extract_bdp): Correct 32 bit validation. - (AT1_MASK, AT2_MASK): Define. - (BBOAT_MASK): Define. - (BBOATCB_MASK, BBOAT2CB_MASK, BBOATBI_MASK): Define. - (BOFM64, BOFP64, BOTM64, BOTP64): Define. - (BODNZM64, BODNZP64, BODZM64, BODZP64): Define. - (PPCCOM32, PPCCOM64): Define. - (powerpc_opcodes): Modify existing 32 bit insns with branch hints - and add new patterns to implement 64 bit branches with hints. Move - booke instructions so they match before ppc64. - - * ppc-dis.c (powerpc_dialect): Set PPC_OPCODE_64 in dialect for - 64 bit default targets, and parse "32" and "64" in options. - Formatting fixes. - (print_insn_powerpc): Pass dialect to operand->extract. - -2001-11-14 Dave Brolley <brolley@redhat.com> - - * cgen-dis.c (count_decodable_bits): New function. - (add_insn_to_hash_chain): New function. - (hash_insn_array): Call add_insn_to_hash_chain. - (hash_insn_list): Call add_insn_to_hash_chain. - * m32r-dis.c: Regenerated. - * fr30-dis.c: Regenerated. - -2001-11-14 Andreas Jaeger <aj@suse.de> - - * i386-dis.c (print_insn): Use x86-64 as option. - -2001-11-14 Alan Modra <amodra@bigpond.net.au> - - * disassemble.c (disassembler): Call print_insn_i386. - * i386-dis.c (SUFFIX_ALWAYS): Define. - (struct dis_private): Add orig_sizeflag. - (print_insn_i386): Make it a wrapper, calling.. - (print_insn): ..The old body of print_insn_i386. Avoid longjmp - warning without using volatile by moving orig_sizeflag to priv, - and removing inbuf. Parse disassembler_options. - (print_insn_i386_att, print_insn_i386_intel): Move initialisation - code to print_insn. - (putop): Remove #ifdef SUFFIX_ALWAYS. - -2001-11-11 Timothy Wall <twall@alum.mit.edu> - - * tic54x-dis.c: Use revised opcode structure. Export opcode - template lookup. - (has_lkaddr): Don't forget about Lmem insns. - * tic54x-opc.c: Add emulation trap. Parallel table now uses - standard opcode templates. - -2001-11-13 Zack Weinberg <zack@codesourcery.com> - - * i386-dis.c (grps): Change "sldt", "str", and "smsw" entries - to "sldtQ", "strQ", "smswQ" respectively; all with Ev operand - category instead of Ew. - -2001-11-12 Niraj Gupta <ngupta@zumanetworks.com> - - * m68k-opc.c: Fix definitions of wddata[bwl]. - -2001-11-09 Richard Sandiford <rsandifo@redhat.com> - - * cgen-asm.c (cgen_parse_keyword): If the keyword is too big to - fit in the buffer, try to match the empty keyword. - -2001-11-09 Nick Clifton <nickc@cambridge.redhat.com> - - * cgen-ibld.in (extract_1): Fix badly placed #if 0. - * fr30-ibld.c: Regenerate. - * m32r-ibld.c: Regenerate. - * openrisc-ibld.c: Regenerate. - -2001-11-04 Chris Demetriou <cgd@broadcom.com> - - * mips-dis.c (print_insn_mips): Remove spaces at end of line. - -2001-11-02 Nick Clifton <nickc@cambridge.redhat.com> - - * configure.in (ALL_LINGUAS): Add "fr", "sv" and "tr". - * configure: Regernate. - * po/fr.po: New file. - * po/sv.po: New file. - * po/tr.po: New file. - -2001-11-01 Stephane Carrez <Stephane.Carrez@worldnet.fr> - - * m68hc11-dis.c (print_insn): Fix disassembly of movb with a - constant as source. - -2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> - - * Makefile.am (CFILES): Add mmix-dis.c and mmix-opc.c. Regenerate - dependencies. - * Makefile.in: Regenerate. - * mmix-dis.c, mmix-opc.c: New files. - -2001-10-29 Kazu Hirata <kazu@hxi.com> - - * d30v-dis.c: Fix a comment typo. - -2001-10-23 Chris Demetriou <cgd@broadcom.com> - - * mips-opc.c (mips_builtin_opcodes): Mark "bgezall" and - "bltzall" as writing GPR 31 (since they do). - - * mips-dis.c (print_insn_arg): Calculate info->target - where appropriate. - (print_insn_mips): Fill in instruction info. - (print_mips16_insn_arg): Remove unneded variable 'val'. - Removed duplicated instruction target calculations, - calculate once and print that result. Use same idiom for - masking the jump segment bits as is used in print_insn_arg. - -2001-10-20 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c (CT): Make it an optional operand. - -2001-10-17 Chris Demetriou <cgd@broadcom.com> - - * mips-dis.c (mips_isa_type): Make the ISA used to disassemble - SB-1 binaries include instructions specific to the SB-1. - * mips-opc.c (SB1): New definition. - (mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps", - "recip.ps", "rsqrt.ps", and "sqrt.ps". - -2001-10-17 matthew green <mrg@redhat.com> - - * ppc-opc.c (STRM): New AltiVec operand. - (XDSS): New AltiVec instruction form. - (mtvscr): Correct operand list. - (dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions. - -2001-10-17 Alan Modra <amodra@bigpond.net.au> - - * po/POTFILES.in: Regenerate. - -2001-10-13 matthew green <mrg@redhat.com> - - * ppc-opc.c (MO): New macro for MO field of mbar instruction. - (powerpc_opcodes): Add rfci, wrtee, wrteei, mfdcrx, mfdcr, - mtdcrx, mtdcr, msync, dcba and mbar as BookE instructions. - -2001-10-13 Nick Clifton <nickc@cambridge.redhat.com> - - * cgen-ibld.in: Include safe-ctype.h in preference to - ctype.h. - * cgen-asm.in: Include safe-ctype.h in preference to - ctype.h. Fix formatting. Use ISSPACE instead of isspace and - TOLOWER instead of tolower. - (@arch@_cgen_build_insn_regex): Remove duplication of syntax - string elements in constructed regular expression. - * fr30-asm.c: Regenerate. - * fr30-desc.c: Regenerate. - * fr30-ibld.c: Regenerate. - * m32r-asm.c: Regenerate. - * m32r-desc.c: Regenerate. - * m32r-ibld.c: Regenerate. - * openrisc-asm.c: Regenerate. - * openrisc-desc.c: Regenerate. - * openrisc-ibld.c: Regenerate. - * po/opcodes.pot: Regenerate. - -2001-10-12 matthew green <mrg@redhat.com> - - * ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New - instruction field instruction/extraction functions for new BookE - DE form instructions. - (CT): New macro for CT field in an X form instruction. - (DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form - instructions. - (PPC64): Don't include PPC_OPCODE_PPC. - (403): New opcode macro for PPC403 processors. - (BOOKE): New opcode macro for BookE processors. - (bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions. - (bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise. - (dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise. - (stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise. - (mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise. - (subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise. - (subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise. - (addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise. - (lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise. - (stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise. - (tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise. - (lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise. - (stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise. - (lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise. - - * ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look - for a disassembler option of `booke', `booke32' or `booke64' to enable - BookE support in the disassembler. - -2001-10-12 John Healy <jhealy@redhat.com> - - * cgen-dis.in (print_insn): Use min (cd->base_insn_bitsize, buflen*8) - for the length when extracting the base part of the insn. - -2001-10-09 Bruno Haible <haible@clisp.cons.org> - - * cgen-asm.in (*_cgen_build_insn_regex): Generate a case sensitive - regular expression. Fix some formatting problems. - * fr30-asm.c: Regenerate. - * openrisc-asm.c: Regenerate. + Merge from mainline: + 2004-03-30 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> * m32r-asm.c: Regenerate. -2001-10-09 Christian Groessler <cpg@aladdin.de> - - * z8k-dis.c (unparse_instr): Fixed formatting. Change disassembly - of indirect register memory accesses to be same format the - assembler accepts. - -2001-10-09 Nick Clifton <nickc@cambridge.redhat.com> - - * sh-opc.h: Fix encoding of least significant nibble of the - DSP single data transfer instructions. - - * sh-dis.c (print_insn_shx): Fix decoding of As opcode in DSP - instructions. - -2001-10-08 Nick Clifton <nickc@cambridge.redhat.com> - - * cgen-asm.in: Fix compile time warning messages in generated - C files. - * cgen-dis.in: The same. - * cgen-ibld.in: The same. - * fr30-asm.c: Regenerate. - * fr30-desc.c: Regenerate. - * fr30-dis.c: Regenerate. - * fr30-ibld.c: Regenerate. - * fr30-opc.c: Regenerate. - * m32r-asm.c: Regenerate. - * m32r-desc.c: Regenerate. - * m32r-dis.c: Regenerate. - * m32r-ibld.c: Regenerate. - * m32r-opc.c: Regenerate. - * m32r-opinst.c Regenerate. - * openrisc-asm.c: Regenerate. - * openrisc-desc.c: Regenerate. - * openrisc-dis.c: Regenerate. - * openrisc-ibld.c: Regenerate. - * openrisc-opc.c: Regenerate. - * openrisc-opc.h: Regenerate. - * Makefile.in: Regenerate. - * po/POTFILES.in: Regenerate. - * po/opcodes.pot: Regenerate. - -2001-10-08 Aldy Hernandez <aldyh@redhat.com> - - * arm-opc.h (arm_opcodes): Add cirrus insns. - - * arm-dis.c (print_insn_arm): Add 'I' case. - -2001-10-03 Alan Modra <amodra@bigpond.net.au> - - * po/POTFILES.in: Regenerate. - * configure: Regenerate. - -2001-10-02 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am (Makefile): Depend on bfd/configure.in. - Run "make dep-am". - * Makefile.in: Regenerate. - -2001-09-30 John Healy <jhealy@redhat.com> - - * cgen-ibld.in (insert_1): Switched bfd_get_bits and bfd_set_bits - calls to cgen_get_insn_value and cgen_put_insn_value calls. - (extract_1): Switched bfd_get_bits call to cgen_get_insn_value call. - -2001-09-30 Hans-Peter Nilsson <hp@bitrange.com> - - * Makefile.am: Update dependencies with "make dep-am". - * Makefile.in: Regenerate. - -2001-09-26 Alan Modra <amodra@bigpond.net.au> - - * arc-dis.c: Formatting fixes. - (my_sprintf): Define using VPARAMS, VA_OPEN, VA_FIXEDARG, VA_CLOSE. - -2001-09-21 Bruno Haible <haible@clisp.cons.org> - - * arc-dis.c: Don't include <ctype.h>. - * openrisc-desc.c: Likewise. - * openrisc-ibld.c: Likewise. - -2001-09-20 Nick Clifton <nickc@cambridge.redhat.com> - - * fr30-opc.c: Fix compile time warning messages. - * i370-opc.c: Fix compile time warning messages. - * i960-dis.c: Fix compile time warning messages. - * m32r-asm.c: Fix compile time warning messages. - * m32r-desc.c: Fix compile time warning messages. - * m32r-dis.c: Fix compile time warning messages. - * m32r-ibld.c: Fix compile time warning messages. - * m32r-opc.c: Fix compile time warning messages. - * m32r-opinst.c: Fix compile time warning messages. - * ns32k-dis.c: Fix compile time warning messages. - * openrisc-asm.c: Fix compile time warning messages. - * openrisc-desc.c: Fix compile time warning messages. - * openrisc-dis.c: Fix compile time warning messages. - * openrisc-ibld.c: Fix compile time warning messages. - * openrisc-opc.c: Fix compile time warning messages. - * pdp11-dis.c: Fix compile time warning messages. - * tic54x-dis.c: Fix compile time warning messages. - * v850-opc.c: Fix compile time warning messages. - * vax-dis.c: Fix compile time warning messages. - * w65-opc.h: Fix compile time warning messages. - * z8k-opc.h: Fix compile time warning messages. - * z8kgen.c: Fix compile time warning messages. - -2001-09-19 Nick Clifton <nickc@cambridge.redhat.com> - - * arm-dis.c: Fix compile time warning messages. - * cgen-asm.c: Fix compile time warning messages. - * cgen-dis.c: Fix compile time warning messages. - * cris-dis.c: Fix compile time warning messages. - * d10v-dis.c: Fix compile time warning messages. - * fr30-asm.c: Fix compile time warning messages. - * fr30-desc.c: Fix compile time warning messages. - * fr30-dis.c: Fix compile time warning messages. - * fr30-ibld.c: Fix compile time warning messages. - -2001-09-18 Bruno Haible <haible@clisp.cons.org> - - * cgen-asm.c: Include "safe-ctype.h" instead of <ctype.h>. - (cgen_parse_keyword): Use ISALNUM instead of isalnum. - * cgen-opc.c: Include "safe-ctype.h" instead of <ctype.h>. - (cgen_keyword_lookup_name): Use ISALPHA/TOLOWER instead of - isalpha/tolower. - (cgen_keyword_add): Use ISALNUM instead of isalnum. - (hash_keyword_name): Use TOLOWER instead of tolower. - * fr30-asm.c: Include "safe-ctype.h" instead of <ctype.h>. - (parse_insn_normal): Use TOLOWER/ISSPACE instead of - tolower/isspace. - (fr30_cgen_assemble_insn): Use ISSPACE instead of isspace. - * fr30-desc.c: Don't include <ctype.h>. - * fr30-ibld.c: Likewise. - * ia64-gen.c: Include "safe-ctype.h" instead of <ctype.h>. - (load_insn_classes, parse_resource_users, load_depfile): Use - ISSPACE instead of isspace. - * m32r-asm.c: Include "safe-ctype.h" instead of <ctype.h>. - (parse_insn_normal): Use TOLOWER/ISSPACE instead of - tolower/isspace. - (m32r_cgen_assemble_insn): Use ISSPACE instead of isspace. - * m32r-desc.c: Don't include <ctype.h>. - * m32r-ibld.c: Likewise. - * openrisc-asm.c: Include "safe-ctype.h" instead of <ctype.h>. - (parse_insn_normal): Use TOLOWER/ISSPACE instead of - tolower/isspace. - (openrisc_cgen_assemble_insn): Use ISSPACE instead of isspace. - -2001-09-18 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * Makefile.am: Add rules and dependencies to create the s/390 opcode - table out of s390-opc.txt automatically. - * configure.in: Add BFD_CC_FOR_BUILD to allow CC_FOR_BUILD to be used. - * s390-mkopc.c (dumpTable): Change output to create a complete file. - * s390-opc.c: New improved opcode format macros and remove the - pregenerated opcode table. - * s390-opc.txt: Adapt to new improved opcode format macros. - -2001-09-14 David Schleef <ds@schleef.org> - - * ppc-opc.c (VXA, VXA_MASK): Fix mask bits. - -2001-09-04 Alan Modra <amodra@bigpond.net.au> - - * i386-dis.c (grps): Don't print the implicit al/ax/eax register - for opcode 0xf6 or 0xf7 forms of mul, imul, div, idiv insns. - -2001-08-31 Eric Christopher <echristo@redhat.com> - Jason Eckhardt <jle@redhat.com> - - * mips-dis.c: Add support for bfd_mach_mipsisa32 and - bfd_mach_mipsisa64. Remove bfd_mach_mips32, bfd_mach_mips32_4k, - bfd_mach_mips64. - -2001-08-31 Andreas Jaeger <aj@suse.de> - - * tic54x-opc.c: Add default initializers to avoid warnings. - - * arc-opc.c: Include "sysdep.h" to get stdio.h as include file. - * arc-ext.c: Likewise. - -2001-08-28 matthew green <mrg@redhat.com> - - * ppc-opc.c (icbt): Order correctly. - -2001-08-27 David Edelsohn <dje@watson.ibm.com> - Torbjorn Granlund <tege@swox.com> - - * ppc-opc.c (DS): Add PPC_OPERAND_DS flag. - (LS): Define. - (insert_ds): Complain if not a multiple of 4. - (XSYNC): Define. - (XSYNC_MASK): Define. - (powerpc_opcodes): Add "slbmte", "lwsync", "ptesync", "slbmfev", - "slbmfee". Modify "sync" to use XSYNC_MASK and LS. - -2001-08-26 Andreas Jaeger <aj@suse.de> - - * h8500-opc.h: Add default initializers to h8500_table to shut up - GCC warnings. - -2001-08-25 Andreas Jaeger <aj@suse.de> - - * tic54x-dis.c: Add unused attributes where needed. - - * z8k-dis.c (output_instr): Add unused attribute. - - * h8300-dis.c: Add missing prototypes. - (bfd_h8_disassemble): Make static. - - * cris-dis.c: Add missing prototype. - * h8500-dis.c: Likewise. - * m68hc11-dis.c: Likewise. - * pj-dis.c: Likewise. - * tic54x-dis.c: Likewise. - * v850-dis.c: Likewise. - * vax-dis.c: Likewise. - * w65-dis.c: Likewise. - * z8k-dis.c: Likewise. - - * d10v-dis.c: Add missing prototype. - (dis_long): Remove unused variable. - (dis_2_short): Likewise. - - * sh-dis.c: Add missing prototypes. - * v850-opc.c: Likewise. - Add unused attributes where needed. - - * ns32k-dis.c: Add missing prototypes. - (bit_extract_simple): Remove unused variable. - -2001-08-23 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * opcodes/s390-opc.c: Add "low or high" and "not low or high" - branch instructions for gcc 3.0. - * opcodes/s390-opc.txt: Likewise. - -2001-08-21 Andreas Jaeger <aj@suse.de> - - * i960-dis.c: Add parameters for prototypes - (ctrl): Add unused attributes. - (cobr): Likewise. - (put_abs): Likewise. - - * mips-dis.c: Add missing prototypes. - * a29k-dis.c: Likewise. - * arc-dis.c: Likewise. - * ia64-opc.c: Likewise. - - * s390-dis.c: Add missing prototypes. - (init_disasm): Remove unused attribute since the parameter is - used. - -2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-opc.c (M1): Define. Reformatted Code. - (mips_builtin_opcodes): Added performance counter opcodes mfpc, mfps, - mtps, mtps. Typo. - -2001-08-16 Jonathan Larmour <jlarmour@redhat.com> - - * mips-opc.c: R3900s can support all branch likely INSN_MACROs where - the corresponding non-likely insn is in MIPS I. - -2001-08-13 Kazu Hirata <kazu@hxi.com> - - * mcore-dis.c: Fix formatting. - * mips-dis.c: Likewise. - * pj-dis.c: Likewise. - * z8k-dis.c: Likewise. - -2001-08-12 Richard Henderson <rth@redhat.com> - - * cgen-ibld.in (extract_normal): Match type of VALUE and MASK - to *VALUEP. Regenerate all cgen files. - -2001-08-10 Richard Sandiford <rsandifo@redhat.com> - - * mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32 - argument. - * mips-opc.c (G6): Undefine. - (mips_builtin_opcodes): Remove gp32 entry for "move". Add macro - as the first "move" alternative. - -2001-08-10 Andreas Jaeger <aj@suse.de> - - * configure.in: Add -Wstrict-prototypes and -Wmissing-prototypes - to build warnings. - * configure: Regenerate. - -2001-08-10 Alan Modra <amodra@bigpond.net.au> - - * ppc-opc.c: Revert 2001-08-08. - -2001-08-09 Alan Modra <amodra@bigpond.net.au> - - * dis-buf.c (generic_strcat_address): Add missing prototype. - #if 0 the functions as it is unused. - -2001-08-08 Alan Modra <amodra@bigpond.net.au> - - 1999-10-25 Torbjorn Granlund <tege@swox.com> - * ppc-opc.c: Include "bfd.h". - (powerpc_operands): Add new field for reloc type. - -2001-07-21 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-dis.c (print_insn_arg): Don't use software integer registers - for coprocessor registers. - (get_mips_isa): Removed. - (is_newabi): New function, checks if NewABI is used. - (_print_insn_mips): Get distinction between old ABI and new ABI right. - -2001-08-01 Christian Groessler <cpg@aladdin.de> - - * z8kgen.c: Fixed indentation of opt[] array. Include stdio.h to - get stderr definition. - (internal, gas): Removed warnings. - (gas): Create a correct final entry for created array. - * z8k-opc.h: Recreated with new z8kgen. - -2001-07-28 Kazu Hirata <kazu@hxi.com> - - * i386-dis.c: Fix formatting. - -2001-07-28 Matthias Kramm <kramm@quiss.org> - - * i386-dis.c: Change formatting conventions for architecture - i386:intel to better match the format of various intel i386 - assemblers, like nasm, tasm or masm. - -2001-07-24 Alan Modra <amodra@bigpond.net.au> - - * Makefile.am: Update dependencies with "make dep-am". - * Makefile.in: Regenerate - -2001-07-24 Kazu Hirata <kazu@hxi.com> - - * alpha-dis.c: Fix formatting. - * cris-dis.c: Likewise. - * d10v-dis.c: Likewise. - * d30v-dis.c: Likewise. - * m10300-dis.c: Likewise. - * tic54x-dis.c: Likewise. - -2001-07-23 Kazu Hirata <kazu@hxi.com> - - * m68k-dis.c: Fix formatting. - * pj-dis.c: Likewise. - * s390-dis.c: Likewise. - * z8k-dis.c: Likewise. - -2001-07-21 Chris Demetriou <cgd@broadcom.com> - - * mips-opc.c (mips_builtin_opcodes): Sort c.le.s and c.lt.s - into the rest of the surrounding definitions. - -2001-07-18 Alan Modra <amodra@bigpond.net.au> - - * i386-dis.c (grps): Print l or w suffix, and require mem modrm - for lgdt, lidt, sgdt, sidt. - -2001-07-13 Philip Blundell <philb@gnu.org> - - * arm-dis.c (print_insn_arm): Use decimal for offsets in LDR/STR. - -2001-07-12 Jeff Johnston <jjohnstn@redhat.com> - - * cgen-asm.in: Include "xregex.h" always to enable the libiberty - regex support. - (@arch@_cgen_build_insn_regex): New routine from Graydon. - (@arch@_cgen_assemble_insn): Add Graydon's code to use regex - to verify if it is worth parsing the insn as insn "x". Also update - error message when insn is not a recognized format of the insn vs - when the insn is completely unrecognized. - -2001-07-11 Frank Ch. Eigler <fche@redhat.com> - - * cgen-dis.in (print_insn): Use cgen_get_insn_value instead of - bfd_get_bits. - * cgen-opc.c (cgen_get_insn_value, cgen_put_insn_value): Respect - non-zero CGEN_CPU_DESC->insn_chunk_bitsize. - -2001-07-09 Andreas Jaeger <aj@suse.de>, Karsten Keil <kkeil@suse.de> - - * i386-dis.c (set_op): Handle 64 bit and 32 bit mode. - (OP_J): Use bfd_vma for mask to work properly with 64 bits. - (op_address,op_riprel): Use bfd_vma to handle 64 bits. - -2001-07-05 Ben Elliston <bje@redhat.com> - - * Makefile.am (CPUDIR): Define. - (stamp-m32r): Update dependencies. - (stamp-fr30): Ditto. - (stamp-openrisc): Ditto. - * Makefile.in: Regenerate. - -2001-07-03 Zoltan Hidvegi <hzoli@hzoli.2y.net> - - * ppc-opc.c: Fix encoding of 'clf' instruction. - -2001-06-30 Geoffrey Keating <geoffk@redhat.com> - - * cgen-ibld.in (insert_normal): Support CGEN_IFLD_SIGN_OPT. - -2001-06-28 Geoffrey Keating <geoffk@redhat.com> - - * cgen-asm.c (cgen_parse_keyword): Allow any first character. - * cgen-opc.c (cgen_keyword_add): Ignore special first - character when building nonalpha_chars field. - -2001-06-24 Ben Elliston <bje@redhat.com> - - * m88k-dis.c: Format to conform to GNU coding standards. - -2001-06-23 Andreas Jaeger <aj@suse.de> - - * disassemble.c (disassembler_usage): Add unused attribute. - -2001-06-22 Eric Christopher <echristo@redhat.com> - - * mips-opc.c: Move prefx to start of the table. - -2001-06-22 Stacey Sheldon <ssheldon@Catena.com> - - * arc-opc.c (insert_st_syntax): Fix over-optimisation of ST - instruction. - -2001-06-22 Pauli <pauli@moreton.com.au> - - * m68k-opc.c: Add wdebug instruction. - -2001-06-15 Aldy Hernandez <aldyh@redhat.com> - - * m10300-opc.c (mn10300_opcodes): Change opcode for AM33 subc. - -2001-06-14 Geoffrey Keating <geoffk@redhat.com> - - * cgen-asm.c (cgen_parse_keyword): When looking for the - boundaries of a keyword, allow any special characters - that are actually in one of the allowed keyword. - * cgen-opc.c (cgen_keyword_add): Add any special characters - to the nonalpha_chars field. - -2001-06-12 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390-opc.c: Add lgh instruction. - * s390-opc.txt: Likewise. - -2001-06-11 Alan Modra <amodra@bigpond.net.au> - - * i386-dis.c: Group function prototypes in one place. - (FLOATCODE): Redefine as 1. - (USE_GROUPS): Redefine as 2. - (USE_PREFIX_USER_TABLE): Redefine as 3. - (X86_64_SPECIAL): Define as 4. - (GRP1b..GRPAMD): Move USE_GROUPS to bytecode1, index to bytecode2. - (PREGRP0..PREGRP26): Similarly with USE_PREFIX_USER_TABLE. - (dis386_att, dis386_intel, disx86_64_att, disx86_64_intel): Delete. - (dis386): New table combining above four tables. - (dis386_twobyte_att, dis386_twobyte_intel): Delete. - (dis386_twobyte): New table combining above two tables. - (x86_64_table): New table to handle x86_64. - (X86_64_0): Define. - (float_mem_att, float_mem_intel): Delet. - (float_mem): New table combining above two tables. - (print_insn_i386): Modify for above. - (dofloat): Likewise. - (putop): Handle '{', '|' and '}' to select alternative mnemonics. - Return 0 on success, 1 if no valid alternative. - (putop <case 'F'>, <case 'H'>): Print nothing for intel_syntax. - (putop <case 'T'>): Move to case 'U', and share case 'Q' code. - (putop <case 'I'>): Move to case 'T', and share case 'P' code. - (OP_REG <case rAX_reg .. rDI_reg>): Handle as for eAX_reg .. eDI_reg - if not 64-bit mode. - (OP_I <case q_mode>): Handle as for v_mode if not 64-bit mode. - (OP_I64): If not 64-bit mode, call OP_I. - OP_OFF64): If not 64-bit mode, call OP_OFF. - (OP_ST, OP_STi, OP_SEG, OP_DIR, OP_OFF, OP_OFF64, OP_MMX): Rename - 'ignore'/'ignored' to 'bytemode'. - -2001-06-10 Alan Modra <amodra@bigpond.net.au> - - * configure.in: Sort 'ta' case statement. - * configure: Regenerate. - - * i386-dis.c (dis386_att): Add 'H' to conditional branch and - loop,jcxz insns. - (disx86_64_att): Likewise. - (dis386_twobyte_att): Likewise. - (print_insn_i386): Don't print branch hints as a prefix. - (putop): 'H' macro prints branch hints. - (get64): Kill compile warnings. - -2001-06-09 Alexandre Oliva <aoliva@redhat.com> - - * sh-opc.h (sh_table): Don't use empty initializers. - -2001-06-06 Christian Groessler <cpg@aladdin.de> - - * z8k-dis.c: Fix formatting. - (unpack_instr): Remove unused cases in switch statement. Add - safety abort() in default case. - (unparse_instr): Add safety abort() in default case. - -2001-06-06 Peter Jakubek <pjak@snafu.de> - - * m68k-dis.c (print_insn_m68k): Fix typo. - * m68k-opc.c (m68k_opcodes): Correct allowed operands for - mcf (ColdFire) div, rem and moveb instructions. - -2001-06-06 Alan Modra <amodra@bigpond.net.au> - - * i386-dis.c (cond_jump_flag, loop_jcxz_flag): Define. - (cond_jump_mode, loop_jcxz_mode): Define. - (dis386_att): Add cond_jump_flag and loop_jcxz_flag as - appropriate, and 'F' suffix to loop insns. - (disx86_64_att): Likewise. - (dis386_twobyte_att): Likewise. - (print_insn_i386): Don't output addr prefix for loop, jcxz insns. - Output data size prefix for long conditional jumps. Output cs and - ds branch hints. - (putop): Handle 'F', and mark PREFIX_ADDR used for case 'E'. - (OP_J): Don't make PREFIX_DATA used. - -2001-06-04 Alexandre Oliva <aoliva@redhat.com> - - * sh-opc.h (sh_table): Complete last element entry to avoid - compiler warning. - -2001-05-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-dis.c (mips_isa_type): Add MIPS r12k support. - -2001-05-23 Alan Modra <amodra@one.net.au> - - * arc-opc.c: Whitespace changes. - -2001-05-18 Hans-Peter Nilsson <hp@axis.com> - - * cris-opc.c (cris_spec_regs): Add missing initializer field for - last element. - -2001-05-15 Frank Ch. Eigler <fche@redhat.com> - - * cgen-dis.in (extract_normal): Complete support for min<base case. - -2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> - - * mips-dis.c (INSNLEN): Rename MAXLEN. - (std_reg_names): Replace by mips32_reg_names and mips64_reg_names. - (print_insn_arg): Remove $ prefix of register names. - (set_mips_isa_type): Remove. - (mips_isa_type): New function. - (get_mips_isa): New Function. - (print_insn_mips): Rename _print_insn_mips. - (_print_insn_mips): New function, contains code which was - duplicated in print_insn_big_mips and print_insn_little_mips. - (print_insn_big_mips): Moved code to _print_insn_mips. - (print_insn_little_mips): Likewise. - (print_mips16_insn_arg): Remove $ prefix of register names. - Print error message before abort. - -2001-05-14 J.T. Conklin <jtc@redback.com> - - * ppc-opc.c (powerpc_opcodes): Fixed extended opcode field of - simplified mnemonics used for setting PPC750-specific special - purpose registers. + 2004-03-08 Nick Clifton <nickc@redhat.com> + * po/de.po: Updated German translation. -2001-05-12 H.J. Lu <hjl@gnu.org> + 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com> + * sh-opc.h: Move fsca and fsrra instructions from sh4a to sh4. + Also correct mistake in the comment. - * i386-dis.c (print_insn_i386): Always set `mod', `reg' and - `rm'. + 2004-02-26 Andrew Stubbs <andrew.stubbs@superh.com> + * sh-dis.c (print_insn_sh): Add REG_N_D nibble type to + ensure that double registers have even numbers. + Add REG_N_B01 for nn01 (binary 01) nibble to ensure + that reserved instruction 0xfffd does not decode the same + as 0xfdfd (ftrv). + * sh-opc.h: Add REG_N_D nibble type and use it whereever + REG_N refers to a double register. + Add REG_N_B01 nibble type and use it instead of REG_NM + in ftrv. + Adjust the bit patterns in a few comments. -2001-05-12 Peter Targett <peter.targett@arccores.com> +2004-04-08 Alan Modra <amodra@bigpond.net.au> - * arc-opc.c (arc_reg_names): Correct attribute for lp_count - register to r/w. Formatting fixes throughout file. + Apply from mainline. + 2004-02-25 Aldy Hernandez <aldyh@redhat.com> + * ppc-opc.c (powerpc_opcodes): Change mask for dcbt and dcbtst. -2001-05-12 Alan Modra <amodra@one.net.au> + 2004-02-20 Aldy Hernandez <aldyh@redhat.com> + * ppc-opc.c (powerpc_opcodes): Move mfmcsrr0 before mfdc_dat. - * i386-dis.c (prefix_user_table): Correct movq2dq, movdq2q, and - movq operands. - (twobyte_has_modrm): Update table. - (need_modrm): Give it file scope. - (MODRM_CHECK): Define. - (dofloat): Use MODRM_CHECK. - (OP_E): Likewise. - (OP_EM): Likewise. - (OP_EX): Likewise. + 2004-02-20 Aldy Hernandez <aldyh@redhat.com> + * ppc-opc.c (powerpc_opcodes): Add m*ivor35. -2001-05-07 Frank Ch. Eigler <fche@redhat.com> + 2004-02-20 Aldy Hernandez <aldyh@redhat.com> + * ppc-opc.c (powerpc_opcodes): Add mfivor32, mfivor33, mfivor34, + mtivor32, mtivor33, mtivor34. - * cgen-dis.in (default_print_insn): Tolerate min<base instructions - even at end of a section. - * cgen-ibld.in (extract_normal): Tolerate min!=base!=max instructions - by ignoring precariously-unpacked insn_value in favor of raw buffer. + 2004-02-19 Aldy Hernandez <aldyh@redhat.com> + * ppc-opc.c (powerpc_opcodes): Add mfmcar. -2001-05-03 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> +2004-03-15 Aldy Hernandez <aldyh@redhat.com> + + * ppc-opc.c (powerpc_opcodes): Add BOOKE versions of mfsprg. - * disassemble.c (disassembler_usage): Remove unused attribute. +2004-03-16 Alan Modra <amodra@bigpond.net.au> -2001-05-04 Frank Ch. Eigler <fche@redhat.com> + * ppc-dis.c (print_insn_powerpc): Don't print tabs. Handle + PPC_OPERANDS_GPR_0. + * ppc-opc.c (RA0): Define. + (RAQ, RAL, RAM, RAS, RSQ, RTQ, RSO): Use PPC_OPERAND_GPR_0. + (RAOPT): Rename from RAO. Update all uses. + (powerpc_opcodes): Use RA0 as appropriate. - * m32r-dis.c, -asm.c, -ibld.c: Regenerated with disassembler fixes. +2004-03-15 Alan Modra <amodra@bigpond.net.au> -2001-05-04 Frank Ch. Eigler <fche@redhat.com> + * sparc-dis.c (print_insn_sparc): Update getword prototype. - * cgen-dis.in (print_insn): Remove call to read_insn. Instead, - assume incoming buffer already has the base insn loaded. Handle - smaller-than-base instructions for variable-length case. +2004-03-13 Alan Modra <amodra@bigpond.net.au> -2001-05-04 Alan Modra <amodra@one.net.au> + Apply the following patches from mainline + 2004-03-12 Michal Ludvig <mludvig@suse.cz> + * i386-dis.c (GRPPLOCK): Delete. + (grps): Delete GRPPLOCK entry. - * i386-dis.c (Ev, Ed): Remove duplicate define. - (Gd): Define. - (XS): Define. - (OP_XS): New function. - (dis386_twobyte_att): Correct pinsrw, pextrw, pmovmskb, and - movmskp operands. - (dis386_twobyte_intel): Likewise. - (prefix_user_table): Use MS for maskmovq operand. + 2004-03-12 Alan Modra <amodra@bigpond.net.au> + * i386-dis.c (OP_M, OP_0f0e, OP_0fae, NOP_Fixup): New functions. + (M, Mp): Use OP_M. + (None, PADLOCK_SPECIAL, PADLOCK_0): Delete. + (GRPPADLCK): Define. + (dis386): Use NOP_Fixup on "nop". + (dis386_twobyte): Use GRPPADLCK on opcode 0xa7. + (twobyte_has_modrm): Set for 0xa7. + (padlock_table): Delete. Move to.. + (grps): ..here, using OP_0f07. Use OP_Ofae on lfence, mfence + and clflush. + (print_insn): Revert PADLOCK_SPECIAL code. + (OP_E): Delete sfence, lfence, mfence checks. -2001-04-27 Johan Rydberg <jrydberg@opencores.org> + 2004-03-12 Jakub Jelinek <jakub@redhat.com> + * i386-dis.c (grps): Use INVLPG_Fixup instead of OP_E for invlpg. + (INVLPG_Fixup): New function. + (PNI_Fixup): Remove ATTRIBUTE_UNUSED from sizeflag. - * Makefile.am: Add OpenRISC target. - * Makefile.in: Regenerated. + 2004-03-12 Alan Modra <amodra@bigpond.net.au> + * i386-dis.c (grps): Use clflush by default for 0x0fae/7. + (OP_E): Twiddle clflush to sfence here. - * disassemble.c (disassembler): Recognize the OpenRISC disassembly. +2004-03-12 Michal Ludvig <mludvig@suse.cz> - * configure.in (bfd_openrisc_arch): Add target. - * configure: Regenerated. + * i386-dis.c (PADLOCK_SPECIAL, PADLOCK_0): New defines. + (dis386_twobyte): Opcode 0xa7 is PADLOCK_0. + (padlock_table): New struct with PadLock instructions. + (print_insn): Handle PADLOCK_SPECIAL. - * openrisc-asm.c: New file. - * openrisc-desc.c: Likewise. - * openrisc-desc.h: Likewise. - * openrisc-dis.c: Likewise. - * openrisc-ibld.c: Likewise. - * openrisc-opc.c: Likewise. - * openrisc-opc.h: Likewise. +2004-02-10 Petko Manolov <petkan@nucleusys.com> -2001-04-24 Christian Groessler <cpg@aladdin.de> + * arm-opc.h Maverick accumulator register opcode fixes. - * z8k-dis.c: add names of control registers (ctrl_names); - (seg_length): provides instruction length fixup for segmented - mode; (unpack_instr): correctly handle ARG_DISP16, ARG_DISP12, - CLASS_0DISP7, CLASS_1DISP7, CLASS_DISP8 and CLASS_PR cases; - (unparse_intr): handle CLASS_PR, print addresses without '#' - * z8k-opc.h: re-created with new z8kgen - * z8kgen.c: merged in fixes which were in existing z8k-opc.h; new - entries for ldctl/ldctlb instruction +2004-02-13 Ben Elliston <bje@wasabisystems.com> -2001-04-06 Andreas Jaeger <aj@suse.de> - - * i386-dis.c: Add ffreep instruction. - -2001-03-30 Alexandre Oliva <aoliva@redhat.com> - - * ppc-opc.c (insert_mbe): Shift mask initializer as long. - -2001-03-24 Alan Modra <alan@linuxcare.com.au> - - * i386-dis.c (PREGRP25): Define. - (dis386_twobyte_att): Use here in place of "movntq" entry. - (dis386_twobyte_intel): Likewise. - (prefix_user_table): Add PREGRP25 entry for "movntq" and "movntdq". - (PREGRP26): Define. - (dis386_twobyte_att): Use here. - (dis386_twobyte_intel): Likewise. - (prefix_user_table): Add PREGRP26 entry for "punpcklqdq". - (prefix_user_table <maskmovdqu>): XM operand, not MX. - (prefix_user_table): Cosmetic changes to "bad" entries. - -2001-03-23 Nick Clifton <nickc@redhat.com> - - * mips-opc.c: Remove extraneous whitespace. - * mips-dis.c: Remove extraneous whitespace. - -2001-03-22 Ben Elliston <bje@redhat.com> - - * cgen-asm.in (@arch@_cgen_assemble_insn): Move tmp_errmsg - declaration inside CGEN_VERBOSE_ASSEMBLER_ERRORS conditional. - * cgen-ibld.in (put_insn_int_value): Mark cd parameter as unused - to allay a compiler warning. - -2001-03-22 Alan Modra <alan@linuxcare.com.au> - - * i386-dis.c (dis386_twobyte_att): Add entries for paddq, psubq. - (dis386_twobyte_intel): Likewise. - (twobyte_has_modrm): Set entry for paddq, psubq. - -2001-03-20 Patrick Macdonald <patrickm@redhat.com> - - * cgen-dis.in (print_insn_@arch@): Add support for target machine - determination via CGEN_COMPUTE_MACH. - * fr30-desc.c: Regenerate. - * fr30-dis.c: Regenerate. - * fr30-opc.h: Regenerate. - * m32r-desc.c: Regenerate. - * m32r-dis.c: Regenerate. - * m32r-opc.h: Regenerate. - * m32r-opinst.c: Regenerate. - -2001-03-20 H.J. Lu <hjl@gnu.org> - - * configure.in: Remove the redundent AC_ARG_PROGRAM. - * configure: Rebuild. - -2001-03-19 Jim Wilson <wilson@redhat.com> - - * ia64-gen.c (fetch_insn_class): If xsect, then ignore comment and - notestr if larger than xsect. - (in_class): Handle format M5. - * ia64-asmtab.c: Regnerate. - -2001-03-19 John David Anglin <dave@hiauly1.hia.nrc.ca> - - * vax-dis.c (print_insn_vax): Only fetch two bytes if the info buffer - has more than one byte left to read. - -2001-03-16 Martin Schwidefsky <schwidefsky@de.ibm.com> - - * s390-opc.c: Add new opcodes. Smooth out formatting. - * s390-opc.txt: Add new opcodes. - -2001-03-06 Nick Clifton <nickc@redhat.com> - - * arm-dis.c (print_insn_thumb): Compute destination address - of BLX(1) instruction by taking bit 1 from PC and not from bit - 0 of the offset. - -2001-03-06 Igor Shevlyakov <igor@windriver.com> - - * m68k-dis.c (print_insn_m68k): Recognize Coldfire CPUs - so command line switches will work. - -2001-03-05 Dave Brolley <brolley@redhat.com> - - * fr30-asm.c: Regenerate. - * fr30-desc.c: Regenerate. - * fr30-desc.h: Regenerate. - * fr30-dis.c: Regenerate. - * fr30-ibld.c: Regenerate. - * fr30-opc.c: Regenerate. - * fr30-opc.h: Regenerate. - * m32r-asm.c: Regenerate. - * m32r-desc.c: Regenerate. - * m32r-desc.h: Regenerate. * m32r-dis.c: Regenerate. - * m32r-ibld.c: Regenerate. - * m32r-opc.c: Regenerate. - * m32r-opc.h: Regenerate. - * m32r-opinst.c: Regenerate. - -2001-02-28 Igor Shevlyakov <igor@windriver.com> - - * m68k-opc.c: fix cpushl according to Motorola. Enable - bunch of instructions for Coldfire 5407 and add all new. - -2001-02-27 Alan Modra <alan@linuxcare.com.au> - - * configure.in (BFD_VERSION): Do without grep. - * configure: Regenerate. - * Makefile.am: Run "make dep-am". - * Makefile.in: Regenerate. - -2001-02-23 David Mosberger <davidm@hpl.hp.com> - - * ia64-opc-a.c: Add missing pseudo-ops for "cmp" and "cmp4". - * ia64-asmtab.c: Regenerate. - -2001-02-21 David Mosberger <davidm@hpl.hp.com> - - * ia64-opc-d.c (ia64_opcodes_d): Break the "add" pattern into two - separate variants: one for IMM22 and the other for IMM14. - * ia64-asmtab.c: Regenerate. - -2001-02-21 Greg McGary <greg@mcgary.org> - - * cgen-opc.c (cgen_get_insn_value): Add missing `return'. - -2001-02-20 H.J. Lu <hjl@gnu.org> - - * Makefile.am (ia64-ic.tbl): Remove the target. - (ia64-raw.tbl): Likewise. - (ia64-waw.tbl): Likewise. - (ia64-war.tbl): Likewise. - (ia64-asmtab.c): Generate it in the source directory. - * Makefile.in: Regenerated. - -2001-02-18 lars brinkhoff <lars@nocrew.org> - - * Makefile.am: Add PDP-11 target. - * configure.in: Likewise. - * disassemble.c: Likewise. - * pdp11-dis.c: New file. - * pdp11-opc.c: New file. - -2001-02-14 Jim Wilson <wilson@redhat.com> - - * ia64-ic.tbl: Update from Intel. Add setf to fr-writers. - * ia64-asmtab.c: Regenerate. - -Mon Feb 12 17:41:26 CET 2001 Jan Hubicka <jh@suse.cz> - - * i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison - instructions. - (putop): Handle 'Y' -2001-02-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl> +2004-01-27 Michael Snyder <msnyder@redhat.com> - * mips-dis.c (print_insn_arg): Use top four bits of the address of - the following instruction not of the jump itself for the jump - target. - (print_mips16_insn_arg): Likewise. + * sh-opc.h (sh_table): "fsrra", not "fssra". -2001-02-11 Michael Sokolov <msokolov@ivan.Harhan.ORG> +2004-01-23 Andrew Over <andrew.over@cs.anu.edu.au> - * Makefile.am (stamp-lib): ranlib the libopcodes.a in the build - directory. - * Makefile.in: Regenerate. - -2001-02-09 Schwidefsky <schwidefsky@de.ibm.com> - - * Makefile.am: Add linux target for S/390. - * Makefile.in: Likewise. - * configure.in: Likewise. - * disassemble.c: Likewise. - * s390-dis.c: New file. - * s390-mkopc.c: New file. - * s390-opc.c: New file. - * s390-opc.txt: New file. - -2001-02-05 Jim Wilson <wilson@redhat.com> - - * ia64-asmtab.c: Revert 2000-12-16 change. - -2001-02-02 Patrick Macdonald <patrickm@redhat.com> - - * fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS. - * m32r-desc.h: Regenerate. - -Thu Feb 1 16:29:06 MET 2001 Jan Hubicka <jh@suse.cz> - - * i386-dis.c (dis386_att, grps): Use 'T' for push/pop - (putop): Handle 'T', alphabetize order, fix 'I' handling in Intel syntax - -2001-01-14 Alan Modra <alan@linuxcare.com.au> - - * hppa-dis.c (print_insn_hppa): Handle '>' and '<' arg types. - -2001-01-13 Nick Clifton <nickc@redhat.com> - - * disassemble.c: Remove spurious white space. + * sparc-opc.c (fdtox, fstox, fqtox, fxtod, fxtos, fxtoq): Tighten + contraints. -Sat Jan 13 01:48:24 MET 2001 Jan Hubicka <jh@suse.cz> +2004-01-19 Andrew Over <andrew.over@cs.anu.edu.au> - * i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret - templates. + * sparc-opc.c (sparc_opcodes) <f[dsq]tox, fxto[dsq]>: Fix args. -2001-01-11 Peter Targett <peter.targett@arccores.com> +2004-01-19 Alan Modra <amodra@bigpond.net.au> - * configure.in: Add arc-ext.lo for bfd_arc_arch selection. - * Makefile.am (C_FILES): Add arc-ext.c. - (ALL_MACHINES) Add arc-ext.lo. - (INCLUDES) Add opcode directory to list. - New dependency entry for arc-ext.lo. - * disassemble.c (disassembler): Correct call to - arc_get_disassembler. - * arc-opc.c: New update for ARC, including full base - instructions for ARC variants. - * arc-dis.h, arc-dis.c: New update for ARC, including - extensibility functionality. - * arc-ext.h, arc-ext.c: New files for handling extensibility. + * i386-dis.c (OP_E): Print scale factor on intel mode sib when not + 1. Don't print scale factor on AT&T mode when index missing. -2001-01-10 Jan Hubicka <jh@suse.cz> +2004-01-16 Alexandre Oliva <aoliva@redhat.com> - * i386-dis.c (PREGRP15 - PREGRP24): New. - (dis386_twobyt): Add SSE2 instructions. - (twobyte_uses_SSE_prefix: Rename from ... ; add new SSE instructions. - (twobyte_uses_f3_prefix): ... this one. - (grps): Add SSE instructions. - (prefix_user_table): Add two new slots; add SSE2 instructions. - (print_insn_i386): Rename uses_f3_prefix to uses_SSE_prefix; - Handle the REPNZ and Data16 prefixes as well; do proper lookup - to prefix_user_table. - (OP_E): Accept mfence and lfence as well. - (OP_MMX): Data16 prefix turns MMX to SSE; support REX extensions. - (OP_XMM): Support REX extensions. - (OP_EM): Likewise. - (OP_EX): Likewise. + * m10300-opc.c (mov): 8- and 24-bit immediates are zero-extended + when loaded into XR registers. -2001-01-09 Nick Clifton <nickc@redhat.com> +2004-01-14 Richard Sandiford <rsandifo@redhat.com> - * arm-dis.c (print_insn): Set pc to zero for instructions with - a reloc associated with them. + * frv-desc.h: Regenerate. + * frv-desc.c: Regenerate. + * frv-opc.c: Regenerate. -2001-01-09 Jeff Johnston <jjohnstn@redhat.com> +2004-01-13 Michael Snyder <msnyder@redhat.com> - * cgen-asm.in (parse_insn_normal): Changed syn to be - CGEN_SYNTAX_CHAR_TYPE. Changed all references to *syn - as character to use CGEN_SYNTAX_CHAR macro and all comparisons - to '\0' to use 0 instead. - * cgen-dis.in (print_insn_normal): Ditto. - * cgen-ibld.in (insert_insn_normal, extract_insn_normal): Ditto. + * sh-dis.c (print_insn_sh): Allocate 4 bytes for insn. -2001-01-05 Jan Hubicka <jh@suse.cz> +2004-01-09 Paul Brook <paul@codesourcery.com> - * i386-dis.c: Add x86_64 support. - (rex): New static variable. - (REX_MODE64, REX_EXTX, REX_EXTY, REX_EXTZ): New constants. - (USED_REX): New macro. - (Ev, Ed, Rm, Iq, Iv64, Cm, Dm, Rm*, Ob64, Ov64): New macros. - (OP_I64, OP_OFF64, OP_IMREG): New functions. - (OP_REG, OP_OFF): Declare. - (get64, get32, get32s): New functions. - (r??_reg): New constants. - (dis386_att): Change templates of instruction implicitly promoted - to 64bit; change e?? to RMe?? for unwind RM byte instructions. - (grps): Likewise. - (dis386_intel): Likewise. - (dixx86_64_att): New table based on dis386_att. - (dixx86_64_intel): New table based on dis386_intel. - (names64, names8rex): New global variable. - (names32, names16): Add extended registers. - (prefix_user_t): Recognize rex prefixes. - (prefix_name): Print REX prefixes nicely. - (op_riprel): New global variable. - (start_pc): Set type to bfd_vma. - (print_insn_i386): Detect the 64bit mode and use proper table; - move ckprefix after initializing the buffer; output unused rex prefixes; - output information about target of RIP relative addresses. - (putop): Support 'O' and 'I'. Update handling of "P', 'Q', 'R' and 'S'; - (print_operand_value): New function. - (OP_E, OP_G, OP_REG, OP_I, OP_J, OP_DIR, OP_OFF, OP_D): Add support for - REX prefix and new modes. - (get64, get32s): New. - (get32): Return bfd_signed_vma type. - (set_op): Initialize the op_riprel. - * disassemble.c (disassembler): Recognize the x86-64 disassembly. + * arm-opc.h (arm_opcodes): Move generic mcrr after known + specific opcodes. -2001-01-03 Richard Sandiford <r.sandiford@redhat.com> - - cgen-dis.in (read_insn): Use bfd_get_bits() - -2001-01-02 Richard Sandiford <rsandifo@redhat.com> - - * cgen-dis.c (hash_insn_array): Use bfd_put_bits(). - (hash_insn_list): Likewise - * cgen-ibld.in (insert_1): Use bfd_put_bits() and bfd_get_bits(). - (extract_1): Use bfd_get_bits(). - (extract_normal): Apply sign extension to both extraction - methods. - * cgen-opc.c (cgen_get_insn_value): Use bfd_get_bits() - (cgen_put_insn_value): Use bfd_put_bits() - -2000-12-28 Frank Ch. Eigler <fche@redhat.com> - - * cgen-asm.in (parse_insn_normal): Print better error message for - instructions with missing operands. - -2000-12-21 Santeri Paavolainen <santtu@ssh.com> - - * cgen-opc.c: Include alloca.h if HAVE_ALLOCA_H is defined. - -2000-12-16 Nick Clifton <nickc@redhat.com> +2004-01-07 Daniel Jacobowitz <drow@mvista.com> + * Makefile.am (libopcodes_la_DEPENDENCIES) + (libopcodes_la_LIBADD): Revert 2003-05-17 change. Add explanatory + comment about the problem. * Makefile.in: Regenerate. - * aclocal.m4: Regenerate. - * config.in: Regenerate. - * configure.in: Add spacing. - * configure: Regenerate. - * ia64-asmtab.c: Regenerate. - * po/opcodes.pot: Regenerate. - -2000-12-12 Frank Ch. Eigler <fche@redhat.com> - - * cgen-asm.in (@arch@_cgen_assemble_insn): Prefer printing insert-time - error messages over later parse-time ones. - -2000-12-12 Jim Wilson <wilson@redhat.com> - - * ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode - argument. - * ia64-gen.c (insert_deplist): Cast sizeof result to int. - (print_dependency_table): Print NULL if semantics field not set. - (insert_opcode_dependencies): Mark cmp parameter as unused. - (print_main_table): Use fprintf_vma to print long long fields. - (main): Mark argv paramter as unused. Convert to old style definition. - * ia64-opc.c (ia64_find_dependency): Cast sizeof result to int. - * ia64-asmtab.c: Regnerate. - -2000-12-09 Nick Clifton <nickc@redhat.com> - - * m32r-dis.c (print_insn): Prevent re-read of instruction from - wrong address. - - * fr30-dis.c: Regenerate. - -2000-12-08 Peter Targett <peter.targett@arccores.com> - - * configure.in: Add arc-ext.lo for bfd_arc_arch selection. - * Makefile.am (C_FILES): Add arc-ext.c. - (ALL_MACHINES) Add arc-ext.lo. - (INCLUDES) Add opcode directory to list. - New dependency entry for arc-ext.lo. - * disassemble.c (disassembler): Correct call to - arc_get_disassembler. - * arc-opc.c: New update for ARC, including full base - instructions for ARC variants. - * arc-dis.h, arc-dis.c: New update for ARC, including - extensibility functionality. - * arc-ext.h, arc-ext.c: New files for handling extensibility. - -2000-12-03 Chris Demetriou cgd@sibyte.com - - * mips-opc.c (mips_builtin_opcodes): Use the WR_HILO, RD_HILO, - MOD_HILO, and MOD_LO macros. - - * mips-opc.c (M1, M2): Delete. - (mips_builtin_opcodes): Remove all uses of M1. - - * mips-opc.c (mips_builtin_opcodes): Make the dmfc2 and dmtc2 - instructions take "G" format second operands and use the - correct flags. - There are mfc3 and mtc3 opcodes, so add dmfc3 and dmtc3 opcodes to - match. - Delete "sel" code operands from mfc1 and mtc1. - Add MIPS64 opcode changes (dclo, dclz), and "sel" code variants - for dm[ft]c[023]. - -2000-12-03 Ed Satterthwaite ehs@sibyte.com and - Chris Demetriou cgd@sibyte.com - - * mips-opc.c (mips_builtin_opcodes): Finish additions - for MIPS32 support, and clean up existing entries for - aesthetics, consistency with the MIPS32 ISA, and - with consistency the rest of the table. - -2000-12-01 Nick Clifton <nickc@redhat.com> - - * mips16-opc.c (mips16_opcodes): Add initialiser for membership - field. - -2000-12-01 Chris Demetriou <cgd@sibyte.com> - - mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument - specifiers. Update 'B' for new constant names, and remove - 'm'. - mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop" - near the top of the array, so they are disassembled properly. - Enable "ssnop" for MIPS32. Add "break" variant with 20 bit - code for MIPS32. Update "clo" and "clz" to use 'U' operand - specifier. Add 'H' format specifier variants for "mfc1," - "mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32. Update - MIPS32 "sdbbp" to use 'B' operand specifier. Add MIPS32 - "wait" variant which uses 'J' operand specifier. - - * mips-dis.c (set_mips_isa_type): Update to use - CPU_UNKNOWN and ISA_* constants. Add bfd_mach_mips32 case. - Replace bfd_mach_mips4K with bfd_mach_mips32_4k case. - * mips-opc.c (I32): New constant for instructions added in - MIPS32. - (P4): Delete. - (mips_builtin_opcodes) Replace all uses of P4 with I32. - - * mips-dis.c (set_mips_isa_type): Add cases for - bfd_mach_mips5 and bfd_mach_mips64. - * mips-opc.c (I64): New definitions. - - * mips-dis.c (set_mips_isa_type): Add case for - bfd_mach_mips_sb1. - -2000-11-28 Hans-Peter Nilsson <hp@bitrange.com> - - * sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned. - (print_insn_ppi): Make nib1, nib2, nib3 unsigned. - Initialize variable dc to NULL. - (print_insn_shx): Remove unused label d_reg_n. - -2000-11-24 Nick Clifton <nickc@redhat.com> - - * arm-opc.h: Add new opcode formatting parameter 'B'. - (arm_opcodes): Add XScale, v5, and v5te instructions. - (thumb_opcodes): Add v5t instructions. - - * arm-dis.c (print_insn_arm): Handle new 'B' format - parameter. - (print_insn_thumb): Decode BLX(1) instruction. - -2000-11-21 Chris Demetriou <cgd@sibyte.com> - - * mips-opc.c: Fix file header comment. - -2000-11-14 Hans-Peter Nilsson <hp@axis.com> - - * cris-dis.c (cris_get_disassembler): If abfd is NULL, return - print_insn_cris_with_register_prefix. - -2000-11-11 Alexandre Oliva <aoliva@redhat.com> - - * sh-opc.h: The operand of `mov.w r0, (<disp>,GBR)' is IMM1, not 0. - -2000-11-07 Matthew Green <mrg@redhat.com> - - * cgen-dis.in (print_insn): All insns which can fit into insn_value - must be loaded there in their entirety. - -2000-10-20 Jakub Jelinek <jakub@redhat.com> - - * sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs. - (compute_arch_mask): Add v8plusb and v9b machines. - (print_insn_sparc): siam mode decoding, accept ASRs up to 25. - * sparc-opc.c: Support for Cheetah instruction set. - (prefetch_table): Add #invalidate. - -2000-10-16 Nick Clifton <nickc@redhat.com> - - * mcore-dis.c (imsk): Change mask for OC to 0xFE00. - -2000-10-06 Dave Brolley <brolley@redhat.com> - - * fr30-desc.h: Regenerate. - * m32r-desc.h: Regenerate. - * m32r-ibld.c: Regenerate. - -2000-10-05 Jim Wilson <wilson@redhat.com> - - * ia64-ic.tbl: Update from Intel. - * ia64-asmtab.c: Regenerate. - -2000-10-04 Kazu Hirata <kazu@hxi.com> - - * ia64-gen.c: Convert C++-style comments to C-style comments. - * tic54x-dis.c: Likewise. - -2000-09-29 Hans-Peter Nilsson <hp@axis.com> - - Changes to add dollar prefix to registers for files where user symbols - don't have a leading underscore. Fix formatting. - * cris-dis.c (REGISTER_PREFIX_CHAR): New. - (format_reg): Add parameter with_reg_prefix. All callers changed. - (print_with_operands): Ditto. - (print_insn_cris_generic): Renamed from print_insn_cris, add - parameter with_reg_prefix. - (print_insn_cris_with_register_prefix, - print_insn_cris_without_register_prefix, cris_get_disassembler): - New. - * disassemble.c (disassembler) [ARCH_cris]: Call cris_get_disassembler. - -2000-09-22 Jim Wilson <wilson@redhat.com> - - * ia64-opc-f.c (ia64_opcodes_f): Add fpcmp pseudo-ops for - gt, ge, ngt, and nge. - * ia64-asmtab.c: Regenerate. - - * ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change. - * ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP. - (lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62". - * ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update. - * ia64-asmtab.c: Regnerate. - -2000-09-13 Anders Norlander <anorland@acc.umu.se> - - * mips-opc.c (mips_builtin_opcodes): Support cache instruction on 4K cores. - Add mfc0 and mtc0 with sub-selection values. - Add clo and clz opcodes. - Add msub and msubu instructions for MIPS32. - Add madd/maddu aliases for mad/madu for MIPS32. - Support wait, deret, eret, movn, pref for MIPS32. - Support tlbp, tlbr, tlbwi, tlbwr. - (P4): New define. - - * mips-dis.c (print_insn_arg): Print sdbbp 'm' args. - (print_insn_arg): Handle 'H' args. - (set_mips_isa_type): Recognize 4K. - Use CPU_* defines instead of hardcoded numbers. - -2000-09-11 Catherine Moore <clm@redhat.com> - - * d30v-opc.c (d30v_operand_t): New operand type Rb2. - (d30v_format_tab): Use Rb2 for modinc and moddec. - -2000-09-07 Catherine Moore <clm@redhat.com> - - * d30v-opc.c (d30v_format_tab): Use format Ra for - modinc and moddec. - -2000-09-06 Alexandre Oliva <aoliva@redhat.com> - - * configure: Rebuilt with new libtool.m4. - -2000-09-05 Nick Clifton <nickc@redhat.com> - - * configure: Regenerate. - * po/opcodes.pot: Regenerate. - -2000-08-31 Alexandre Oliva <aoliva@redhat.com> - - * acinclude.m4: Include libtool and gettext macros from the - top level. - * aclocal.m4, configure: Rebuilt. - -2000-08-30 Kazu Hirata <kazu@hxi.com> - - * tic80-dis.c: Fix formatting. - -2000-08-29 Kazu Hirata <kazu@hxi.com> - - * w65-dis.c: Fix formatting. - -2000-08-28 Mark Hatle <mhatle@mvista.com> - - * ppc-opc.c: Add XTLB macro for a few PPC 4xx extended mnemonics. - (powerpc_opcodes): Add table entries for PPC 405 instructions. - Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403 - instructions. Added extended mnemonic mftbl as defined in the - 405GP manual for all PPCs. - -2000-08-28 Jim Wilson <wilson@redhat.com> - - * ia64-dis.c (print_insn_ia64): Add failed label after ia64_free_opcode - call. Change last goto to use failed instead of done. - -2000-08-28 Dave Brolley <brolley@redhat.com> - - * cgen-ibld.in (cgen_put_insn_int_value): New function. - (insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P. - (insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P. - (extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P. - * cgen-dis.in (read_insn): New static function. - (print_insn): Use read_insn to read the insn into the buffer and set - up for disassembly. - (print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is - in the buffer. - * fr30-asm.c: Regenerated. - * fr30-desc.c: Regenerated. - * fr30-desc.h: Regenerated. - * fr30-dis.c: Regenerated. - * fr30-ibld.c: Regenerated. - * fr30-opc.c: Regenerated. - * fr30-opc.h: Regenerated. - * m32r-asm.c: Regenerated. - * m32r-desc.c: Regenerated. - * m32r-desc.h: Regenerated. - * m32r-dis.c: Regenerated. - * m32r-ibld.c: Regenerated. - * m32r-opc.c: Regenerated. - -2000-08-28 Kazu Hirata <kazu@hxi.com> - - * tic30-dis.c: Fix formatting. - -2000-08-27 Kazu Hirata <kazu@hxi.com> - - * sh-dis.c: Fix formatting. - -2000-08-24 David Edelsohn <dje@watson.ibm.com> - - * ppc-opc.c (powerpc_opcodes): Add rfid, mtsrd, mtsrdin, mtmsrd. - -2000-08-24 Kazu Hirata <kazu@hxi.com> - - * z8k-dis.c: Fix formatting. - -2000-08-16 Jim Wilson <wilson@redhat.com> - - * ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete - break, mov-immediate, nop. - * ia64-opc-f.c: Delete fpsub instructions. - * ia64-opc-m.c: Add POSTINC to all instructions with postincrement - address operand. Rewrite using macros to avoid long lines. - * ia64-opc.h (POSTINC): Define. - * ia64-asmtab.c: Regenerate. - -2000-08-15 Jim Wilson <wilson@redhat.com> - - * ia64-ic.tbl: Add missing entries. - -2000-08-08 Jason Eckhardt <jle@redhat.com> - - * i860-dis.c (print_br_address): Change third argument from int - to long. - -2000-08-07 Richard Henderson <rth@redhat.com> - - * ia64-dis.c (print_insn_ia64): Get byte skip count correct - for MLI templates. Handle IA64_OPND_TGT64. - -2000-08-04 Ben Elliston <bje@redhat.com> - - * cgen-dis.in, cgen-asm.in, cgen-ibld.in: New files. - * cgen.sh: Likewise. - -2000-08-02 Jim Wilson <wilson@redhat.com> - - * ia64-dis.c (print_insn_ia64): Call ia64_free_opcode at end. - -2000-07-29 Marek Michalkiewicz <marekm@linux.org.pl> - - * avr-dis.c (avr_operand): Use PARAMS macro in declaration. - Change return type from void to int. Check the combination - of operands, return 1 if valid. Fix to avoid BUF overflow. - Report undefined combinations of operands in COMMENT. - Report internal errors to stderr. Output the adiw/sbiw - constant operand in both decimal and hex. - (print_insn_avr): Disassemble ldd/std with displacement of 0 - as ld/st. Check avr_operand () return value, handle invalid - combinations of operands like unknown opcodes. - -2000-07-28 Ben Elliston <bje@redhat.com> - - * Makefile.am (CGEN, CGENDEPS, CGENDIR, CGENFLAGS): New. - (run-cgen, stamp-m32r, stamp-fr30): New targets. - * Makefile.in: Regenerate. - * configure.in: Add --enable-cgen-maint option. - * configure: Regenerate. - -2000-07-26 Dave Brolley <brolley@redhat.com> - - * cgen-opc.c (cgen_hw_lookup_by_name): 'i' is now unsigned. - (cgen_hw_lookup_by_num): Ditto. - (cgen_operand_lookup_by_name): Ditto. - (print_address): Ditto. - (print_keyword): Ditto. - * cgen-dis.c (hash_insn_array): Mark unused parameters with - ATTRIBUTE_UNUSED. - * cgen-asm.c (hash_insn_array): Mark unused parameters with - ATTRIBUTE_UNUSED. - (cgen_parse_keyword): Ditto. - -2000-07-22 Jason Eckhardt <jle@redhat.com> - - * i860-dis.c: New file. - (print_insn_i860): New function. - (print_br_address): New function. - (sign_extend): New function. - (BITWISE_OP): New macro. - (I860_REG_PREFIX): New macro. - (grnames, frnames, crnames): New structures. - - * disassemble.c (ARCH_i860): Define. - (disassembler): Add check for bfd_arch_i860 to set disassemble - function to print_insn_i860. - - * Makefile.in (CFILES): Added i860-dis.c. - (ALL_MACHINES): Added i860-dis.lo. - (i860-dis.lo): New dependences. - - * configure.in: New bits for bfd_i860_arch. - - * configure: Regenerated. - -2000-07-20 Hans-Peter Nilsson <hp@axis.com> - - * Makefile.am (CFILES): Add cris-dis.c and cris-opc.c. - (ALL_MACHINES): Add cris-dis.lo and cris-opc.lo. - (cris-dis.lo, cris-opc.lo): New rules. - * Makefile.in: Rebuild. - * configure.in (bfd_cris_arch): New target. - * configure: Rebuild. - * disassemble.c (ARCH_cris): Define. - (disassembler): Support ARCH_cris. - * cris-dis.c, cris-opc.c: New files. - * po/POTFILES.in, po/opcodes.pot: Regenerate. - -2000-07-11 Jakub Jelinek <jakub@redhat.com> - - * sparc-opc.c (sparc_opcodes): popc has 0 in rs1, not rs2. - Reported by Bill Clarke <llib@computer.org>. - -2000-07-09 Geoffrey Keating <geoffk@redhat.com> - - * ppc-opc.c (powerpc_opcodes): Correct suffix for vslw. - Patch by Randall J Fisher <rfisher@ecn.purdue.edu>. - -2000-07-09 Alan Modra <alan@linuxcare.com.au> - - * hppa-dis.c (fput_reg, fput_fp_reg, fput_fp_reg_r, fput_creg, - fput_const, extract_3, extract_5_load, extract_5_store, - extract_5r_store, extract_5R_store, extract_10U_store, - extract_5Q_store, extract_11, extract_14, extract_16, extract_21, - extract_12, extract_17, extract_22): Prototype. - (print_insn_hppa): Rename inner block opcode -> opc to avoid - shadowing outer block. - (GET_BIT): Define. - -2000-07-05 DJ Delorie <dj@redhat.com> - - * MAINTAINERS: new - -2000-07-04 Alexandre Oliva <aoliva@redhat.com> - - * arm-dis.c (print_insn_arm): Output combinations of PSR flags. - -2000-07-03 Marek Michalkiewicz <marekm@linux.org.pl> - - * avr-dis.c (avr_operand): Change _ () to _() around all strings - marked for translation (exception from the usual coding style). - (print_insn_avr): Initialize insn2 to avoid warnings. - -2000-07-03 Kazu Hirata <kazu@hxi.com> - - * h8300-dis.c (bfd_h8_disassemble): Improve readability. - * h8500-dis.c: Fix formatting. - -2000-07-01 Alan Modra <alan@linuxcare.com.au> - - * Makefile.am (DEP): Fix 2000-06-22. grep after running dep.sed - (CLEANFILES): Add DEPA. - * Makefile.in: Regenerate. - -2000-06-26 Scott Bambrough <scottb@netwinder.org> - - * arm-dis.c (regnames): Add an additional register set to match - the set used by GCC. Make it the default. - -2000-06-22 Alan Modra <alan@linuxcare.com.au> - - * Makefile.am (DEP): grep for leading `/' in DEP1, and fail if we - find one. - * Makefile.in: Regenerate. - -2000-06-20 H.J. Lu <hjl@gnu.org> - - * Makefile.am: Rebuild dependency. - * Makefile.in: Rebuild. - -2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> - - * Makefile.in, configure: regenerate - * disassemble.c (disassembler): Recognize ARCH_m68hc12, - ARCH_m68hc11. - * m68hc11-dis.c (read_memory, print_insn, print_insn_m68hc12): - New functions. - * configure.in: Recognize m68hc12 and m68hc11. - * m68hc11-dis.c, m68hc11-opc.c: New files for support of m68hc1x - * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly - and opcode generation for m68hc11 and m68hc12. - -2000-06-16 Nick Duffek <nsd@redhat.com> - - * disassemble.c (disassembler): Refer to the PowerPC 620 using - bfd_mach_ppc_620 instead of 620. - -2000-06-12 Kazu Hirata <kazu@hxi.com> - - * h8300-dis.c: Fix formatting. - (bfd_h8_disassemble): Distinguish adds/subs, inc/dec.[wl] - correctly. - -2000-06-09 Denis Chertykov <denisc@overta.ru> - - * avr-dis.c (avr_operand): Bugfix for jmp/call address. - -2000-06-07 Denis Chertykov <denisc@overta.ru> - - * avr-dis.c: completely rewritten. - -2000-06-02 Kazu Hirata <kazu@hxi.com> - - * h8300-dis.c: Follow the GNU coding style. - (bfd_h8_disassemble) Fix a typo. - -2000-06-01 Kazu Hirata <kazu@hxi.com> - - * h8300-dis.c (bfd_h8_disassemble_init): Fix a typo. - (bfd_h8_disassemble): Distinguish the operand size of inc/dev.[wl] - correctly. Fix a typo. - -2000-05-31 Nick Clifton <nickc@redhat.com> - - * opintl.h (_(String)): Explain why dgettext is used instead of - gettext. - -2000-05-30 Nick Clifton <nickc@redhat.com> - - * opintl.h (gettext, dgettext, dcgettext, textdomain, - bindtextdomain): Replace defines with those from intl/libgettext.h - to quieten gcc warnings. - -2000-05-26 Alan Modra <alan@linuxcare.com.au> - - * Makefile.am: Update dependencies with "make dep-am" - * Makefile.in: Regenerate. - -2000-05-25 Alexandre Oliva <aoliva@redhat.com> - - * m10300-dis.c (disassemble): Don't assume 32-bit longs when - sign-extending operands. - -2000-05-15 Donald Lindsay <dlindsay@redhat.com> - - * d10v-opc.c (d10v_opcodes): add ALONE tag to all short branches - except brf's. - -2000-05-21 Nick Clifton <nickc@redhat.com> - - * Makefile.am (LIBIBERTY): Define. - -2000-05-19 Diego Novillo <dnovillo@redhat.com> - - * mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES. - (STD_REGISTER_NAMES): New name for REGISTER_NAMES. - (reg_names): Rename to std_reg_names. Change it to a char ** - static variable. - (std_reg_names): New name for reg_names. - (set_mips_isa_type): Set reg_names to point to std_reg_names by - default. - -2000-05-16 Frank Ch. Eigler <fche@redhat.com> - - * fr30-desc.h: Partially regenerated to account for changed - CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros. - * m32r-desc.h: Ditto. - -2000-05-15 Nick Clifton <nickc@redhat.com> - - * arm-opc.h: Use upper case for flasg in MSR and MRS - instructions. Allow any bit to be set in the field_mask of - the MSR instruction. - - * arm-dis.c (print_insn_arm): Decode _x and _s bits of the - field_mask of an MSR instruction. - -2000-05-11 Thomas de Lellis <tdel@windriver.com> - - * arm-opc.h: Disassembly of thumb ldsb/ldsh - instructions changed to ldrsb/ldrsh. - -2000-05-11 Ulf Carlsson <ulfc@engr.sgi.com> - - * mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit - target addresses for 'jal' and 'j'. - -2000-05-10 Geoff Keating <geoffk@redhat.com> - - * ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes - also available in common mode when powerpc syntax is being used. - -2000-05-08 Alan Modra <alan@linuxcare.com.au> - - * m68k-dis.c (dummy_printer): Add ATTRIBUTE_UNUSED to args. - (dummy_print_address): Ditto. - -2000-05-04 Timothy Wall <twall@redhat.com> - - * tic54x-opc.c: New. - * tic54x-dis.c: New. - * disassemble.c (disassembler): Add ARCH_tic54x. - * configure.in: Added tic54x target. - * configure: Ditto. - * Makefile.am: Add tic54x dependencies. - * Makefile.in: Ditto. - -2000-05-03 J.T. Conklin <jtc@redback.com> - - * ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for - vector unit operands. - (VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector - unit instruction formats. - (PPCVEC): New macro, mask for vector instructions. - (powerpc_operands): Add table entries for above operand types. - (powerpc_opcodes): Add table entries for vector instructions. - - * ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask. - (print_insn_little_powerpc): Likewise. - (print_insn_powerpc): Prepend 'v' when printing vector registers. - -2000-04-24 Clinton Popetz <cpopetz@redhat.com> - - * configure.in: Add bfd_powerpc_64_arch. - * disassemble.c (disassembler): Use print_insn_big_powerpc for - 64 bit code. - -2000-04-24 Nick Clifton <nickc@redhat.com> - - * fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow - field. - -2000-04-23 Denis Chertykov <denisc@overta.ru> - - * avr-dis.c (reg_fmul_d): New. Extract destination register from - FMUL instruction. - (reg_fmul_r): New. Extract source register from FMUL instruction. - (reg_muls_d): New. Extract destination register from MULS instruction. - (reg_muls_r): New. Extract source register from MULS instruction. - (reg_movw_d): New. Extract destination register from MOVW instruction. - (reg_movw_r): New. Extract source register from MOVW instruction. - (print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU, - EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions. - -2000-04-22 Timothy Wall <twall@redhat.com> - - * ia64-gen.c (general): Add an ordered table of primary - opcode names, as well as priority fields to disassembly data - structures to enforce a preferred disassembly format based on the - ordering of the opcode tables. - (load_insn_classes): Show a useful message if IC tables are missing. - (load_depfile): Ditto. - * ia64-asmtab.h (struct ia64_dis_names ): Add priority flag to - distinguish preferred disassembly. - * ia64-opc-f.c: Reorder some insn for preferred disassembly - format. Fix incorrect flag on fma.s/fma.s.s0. - * ia64-opc.c: Scan *all* disassembly matches and use the one with - the highest priority. - * ia64-opc-b.c: Use more abbreviations. - * ia64-asmtab.c: Regenerate. - -2000-04-21 Jason Eckhardt <jle@redhat.com> - - * hppa-dis.c (extract_16): New function. - (print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of - new operand types l,y,&,fe,fE,fx. - -2000-04-21 Richard Henderson <rth@redhat.com> - David Mosberger <davidm@hpl.hp.com> - Timothy Wall <twall@redhat.com> - Bob Manson <manson@charmed.cygnus.com> - Jim Wilson <wilson@redhat.com> - - * Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h. - (CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c, - ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c, - ia64-asmtab.c. - (ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo. - (ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen, - ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules. - * Makefile.in: Rebuild. - * configure Rebuild. - * configure.in (bfd_ia64_arch): New target. - * disassemble.c (ARCH_ia64): Define. - (disassembler): Support ARCH_ia64. - * ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl, - ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c, - ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl, - ia64-war.tbl, ia64-waw.tbl: New files. - -2000-04-20 Alexandre Oliva <aoliva@redhat.com> - - * m10300-dis.c (HAVE_AM30, HAVE_AM33): Define. - (disassemble): Use them. - -2000-04-14 Alan Modra <alan@linuxcare.com.au> - - * sysdep.h: Include "ansidecl.h" not <ansidecl.h> - * Makefile.am: Update dependencies. - * Makefile.in: Regenerate. - -2000-04-14 Michael Sokolov <msokolov@ivan.Harhan.ORG> - - * a29k-dis.c, alpha-dis.c, alpha-opc.c, arc-dis.c, arc-opc.c, - avr-dis.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c, - disassemble.c, h8300-dis.c, h8500-dis.c, hppa-dis.c, i370-dis.c, - i370-opc.c, i960-dis.c, m10200-dis.c, m10200-opc.c, m10300-dis.c, - m10300-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, mcore-dis.c, - mips-dis.c, mips-opc.c, mips16-opc.c, pj-dis.c, pj-opc.c, - ppc-dis.c, ppc-opc.c, sh-dis.c, sparc-dis.c, sparc-opc.c, - tic80-dis.c, tic80-opc.c, v850-dis.c, v850-opc.c, vax-dis.c, - w65-dis.c, z8k-dis.c, z8kgen.c: Include sysdep.h. Remove - ansidecl.h as sysdep.h includes it. - -2000-04-7 Andrew Cagney <cagney@b1.redhat.com> - - * configure.in (WARN_CFLAGS): Set to -W -Wall by default. Add - --enable-build-warnings option. - * Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions. - * Makefile.in, configure: Re-generate. - -2000-04-05 J"orn Rennecke <amylaar@redhat.com> - - * sh-opc.h (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs. - stc GBR,@-<REG_N> is available for arch_sh1_up. - Group parallel processing insn with identical mnemonics together. - Make three-operand psha / pshl come first. - -2000-04-05 J"orn Rennecke <amylaar@redhat.co.uk> - - * sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4. - Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. - (sh_arg_type): Add A_PC. - (sh_table): Update entries using immediates. Add repeat. - * sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4. - Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. - -2000-04-04 Alan Modra <alan@linuxcare.com.au> - - * po/opcodes.pot: Regenerate. - - * Makefile.am (MKDEP): Use gcc -MM rather than mkdep. - (DEP): Quote when passing vars to sub-make. Add warning message - to end. - (DEP1): Rewrite for "gcc -MM". - (CLEANFILES): Add DEP2. - Update dependencies. - * Makefile.in: Regenerate. - -2000-04-03 Denis Chertykov <denisc@overta.ru> - - * avr-dis.c: Syntax cleanup. - (add0fff): Print the pc relative address as a signed number. - (add03f8): Likewise. - -2000-04-01 Ian Lance Taylor <ian@zembu.com> - - * disassemble.c (disassembler_usage): Don't use a prototype. Mark - the parameter ATTRIBUTE_UNUSED. - * ppc-opc.c: Add ATTRIBUTE_UNUSED as needed. - -2000-04-01 Alexandre Oliva <aoliva@redhat.com> - - * m10300-opc.c: SP-based offsets are always unsigned. - -2000-03-29 Thomas de Lellis <tdel@windriver.com> - - * arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal" - [branch always] instead of "undefined". - -2000-03-27 Nick Clifton <nickc@redhat.com> - - * d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of - short instructions, from end of list of long instructions. - -2000-03-27 Ian Lance Taylor <ian@zembu.com> - - * Makefile.am (CFILES): Add avr-dis.c. - (ALL_MACHINES): Add avr-dis.lo. - -2000-03-27 Alan Modra <alan@linuxcare.com> - - * avr-dis.c (add0fff, add03f8): Don't use structure bitfields to - truncate integers. - (print_insn_avr): Call function via pointer in K&R compatible way. - (dispLDD, regPP, reg50, reg104, reg40, reg20w, lit404, lit204, - add0fff, add03f8): Convert to old style function declaration and - add prototype. - (avrdis_opcode): Add prototype. - -2000-03-27 Denis Chertykov <denisc@overta.ru> - - * avr-dis.c: New file. AVR disassembler. - * configure.in (bfd_avr_arch): New architecture support. - * disassemble.c: Likewise. - * configure: Regenerate. - -2000-03-06 J"oern Rennecke <amylaar@redhat.com> - - * sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement. - -2000-03-02 J"orn Rennecke <amylaar@redhat.co.uk> - - * d30v-dis.c (print_insn): Remove d*i hacks. Use per-operand - flag to determine if operand is pc-relative. - * d30v-opc.c: - (d30v_format_table): - (REL6S3): Renamed from IMM6S3. - Added flag OPERAND_PCREL. - (REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with - added flag OPERAND_PCREL. - (IMM12S3U): Replaced with REL12S3. - (SHORT_D2, LONG_D): Delay target is pc-relative. - (SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r): - Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r, - using the REL* operands. - (LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D. - (SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B, - LONG_Db, using REL* operands. - (SHORT_U, SHORT_A5S): Removed stray alternatives. - (d30v_opcode_table): Use new *r formats. - -2000-02-28 Nick Clifton <nickc@redhat.com> - - * m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with - 'signed_overflow_ok_p'. - -2000-02-27 Eli Zaretskii <eliz@is.elta.co.il> - - * Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the - name of the libtool directory. - * Makefile.in: Rebuild. - -2000-02-24 Nick Clifton <nickc@redhat.com> - - * cgen-opc.c (cgen_set_signed_overflow_ok): New function. - (cgen_clear_signed_overflow_ok): New function. - (cgen_signed_overflow_ok_p): New function. - -2000-02-23 Andrew Haley <aph@redhat.com> - - * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c, - m32r-ibld.c, m32r-opc.h: Rebuild. - -2000-02-23 Linas Vepstas <linas@linas.org> - - * i370-dis.c, i370-opc.c: New. - - * disassemble.c (ARCH_i370): Define. - (disassembler): Handle it. - - * Makefile.am: Add support for Linux/IBM 370. - * configure.in: Likewise. - - * Makefile.in: Regenerate. - * configure: Likewise. - -2000-02-22 Chandra Chavva <cchavva@redhat.com> - - * d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to - ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel - procedure. - -2000-02-22 Andrew Haley <aph@redhat.com> - - * mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER: - force gp32 to zero. - * mips-opc.c (G6): New define. - (mips_builtin_op): Add "move" definition for -gp32. - -2000-02-22 Ian Lance Taylor <ian@zembu.com> - - From Grant Erickson <gerickso@Brocade.COM>: - * ppc-opc.c: Correct dcread--it takes 3 arguments, not 2. - -2000-02-21 Alan Modra <alan@spri.levels.unisa.edu.au> - - * dis-buf.c (buffer_read_memory): Change `length' param and all int - vars to unsigned. - -2000-02-17 J"orn Rennecke <amylaar@redhat.co.uk> - - * sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions. - (print_insn_ppi): Likewise. - (print_insn_shx): Use info->mach to select appropriate insn set. - Add support for sh-dsp. Remove FD_REG_N support. - * sh-opc.h (sh_nibble_type): Add new values for sh-dsp support. - (sh_arg_type): Likewise. Remove FD_REG_N. - (sh_dsp_reg_nums): New enum. - (arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros. - (arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise. - (arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise. - (arch_sh3_dsp_up): Likewise. - (sh_opcode_info): New field: arch. - (sh_table): Split up insn with FD_REG_N into ones with F_REG_N and - D_REG_N. Fill in arch field. Add sh-dsp insns. - -2000-02-14 Fernando Nasser <fnasser@totem.to.redhat.com> - - * arm-dis.c: Change flavor name from atpcs-special to - special-atpcs to prevent name conflict in gdb. - (get_arm_regname_num_options, set_arm_regname_option, - get_arm_regnames): New functions. API to access the several - flavor of register names. Note: Used by gdb. - (print_insn_thumb): Use the register name entry from the currently - selected flavor for LR and PC. - -2000-02-10 Nick Clifton <nickc@redhat.com> - - * mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR - classes. - (mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and - "mulsh.h" instructions. - * mcore-dis.c (imsk array): Add masks for MULSH and OPSR - classes. - (print_insn_mcore): Add support for little endian targets. - Add support for MULSH and OPSR classes. - -2000-02-07 Nick Clifton <nickc@redhat.com> - - * arm-dis.c (parse_arm_diassembler_option): Rename again. - Previous delat did not take. - -2000-02-03 Timothy Wall <twall@redhat.com> - - * dis-buf.c (buffer_read_memory): Use octets_per_byte field - to adjust target address bounds checking and calculate the - appropriate octet offset into data. - -2000-01-27 Nick Clifton <nickc@redhat.com> - - * arm-dis.c: (parse_disassembler_option): Rename to - parse_arm_disassembler_option and allow to be exported. - - * disassemble.c (disassembler_usage): New function: Print out any - target specific disassembler options. - Call arm_disassembler_options() if the ARM architecture is being - supported. - - * arm-dis.c (NUM_ELEM): Define this macro if not already - defined. - (arm_regname): New struct type for ARM register names. - (arm_toggle_regnames): Delete. - (parse_disassembler_option): Use register name structure. - (print_insn): New function: Combines duplicate code found in - print_insn_big_arm and print_insn_little_arm. - (print_insn_big_arm): Call print_insn. - (print_insn_little_arm): Call print_insn. - (print_arm_disassembler_options): Display list of supported, - ARM specific disassembler options. - -2000-01-27 Thomas de Lellis <tdel@windriver.com> - - * arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the - ARM_STT_16BIT flag as Thumb code symbols. - - * arm-dis.c (printf_insn_little_arm): Ditto. - -2000-01-25 Thomas de Lellis <tdel@windriver.com> - - * arm-dis.c (printf_insn_thumb): Prevent double dumping - of raw thumb instructions. -2000-01-20 Nick Clifton <nickc@redhat.com> +2004-01-06 Alexandre Oliva <aoliva@redhat.com> - * mcore-opc.h (mcore_table): Add "add" as an alias for "addu". + 2003-12-19 Alexandre Oliva <aoliva@redhat.com> + * frv-asm.c (parse_ulo16, parse_uhi16, parse_d12): Fix some + cut&paste errors in shifting/truncating numerical operands. + 2003-08-04 Alexandre Oliva <aoliva@redhat.com> + * frv-asm.c (parse_ulo16): Parse gotofflo and gotofffuncdesclo. + (parse_uslo16): Likewise. + (parse_uhi16): Parse gotoffhi and gotofffuncdeschi. + (parse_d12): Parse gotoff12 and gotofffuncdesc12. + (parse_s12): Likewise. + 2003-08-04 Alexandre Oliva <aoliva@redhat.com> + * frv-asm.c (parse_ulo16): Parse gotlo and gotfuncdesclo. + (parse_uslo16): Likewise. + (parse_uhi16): Parse gothi and gotfuncdeschi. + (parse_d12): Parse got12 and gotfuncdesc12. + (parse_s12): Likewise. -2000-01-03 Nick Clifton <nickc@cygnus.com> +2004-01-02 Albert Bartoszko <albar@nt.kegel.com.pl> - * arm-dis.c (streq): New macro. - (strneq): New macro. - (force_thumb): ew local variable. - (parse_disassembler_option): New function: Parse a single, ARM - specific disassembler command line switch. - (parse_disassembler_option): Call parse_disassembler_option to - parse individual command line switches. - (print_insn_big_arm): Check force_thumb. - (print_insn_little_arm): Check force_thumb. + * msp430-dis.c (msp430_doubleoperand): Check for an 'add' + instruction which looks similar to an 'rla' instruction. -For older changes see ChangeLog-9899 +For older changes see ChangeLog-0203 Local Variables: mode: change-log diff --git a/contrib/binutils/opcodes/ChangeLog-0001 b/contrib/binutils/opcodes/ChangeLog-0001 new file mode 100644 index 0000000..085453a --- /dev/null +++ b/contrib/binutils/opcodes/ChangeLog-0001 @@ -0,0 +1,2224 @@ +2001-12-31 Jeffrey A Law (law@redhat.com) + + * hppa-dis.c (print_insn_hppa): Handle new 'c' mode completers, + 'X', 'M', and 'A'. No longer emit a space after 'x' or 's'. + Always emit a space after 'H'. + +2001-12-18 matthew green <mrg@redhat.com> + + * ppc-opc.c (PPCVEC): Include PPC_OPCODE_ANY. + +2001-12-17 Richard Henderson <rth@redhat.com> + + * alpha-opc.c (unop): Encode with RB as $sp. + +2001-12-07 Geoffrey Keating <geoffk@redhat.com> + + * Makefile.am: Add support for xstormy16. + * Makefile.in: Regenerate. + * configure.in: Add support for xstormy16. + * configure: Regenerate. + * disassemble.c: Add support for xstormy16. + * xstormy16-asm.c: New generated file. + * xstormy16-desc.c: New generated file. + * xstormy16-desc.h: New generated file. + * xstormy16-dis.c: New generated file. + * xstormy16-ibld.c: New generated file. + * xstormy16-opc.c: New generated file. + * xstormy16-opc.h: New generated file. + +2001-12-06 Richard Henderson <rth@redhat.com> + + * alpha-opc.c (alpha_opcodes): Add wh64en. + +2001-12-04 Alexandre Oliva <aoliva@redhat.com> + + * d10v-opc.c (d10v_predefined_registers): Remove warnings + introduced in Nov 29's patch. + + * d10v-dis.c (print_operand): Apply REGISTER_MASK to `num' of + unmatched register. + + * d10v-dis.c (print_operand): Disregard OPERAND_SP in register + predefined value. + + * d10v-opc.c (RSRC_NOSP): New macro. + (d10v_operands): Add it. + (d10v_opcodes): Use RSRC_NOSP in post-decrement "st" and "st2w". + +2001-11-29 Alexandre Oliva <aoliva@redhat.com> + + * d10v-opc.c (d10v_predefined_registers): Mark `sp' as OPERAND_SP. + (RSRC_SP): New macro. + (d10v_operands): Add it. + (d10v_opcodes): Adjust "st" and "st2w" to use RSRC_SP. + +2001-11-23 Lars Brinkhoff <lars@nocrew.org> + + * pdp11-dis.c (print_insn_pdp11): Handle illegal instructions. + Also, break out of the loop as soon as an instruction has been + printed. + +2001-11-17 matthew green <mrg@redhat.com> + + * ppc-opc.c (mfvrsave, mtvrsave): New instructions. + +2001-11-15 Alan Modra <amodra@bigpond.net.au> + + * po/POTFILES.in: Regenerate. + + * ppc-opc.c (PPC64): Revert 2001-10-12. Do include PPC_OPCODE_PPC. + (insert_bat, extract_bat, insert_bba, extract_bba, + insert_bd, extract_bd, insert_bdm, extract_bdm, + insert_bdp, extract_bdp, valid_bo, + insert_bo, extract_bo, insert_boe, extract_boe, + insert_ds, extract_ds, insert_de, extract_de, + insert_des, extract_des, insert_li, extract_li, + insert_mbe, extract_mbe, insert_mb6, extract_mb6, + insert_nb, extract_nb, insert_nsi, extract_nsi, + insert_ral, insert_ram, insert_ras, + insert_rbs, extract_rbs, insert_sh6, extract_sh6, + insert_spr, extract_spr, insert_tbr, extract_tbr): Add dialect param. + (extract_bd, extract_bdm, extract_bdp, + extract_ds, extract_des, + extract_li, extract_nsi): Implement sign extension without conditional. + (insert_bdm, extract_bdm, + insert_bdp, extract_bdp, valid_bo): Handle 64 bit branch hints. + (extract_bdm, extract_bdp): Correct 32 bit validation. + (AT1_MASK, AT2_MASK): Define. + (BBOAT_MASK): Define. + (BBOATCB_MASK, BBOAT2CB_MASK, BBOATBI_MASK): Define. + (BOFM64, BOFP64, BOTM64, BOTP64): Define. + (BODNZM64, BODNZP64, BODZM64, BODZP64): Define. + (PPCCOM32, PPCCOM64): Define. + (powerpc_opcodes): Modify existing 32 bit insns with branch hints + and add new patterns to implement 64 bit branches with hints. Move + booke instructions so they match before ppc64. + + * ppc-dis.c (powerpc_dialect): Set PPC_OPCODE_64 in dialect for + 64 bit default targets, and parse "32" and "64" in options. + Formatting fixes. + (print_insn_powerpc): Pass dialect to operand->extract. + +2001-11-14 Dave Brolley <brolley@redhat.com> + + * cgen-dis.c (count_decodable_bits): New function. + (add_insn_to_hash_chain): New function. + (hash_insn_array): Call add_insn_to_hash_chain. + (hash_insn_list): Call add_insn_to_hash_chain. + * m32r-dis.c: Regenerated. + * fr30-dis.c: Regenerated. + +2001-11-14 Andreas Jaeger <aj@suse.de> + + * i386-dis.c (print_insn): Use x86-64 as option. + +2001-11-14 Alan Modra <amodra@bigpond.net.au> + + * disassemble.c (disassembler): Call print_insn_i386. + * i386-dis.c (SUFFIX_ALWAYS): Define. + (struct dis_private): Add orig_sizeflag. + (print_insn_i386): Make it a wrapper, calling.. + (print_insn): ..The old body of print_insn_i386. Avoid longjmp + warning without using volatile by moving orig_sizeflag to priv, + and removing inbuf. Parse disassembler_options. + (print_insn_i386_att, print_insn_i386_intel): Move initialisation + code to print_insn. + (putop): Remove #ifdef SUFFIX_ALWAYS. + +2001-11-11 Timothy Wall <twall@alum.mit.edu> + + * tic54x-dis.c: Use revised opcode structure. Export opcode + template lookup. + (has_lkaddr): Don't forget about Lmem insns. + * tic54x-opc.c: Add emulation trap. Parallel table now uses + standard opcode templates. + +2001-11-13 Zack Weinberg <zack@codesourcery.com> + + * i386-dis.c (grps): Change "sldt", "str", and "smsw" entries + to "sldtQ", "strQ", "smswQ" respectively; all with Ev operand + category instead of Ew. + +2001-11-12 Niraj Gupta <ngupta@zumanetworks.com> + + * m68k-opc.c: Fix definitions of wddata[bwl]. + +2001-11-09 Richard Sandiford <rsandifo@redhat.com> + + * cgen-asm.c (cgen_parse_keyword): If the keyword is too big to + fit in the buffer, try to match the empty keyword. + +2001-11-09 Nick Clifton <nickc@cambridge.redhat.com> + + * cgen-ibld.in (extract_1): Fix badly placed #if 0. + * fr30-ibld.c: Regenerate. + * m32r-ibld.c: Regenerate. + * openrisc-ibld.c: Regenerate. + +2001-11-04 Chris Demetriou <cgd@broadcom.com> + + * mips-dis.c (print_insn_mips): Remove spaces at end of line. + +2001-11-02 Nick Clifton <nickc@cambridge.redhat.com> + + * configure.in (ALL_LINGUAS): Add "fr", "sv" and "tr". + * configure: Regernate. + * po/fr.po: New file. + * po/sv.po: New file. + * po/tr.po: New file. + +2001-11-01 Stephane Carrez <Stephane.Carrez@worldnet.fr> + + * m68hc11-dis.c (print_insn): Fix disassembly of movb with a + constant as source. + +2001-10-30 Hans-Peter Nilsson <hp@bitrange.com> + + * Makefile.am (CFILES): Add mmix-dis.c and mmix-opc.c. Regenerate + dependencies. + * Makefile.in: Regenerate. + * mmix-dis.c, mmix-opc.c: New files. + +2001-10-29 Kazu Hirata <kazu@hxi.com> + + * d30v-dis.c: Fix a comment typo. + +2001-10-23 Chris Demetriou <cgd@broadcom.com> + + * mips-opc.c (mips_builtin_opcodes): Mark "bgezall" and + "bltzall" as writing GPR 31 (since they do). + + * mips-dis.c (print_insn_arg): Calculate info->target + where appropriate. + (print_insn_mips): Fill in instruction info. + (print_mips16_insn_arg): Remove unneded variable 'val'. + Removed duplicated instruction target calculations, + calculate once and print that result. Use same idiom for + masking the jump segment bits as is used in print_insn_arg. + +2001-10-20 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (CT): Make it an optional operand. + +2001-10-17 Chris Demetriou <cgd@broadcom.com> + + * mips-dis.c (mips_isa_type): Make the ISA used to disassemble + SB-1 binaries include instructions specific to the SB-1. + * mips-opc.c (SB1): New definition. + (mips_builtin_opcodes): Add SB-1 extension opcodes "div.ps", + "recip.ps", "rsqrt.ps", and "sqrt.ps". + +2001-10-17 matthew green <mrg@redhat.com> + + * ppc-opc.c (STRM): New AltiVec operand. + (XDSS): New AltiVec instruction form. + (mtvscr): Correct operand list. + (dst, dstt, dstst, dststt, dss, dssall): AltiVec instructions. + +2001-10-17 Alan Modra <amodra@bigpond.net.au> + + * po/POTFILES.in: Regenerate. + +2001-10-13 matthew green <mrg@redhat.com> + + * ppc-opc.c (MO): New macro for MO field of mbar instruction. + (powerpc_opcodes): Add rfci, wrtee, wrteei, mfdcrx, mfdcr, + mtdcrx, mtdcr, msync, dcba and mbar as BookE instructions. + +2001-10-13 Nick Clifton <nickc@cambridge.redhat.com> + + * cgen-ibld.in: Include safe-ctype.h in preference to + ctype.h. + * cgen-asm.in: Include safe-ctype.h in preference to + ctype.h. Fix formatting. Use ISSPACE instead of isspace and + TOLOWER instead of tolower. + (@arch@_cgen_build_insn_regex): Remove duplication of syntax + string elements in constructed regular expression. + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-ibld.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-ibld.c: Regenerate. + * openrisc-asm.c: Regenerate. + * openrisc-desc.c: Regenerate. + * openrisc-ibld.c: Regenerate. + * po/opcodes.pot: Regenerate. + +2001-10-12 matthew green <mrg@redhat.com> + + * ppc-opc.c (insert_de, extract_de, insert_des, extract_des): New + instruction field instruction/extraction functions for new BookE + DE form instructions. + (CT): New macro for CT field in an X form instruction. + (DE, DES, DEO, DE_MASK): New macros for DE/DES fields in DE form + instructions. + (PPC64): Don't include PPC_OPCODE_PPC. + (403): New opcode macro for PPC403 processors. + (BOOKE): New opcode macro for BookE processors. + (bce, bcel, bcea, bcela, bclre, bclrel: New BookE instructions. + (bcctre, bcctrel, be, bel, bea, bela, icbt, icbte, lwzxe): Likewise. + (dcbste, lwzuxe, luxe, dcbfe, lbzxe, lwarxe, lbzuxe): Likewise. + (stwcxe, stwxe, stxe, stwuxe, stuxe, stbxe, dcbtste, stbuxe): Likewise. + (mfapidi, dcbte, lhzxe, lhzuxe, lhaxe, lhauxe, subfe64): Likewise. + (subfeo64, adde64, addeo64, sthxe, sthuxe, subfze64): Likewise. + (subfzeo64, addze64, addzeo64, dcbie, subfme64, subfmeo64): Likewise. + (addme64, addmeo64, stdcxe., mcrxr64, lwbrxe, lfsxe, lfsuxe): Likewise. + (lfdxe, lfduxe, stwbrxe, stfsxe, stfsuxe, stfdxe, dcbae): Likewise. + (stfduxe, tlbivax, tlbivaxe, lhbrxe, ldxe, lduxe, tlbsx): Likewise. + (tlbsxe, sthbrxe, stdxe, stduxe, icbie, stfiwxe, dcbze, lbze): Likewise. + (lbzue, ldue, lhze, lhzue, lhae, lhaue, lwze, lwzue): Likewise. + (stbe, stbue, sthe, sthue, stwe, stwue, lfse, lfsue, lfde): Likewise. + (lfdue, stde, stdue, stfse, stfsue, stfde, stfdue): Likewise. + + * ppc-dis.c (print_insn_big_powerpc, print_insn_little_powerpc): Look + for a disassembler option of `booke', `booke32' or `booke64' to enable + BookE support in the disassembler. + +2001-10-12 John Healy <jhealy@redhat.com> + + * cgen-dis.in (print_insn): Use min (cd->base_insn_bitsize, buflen*8) + for the length when extracting the base part of the insn. + +2001-10-09 Bruno Haible <haible@clisp.cons.org> + + * cgen-asm.in (*_cgen_build_insn_regex): Generate a case sensitive + regular expression. Fix some formatting problems. + * fr30-asm.c: Regenerate. + * openrisc-asm.c: Regenerate. + * m32r-asm.c: Regenerate. + +2001-10-09 Christian Groessler <cpg@aladdin.de> + + * z8k-dis.c (unparse_instr): Fixed formatting. Change disassembly + of indirect register memory accesses to be same format the + assembler accepts. + +2001-10-09 Nick Clifton <nickc@cambridge.redhat.com> + + * sh-opc.h: Fix encoding of least significant nibble of the + DSP single data transfer instructions. + + * sh-dis.c (print_insn_shx): Fix decoding of As opcode in DSP + instructions. + +2001-10-08 Nick Clifton <nickc@cambridge.redhat.com> + + * cgen-asm.in: Fix compile time warning messages in generated + C files. + * cgen-dis.in: The same. + * cgen-ibld.in: The same. + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-dis.c: Regenerate. + * fr30-ibld.c: Regenerate. + * fr30-opc.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-ibld.c: Regenerate. + * m32r-opc.c: Regenerate. + * m32r-opinst.c Regenerate. + * openrisc-asm.c: Regenerate. + * openrisc-desc.c: Regenerate. + * openrisc-dis.c: Regenerate. + * openrisc-ibld.c: Regenerate. + * openrisc-opc.c: Regenerate. + * openrisc-opc.h: Regenerate. + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2001-10-08 Aldy Hernandez <aldyh@redhat.com> + + * arm-opc.h (arm_opcodes): Add cirrus insns. + + * arm-dis.c (print_insn_arm): Add 'I' case. + +2001-10-03 Alan Modra <amodra@bigpond.net.au> + + * po/POTFILES.in: Regenerate. + * configure: Regenerate. + +2001-10-02 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am (Makefile): Depend on bfd/configure.in. + Run "make dep-am". + * Makefile.in: Regenerate. + +2001-09-30 John Healy <jhealy@redhat.com> + + * cgen-ibld.in (insert_1): Switched bfd_get_bits and bfd_set_bits + calls to cgen_get_insn_value and cgen_put_insn_value calls. + (extract_1): Switched bfd_get_bits call to cgen_get_insn_value call. + +2001-09-30 Hans-Peter Nilsson <hp@bitrange.com> + + * Makefile.am: Update dependencies with "make dep-am". + * Makefile.in: Regenerate. + +2001-09-26 Alan Modra <amodra@bigpond.net.au> + + * arc-dis.c: Formatting fixes. + (my_sprintf): Define using VPARAMS, VA_OPEN, VA_FIXEDARG, VA_CLOSE. + +2001-09-21 Bruno Haible <haible@clisp.cons.org> + + * arc-dis.c: Don't include <ctype.h>. + * openrisc-desc.c: Likewise. + * openrisc-ibld.c: Likewise. + +2001-09-20 Nick Clifton <nickc@cambridge.redhat.com> + + * fr30-opc.c: Fix compile time warning messages. + * i370-opc.c: Fix compile time warning messages. + * i960-dis.c: Fix compile time warning messages. + * m32r-asm.c: Fix compile time warning messages. + * m32r-desc.c: Fix compile time warning messages. + * m32r-dis.c: Fix compile time warning messages. + * m32r-ibld.c: Fix compile time warning messages. + * m32r-opc.c: Fix compile time warning messages. + * m32r-opinst.c: Fix compile time warning messages. + * ns32k-dis.c: Fix compile time warning messages. + * openrisc-asm.c: Fix compile time warning messages. + * openrisc-desc.c: Fix compile time warning messages. + * openrisc-dis.c: Fix compile time warning messages. + * openrisc-ibld.c: Fix compile time warning messages. + * openrisc-opc.c: Fix compile time warning messages. + * pdp11-dis.c: Fix compile time warning messages. + * tic54x-dis.c: Fix compile time warning messages. + * v850-opc.c: Fix compile time warning messages. + * vax-dis.c: Fix compile time warning messages. + * w65-opc.h: Fix compile time warning messages. + * z8k-opc.h: Fix compile time warning messages. + * z8kgen.c: Fix compile time warning messages. + +2001-09-19 Nick Clifton <nickc@cambridge.redhat.com> + + * arm-dis.c: Fix compile time warning messages. + * cgen-asm.c: Fix compile time warning messages. + * cgen-dis.c: Fix compile time warning messages. + * cris-dis.c: Fix compile time warning messages. + * d10v-dis.c: Fix compile time warning messages. + * fr30-asm.c: Fix compile time warning messages. + * fr30-desc.c: Fix compile time warning messages. + * fr30-dis.c: Fix compile time warning messages. + * fr30-ibld.c: Fix compile time warning messages. + +2001-09-18 Bruno Haible <haible@clisp.cons.org> + + * cgen-asm.c: Include "safe-ctype.h" instead of <ctype.h>. + (cgen_parse_keyword): Use ISALNUM instead of isalnum. + * cgen-opc.c: Include "safe-ctype.h" instead of <ctype.h>. + (cgen_keyword_lookup_name): Use ISALPHA/TOLOWER instead of + isalpha/tolower. + (cgen_keyword_add): Use ISALNUM instead of isalnum. + (hash_keyword_name): Use TOLOWER instead of tolower. + * fr30-asm.c: Include "safe-ctype.h" instead of <ctype.h>. + (parse_insn_normal): Use TOLOWER/ISSPACE instead of + tolower/isspace. + (fr30_cgen_assemble_insn): Use ISSPACE instead of isspace. + * fr30-desc.c: Don't include <ctype.h>. + * fr30-ibld.c: Likewise. + * ia64-gen.c: Include "safe-ctype.h" instead of <ctype.h>. + (load_insn_classes, parse_resource_users, load_depfile): Use + ISSPACE instead of isspace. + * m32r-asm.c: Include "safe-ctype.h" instead of <ctype.h>. + (parse_insn_normal): Use TOLOWER/ISSPACE instead of + tolower/isspace. + (m32r_cgen_assemble_insn): Use ISSPACE instead of isspace. + * m32r-desc.c: Don't include <ctype.h>. + * m32r-ibld.c: Likewise. + * openrisc-asm.c: Include "safe-ctype.h" instead of <ctype.h>. + (parse_insn_normal): Use TOLOWER/ISSPACE instead of + tolower/isspace. + (openrisc_cgen_assemble_insn): Use ISSPACE instead of isspace. + +2001-09-18 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * Makefile.am: Add rules and dependencies to create the s/390 opcode + table out of s390-opc.txt automatically. + * configure.in: Add BFD_CC_FOR_BUILD to allow CC_FOR_BUILD to be used. + * s390-mkopc.c (dumpTable): Change output to create a complete file. + * s390-opc.c: New improved opcode format macros and remove the + pregenerated opcode table. + * s390-opc.txt: Adapt to new improved opcode format macros. + +2001-09-14 David Schleef <ds@schleef.org> + + * ppc-opc.c (VXA, VXA_MASK): Fix mask bits. + +2001-09-04 Alan Modra <amodra@bigpond.net.au> + + * i386-dis.c (grps): Don't print the implicit al/ax/eax register + for opcode 0xf6 or 0xf7 forms of mul, imul, div, idiv insns. + +2001-08-31 Eric Christopher <echristo@redhat.com> + Jason Eckhardt <jle@redhat.com> + + * mips-dis.c: Add support for bfd_mach_mipsisa32 and + bfd_mach_mipsisa64. Remove bfd_mach_mips32, bfd_mach_mips32_4k, + bfd_mach_mips64. + +2001-08-31 Andreas Jaeger <aj@suse.de> + + * tic54x-opc.c: Add default initializers to avoid warnings. + + * arc-opc.c: Include "sysdep.h" to get stdio.h as include file. + * arc-ext.c: Likewise. + +2001-08-28 matthew green <mrg@redhat.com> + + * ppc-opc.c (icbt): Order correctly. + +2001-08-27 David Edelsohn <dje@watson.ibm.com> + Torbjorn Granlund <tege@swox.com> + + * ppc-opc.c (DS): Add PPC_OPERAND_DS flag. + (LS): Define. + (insert_ds): Complain if not a multiple of 4. + (XSYNC): Define. + (XSYNC_MASK): Define. + (powerpc_opcodes): Add "slbmte", "lwsync", "ptesync", "slbmfev", + "slbmfee". Modify "sync" to use XSYNC_MASK and LS. + +2001-08-26 Andreas Jaeger <aj@suse.de> + + * h8500-opc.h: Add default initializers to h8500_table to shut up + GCC warnings. + +2001-08-25 Andreas Jaeger <aj@suse.de> + + * tic54x-dis.c: Add unused attributes where needed. + + * z8k-dis.c (output_instr): Add unused attribute. + + * h8300-dis.c: Add missing prototypes. + (bfd_h8_disassemble): Make static. + + * cris-dis.c: Add missing prototype. + * h8500-dis.c: Likewise. + * m68hc11-dis.c: Likewise. + * pj-dis.c: Likewise. + * tic54x-dis.c: Likewise. + * v850-dis.c: Likewise. + * vax-dis.c: Likewise. + * w65-dis.c: Likewise. + * z8k-dis.c: Likewise. + + * d10v-dis.c: Add missing prototype. + (dis_long): Remove unused variable. + (dis_2_short): Likewise. + + * sh-dis.c: Add missing prototypes. + * v850-opc.c: Likewise. + Add unused attributes where needed. + + * ns32k-dis.c: Add missing prototypes. + (bit_extract_simple): Remove unused variable. + +2001-08-23 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390-opc.c: Add "low or high" and "not low or high" + branch instructions for gcc 3.0. + * s390-opc.txt: Likewise. + +2001-08-21 Andreas Jaeger <aj@suse.de> + + * i960-dis.c: Add parameters for prototypes + (ctrl): Add unused attributes. + (cobr): Likewise. + (put_abs): Likewise. + + * mips-dis.c: Add missing prototypes. + * a29k-dis.c: Likewise. + * arc-dis.c: Likewise. + * ia64-opc.c: Likewise. + + * s390-dis.c: Add missing prototypes. + (init_disasm): Remove unused attribute since the parameter is + used. + +2001-08-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips-opc.c (M1): Define. Reformatted Code. + (mips_builtin_opcodes): Added performance counter opcodes mfpc, mfps, + mtps, mtps. Typo. + +2001-08-16 Jonathan Larmour <jlarmour@redhat.com> + + * mips-opc.c: R3900s can support all branch likely INSN_MACROs where + the corresponding non-likely insn is in MIPS I. + +2001-08-13 Kazu Hirata <kazu@hxi.com> + + * mcore-dis.c: Fix formatting. + * mips-dis.c: Likewise. + * pj-dis.c: Likewise. + * z8k-dis.c: Likewise. + +2001-08-12 Richard Henderson <rth@redhat.com> + + * cgen-ibld.in (extract_normal): Match type of VALUE and MASK + to *VALUEP. Regenerate all cgen files. + +2001-08-10 Richard Sandiford <rsandifo@redhat.com> + + * mips-dis.c (print_insn_mips): Remove OPCODE_IS_MEMBER's gp32 + argument. + * mips-opc.c (G6): Undefine. + (mips_builtin_opcodes): Remove gp32 entry for "move". Add macro + as the first "move" alternative. + +2001-08-10 Andreas Jaeger <aj@suse.de> + + * configure.in: Add -Wstrict-prototypes and -Wmissing-prototypes + to build warnings. + * configure: Regenerate. + +2001-08-10 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c: Revert 2001-08-08. + +2001-08-09 Alan Modra <amodra@bigpond.net.au> + + * dis-buf.c (generic_strcat_address): Add missing prototype. + #if 0 the functions as it is unused. + +2001-08-08 Alan Modra <amodra@bigpond.net.au> + + 1999-10-25 Torbjorn Granlund <tege@swox.com> + * ppc-opc.c: Include "bfd.h". + (powerpc_operands): Add new field for reloc type. + +2001-07-21 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips-dis.c (print_insn_arg): Don't use software integer registers + for coprocessor registers. + (get_mips_isa): Removed. + (is_newabi): New function, checks if NewABI is used. + (_print_insn_mips): Get distinction between old ABI and new ABI right. + +2001-08-01 Christian Groessler <cpg@aladdin.de> + + * z8kgen.c: Fixed indentation of opt[] array. Include stdio.h to + get stderr definition. + (internal, gas): Removed warnings. + (gas): Create a correct final entry for created array. + * z8k-opc.h: Recreated with new z8kgen. + +2001-07-28 Kazu Hirata <kazu@hxi.com> + + * i386-dis.c: Fix formatting. + +2001-07-28 Matthias Kramm <kramm@quiss.org> + + * i386-dis.c: Change formatting conventions for architecture + i386:intel to better match the format of various intel i386 + assemblers, like nasm, tasm or masm. + +2001-07-24 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Update dependencies with "make dep-am". + * Makefile.in: Regenerate + +2001-07-24 Kazu Hirata <kazu@hxi.com> + + * alpha-dis.c: Fix formatting. + * cris-dis.c: Likewise. + * d10v-dis.c: Likewise. + * d30v-dis.c: Likewise. + * m10300-dis.c: Likewise. + * tic54x-dis.c: Likewise. + +2001-07-23 Kazu Hirata <kazu@hxi.com> + + * m68k-dis.c: Fix formatting. + * pj-dis.c: Likewise. + * s390-dis.c: Likewise. + * z8k-dis.c: Likewise. + +2001-07-21 Chris Demetriou <cgd@broadcom.com> + + * mips-opc.c (mips_builtin_opcodes): Sort c.le.s and c.lt.s + into the rest of the surrounding definitions. + +2001-07-18 Alan Modra <amodra@bigpond.net.au> + + * i386-dis.c (grps): Print l or w suffix, and require mem modrm + for lgdt, lidt, sgdt, sidt. + +2001-07-13 Philip Blundell <philb@gnu.org> + + * arm-dis.c (print_insn_arm): Use decimal for offsets in LDR/STR. + +2001-07-12 Jeff Johnston <jjohnstn@redhat.com> + + * cgen-asm.in: Include "xregex.h" always to enable the libiberty + regex support. + (@arch@_cgen_build_insn_regex): New routine from Graydon. + (@arch@_cgen_assemble_insn): Add Graydon's code to use regex + to verify if it is worth parsing the insn as insn "x". Also update + error message when insn is not a recognized format of the insn vs + when the insn is completely unrecognized. + +2001-07-11 Frank Ch. Eigler <fche@redhat.com> + + * cgen-dis.in (print_insn): Use cgen_get_insn_value instead of + bfd_get_bits. + * cgen-opc.c (cgen_get_insn_value, cgen_put_insn_value): Respect + non-zero CGEN_CPU_DESC->insn_chunk_bitsize. + +2001-07-09 Andreas Jaeger <aj@suse.de>, Karsten Keil <kkeil@suse.de> + + * i386-dis.c (set_op): Handle 64 bit and 32 bit mode. + (OP_J): Use bfd_vma for mask to work properly with 64 bits. + (op_address,op_riprel): Use bfd_vma to handle 64 bits. + +2001-07-05 Ben Elliston <bje@redhat.com> + + * Makefile.am (CPUDIR): Define. + (stamp-m32r): Update dependencies. + (stamp-fr30): Ditto. + (stamp-openrisc): Ditto. + * Makefile.in: Regenerate. + +2001-07-03 Zoltan Hidvegi <hzoli@hzoli.2y.net> + + * ppc-opc.c: Fix encoding of 'clf' instruction. + +2001-06-30 Geoffrey Keating <geoffk@redhat.com> + + * cgen-ibld.in (insert_normal): Support CGEN_IFLD_SIGN_OPT. + +2001-06-28 Geoffrey Keating <geoffk@redhat.com> + + * cgen-asm.c (cgen_parse_keyword): Allow any first character. + * cgen-opc.c (cgen_keyword_add): Ignore special first + character when building nonalpha_chars field. + +2001-06-24 Ben Elliston <bje@redhat.com> + + * m88k-dis.c: Format to conform to GNU coding standards. + +2001-06-23 Andreas Jaeger <aj@suse.de> + + * disassemble.c (disassembler_usage): Add unused attribute. + +2001-06-22 Eric Christopher <echristo@redhat.com> + + * mips-opc.c: Move prefx to start of the table. + +2001-06-22 Stacey Sheldon <ssheldon@Catena.com> + + * arc-opc.c (insert_st_syntax): Fix over-optimisation of ST + instruction. + +2001-06-22 Pauli <pauli@moreton.com.au> + + * m68k-opc.c: Add wdebug instruction. + +2001-06-15 Aldy Hernandez <aldyh@redhat.com> + + * m10300-opc.c (mn10300_opcodes): Change opcode for AM33 subc. + +2001-06-14 Geoffrey Keating <geoffk@redhat.com> + + * cgen-asm.c (cgen_parse_keyword): When looking for the + boundaries of a keyword, allow any special characters + that are actually in one of the allowed keyword. + * cgen-opc.c (cgen_keyword_add): Add any special characters + to the nonalpha_chars field. + +2001-06-12 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390-opc.c: Add lgh instruction. + * s390-opc.txt: Likewise. + +2001-06-11 Alan Modra <amodra@bigpond.net.au> + + * i386-dis.c: Group function prototypes in one place. + (FLOATCODE): Redefine as 1. + (USE_GROUPS): Redefine as 2. + (USE_PREFIX_USER_TABLE): Redefine as 3. + (X86_64_SPECIAL): Define as 4. + (GRP1b..GRPAMD): Move USE_GROUPS to bytecode1, index to bytecode2. + (PREGRP0..PREGRP26): Similarly with USE_PREFIX_USER_TABLE. + (dis386_att, dis386_intel, disx86_64_att, disx86_64_intel): Delete. + (dis386): New table combining above four tables. + (dis386_twobyte_att, dis386_twobyte_intel): Delete. + (dis386_twobyte): New table combining above two tables. + (x86_64_table): New table to handle x86_64. + (X86_64_0): Define. + (float_mem_att, float_mem_intel): Delet. + (float_mem): New table combining above two tables. + (print_insn_i386): Modify for above. + (dofloat): Likewise. + (putop): Handle '{', '|' and '}' to select alternative mnemonics. + Return 0 on success, 1 if no valid alternative. + (putop <case 'F'>, <case 'H'>): Print nothing for intel_syntax. + (putop <case 'T'>): Move to case 'U', and share case 'Q' code. + (putop <case 'I'>): Move to case 'T', and share case 'P' code. + (OP_REG <case rAX_reg .. rDI_reg>): Handle as for eAX_reg .. eDI_reg + if not 64-bit mode. + (OP_I <case q_mode>): Handle as for v_mode if not 64-bit mode. + (OP_I64): If not 64-bit mode, call OP_I. + OP_OFF64): If not 64-bit mode, call OP_OFF. + (OP_ST, OP_STi, OP_SEG, OP_DIR, OP_OFF, OP_OFF64, OP_MMX): Rename + 'ignore'/'ignored' to 'bytemode'. + +2001-06-10 Alan Modra <amodra@bigpond.net.au> + + * configure.in: Sort 'ta' case statement. + * configure: Regenerate. + + * i386-dis.c (dis386_att): Add 'H' to conditional branch and + loop,jcxz insns. + (disx86_64_att): Likewise. + (dis386_twobyte_att): Likewise. + (print_insn_i386): Don't print branch hints as a prefix. + (putop): 'H' macro prints branch hints. + (get64): Kill compile warnings. + +2001-06-09 Alexandre Oliva <aoliva@redhat.com> + + * sh-opc.h (sh_table): Don't use empty initializers. + +2001-06-06 Christian Groessler <cpg@aladdin.de> + + * z8k-dis.c: Fix formatting. + (unpack_instr): Remove unused cases in switch statement. Add + safety abort() in default case. + (unparse_instr): Add safety abort() in default case. + +2001-06-06 Peter Jakubek <pjak@snafu.de> + + * m68k-dis.c (print_insn_m68k): Fix typo. + * m68k-opc.c (m68k_opcodes): Correct allowed operands for + mcf (ColdFire) div, rem and moveb instructions. + +2001-06-06 Alan Modra <amodra@bigpond.net.au> + + * i386-dis.c (cond_jump_flag, loop_jcxz_flag): Define. + (cond_jump_mode, loop_jcxz_mode): Define. + (dis386_att): Add cond_jump_flag and loop_jcxz_flag as + appropriate, and 'F' suffix to loop insns. + (disx86_64_att): Likewise. + (dis386_twobyte_att): Likewise. + (print_insn_i386): Don't output addr prefix for loop, jcxz insns. + Output data size prefix for long conditional jumps. Output cs and + ds branch hints. + (putop): Handle 'F', and mark PREFIX_ADDR used for case 'E'. + (OP_J): Don't make PREFIX_DATA used. + +2001-06-04 Alexandre Oliva <aoliva@redhat.com> + + * sh-opc.h (sh_table): Complete last element entry to avoid + compiler warning. + +2001-05-16 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips-dis.c (mips_isa_type): Add MIPS r12k support. + +2001-05-23 Alan Modra <amodra@one.net.au> + + * arc-opc.c: Whitespace changes. + +2001-05-18 Hans-Peter Nilsson <hp@axis.com> + + * cris-opc.c (cris_spec_regs): Add missing initializer field for + last element. + +2001-05-15 Frank Ch. Eigler <fche@redhat.com> + + * cgen-dis.in (extract_normal): Complete support for min<base case. + +2001-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips-dis.c (INSNLEN): Rename MAXLEN. + (std_reg_names): Replace by mips32_reg_names and mips64_reg_names. + (print_insn_arg): Remove $ prefix of register names. + (set_mips_isa_type): Remove. + (mips_isa_type): New function. + (get_mips_isa): New Function. + (print_insn_mips): Rename _print_insn_mips. + (_print_insn_mips): New function, contains code which was + duplicated in print_insn_big_mips and print_insn_little_mips. + (print_insn_big_mips): Moved code to _print_insn_mips. + (print_insn_little_mips): Likewise. + (print_mips16_insn_arg): Remove $ prefix of register names. + Print error message before abort. + +2001-05-14 J.T. Conklin <jtc@redback.com> + + * ppc-opc.c (powerpc_opcodes): Fixed extended opcode field of + simplified mnemonics used for setting PPC750-specific special + purpose registers. + +2001-05-12 H.J. Lu <hjl@gnu.org> + + * i386-dis.c (print_insn_i386): Always set `mod', `reg' and + `rm'. + +2001-05-12 Peter Targett <peter.targett@arccores.com> + + * arc-opc.c (arc_reg_names): Correct attribute for lp_count + register to r/w. Formatting fixes throughout file. + +2001-05-12 Alan Modra <amodra@one.net.au> + + * i386-dis.c (prefix_user_table): Correct movq2dq, movdq2q, and + movq operands. + (twobyte_has_modrm): Update table. + (need_modrm): Give it file scope. + (MODRM_CHECK): Define. + (dofloat): Use MODRM_CHECK. + (OP_E): Likewise. + (OP_EM): Likewise. + (OP_EX): Likewise. + +2001-05-07 Frank Ch. Eigler <fche@redhat.com> + + * cgen-dis.in (default_print_insn): Tolerate min<base instructions + even at end of a section. + * cgen-ibld.in (extract_normal): Tolerate min!=base!=max instructions + by ignoring precariously-unpacked insn_value in favor of raw buffer. + +2001-05-03 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * disassemble.c (disassembler_usage): Remove unused attribute. + +2001-05-04 Frank Ch. Eigler <fche@redhat.com> + + * m32r-dis.c, -asm.c, -ibld.c: Regenerated with disassembler fixes. + +2001-05-04 Frank Ch. Eigler <fche@redhat.com> + + * cgen-dis.in (print_insn): Remove call to read_insn. Instead, + assume incoming buffer already has the base insn loaded. Handle + smaller-than-base instructions for variable-length case. + +2001-05-04 Alan Modra <amodra@one.net.au> + + * i386-dis.c (Ev, Ed): Remove duplicate define. + (Gd): Define. + (XS): Define. + (OP_XS): New function. + (dis386_twobyte_att): Correct pinsrw, pextrw, pmovmskb, and + movmskp operands. + (dis386_twobyte_intel): Likewise. + (prefix_user_table): Use MS for maskmovq operand. + +2001-04-27 Johan Rydberg <jrydberg@opencores.org> + + * Makefile.am: Add OpenRISC target. + * Makefile.in: Regenerated. + + * disassemble.c (disassembler): Recognize the OpenRISC disassembly. + + * configure.in (bfd_openrisc_arch): Add target. + * configure: Regenerated. + + * openrisc-asm.c: New file. + * openrisc-desc.c: Likewise. + * openrisc-desc.h: Likewise. + * openrisc-dis.c: Likewise. + * openrisc-ibld.c: Likewise. + * openrisc-opc.c: Likewise. + * openrisc-opc.h: Likewise. + +2001-04-24 Christian Groessler <cpg@aladdin.de> + + * z8k-dis.c: add names of control registers (ctrl_names); + (seg_length): provides instruction length fixup for segmented + mode; (unpack_instr): correctly handle ARG_DISP16, ARG_DISP12, + CLASS_0DISP7, CLASS_1DISP7, CLASS_DISP8 and CLASS_PR cases; + (unparse_intr): handle CLASS_PR, print addresses without '#' + * z8k-opc.h: re-created with new z8kgen + * z8kgen.c: merged in fixes which were in existing z8k-opc.h; new + entries for ldctl/ldctlb instruction + +2001-04-06 Andreas Jaeger <aj@suse.de> + + * i386-dis.c: Add ffreep instruction. + +2001-03-30 Alexandre Oliva <aoliva@redhat.com> + + * ppc-opc.c (insert_mbe): Shift mask initializer as long. + +2001-03-24 Alan Modra <alan@linuxcare.com.au> + + * i386-dis.c (PREGRP25): Define. + (dis386_twobyte_att): Use here in place of "movntq" entry. + (dis386_twobyte_intel): Likewise. + (prefix_user_table): Add PREGRP25 entry for "movntq" and "movntdq". + (PREGRP26): Define. + (dis386_twobyte_att): Use here. + (dis386_twobyte_intel): Likewise. + (prefix_user_table): Add PREGRP26 entry for "punpcklqdq". + (prefix_user_table <maskmovdqu>): XM operand, not MX. + (prefix_user_table): Cosmetic changes to "bad" entries. + +2001-03-23 Nick Clifton <nickc@redhat.com> + + * mips-opc.c: Remove extraneous whitespace. + * mips-dis.c: Remove extraneous whitespace. + +2001-03-22 Ben Elliston <bje@redhat.com> + + * cgen-asm.in (@arch@_cgen_assemble_insn): Move tmp_errmsg + declaration inside CGEN_VERBOSE_ASSEMBLER_ERRORS conditional. + * cgen-ibld.in (put_insn_int_value): Mark cd parameter as unused + to allay a compiler warning. + +2001-03-22 Alan Modra <alan@linuxcare.com.au> + + * i386-dis.c (dis386_twobyte_att): Add entries for paddq, psubq. + (dis386_twobyte_intel): Likewise. + (twobyte_has_modrm): Set entry for paddq, psubq. + +2001-03-20 Patrick Macdonald <patrickm@redhat.com> + + * cgen-dis.in (print_insn_@arch@): Add support for target machine + determination via CGEN_COMPUTE_MACH. + * fr30-desc.c: Regenerate. + * fr30-dis.c: Regenerate. + * fr30-opc.h: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + +2001-03-20 H.J. Lu <hjl@gnu.org> + + * configure.in: Remove the redundent AC_ARG_PROGRAM. + * configure: Rebuild. + +2001-03-19 Jim Wilson <wilson@redhat.com> + + * ia64-gen.c (fetch_insn_class): If xsect, then ignore comment and + notestr if larger than xsect. + (in_class): Handle format M5. + * ia64-asmtab.c: Regnerate. + +2001-03-19 John David Anglin <dave@hiauly1.hia.nrc.ca> + + * vax-dis.c (print_insn_vax): Only fetch two bytes if the info buffer + has more than one byte left to read. + +2001-03-16 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390-opc.c: Add new opcodes. Smooth out formatting. + * s390-opc.txt: Add new opcodes. + +2001-03-06 Nick Clifton <nickc@redhat.com> + + * arm-dis.c (print_insn_thumb): Compute destination address + of BLX(1) instruction by taking bit 1 from PC and not from bit + 0 of the offset. + +2001-03-06 Igor Shevlyakov <igor@windriver.com> + + * m68k-dis.c (print_insn_m68k): Recognize Coldfire CPUs + so command line switches will work. + +2001-03-05 Dave Brolley <brolley@redhat.com> + + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-desc.h: Regenerate. + * fr30-dis.c: Regenerate. + * fr30-ibld.c: Regenerate. + * fr30-opc.c: Regenerate. + * fr30-opc.h: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-desc.h: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-ibld.c: Regenerate. + * m32r-opc.c: Regenerate. + * m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + +2001-02-28 Igor Shevlyakov <igor@windriver.com> + + * m68k-opc.c: fix cpushl according to Motorola. Enable + bunch of instructions for Coldfire 5407 and add all new. + +2001-02-27 Alan Modra <alan@linuxcare.com.au> + + * configure.in (BFD_VERSION): Do without grep. + * configure: Regenerate. + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2001-02-23 David Mosberger <davidm@hpl.hp.com> + + * ia64-opc-a.c: Add missing pseudo-ops for "cmp" and "cmp4". + * ia64-asmtab.c: Regenerate. + +2001-02-21 David Mosberger <davidm@hpl.hp.com> + + * ia64-opc-d.c (ia64_opcodes_d): Break the "add" pattern into two + separate variants: one for IMM22 and the other for IMM14. + * ia64-asmtab.c: Regenerate. + +2001-02-21 Greg McGary <greg@mcgary.org> + + * cgen-opc.c (cgen_get_insn_value): Add missing `return'. + +2001-02-20 H.J. Lu <hjl@gnu.org> + + * Makefile.am (ia64-ic.tbl): Remove the target. + (ia64-raw.tbl): Likewise. + (ia64-waw.tbl): Likewise. + (ia64-war.tbl): Likewise. + (ia64-asmtab.c): Generate it in the source directory. + * Makefile.in: Regenerated. + +2001-02-18 lars brinkhoff <lars@nocrew.org> + + * Makefile.am: Add PDP-11 target. + * configure.in: Likewise. + * disassemble.c: Likewise. + * pdp11-dis.c: New file. + * pdp11-opc.c: New file. + +2001-02-14 Jim Wilson <wilson@redhat.com> + + * ia64-ic.tbl: Update from Intel. Add setf to fr-writers. + * ia64-asmtab.c: Regenerate. + +2001-02-12 Jan Hubicka <jh@suse.cz> + + * i386-dis.c (prefix_user_t): Add 'Y' to SSE ineger converison + instructions. + (putop): Handle 'Y' + +2001-02-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl> + + * mips-dis.c (print_insn_arg): Use top four bits of the address of + the following instruction not of the jump itself for the jump + target. + (print_mips16_insn_arg): Likewise. + +2001-02-11 Michael Sokolov <msokolov@ivan.Harhan.ORG> + + * Makefile.am (stamp-lib): ranlib the libopcodes.a in the build + directory. + * Makefile.in: Regenerate. + +2001-02-09 Schwidefsky <schwidefsky@de.ibm.com> + + * Makefile.am: Add linux target for S/390. + * Makefile.in: Likewise. + * configure.in: Likewise. + * disassemble.c: Likewise. + * s390-dis.c: New file. + * s390-mkopc.c: New file. + * s390-opc.c: New file. + * s390-opc.txt: New file. + +2001-02-05 Jim Wilson <wilson@redhat.com> + + * ia64-asmtab.c: Revert 2000-12-16 change. + +2001-02-02 Patrick Macdonald <patrickm@redhat.com> + + * fr30-desc.h: Regenerate with CGEN_MAX_SYNTAX_ELEMENTS. + * m32r-desc.h: Regenerate. + +2001-02-01 Jan Hubicka <jh@suse.cz> + + * i386-dis.c (dis386_att, grps): Use 'T' for push/pop + (putop): Handle 'T', alphabetize order, fix 'I' handling in Intel syntax + +2001-01-14 Alan Modra <alan@linuxcare.com.au> + + * hppa-dis.c (print_insn_hppa): Handle '>' and '<' arg types. + +2001-01-13 Nick Clifton <nickc@redhat.com> + + * disassemble.c: Remove spurious white space. + +2001-01-13 Jan Hubicka <jh@suse.cz> + + * i386-dis.c (dis386_att, disx86_64_att): Fix ret, lret and iret + templates. + +2001-01-11 Peter Targett <peter.targett@arccores.com> + + * configure.in: Add arc-ext.lo for bfd_arc_arch selection. + * Makefile.am (C_FILES): Add arc-ext.c. + (ALL_MACHINES) Add arc-ext.lo. + (INCLUDES) Add opcode directory to list. + New dependency entry for arc-ext.lo. + * disassemble.c (disassembler): Correct call to + arc_get_disassembler. + * arc-opc.c: New update for ARC, including full base + instructions for ARC variants. + * arc-dis.h, arc-dis.c: New update for ARC, including + extensibility functionality. + * arc-ext.h, arc-ext.c: New files for handling extensibility. + +2001-01-10 Jan Hubicka <jh@suse.cz> + + * i386-dis.c (PREGRP15 - PREGRP24): New. + (dis386_twobyt): Add SSE2 instructions. + (twobyte_uses_SSE_prefix: Rename from ... ; add new SSE instructions. + (twobyte_uses_f3_prefix): ... this one. + (grps): Add SSE instructions. + (prefix_user_table): Add two new slots; add SSE2 instructions. + (print_insn_i386): Rename uses_f3_prefix to uses_SSE_prefix; + Handle the REPNZ and Data16 prefixes as well; do proper lookup + to prefix_user_table. + (OP_E): Accept mfence and lfence as well. + (OP_MMX): Data16 prefix turns MMX to SSE; support REX extensions. + (OP_XMM): Support REX extensions. + (OP_EM): Likewise. + (OP_EX): Likewise. + +2001-01-09 Nick Clifton <nickc@redhat.com> + + * arm-dis.c (print_insn): Set pc to zero for instructions with + a reloc associated with them. + +2001-01-09 Jeff Johnston <jjohnstn@redhat.com> + + * cgen-asm.in (parse_insn_normal): Changed syn to be + CGEN_SYNTAX_CHAR_TYPE. Changed all references to *syn + as character to use CGEN_SYNTAX_CHAR macro and all comparisons + to '\0' to use 0 instead. + * cgen-dis.in (print_insn_normal): Ditto. + * cgen-ibld.in (insert_insn_normal, extract_insn_normal): Ditto. + +2001-01-05 Jan Hubicka <jh@suse.cz> + + * i386-dis.c: Add x86_64 support. + (rex): New static variable. + (REX_MODE64, REX_EXTX, REX_EXTY, REX_EXTZ): New constants. + (USED_REX): New macro. + (Ev, Ed, Rm, Iq, Iv64, Cm, Dm, Rm*, Ob64, Ov64): New macros. + (OP_I64, OP_OFF64, OP_IMREG): New functions. + (OP_REG, OP_OFF): Declare. + (get64, get32, get32s): New functions. + (r??_reg): New constants. + (dis386_att): Change templates of instruction implicitly promoted + to 64bit; change e?? to RMe?? for unwind RM byte instructions. + (grps): Likewise. + (dis386_intel): Likewise. + (dixx86_64_att): New table based on dis386_att. + (dixx86_64_intel): New table based on dis386_intel. + (names64, names8rex): New global variable. + (names32, names16): Add extended registers. + (prefix_user_t): Recognize rex prefixes. + (prefix_name): Print REX prefixes nicely. + (op_riprel): New global variable. + (start_pc): Set type to bfd_vma. + (print_insn_i386): Detect the 64bit mode and use proper table; + move ckprefix after initializing the buffer; output unused rex prefixes; + output information about target of RIP relative addresses. + (putop): Support 'O' and 'I'. Update handling of "P', 'Q', 'R' and 'S'; + (print_operand_value): New function. + (OP_E, OP_G, OP_REG, OP_I, OP_J, OP_DIR, OP_OFF, OP_D): Add support for + REX prefix and new modes. + (get64, get32s): New. + (get32): Return bfd_signed_vma type. + (set_op): Initialize the op_riprel. + * disassemble.c (disassembler): Recognize the x86-64 disassembly. + +2001-01-03 Richard Sandiford <r.sandiford@redhat.com> + + cgen-dis.in (read_insn): Use bfd_get_bits() + +2001-01-02 Richard Sandiford <rsandifo@redhat.com> + + * cgen-dis.c (hash_insn_array): Use bfd_put_bits(). + (hash_insn_list): Likewise + * cgen-ibld.in (insert_1): Use bfd_put_bits() and bfd_get_bits(). + (extract_1): Use bfd_get_bits(). + (extract_normal): Apply sign extension to both extraction + methods. + * cgen-opc.c (cgen_get_insn_value): Use bfd_get_bits() + (cgen_put_insn_value): Use bfd_put_bits() + +2000-12-28 Frank Ch. Eigler <fche@redhat.com> + + * cgen-asm.in (parse_insn_normal): Print better error message for + instructions with missing operands. + +2000-12-21 Santeri Paavolainen <santtu@ssh.com> + + * cgen-opc.c: Include alloca.h if HAVE_ALLOCA_H is defined. + +2000-12-16 Nick Clifton <nickc@redhat.com> + + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * configure.in: Add spacing. + * configure: Regenerate. + * ia64-asmtab.c: Regenerate. + * po/opcodes.pot: Regenerate. + +2000-12-12 Frank Ch. Eigler <fche@redhat.com> + + * cgen-asm.in (@arch@_cgen_assemble_insn): Prefer printing insert-time + error messages over later parse-time ones. + +2000-12-12 Jim Wilson <wilson@redhat.com> + + * ia64-dis.c (print_insn_ia64): Cast away const on ia64_free_opcode + argument. + * ia64-gen.c (insert_deplist): Cast sizeof result to int. + (print_dependency_table): Print NULL if semantics field not set. + (insert_opcode_dependencies): Mark cmp parameter as unused. + (print_main_table): Use fprintf_vma to print long long fields. + (main): Mark argv paramter as unused. Convert to old style definition. + * ia64-opc.c (ia64_find_dependency): Cast sizeof result to int. + * ia64-asmtab.c: Regnerate. + +2000-12-09 Nick Clifton <nickc@redhat.com> + + * m32r-dis.c (print_insn): Prevent re-read of instruction from + wrong address. + + * fr30-dis.c: Regenerate. + +2000-12-08 Peter Targett <peter.targett@arccores.com> + + * configure.in: Add arc-ext.lo for bfd_arc_arch selection. + * Makefile.am (C_FILES): Add arc-ext.c. + (ALL_MACHINES) Add arc-ext.lo. + (INCLUDES) Add opcode directory to list. + New dependency entry for arc-ext.lo. + * disassemble.c (disassembler): Correct call to + arc_get_disassembler. + * arc-opc.c: New update for ARC, including full base + instructions for ARC variants. + * arc-dis.h, arc-dis.c: New update for ARC, including + extensibility functionality. + * arc-ext.h, arc-ext.c: New files for handling extensibility. + +2000-12-03 Chris Demetriou cgd@sibyte.com + + * mips-opc.c (mips_builtin_opcodes): Use the WR_HILO, RD_HILO, + MOD_HILO, and MOD_LO macros. + + * mips-opc.c (M1, M2): Delete. + (mips_builtin_opcodes): Remove all uses of M1. + + * mips-opc.c (mips_builtin_opcodes): Make the dmfc2 and dmtc2 + instructions take "G" format second operands and use the + correct flags. + There are mfc3 and mtc3 opcodes, so add dmfc3 and dmtc3 opcodes to + match. + Delete "sel" code operands from mfc1 and mtc1. + Add MIPS64 opcode changes (dclo, dclz), and "sel" code variants + for dm[ft]c[023]. + +2000-12-03 Ed Satterthwaite ehs@sibyte.com and + Chris Demetriou cgd@sibyte.com + + * mips-opc.c (mips_builtin_opcodes): Finish additions + for MIPS32 support, and clean up existing entries for + aesthetics, consistency with the MIPS32 ISA, and + with consistency the rest of the table. + +2000-12-01 Nick Clifton <nickc@redhat.com> + + * mips16-opc.c (mips16_opcodes): Add initialiser for membership + field. + +2000-12-01 Chris Demetriou <cgd@sibyte.com> + + mips-dis.c (print_insn_arg): Handle new 'U' and 'J' argument + specifiers. Update 'B' for new constant names, and remove + 'm'. + mips-opc.c (mips_builtin_opcodes): Place "pref" and "ssnop" + near the top of the array, so they are disassembled properly. + Enable "ssnop" for MIPS32. Add "break" variant with 20 bit + code for MIPS32. Update "clo" and "clz" to use 'U' operand + specifier. Add 'H' format specifier variants for "mfc1," + "mfc2," "mfc3," "mtc1," "mtc2," and "mtc3" for MIPS32. Update + MIPS32 "sdbbp" to use 'B' operand specifier. Add MIPS32 + "wait" variant which uses 'J' operand specifier. + + * mips-dis.c (set_mips_isa_type): Update to use + CPU_UNKNOWN and ISA_* constants. Add bfd_mach_mips32 case. + Replace bfd_mach_mips4K with bfd_mach_mips32_4k case. + * mips-opc.c (I32): New constant for instructions added in + MIPS32. + (P4): Delete. + (mips_builtin_opcodes) Replace all uses of P4 with I32. + + * mips-dis.c (set_mips_isa_type): Add cases for + bfd_mach_mips5 and bfd_mach_mips64. + * mips-opc.c (I64): New definitions. + + * mips-dis.c (set_mips_isa_type): Add case for + bfd_mach_mips_sb1. + +2000-11-28 Hans-Peter Nilsson <hp@bitrange.com> + + * sh-dis.c (print_insn_ddt): Make insn_x, insn_y unsigned. + (print_insn_ppi): Make nib1, nib2, nib3 unsigned. + Initialize variable dc to NULL. + (print_insn_shx): Remove unused label d_reg_n. + +2000-11-24 Nick Clifton <nickc@redhat.com> + + * arm-opc.h: Add new opcode formatting parameter 'B'. + (arm_opcodes): Add XScale, v5, and v5te instructions. + (thumb_opcodes): Add v5t instructions. + + * arm-dis.c (print_insn_arm): Handle new 'B' format + parameter. + (print_insn_thumb): Decode BLX(1) instruction. + +2000-11-21 Chris Demetriou <cgd@sibyte.com> + + * mips-opc.c: Fix file header comment. + +2000-11-14 Hans-Peter Nilsson <hp@axis.com> + + * cris-dis.c (cris_get_disassembler): If abfd is NULL, return + print_insn_cris_with_register_prefix. + +2000-11-11 Alexandre Oliva <aoliva@redhat.com> + + * sh-opc.h: The operand of `mov.w r0, (<disp>,GBR)' is IMM1, not 0. + +2000-11-07 Matthew Green <mrg@redhat.com> + + * cgen-dis.in (print_insn): All insns which can fit into insn_value + must be loaded there in their entirety. + +2000-10-20 Jakub Jelinek <jakub@redhat.com> + + * sparc-dis.c (v9a_asr_reg_names): Add v9b ASRs. + (compute_arch_mask): Add v8plusb and v9b machines. + (print_insn_sparc): siam mode decoding, accept ASRs up to 25. + * sparc-opc.c: Support for Cheetah instruction set. + (prefetch_table): Add #invalidate. + +2000-10-16 Nick Clifton <nickc@redhat.com> + + * mcore-dis.c (imsk): Change mask for OC to 0xFE00. + +2000-10-06 Dave Brolley <brolley@redhat.com> + + * fr30-desc.h: Regenerate. + * m32r-desc.h: Regenerate. + * m32r-ibld.c: Regenerate. + +2000-10-05 Jim Wilson <wilson@redhat.com> + + * ia64-ic.tbl: Update from Intel. + * ia64-asmtab.c: Regenerate. + +2000-10-04 Kazu Hirata <kazu@hxi.com> + + * ia64-gen.c: Convert C++-style comments to C-style comments. + * tic54x-dis.c: Likewise. + +2000-09-29 Hans-Peter Nilsson <hp@axis.com> + + Changes to add dollar prefix to registers for files where user symbols + don't have a leading underscore. Fix formatting. + * cris-dis.c (REGISTER_PREFIX_CHAR): New. + (format_reg): Add parameter with_reg_prefix. All callers changed. + (print_with_operands): Ditto. + (print_insn_cris_generic): Renamed from print_insn_cris, add + parameter with_reg_prefix. + (print_insn_cris_with_register_prefix, + print_insn_cris_without_register_prefix, cris_get_disassembler): + New. + * disassemble.c (disassembler) [ARCH_cris]: Call cris_get_disassembler. + +2000-09-22 Jim Wilson <wilson@redhat.com> + + * ia64-opc-f.c (ia64_opcodes_f): Add fpcmp pseudo-ops for + gt, ge, ngt, and nge. + * ia64-asmtab.c: Regenerate. + + * ia64-dis.c (print_insn_ia64): Revert Aug 7 byte skip count change. + * ia64-gen.c (parse_semantics): Handle IA64_DVS_STOP. + (lookup_specifier): Handle "PR%, 1 to 15" and "PR%, 16 to 62". + * ia64-ic.tbl, ia64-raw.tbl, ia64-war.tbl, ia64-waw.tbl: Update. + * ia64-asmtab.c: Regnerate. + +2000-09-13 Anders Norlander <anorland@acc.umu.se> + + * mips-opc.c (mips_builtin_opcodes): Support cache instruction on 4K cores. + Add mfc0 and mtc0 with sub-selection values. + Add clo and clz opcodes. + Add msub and msubu instructions for MIPS32. + Add madd/maddu aliases for mad/madu for MIPS32. + Support wait, deret, eret, movn, pref for MIPS32. + Support tlbp, tlbr, tlbwi, tlbwr. + (P4): New define. + + * mips-dis.c (print_insn_arg): Print sdbbp 'm' args. + (print_insn_arg): Handle 'H' args. + (set_mips_isa_type): Recognize 4K. + Use CPU_* defines instead of hardcoded numbers. + +2000-09-11 Catherine Moore <clm@redhat.com> + + * d30v-opc.c (d30v_operand_t): New operand type Rb2. + (d30v_format_tab): Use Rb2 for modinc and moddec. + +2000-09-07 Catherine Moore <clm@redhat.com> + + * d30v-opc.c (d30v_format_tab): Use format Ra for + modinc and moddec. + +2000-09-06 Alexandre Oliva <aoliva@redhat.com> + + * configure: Rebuilt with new libtool.m4. + +2000-09-05 Nick Clifton <nickc@redhat.com> + + * configure: Regenerate. + * po/opcodes.pot: Regenerate. + +2000-08-31 Alexandre Oliva <aoliva@redhat.com> + + * acinclude.m4: Include libtool and gettext macros from the + top level. + * aclocal.m4, configure: Rebuilt. + +2000-08-30 Kazu Hirata <kazu@hxi.com> + + * tic80-dis.c: Fix formatting. + +2000-08-29 Kazu Hirata <kazu@hxi.com> + + * w65-dis.c: Fix formatting. + +2000-08-28 Mark Hatle <mhatle@mvista.com> + + * ppc-opc.c: Add XTLB macro for a few PPC 4xx extended mnemonics. + (powerpc_opcodes): Add table entries for PPC 405 instructions. + Changed rfci, icbt, mfdcr, dccci, mtdcr, iccci from PPC to PPC403 + instructions. Added extended mnemonic mftbl as defined in the + 405GP manual for all PPCs. + +2000-08-28 Jim Wilson <wilson@redhat.com> + + * ia64-dis.c (print_insn_ia64): Add failed label after ia64_free_opcode + call. Change last goto to use failed instead of done. + +2000-08-28 Dave Brolley <brolley@redhat.com> + + * cgen-ibld.in (cgen_put_insn_int_value): New function. + (insert_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P. + (insert_insn_normal): Use cgen_put_insn_int_value with CGEN_INT_INSN_P. + (extract_normal): Allow for non-zero word_offset with CGEN_INT_INSN_P. + * cgen-dis.in (read_insn): New static function. + (print_insn): Use read_insn to read the insn into the buffer and set + up for disassembly. + (print_insn): in CGEN_INT_INSN_P, make sure that the entire insn is + in the buffer. + * fr30-asm.c: Regenerated. + * fr30-desc.c: Regenerated. + * fr30-desc.h: Regenerated. + * fr30-dis.c: Regenerated. + * fr30-ibld.c: Regenerated. + * fr30-opc.c: Regenerated. + * fr30-opc.h: Regenerated. + * m32r-asm.c: Regenerated. + * m32r-desc.c: Regenerated. + * m32r-desc.h: Regenerated. + * m32r-dis.c: Regenerated. + * m32r-ibld.c: Regenerated. + * m32r-opc.c: Regenerated. + +2000-08-28 Kazu Hirata <kazu@hxi.com> + + * tic30-dis.c: Fix formatting. + +2000-08-27 Kazu Hirata <kazu@hxi.com> + + * sh-dis.c: Fix formatting. + +2000-08-24 David Edelsohn <dje@watson.ibm.com> + + * ppc-opc.c (powerpc_opcodes): Add rfid, mtsrd, mtsrdin, mtmsrd. + +2000-08-24 Kazu Hirata <kazu@hxi.com> + + * z8k-dis.c: Fix formatting. + +2000-08-16 Jim Wilson <wilson@redhat.com> + + * ia64-ic.tbl (pr-readers-nobr-nomovpr): Add addl, adds. Delete + break, mov-immediate, nop. + * ia64-opc-f.c: Delete fpsub instructions. + * ia64-opc-m.c: Add POSTINC to all instructions with postincrement + address operand. Rewrite using macros to avoid long lines. + * ia64-opc.h (POSTINC): Define. + * ia64-asmtab.c: Regenerate. + +2000-08-15 Jim Wilson <wilson@redhat.com> + + * ia64-ic.tbl: Add missing entries. + +2000-08-08 Jason Eckhardt <jle@redhat.com> + + * i860-dis.c (print_br_address): Change third argument from int + to long. + +2000-08-07 Richard Henderson <rth@redhat.com> + + * ia64-dis.c (print_insn_ia64): Get byte skip count correct + for MLI templates. Handle IA64_OPND_TGT64. + +2000-08-04 Ben Elliston <bje@redhat.com> + + * cgen-dis.in, cgen-asm.in, cgen-ibld.in: New files. + * cgen.sh: Likewise. + +2000-08-02 Jim Wilson <wilson@redhat.com> + + * ia64-dis.c (print_insn_ia64): Call ia64_free_opcode at end. + +2000-07-29 Marek Michalkiewicz <marekm@linux.org.pl> + + * avr-dis.c (avr_operand): Use PARAMS macro in declaration. + Change return type from void to int. Check the combination + of operands, return 1 if valid. Fix to avoid BUF overflow. + Report undefined combinations of operands in COMMENT. + Report internal errors to stderr. Output the adiw/sbiw + constant operand in both decimal and hex. + (print_insn_avr): Disassemble ldd/std with displacement of 0 + as ld/st. Check avr_operand () return value, handle invalid + combinations of operands like unknown opcodes. + +2000-07-28 Ben Elliston <bje@redhat.com> + + * Makefile.am (CGEN, CGENDEPS, CGENDIR, CGENFLAGS): New. + (run-cgen, stamp-m32r, stamp-fr30): New targets. + * Makefile.in: Regenerate. + * configure.in: Add --enable-cgen-maint option. + * configure: Regenerate. + +2000-07-26 Dave Brolley <brolley@redhat.com> + + * cgen-opc.c (cgen_hw_lookup_by_name): 'i' is now unsigned. + (cgen_hw_lookup_by_num): Ditto. + (cgen_operand_lookup_by_name): Ditto. + (print_address): Ditto. + (print_keyword): Ditto. + * cgen-dis.c (hash_insn_array): Mark unused parameters with + ATTRIBUTE_UNUSED. + * cgen-asm.c (hash_insn_array): Mark unused parameters with + ATTRIBUTE_UNUSED. + (cgen_parse_keyword): Ditto. + +2000-07-22 Jason Eckhardt <jle@redhat.com> + + * i860-dis.c: New file. + (print_insn_i860): New function. + (print_br_address): New function. + (sign_extend): New function. + (BITWISE_OP): New macro. + (I860_REG_PREFIX): New macro. + (grnames, frnames, crnames): New structures. + + * disassemble.c (ARCH_i860): Define. + (disassembler): Add check for bfd_arch_i860 to set disassemble + function to print_insn_i860. + + * Makefile.in (CFILES): Added i860-dis.c. + (ALL_MACHINES): Added i860-dis.lo. + (i860-dis.lo): New dependences. + + * configure.in: New bits for bfd_i860_arch. + + * configure: Regenerated. + +2000-07-20 Hans-Peter Nilsson <hp@axis.com> + + * Makefile.am (CFILES): Add cris-dis.c and cris-opc.c. + (ALL_MACHINES): Add cris-dis.lo and cris-opc.lo. + (cris-dis.lo, cris-opc.lo): New rules. + * Makefile.in: Rebuild. + * configure.in (bfd_cris_arch): New target. + * configure: Rebuild. + * disassemble.c (ARCH_cris): Define. + (disassembler): Support ARCH_cris. + * cris-dis.c, cris-opc.c: New files. + * po/POTFILES.in, po/opcodes.pot: Regenerate. + +2000-07-11 Jakub Jelinek <jakub@redhat.com> + + * sparc-opc.c (sparc_opcodes): popc has 0 in rs1, not rs2. + Reported by Bill Clarke <llib@computer.org>. + +2000-07-09 Geoffrey Keating <geoffk@redhat.com> + + * ppc-opc.c (powerpc_opcodes): Correct suffix for vslw. + Patch by Randall J Fisher <rfisher@ecn.purdue.edu>. + +2000-07-09 Alan Modra <alan@linuxcare.com.au> + + * hppa-dis.c (fput_reg, fput_fp_reg, fput_fp_reg_r, fput_creg, + fput_const, extract_3, extract_5_load, extract_5_store, + extract_5r_store, extract_5R_store, extract_10U_store, + extract_5Q_store, extract_11, extract_14, extract_16, extract_21, + extract_12, extract_17, extract_22): Prototype. + (print_insn_hppa): Rename inner block opcode -> opc to avoid + shadowing outer block. + (GET_BIT): Define. + +2000-07-05 DJ Delorie <dj@redhat.com> + + * MAINTAINERS: new + +2000-07-04 Alexandre Oliva <aoliva@redhat.com> + + * arm-dis.c (print_insn_arm): Output combinations of PSR flags. + +2000-07-03 Marek Michalkiewicz <marekm@linux.org.pl> + + * avr-dis.c (avr_operand): Change _ () to _() around all strings + marked for translation (exception from the usual coding style). + (print_insn_avr): Initialize insn2 to avoid warnings. + +2000-07-03 Kazu Hirata <kazu@hxi.com> + + * h8300-dis.c (bfd_h8_disassemble): Improve readability. + * h8500-dis.c: Fix formatting. + +2000-07-01 Alan Modra <alan@linuxcare.com.au> + + * Makefile.am (DEP): Fix 2000-06-22. grep after running dep.sed + (CLEANFILES): Add DEPA. + * Makefile.in: Regenerate. + +2000-06-26 Scott Bambrough <scottb@netwinder.org> + + * arm-dis.c (regnames): Add an additional register set to match + the set used by GCC. Make it the default. + +2000-06-22 Alan Modra <alan@linuxcare.com.au> + + * Makefile.am (DEP): grep for leading `/' in DEP1, and fail if we + find one. + * Makefile.in: Regenerate. + +2000-06-20 H.J. Lu <hjl@gnu.org> + + * Makefile.am: Rebuild dependency. + * Makefile.in: Rebuild. + +2000-06-18 Stephane Carrez <stcarrez@worldnet.fr> + + * Makefile.in, configure: regenerate + * disassemble.c (disassembler): Recognize ARCH_m68hc12, + ARCH_m68hc11. + * m68hc11-dis.c (read_memory, print_insn, print_insn_m68hc12): + New functions. + * configure.in: Recognize m68hc12 and m68hc11. + * m68hc11-dis.c, m68hc11-opc.c: New files for support of m68hc1x + * Makefile.am (CFILES, ALL_MACHINES): New files for disassembly + and opcode generation for m68hc11 and m68hc12. + +2000-06-16 Nick Duffek <nsd@redhat.com> + + * disassemble.c (disassembler): Refer to the PowerPC 620 using + bfd_mach_ppc_620 instead of 620. + +2000-06-12 Kazu Hirata <kazu@hxi.com> + + * h8300-dis.c: Fix formatting. + (bfd_h8_disassemble): Distinguish adds/subs, inc/dec.[wl] + correctly. + +2000-06-09 Denis Chertykov <denisc@overta.ru> + + * avr-dis.c (avr_operand): Bugfix for jmp/call address. + +2000-06-07 Denis Chertykov <denisc@overta.ru> + + * avr-dis.c: completely rewritten. + +2000-06-02 Kazu Hirata <kazu@hxi.com> + + * h8300-dis.c: Follow the GNU coding style. + (bfd_h8_disassemble) Fix a typo. + +2000-06-01 Kazu Hirata <kazu@hxi.com> + + * h8300-dis.c (bfd_h8_disassemble_init): Fix a typo. + (bfd_h8_disassemble): Distinguish the operand size of inc/dev.[wl] + correctly. Fix a typo. + +2000-05-31 Nick Clifton <nickc@redhat.com> + + * opintl.h (_(String)): Explain why dgettext is used instead of + gettext. + +2000-05-30 Nick Clifton <nickc@redhat.com> + + * opintl.h (gettext, dgettext, dcgettext, textdomain, + bindtextdomain): Replace defines with those from intl/libgettext.h + to quieten gcc warnings. + +2000-05-26 Alan Modra <alan@linuxcare.com.au> + + * Makefile.am: Update dependencies with "make dep-am" + * Makefile.in: Regenerate. + +2000-05-25 Alexandre Oliva <aoliva@redhat.com> + + * m10300-dis.c (disassemble): Don't assume 32-bit longs when + sign-extending operands. + +2000-05-15 Donald Lindsay <dlindsay@redhat.com> + + * d10v-opc.c (d10v_opcodes): add ALONE tag to all short branches + except brf's. + +2000-05-21 Nick Clifton <nickc@redhat.com> + + * Makefile.am (LIBIBERTY): Define. + +2000-05-19 Diego Novillo <dnovillo@redhat.com> + + * mips-dis.c (REGISTER_NAMES): Rename to STD_REGISTER_NAMES. + (STD_REGISTER_NAMES): New name for REGISTER_NAMES. + (reg_names): Rename to std_reg_names. Change it to a char ** + static variable. + (std_reg_names): New name for reg_names. + (set_mips_isa_type): Set reg_names to point to std_reg_names by + default. + +2000-05-16 Frank Ch. Eigler <fche@redhat.com> + + * fr30-desc.h: Partially regenerated to account for changed + CGEN_MAX_* -> CGEN_ACTUAL_MAX_* macros. + * m32r-desc.h: Ditto. + +2000-05-15 Nick Clifton <nickc@redhat.com> + + * arm-opc.h: Use upper case for flasg in MSR and MRS + instructions. Allow any bit to be set in the field_mask of + the MSR instruction. + + * arm-dis.c (print_insn_arm): Decode _x and _s bits of the + field_mask of an MSR instruction. + +2000-05-11 Thomas de Lellis <tdel@windriver.com> + + * arm-opc.h: Disassembly of thumb ldsb/ldsh + instructions changed to ldrsb/ldrsh. + +2000-05-11 Ulf Carlsson <ulfc@engr.sgi.com> + + * mips-dis.c (print_insn_arg): Don't mask top 32 bits of 64-bit + target addresses for 'jal' and 'j'. + +2000-05-10 Geoff Keating <geoffk@redhat.com> + + * ppc-opc.c (powerpc_opcodes): Make the predicted-branch opcodes + also available in common mode when powerpc syntax is being used. + +2000-05-08 Alan Modra <alan@linuxcare.com.au> + + * m68k-dis.c (dummy_printer): Add ATTRIBUTE_UNUSED to args. + (dummy_print_address): Ditto. + +2000-05-04 Timothy Wall <twall@redhat.com> + + * tic54x-opc.c: New. + * tic54x-dis.c: New. + * disassemble.c (disassembler): Add ARCH_tic54x. + * configure.in: Added tic54x target. + * configure: Ditto. + * Makefile.am: Add tic54x dependencies. + * Makefile.in: Ditto. + +2000-05-03 J.T. Conklin <jtc@redback.com> + + * ppc-opc.c (VA, VB, VC, VD, VS, SIMM, UIMM, SHB): New macros, for + vector unit operands. + (VX, VX_MASK, VXA, VXA_MASK, VXR, VXR_MASK): New macros, for vector + unit instruction formats. + (PPCVEC): New macro, mask for vector instructions. + (powerpc_operands): Add table entries for above operand types. + (powerpc_opcodes): Add table entries for vector instructions. + + * ppc-dis.c (print_insn_big_powerpc): Add PPC_OPCODE_ALTIVEC to mask. + (print_insn_little_powerpc): Likewise. + (print_insn_powerpc): Prepend 'v' when printing vector registers. + +2000-04-24 Clinton Popetz <cpopetz@redhat.com> + + * configure.in: Add bfd_powerpc_64_arch. + * disassemble.c (disassembler): Use print_insn_big_powerpc for + 64 bit code. + +2000-04-24 Nick Clifton <nickc@redhat.com> + + * fr30-desc.c (fr30_cgen_cpu_open): Initialise signed_overflow + field. + +2000-04-23 Denis Chertykov <denisc@overta.ru> + + * avr-dis.c (reg_fmul_d): New. Extract destination register from + FMUL instruction. + (reg_fmul_r): New. Extract source register from FMUL instruction. + (reg_muls_d): New. Extract destination register from MULS instruction. + (reg_muls_r): New. Extract source register from MULS instruction. + (reg_movw_d): New. Extract destination register from MOVW instruction. + (reg_movw_r): New. Extract source register from MOVW instruction. + (print_insn_avr): Handle MOVW, MULS, MULSU, FMUL, FMULS, FMULSU, + EICALL, EIJMP, LPM r,Z, ELPM r,Z, SPM, ESPM instructions. + +2000-04-22 Timothy Wall <twall@redhat.com> + + * ia64-gen.c (general): Add an ordered table of primary + opcode names, as well as priority fields to disassembly data + structures to enforce a preferred disassembly format based on the + ordering of the opcode tables. + (load_insn_classes): Show a useful message if IC tables are missing. + (load_depfile): Ditto. + * ia64-asmtab.h (struct ia64_dis_names ): Add priority flag to + distinguish preferred disassembly. + * ia64-opc-f.c: Reorder some insn for preferred disassembly + format. Fix incorrect flag on fma.s/fma.s.s0. + * ia64-opc.c: Scan *all* disassembly matches and use the one with + the highest priority. + * ia64-opc-b.c: Use more abbreviations. + * ia64-asmtab.c: Regenerate. + +2000-04-21 Jason Eckhardt <jle@redhat.com> + + * hppa-dis.c (extract_16): New function. + (print_insn_hppa): Fix incorrect handling of 'fe'. Added handling of + new operand types l,y,&,fe,fE,fx. + +2000-04-21 Richard Henderson <rth@redhat.com> + David Mosberger <davidm@hpl.hp.com> + Timothy Wall <twall@redhat.com> + Bob Manson <manson@charmed.cygnus.com> + Jim Wilson <wilson@redhat.com> + + * Makefile.am (HFILES): Add ia64-asmtab.h, ia64-opc.h. + (CFILES): Add ia64-dis.c, ia64-opc-a.c, ia64-opc-b.c, ia64-opc-f.c, + ia64-opc-i.c, ia64-opc-m.c, ia64-opc-d.c, ia64-opc.c, ia64-gen.c, + ia64-asmtab.c. + (ALL_MACHINES): Add ia64-dis.lo, ia64-opc.lo. + (ia64-ic.tbl, ia64-raw.tbl, ia64-waw.tbl, ia64-war.tbl, ia64-gen, + ia64-gen.o, ia64-asmtab.c, ia64-dis.lo, ia64-opc.lo): New rules. + * Makefile.in: Rebuild. + * configure Rebuild. + * configure.in (bfd_ia64_arch): New target. + * disassemble.c (ARCH_ia64): Define. + (disassembler): Support ARCH_ia64. + * ia64-asmtab.c, ia64-asmtab.h, ia64-dis.c, ia64-gen.c ia64-ic.tbl, + ia64-opc-a.c, ia64-opc-b.c, ia64-opc-d.c ia64-opc-f.c, ia64-opc-i.c, + ia64-opc-m.c, ia64-opc-x.c, ia64-opc.c, ia64-opc.h, ia64-raw.tbl, + ia64-war.tbl, ia64-waw.tbl: New files. + +2000-04-20 Alexandre Oliva <aoliva@redhat.com> + + * m10300-dis.c (HAVE_AM30, HAVE_AM33): Define. + (disassemble): Use them. + +2000-04-14 Alan Modra <alan@linuxcare.com.au> + + * sysdep.h: Include "ansidecl.h" not <ansidecl.h> + * Makefile.am: Update dependencies. + * Makefile.in: Regenerate. + +2000-04-14 Michael Sokolov <msokolov@ivan.Harhan.ORG> + + * a29k-dis.c, alpha-dis.c, alpha-opc.c, arc-dis.c, arc-opc.c, + avr-dis.c, d10v-dis.c, d10v-opc.c, d30v-dis.c, d30v-opc.c, + disassemble.c, h8300-dis.c, h8500-dis.c, hppa-dis.c, i370-dis.c, + i370-opc.c, i960-dis.c, m10200-dis.c, m10200-opc.c, m10300-dis.c, + m10300-opc.c, m68k-dis.c, m68k-opc.c, m88k-dis.c, mcore-dis.c, + mips-dis.c, mips-opc.c, mips16-opc.c, pj-dis.c, pj-opc.c, + ppc-dis.c, ppc-opc.c, sh-dis.c, sparc-dis.c, sparc-opc.c, + tic80-dis.c, tic80-opc.c, v850-dis.c, v850-opc.c, vax-dis.c, + w65-dis.c, z8k-dis.c, z8kgen.c: Include sysdep.h. Remove + ansidecl.h as sysdep.h includes it. + +2000-04-7 Andrew Cagney <cagney@b1.redhat.com> + + * configure.in (WARN_CFLAGS): Set to -W -Wall by default. Add + --enable-build-warnings option. + * Makefile.am (AM_CFLAGS, WARN_CFLAGS): Add definitions. + * Makefile.in, configure: Re-generate. + +2000-04-05 J"orn Rennecke <amylaar@redhat.com> + + * sh-opc.h (sh_table): Use A_DISP_PC / PCRELIMM_8BY2 for ldre & ldrs. + stc GBR,@-<REG_N> is available for arch_sh1_up. + Group parallel processing insn with identical mnemonics together. + Make three-operand psha / pshl come first. + +2000-04-05 J"orn Rennecke <amylaar@redhat.co.uk> + + * sh-opc.h (sh_nibble_type): Remove DISP_8 and DISP_4. + Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. + (sh_arg_type): Add A_PC. + (sh_table): Update entries using immediates. Add repeat. + * sh-dis.c (print_insn_shx): Remove DISP_8 and DISP_4. + Split IMM_[48]{,BY[24]} into IMM[01]_[48]{,BY[24]}. Add REPEAT. + +2000-04-04 Alan Modra <alan@linuxcare.com.au> + + * po/opcodes.pot: Regenerate. + + * Makefile.am (MKDEP): Use gcc -MM rather than mkdep. + (DEP): Quote when passing vars to sub-make. Add warning message + to end. + (DEP1): Rewrite for "gcc -MM". + (CLEANFILES): Add DEP2. + Update dependencies. + * Makefile.in: Regenerate. + +2000-04-03 Denis Chertykov <denisc@overta.ru> + + * avr-dis.c: Syntax cleanup. + (add0fff): Print the pc relative address as a signed number. + (add03f8): Likewise. + +2000-04-01 Ian Lance Taylor <ian@zembu.com> + + * disassemble.c (disassembler_usage): Don't use a prototype. Mark + the parameter ATTRIBUTE_UNUSED. + * ppc-opc.c: Add ATTRIBUTE_UNUSED as needed. + +2000-04-01 Alexandre Oliva <aoliva@redhat.com> + + * m10300-opc.c: SP-based offsets are always unsigned. + +2000-03-29 Thomas de Lellis <tdel@windriver.com> + + * arm-opc.h (thumb_opcodes): Disassemble 0xde.. to "bal" + [branch always] instead of "undefined". + +2000-03-27 Nick Clifton <nickc@redhat.com> + + * d30v-opc.c (d30v_format_table): Move SHORT_AR to end of list of + short instructions, from end of list of long instructions. + +2000-03-27 Ian Lance Taylor <ian@zembu.com> + + * Makefile.am (CFILES): Add avr-dis.c. + (ALL_MACHINES): Add avr-dis.lo. + +2000-03-27 Alan Modra <alan@linuxcare.com> + + * avr-dis.c (add0fff, add03f8): Don't use structure bitfields to + truncate integers. + (print_insn_avr): Call function via pointer in K&R compatible way. + (dispLDD, regPP, reg50, reg104, reg40, reg20w, lit404, lit204, + add0fff, add03f8): Convert to old style function declaration and + add prototype. + (avrdis_opcode): Add prototype. + +2000-03-27 Denis Chertykov <denisc@overta.ru> + + * avr-dis.c: New file. AVR disassembler. + * configure.in (bfd_avr_arch): New architecture support. + * disassemble.c: Likewise. + * configure: Regenerate. + +2000-03-06 J"oern Rennecke <amylaar@redhat.com> + + * sh-opc.h (sh_table): ldre and ldrs have a *signed* displacement. + +2000-03-02 J"orn Rennecke <amylaar@redhat.co.uk> + + * d30v-dis.c (print_insn): Remove d*i hacks. Use per-operand + flag to determine if operand is pc-relative. + * d30v-opc.c: + (d30v_format_table): + (REL6S3): Renamed from IMM6S3. + Added flag OPERAND_PCREL. + (REL12S3, REL18S3, REL32): Split from IMM12S3, IMM18S3, REL32, with + added flag OPERAND_PCREL. + (IMM12S3U): Replaced with REL12S3. + (SHORT_D2, LONG_D): Delay target is pc-relative. + (SHORT_B2r, SHORT_B3r, SHORT_B3br, SHORT_D2r, LONG_Ur, LONG_2r): + Split from SHORT_B2, SHORT_D2, SHORT_B3b, SHORT_D2, LONG_U, LONG_2r, + using the REL* operands. + (LONG_2br, LONG_Dr): Likewise, from LONG_2b, LONG_D. + (SHORT_D1r, SHORT_D2Br, LONG_Dbr): Renamed from SHORT_D1, SHORT_D2B, + LONG_Db, using REL* operands. + (SHORT_U, SHORT_A5S): Removed stray alternatives. + (d30v_opcode_table): Use new *r formats. + +2000-02-28 Nick Clifton <nickc@redhat.com> + + * m32r-desc.c (m32r_cgen_cpu_open): Replace 'flags' with + 'signed_overflow_ok_p'. + +2000-02-27 Eli Zaretskii <eliz@is.elta.co.il> + + * Makefile.am (stamp-lib): Use $(LIBTOOL) --config to get the + name of the libtool directory. + * Makefile.in: Rebuild. + +2000-02-24 Nick Clifton <nickc@redhat.com> + + * cgen-opc.c (cgen_set_signed_overflow_ok): New function. + (cgen_clear_signed_overflow_ok): New function. + (cgen_signed_overflow_ok_p): New function. + +2000-02-23 Andrew Haley <aph@redhat.com> + + * m32r-asm.c, m32r-desc.c, m32r-desc.h, m32r-dis.c, + m32r-ibld.c, m32r-opc.h: Rebuild. + +2000-02-23 Linas Vepstas <linas@linas.org> + + * i370-dis.c, i370-opc.c: New. + + * disassemble.c (ARCH_i370): Define. + (disassembler): Handle it. + + * Makefile.am: Add support for Linux/IBM 370. + * configure.in: Likewise. + + * Makefile.in: Regenerate. + * configure: Likewise. + +2000-02-22 Chandra Chavva <cchavva@redhat.com> + + * d30v-opc.c (d30v_opcode_tab) : Added FLAG_NOT_WITH_ADDSUBppp to + ST2H, STB, STH, STHH, STW and ST2H opcodes to prohibit parallel + procedure. + +2000-02-22 Andrew Haley <aph@redhat.com> + + * mips-dis.c (_print_insn_mips): New arg for OPCODE_IS_MEMBER: + force gp32 to zero. + * mips-opc.c (G6): New define. + (mips_builtin_op): Add "move" definition for -gp32. + +2000-02-22 Ian Lance Taylor <ian@zembu.com> + + From Grant Erickson <gerickso@Brocade.COM>: + * ppc-opc.c: Correct dcread--it takes 3 arguments, not 2. + +2000-02-21 Alan Modra <alan@spri.levels.unisa.edu.au> + + * dis-buf.c (buffer_read_memory): Change `length' param and all int + vars to unsigned. + +2000-02-17 J"orn Rennecke <amylaar@redhat.co.uk> + + * sh-dis.c (print_movxy, print_insn_ddt, print_dsp_reg): New functions. + (print_insn_ppi): Likewise. + (print_insn_shx): Use info->mach to select appropriate insn set. + Add support for sh-dsp. Remove FD_REG_N support. + * sh-opc.h (sh_nibble_type): Add new values for sh-dsp support. + (sh_arg_type): Likewise. Remove FD_REG_N. + (sh_dsp_reg_nums): New enum. + (arch_sh1, arch_sh2, arch_sh3, arch_sh3e, arch_sh4): New macros. + (arch_sh_dsp, arch_sh3_dsp, arch_sh1_up, arch_sh2_up): Likewise. + (arch_sh3_up, arch_sh3e_up, arch_sh4_up, arch_sh_dsp_up): Likewise. + (arch_sh3_dsp_up): Likewise. + (sh_opcode_info): New field: arch. + (sh_table): Split up insn with FD_REG_N into ones with F_REG_N and + D_REG_N. Fill in arch field. Add sh-dsp insns. + +2000-02-14 Fernando Nasser <fnasser@totem.to.redhat.com> + + * arm-dis.c: Change flavor name from atpcs-special to + special-atpcs to prevent name conflict in gdb. + (get_arm_regname_num_options, set_arm_regname_option, + get_arm_regnames): New functions. API to access the several + flavor of register names. Note: Used by gdb. + (print_insn_thumb): Use the register name entry from the currently + selected flavor for LR and PC. + +2000-02-10 Nick Clifton <nickc@redhat.com> + + * mcore-opc.h (enum mcore_opclass): Add MULSH and OPSR + classes. + (mcore_table): Add "idly4", "psrclr", "psrset", "mulsh" and + "mulsh.h" instructions. + * mcore-dis.c (imsk array): Add masks for MULSH and OPSR + classes. + (print_insn_mcore): Add support for little endian targets. + Add support for MULSH and OPSR classes. + +2000-02-07 Nick Clifton <nickc@redhat.com> + + * arm-dis.c (parse_arm_diassembler_option): Rename again. + Previous delat did not take. + +2000-02-03 Timothy Wall <twall@redhat.com> + + * dis-buf.c (buffer_read_memory): Use octets_per_byte field + to adjust target address bounds checking and calculate the + appropriate octet offset into data. + +2000-01-27 Nick Clifton <nickc@redhat.com> + + * arm-dis.c: (parse_disassembler_option): Rename to + parse_arm_disassembler_option and allow to be exported. + + * disassemble.c (disassembler_usage): New function: Print out any + target specific disassembler options. + Call arm_disassembler_options() if the ARM architecture is being + supported. + + * arm-dis.c (NUM_ELEM): Define this macro if not already + defined. + (arm_regname): New struct type for ARM register names. + (arm_toggle_regnames): Delete. + (parse_disassembler_option): Use register name structure. + (print_insn): New function: Combines duplicate code found in + print_insn_big_arm and print_insn_little_arm. + (print_insn_big_arm): Call print_insn. + (print_insn_little_arm): Call print_insn. + (print_arm_disassembler_options): Display list of supported, + ARM specific disassembler options. + +2000-01-27 Thomas de Lellis <tdel@windriver.com> + + * arm-dis.c (printf_insn_big_arm): Treat ELF symbols with the + ARM_STT_16BIT flag as Thumb code symbols. + + * arm-dis.c (printf_insn_little_arm): Ditto. + +2000-01-25 Thomas de Lellis <tdel@windriver.com> + + * arm-dis.c (printf_insn_thumb): Prevent double dumping + of raw thumb instructions. + +2000-01-20 Nick Clifton <nickc@redhat.com> + + * mcore-opc.h (mcore_table): Add "add" as an alias for "addu". + +2000-01-03 Nick Clifton <nickc@cygnus.com> + + * arm-dis.c (streq): New macro. + (strneq): New macro. + (force_thumb): ew local variable. + (parse_disassembler_option): New function: Parse a single, ARM + specific disassembler command line switch. + (parse_disassembler_option): Call parse_disassembler_option to + parse individual command line switches. + (print_insn_big_arm): Check force_thumb. + (print_insn_little_arm): Check force_thumb. + +For older changes see ChangeLog-9899 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/contrib/binutils/opcodes/ChangeLog-0203 b/contrib/binutils/opcodes/ChangeLog-0203 new file mode 100644 index 0000000..25ed8b5 --- /dev/null +++ b/contrib/binutils/opcodes/ChangeLog-0203 @@ -0,0 +1,2110 @@ +2003-12-15 Christian Groessler <chris@groessler.org> + + * z8k-dis.c (intr_names): Removed. + (print_intr, print_flags): New functions. + (unparse_instr): Use new functions. + +2003-12-15 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> + + * m32r-opc.c: Regenerate. + +2003-12-14 Mark Mitchell <mark@codesourcery.com> + + * arm-opc.h (arm_opcodes): Put V6 instructions before XScale + instructions. + +2003-12-13 Hans-Peter Nilsson <hp@bitrange.com> + + * mmix-opc.c (mmix_opcodes): Use GO_INSN_BYTE, PUSHGO_INSN_BYTE, + SETL_INSN_BYTE, INCH_INSN_BYTE, INCMH_INSN_BYTE, INCML_INSN_BYTE + and SWYM_INSN_BYTE instead of raw numbers. + +2003-12-10 Zack Weinberg <zack@codesourcery.com> + + * ppc-opc.c (MO): Make optional. + (RAO, RSO, SHO): New optional forms of RA, RS, SH operands. + (tlbwe): Accept for both PPC403 and BOOKE. Make all operands optional. + +2003-12-05 Ricardo Anguiano <anguiano@codesourcery.com> + Mark Mitchell <mark@codesourcery.com> + Richard Earnshaw <rearnsha@arm.com> + + * arm-dis.c (print_arm_insn): Add 'W' macro. + * arm-opc.h (arm_opcodes): Add V6 instructions. + (thumb_opcodes): Likewise. + +2003-12-04 Alan Modra <amodra@bigpond.net.au> + + * openrisc-asm.c: Regenerate. + * pj-opc.c: Update copyright date. + +2003-12-03 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com> + + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-desc.h: Regenerate. + * m32r-dis.c: Regenerate. + * m32r-ibld.c: Regenerate. + * m32r-opc.c: Regenerate. + * m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + +2003-12-02 Alexandre Oliva <aoliva@redhat.com> + + * sh-opc.h: Add support for sh4a and no-fpu variants. + * sh-dis.c: Ditto. + +2003-12-02 Kazu Hirata <kazu@cs.umass.edu> + + * alpha-opc.c: Remove ARGSUSED. + * i370-opc.c: Likewise. + * ppc-opc.c: Likewise. + +2003-12-02 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2003-11-28 Christian Groessler <chris@groessler.org> + + * z8k-dis.c: Convert to ISO C90. + * z8kgen.c: Convert to ISO C90. + (opt): Move long opcode for "ldb rdb,imm8" after short one, now + the short one is created when assembling. + * z8k-opc.h: Regenerate with new z8kgen.c. + +2003-11-19 Kazu Hirata <kazu@cs.umass.edu> + + * h8300-dis.c (print_colon_thingie): Remove. + +2003-11-18 Maciej W. Rozycki <macro@ds2.pg.gda.pl> + + * mips-opc.c (mips_builtin_opcodes): Handle new macros: "lca" and + "dlca". + +2003-11-14 Nick Clifton <nickc@redhat.com> + + * dis-init.c (init_disassemble_info): Initialise + symbol_is_valid field. + * dis-buf.c (generic_symbol_is_valid): New function. Always + returns TRUE. + * arm-dis.c (arm_symbol_is_valid): New function. Return FALSE + for ARM ELF mapping symbols. + * disassemble.c (disassemble_init_for_target): Set + symbol_is_valid field to arm_symbol_is_valid of the target is + an ARM. + +2003-11-05 H.J. Lu <hongjiu.lu@intel.com> + + * m68k-opc.c (m68k_opcodes): Reorder "fmovel". + +2003-11-03 Daniel Jacobowitz <drow@mvista.com> + + * arm-dis.c (print_arm_insn): Print "-" after "#". + +2003-10-30 Falk Hueffner <falk.hueffner@student.uni-tuebingen.de> + + * alpha-opc.c: Add support for a second argument to RPCC. + +2003-10-27 Stephane Carrez <stcarrez@nerim.fr> + + * m68hc11-dis.c: Convert to ISO C90 prototypes. + +2003-10-21 Peter Barada <pbarada@mail.wm.sps.mot.com> + Bernardo Innocenti <bernie@develer.com> + + * m68k-dis.c: Add MCFv4/MCF5528x support. + * m68k-opc.c: Likewise. + +2003-10-10 Dave Brolley <brolley@redhat.com> + + * frv-asm.c,frv-desc.c,frv-opc.c: Regenerated. + +2003-10-08 Dave Brolley <brolley@redhat.com> + + * frv-desc.[ch], frv-opc.[ch]: Regenerated. + +2003-09-30 Bob Wilson <bob.wilson@acm.org> + + * xtensa-dis.c (fetch_data): Remove numBytes parameter. + (print_insn_xtensa): Fix call to fetch_data. + +2003-09-30 Chris Demetriou <cgd@broadcom.com> + + * mips-dis.c (mips_arch_choices): Add entry for "mips64r2" + (print_insn_args): Add handing for +E, +F, +G, and +H. + * mips-opc.c (I65): New define for MIPS64r2. + (mips_builtin_opcodes): Add "dext", "dextm", "dextu", "dins", + "dinsm", "dinsu", "drotl", "drotr", "drotr32", "drotrv", "dsbh", + and "dshd" for MIPS64r2. Adjust "dror", "dror32", and "drorv" to + be supported on MIPS64r2. + +2003-09-24 Dave Brolley <brolley@redhat.com> + + * frv-desc.c, frv-opc.c, frv-opc.h: Regenerated. + +2003-09-14 Andreas Jaeger <aj@suse.de> + + * i386-dis.c: Convert to ISO C90 prototypes. + * i370-dis.c: Likewise. + * i370-opc.c: Likewiwse. + * i960-dis.c: Likewise. + * ia64-opc.c: Likewise. + +2003-09-09 Dave Brolley <brolley@redhat.com> + + * frv-desc.c: Regenerated. + +2003-09-08 Dave Brolley <brolley@redhat.com> + + On behalf of Doug Evans <dje@sebabeach.org> + * Makefile.am (run-cgen): Pass new args archfile and opcfile + to cgen.sh. + (stamp-ip2k,stamp-m32r,stamp-fr30,stamp-frv,stamp-openrisc, + stamp-iq2000,stamp-xstormy16): Pass paths of .cpu and .opc files + to cgen.sh. + (stamp-frv): Delete hardcoded path spec workaround. + * Makefile.in: Regenerate. + * cgen.sh: New args archfile and opcfile. Pass on to cgen. + +2003-09-04 Nick Clifton <nickc@redhat.com> + + * v850-dis.c (disassemble): Accept bfd_mach_v850e1. + * v850-opc.c (v850_opcodes): Add DBTRAP and DBRET instructions. + +2003-09-04 Alan Modra <amodra@bigpond.net.au> + + * ppc-dis.c (struct dis_private): New. + (powerpc_dialect): Make static. Accept -Many in addition to existing + options. Save dialect in dis_private. + (print_insn_big_powerpc): Retrieve dialect from dis_private. + (print_insn_little_powerpc): Likewise. + (print_insn_powerpc): Call powpc_dialect here. Remove unnecessary + efs/altivec check. Try harder to disassemble if given -Many. + * ppc-opc.c (insert_fxm): Expand comment. + (PPC, PPCCOM, PPC32, PPC64, PPCVEC): Remove PPC_OPCODE_ANY. + (POWER, POWER2, PPCPWR2, POWER32, COM, COM32, M601, PWRCOM): Likewise. + (POWER4): Remove PPCCOM. + (PPCONLY): Don't define. Update all occurrences to PPC. + +2003-09-03 Andrew Cagney <cagney@redhat.com> + + * dis-init.c (init_disassemble_info): New file and function. + * Makefile.am (CFILES): Add "dis-init.c". + (libopcodes_la_SOURCES): Add "dis-init.c". + (dis-init.lo): Specify dependencies. + * Makefile.in: Regenerate. + +2003-09-03 Dave Brolley <brolley@redhat.com> + + * frv-*: Regenerated. + +2003-09-02 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (powerpc_opcodes): Combine identical PPC403/BOOKE entries. + Move duplicate mnemonic entries together. Use RS instead of RT on + all mt*. + * ppc-dis.c: Convert to ISO C. + +2003-08-29 Dave Brolley <brolley@redhat.com> + + * Makefile.am (stamp-frv): Copy frv.cpu and frv.opc from + $(srcdir)/../cpu temporarily when regenerating source files. + * Makefile.in: Regenerated. + +2003-08-19 Nick Clifton <nickc@redhat.com> + + * arm-dis.c (print_insn_arm: case 'A'): Add code to + disassemble unindexed form of Addressing Mode 5. + +2003-08-19 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (PPC440): Define. + (powerpc_opcodes): Allow mac*, mul*, nmac*, dccci, dcread, iccci, + icread instructions when PPC440. Add dlmzb instruction. + +2003-08-14 Alan Modra <amodra@bigpond.net.au> + + * dep-in.sed: Remove libintl.h. + * Makefile.am (POTFILES.in): Unset LC_COLLATE. + Run "make dep-am". + * Makefile.in: Regenerate. + +2003-08-07 Michael Meissner <gnu@the-meissners.org> + + * cgen-asm.c (hash_insn_array): Remove PARAMS macro. + (hash_insn_list): Ditto. + (build_asm_hash_table): Ditto. + (cgen_set_parse_operand_fn): Prototype definition. + (cgen_init_parse_operand): Ditto. + (hash_insn_array): Ditto. + (hash_insn_list): Ditto. + (build_asm_hash_table): Ditto. + (cgen_asm_lookup_insn): Ditto. + (cgen_parse_keyword): Ditto. + (cgen_parse_signed_integer): Ditto. + (cgen_parse_unsigned_integer): Ditto. + (cgen_parse_address): Ditto. + (cgen_validate_signed_integer): Ditto. + (cgen_validate_unsigned_integer): Ditto. + + * cgen-opc.c (hash_keyword_name): Remove PARAMS macro. + (hash_keyword_value): Ditto. + (build_keyword_hash_tables): Ditto. + (cgen_keyword_lookup_name): Prototype definition. + (cgen_keyword_lookup_value): Ditto. + (cgen_keyword_add): Ditto. + (cgen_keyword_search_init): Ditto. + (cgen_keyword_search_next): Ditto. + (hash_keyword_name): Ditto. + (hash_keyword_value): Ditto. + (build_keyword_hash_tables): Ditto. + (cgen_hw_lookup_by_name): Ditto. + (cgen_hw_lookup_by_num): Ditto. + (cgen_operand_lookup_by_name): Ditto. + (cgen_operand_lookup_by_num): Ditto. + (cgen_insn_count): Ditto. + (cgen_macro_insn_count): Ditto. + (cgen_get_insn_value): Ditto. + (cgen_put_insn_value): Ditto. + (cgen_lookup_insn): Ditto. + (cgen_get_insn_operands): Ditto. + (cgen_lookup_get_insn_operands): Ditto. + (cgen_set_signed_overflow_ok): Ditto. + (cgen_clear_signed_overflow_ok): Ditto. + (cgen_signed_overflow_ok_p): Ditto. + + * cgen-dis.c (hash_insn_array): Remove PARAMS macro. + (hash_insn_list): Ditto. + (build_dis_hash_table): Ditto. + (count_decodable_bits): Ditto. + (add_insn_to_hash_chain): Ditto. + (count_decodable_bits): Prototype definition. + (add_insn_to_hash_chain): Ditto. + (hash_insn_array): Ditto. + (hash_insn_list): Ditto. + (build_dis_hash_table): Ditto. + (cgen_dis_lookup_insn): Ditto. + + * cgen-asm.in (parse_insn_normal): Remove PARAMS macro. + (@arch@_cgen_build_insn_regex): Prototype definition. + (parse_insn_normal): Ditto. + (@arch@_cgen_assemble_insn): Ditto. + (@arch@_cgen_asm_hash_keywords): Ditto. + + * cgen-dis.in (print_normal): Remove PARAMS macro. Use void * + instead of PTR. + (print_address): Ditto. + (print_keyword): Ditto. + (print_insn_normal): Ditto. + (print_insn): Ditto. + (default_print_insn): Ditto. + (read_insn): Ditto. + (print_normal): Prototype definition. Use void * instead of PTR. + (print_address): Ditto. + (print_keyword): Ditto. + (print_insn_normal): Ditto. + (read_insn): Ditto. + (print_insn): Ditto. + (default_print_insn): Ditto. + (print_insn_@arch@): Ditto. + + * cgen-ibld.in (insert_normal): Remove PARAMS macro. + (insn_insn_normal): Ditto. + (extract_normal): Ditto. + (extract_insn_normal): Ditto. + (put_insn_int_value): Ditto. + (insert_1): Ditto. + (fill_cache): Ditto. + (extract_1): Ditto. + (insert_1): Prototype definition. + (insert_normal): Ditto. + (insert_insn_normal): Ditto. + (put_insn_int_value): Ditto. + (fill_cache): Ditto. + (extract_1): Ditto. + (extract_normal): Ditto. + (extract_insn_normal): Ditto. + + * fr30-asm.c: Regenerate. + * fr30-dis.c: Ditto. + * fr30-ibld.c: Ditto. + * frv-asm.c: Ditto. + * frv-dis.c: Ditto. + * frv-ibld.c: Ditto. + * ip2k-asm.c: Ditto. + * ip2k-dis.c: Ditto. + * ip2k-ibld.c: Ditto. + * iq2000-asm.c: Ditto. + * iq2000-dis.c: Ditto. + * iq2000-ibld.c: Ditto. + * m32r-asm.c: Ditto. + * m32r-dis.c: Ditto. + * m32r-ibld.c: Ditto. + * openrisc-asm.c: Ditto. + * openrisc-dis.c: Ditto. + * openrisc-ibld.c: Ditto. + * xstormy16-asm.c: Ditto. + * xstormy16-dis.c: Ditto. + * xstormy16-ibld.c: Ditto. + +2003-08-06 Nick Clifton <nickc@redhat.com> + + * po/fr.po: Updated French translation. + +2003-08-05 Nick Clifton <nickc@redhat.com> + + * configure.in (ALL_LINGUAS): Add nl. + * configure: Regenerate. + * po/nl.po: New Dutch translation. + +2003-07-30 Jason Eckhardt <jle@rice.edu> + + * i860-dis.c: Convert to ISO C90. Remove superflous prototypes. + +2003-07-30 Nick Clifton <nickc@redhat.com> + + * po/ro.po: Updated Romanian translation. + +2003-07-29 Jakub Jelinek <jakub@redhat.com> + + * ppc-opc.c (insert_mbe, extract_mbe): Shift 1L instead of 1 up. + +2003-07-24 Nick Clifton <nickc@redhat.com> + + * po/fr.po: Updated French translation. + +2003-07-18 Nick Clifton <nickc@redhat.com> + + * arm-dis.c (parse_arm_disassembler_option): Do not expect + option string to be NUL terminated. + (parse_disassembler_options): Allow options to be space or + comma separated. + +2003-07-17 Nick Clifton <nickc@redhat.com> + + * po/es.po: New Spanish translation. + * po/sv.po: New Swedish translation. + * po/opcodes.pot: Regenerate. + +2003-07-15 Richard Sandiford <rsandifo@redhat.com> + + * mips-dis.c (mips_arch_choices): Add rm7000 and rm9000 entries. + +2003-07-14 Nick Clifton <nickc@redhat.com> + + * po/tr.po: Update with latest version. + * po/POTFILES.in: Regenerate. + * Makefile.in: Regenerate. + +2003-07-11 Alan Modra <amodra@bigpond.net.au> + + * po/opcodes.pot: Regenerate. + +2003-07-09 Alexandre Oliva <aoliva@redhat.com> + + 2000-05-25 Alexandre Oliva <aoliva@cygnus.com> + * m10300-dis.c (disassemble): Negate negative accumulator's shift. + 2000-05-24 Alexandre Oliva <aoliva@cygnus.com> + * m10300-dis.c (disassemble, case FSREG, FDREG): Don't assume + 32-bit longs when sign-extending operands. + 2000-04-20 Alexandre Oliva <aoliva@cygnus.com> + * m10300-opc.c: Remove MN10300_OPERAND_RELAX from all FSREGs. + * m10300-dis.c (HAVE_AM33_2): Define. + (disassemble): Use it. + (HAVE_AM33): Redefine. + (print_insn_mn10300): Fix mask for 5-byte extended insns. + 2000-04-01 Alexandre Oliva <aoliva@cygnus.com> + * m10300-opc.c: Renamed AM332 to AM33_2. + 2000-03-31 Alexandre Oliva <aoliva@cygnus.com> + * m10300-opc.c: Defined AM33 2.0 register operands. Added support + for AM33 2.0 `imm8,(abs16)' addressing mode for btst, bset and + bclr. Implemented `fbCC', `flCC', `dcpf' and all FP insns. + * m10300-dis.c (print_insn_mn10300): Recognize 5byte extended + insn code of AM33 2.0. + (disassemble): Recognize FMT_D3. Print out FP register names. + +2003-07-09 Chris Demetriou <cgd@broadcom.com> + + * mips-dis.c (set_default_mips_dis_options): Get BFD from + the disassembler_info's section, rather than from the + disassembler_info's symbols pointer. + +2003-07-07 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c: Remove NULL pointer checks. Formatting. Remove + extraneous ATTRIBUTE_UNUSED. + * ppc-dis.c (print_insn_powerpc): Always pass a valid address to + operand->extract. + +2003-07-04 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c: Convert to C90, removing unnecessary prototypes and + casts. Formatting. + + * ppc-opc.c: Remove PARAMS from prototypes. + (FXM4): Define. + (insert_fxm): New function, used by both FXM and FXM4. + (extract_fxm): Likewise. + (XFXFXM_MASK): Remove 1 << 20 term. + (powerpc_opcodes): Add Power4 version of "mfcr". Simplify "mtcr" mask. + +2003-07-01 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390-dis.c (s390_extract_operand): Add support for long displacements. + * s390-mkopc.c (s390_opcode_cpu_val): Add support for cpu type z990. + * s390-opc.c (D20_20): Add define for 20 bit displacements. + (INSTR_RRF_R0RR, INSTR_RSL_R0RD, INSTR_RSY_RRRD, INSTR_RSY_RURD, + INSTR_RSY_AARD, INSTR_RXY_RRRD, INSTR_RXY_FRRD, INSTR_SIY_URD): Add + new instruction formats. + (MASK_RRF_R0RR, MASK_RSL_R0RD, MASK_RSY_RRRD, MASK_RSY_RURD, + MASK_RSY_AARD, MASK_RXY_RRRD, MASK_RXY_FRRD, MASK_SIY_URD): Likewise. + (s390_opformats): Likewise. + * s390-opc.txt: Add new instructions for cpu type z990. Add missing + hfp instructions. Add missing instructions pgin, pgout and xsch. + +2003-06-23 H.J. Lu <hongjiu.lu@intel.com> + + * i386-dis.c (PNI_Fixup): New. Fix up "mwait" and "monitor" in + Intel Precott New Instructions. + (PREGRP27): New. Added for "addsubpd" and "addsubps". + (PREGRP28): New. Added for "haddpd" and "haddps". + (PREGRP29): New. Added for "hsubpd" and "hsubps". + (PREGRP30): New. Added for "movsldup" and "movddup". + (PREGRP31): New. Added for "movshdup" and "movhpd". + (PREGRP32): New. Added for "lddqu". + (dis386_twobyte): Use PREGRP30 to replace the "movlpX" entry. + Use PREGRP31 to replace the "movhpX" entry. Use PREGRP28 for + entry 0x7c. Use PREGRP29 for entry 0x7d. Use PREGRP27 for + entry 0xd0. Use PREGRP32 for entry 0xf0. + (twobyte_has_modrm): Updated. + (twobyte_uses_SSE_prefix): Likewise. + (grps): Use PNI_Fixup in the "sidtQ" entry. + (prefix_user_table): Add PREGRP27, PREGRP28, PREGRP29, PREGRP30, + PREGRP31 and PREGRP32. + (float_mem): Use "fisttp{l||l|}" in entry 1 in opcode 0xdb. + Use "fisttpll" in entry 1 in opcode 0xdd. + Use "fisttp" in entry 1 in opcode 0xdf. + +2003-06-19 Christian Groessler <chris@groessler.org> + + * z8k-dis.c (instr_data_s): Change tabl_index from long to int. + (print_insn_z8k): Correctly check return value from + z8k_lookup_instr call. + (unparse_instr): Handle CLASS_IRO case. + * z8kgen.c: Fix function definitions. Fix formatting. + (opt): Add brk opcode alias for non-simulator breakpoint. Add + missing and fix existing in/out and sin/sout opcode definitions. + (args): "@ri", "@ro" - add CLASS_IRO register usage for in/out + opcodes. + (internal): Check p->flags for non-zero before dereferencing it. + (gas): Add CLASS_IRO line. Insert new OPC_xxx lines for the added + opcodes and renumber the remaining lines repectively. + (main): Remove "-d" command line switch. + * z8k-opc.h: Regenerate with new z8kgen.c. + +2003-06-11 H.J. Lu <hongjiu.lu@intel.com> + + * po/Make-in (DESTDIR): New. + (install-data-yes): Support $(DESTDIR). + (uninstall): Likewise. + +2003-06-11 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2003-06-10 Doug Evans <dje@sebabeach.org> + + * cgen-asm.in (@arch@_cgen_assemble_insn): CGEN_INSN_RELAX renamed to + CGEN_INSN_RELAXED. + * fr30-asm.c,fr30-desc.c,fr30-desc.h: Regenerate. + * frv-asm.c,frv-desc.c,frv-desc.h: Regenerate. + * ip2k-asm.c,ip2k-desc.c,ip2k-desc.h: Regenerate. + * iq2000-asm.c,iq2000-desc.c,iq2000-desc.h: Regenerate. + * m32r-asm.c,m32r-desc.c,m32r-desc.h,m32r-opc.c: Regenerate. + * openrisc-asm.c,openrisc-desc.c,openrisc-desc.h: Regenerate. + * xstormy16-asm.c,xstormy16-desc.c,xstormy16-desc.h: Regenerate. + +2003-06-10 Gary Hade <garyhade@us.ibm.com> + Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (DQ, RAQ, RSQ, RTQ): Define. + (insert_dq, extract_dq, insert_raq, insert_rtq, insert_rsq): New. + (powerpc_opcodes): Add "attn", "lq" and "stq". + +2003-06-10 Richard Sandiford <rsandifo@redhat.com> + + * h8300-dis.c (bfd_h8_disassemble): Don't print brackets round + rts/l and rte/l register lists. + +2003-06-03 Nick Clifton <nickc@redhat.com> + + * frv-desc.c: Regenerate. + * frv-opc.c: Regenerate. + * frv-asm.c: Regenerate. + * frv-desc.h: Regenerate. + * frv-dis.c: Regenerate. + * frv-ibld.c: Regenerate. + * frv-opc.h: Regenerate. + * po/opcodes.pot: Regenerate. + +2003-06-03 Michael Snyder <msnyder@redhat.com> + and Bernd Schmidt <bernds@redhat.com> + and Alexandre Oliva <aoliva@redhat.com> + + * disassemble.c (disassembler): Add support for h8300sx. + * h8300-dis.c: Ditto. + +2003-06-03 Nick Clifton <nickc@redhat.com> + + * frv-desc.c: Regenerate. + * frv-opc.c: Regenerate. + + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * configure: Regenerate. + * iq2000-asm.c: Regenerate. + * iq2000-desc.c: Regenerate. + * iq2000-desc.h: Regenerate. + * iq2000-dis.c: Regenerate. + * iq2000-ibld.c: Regenerate. + * iq2000-opc.c: Regenerate. + * iq2000-opc.h: Regenerate. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2003-05-23 Jason Eckhardt <jle@rice.edu> + + * i860-dis.c (crnames): Add bear, ccr, p0, p1, p2, p3. + (print_insn_i860): Grab 4 bits of the control register field + instead of 3. + +2003-05-18 Jason Eckhardt <jle@rice.edu> + + * i860-dis.c (print_insn_i860): Instruction shrd has a dual bit, + print it. + +2003-05-17 Andreas Jaeger <aj@suse.de> + + * Makefile.am (libopcodes_la_LIBADD): Add libbfd.la. + (libopcodes_la_DEPENDENCIES): Add libbfd.la. + * Makefile.in: Regenerated. + +2003-05-16 Nick Clifton <nickc@redhat.com> + + * configure.in (ALL_LINGUAS): Add Romanian translation. + * configure: Regenerate. + * po/ro.po: New file: Romanian translation. + +2003-05-12 Dhananjay Deshpande <dhananjayd@kpitcummins.com> + + * disassemble.c (disassembler): Add support for h8300hn and h8300sn. + +2003-05-09 Alan Modra <amodra@bigpond.net.au> + + * i386-dis.c (print_insn): Test intel_syntax against (char) -1 in + case char is unsigned. + +2003-05-01 Christian Groessler <chris@groessler.org> + + * z8k-dis.c (z8k_lookup_instr): Optimize FETCH_DATA calls. + (unpack_instr): Fix representation of segmented addresses. + (intr_name): Added, contains names of the parameters to the EI/DI + instructions. + (unparse_instr): Fix display of EI/DI parameters. + +2003-04-22 Doug Evans <dje@sebabeach.org> + + * fr30-desc.c,fr30-desc.h,fr30-opc.c,fr30-opc.h: Regenerate. + * frv-desc.c,frv-desc.h,frv-opc.c,frv-opc.h: Regenerate. + * ip2k-desc.c,ip2k-desc.h,ip2k-opc.c,ip2k-opc.h: Regenerate. + * m32r-desc.c,m32r-desc.h,m32r-opc.c,m32r-opc.h: Regenerate. + * m32r-opinst.c: Regenerate. + * openrisc-desc.c,openrisc-desc.h,openrisc-opc.c,openrisc-opc.h: Regenerate. + * xstormy16-desc.c,xstormy16-desc.h,xstormy16-opc.c,xstormy16-opc.h: Regenerate. + +2003-04-15 Rohit Kumar Srivastava <rohits@kpitcummins.com> + + * h8500-opc.c: Replace occurrances of 'Hitachi' with 'Renesas'. + +2003-04-07 James E Wilson <wilson@tuliptree.org> + + * ia64-ic.tbl (fr-readers): Add mem-writers-fp. + * ia64-asmtab.c: Regenerate. + +2003-04-08 Alexandre Oliva <aoliva@redhat.com> + + * mips-dis.c (mips_gpr_names_newabi): Reverted previous patch. + +2003-04-07 Alexandre Oliva <aoliva@redhat.com> + + * mips-dis.c (mips_gpr_names_newabi): $12-$15 are named $t4-$t7. + +2003-04-04 Svein E. Seldal <Svein.Seldal@solidas.com> + + * tic4x-dis.c: Namespace cleanup. Replace s/c4x/tic4x and + s/c3x/tic3x/ + +2003-04-01 Nick Clifton <nickc@redhat.com> + + * arm-dis.c: Remove presence of (r) and (tm) symbols. + * arm-opc.h: Remove presence of (r) and (tm) symbols. + +2003-03-25 Stan Cox <scox@redhat.com> + Nick Clifton <nickc@redhat.com> + + Contribute support for Intel's iWMMXt chip - an ARM variant: + + * arm-dis.c (regnames): Add iWMMXt register names. + (set_iwmmxt_regnames): New function. + (print_insn_arm): Handle iWMMXt formatters. + * arm-opc.h: Document iWMMXt formatters. + (arm_opcod): Add iWMMXt instructions. + +2003-03-22 Doug Evans <dje@sebabeach.org> + + * i386-dis.c (dis386): Recognize icebp (0xf1). + +2003-03-21 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390-dis.c (init_disasm): Rename S390_OPCODE_ESAME to + S390_OPCODE_ZARCH. + (print_insn_s390): Use new modes field of s390_opcodes. + * s390-mkopc.c (ARCHBITS_ESAONLY, ARCHBITS_ESA, ARCHBITS_ESAME): Remove. + (s390_opcode_mode_val, s390_opcode_cpu_val): New enums. + (struct op_struct): Remove archbits. Add mode_bits and min_cpu. + (insertOpcode): Replace archbits by min_cpu and mode_bits. + (dumpTable): Write mode_bits and min_cpu instead of archbits. + (main): Adapt to new format in s390-opcode.txt. + * s390-opc.c (s390_opformats): Replace archbits by min_cpu and + mode_bits. + * s390-opc.txt: Replace archbits by min_cpu and mode_bits. + +2003-03-17 Nick Clifton <nickc@redhat.com> + + * ppc-opc.c: Fix formatting. Update copyright date. + +2003-03-14 Daniel Jacobowitz <drow@mvista.com> + + * ppc-opc.c (powerpc_opcodes): Readd tlbre for PPC403. + +2003-02-25 Alan Modra <amodra@bigpond.net.au> + + * hppa-dis.c: Formatting. + +2003-02-25 Matthew Wilcox <willy@debian.org> + + * hppa-dis.c (print_insn_hppa): Implement fcnv instruction modifiers. + + * hppa-dis.c (print_insn_hppa <2 bit space register>): Do not print + the space register when the value is zero. + +2003-02-23 Elias Athanasopoulos <elathan@phys.uoa.gr> + + * mips-dis.c (print_mips_disassembler_options): Make 'i' unsigned, + use ARRAY_SIZE in loops. + +2003-02-12 Dave Brolley <brolley@redhat.com> + + * fr30-desc.c: Regenerate. + +2003-02-06 Gwenole Beauchesne <gbeauchesne@mandrakesoft.com> + + * i386-dis.c (dq_mode, Edq): Define. + (dis386_twobyte): Correct movd operands. + (OP_E): Handle dq_mode case. + +2003-01-29 Henric Jungheim <henric@attbi.com> + + * sparc-dis.c (print_insn_sparc): When examining values added in + to rs1, make sure that there are previous instructions. + +2003-01-23 Nick Clifton <nickc@redhat.com> + + * Add sh2e support: + + 2002-04-02 Alexandre Oliva <aoliva@redhat.com> + + * sh-dis.c (print_insn_shx): Handle bfd_mach_sh2e. + * sh-opc.h (arch_sh2e, arch_sh2e_up): New. + (arch_sh2_up): Added sh2e. + (sh_table): Replaced all occurrences of arch_sh3e_up with + arch_sh2e_up, except in fsqrt. + +2003-01-23 Alan Modra <amodra@bigpond.net.au> + + * sh64-dis.c: Include elf32-sh64.h. + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2003-01-17 Richard Henderson <rth@redhat.com> + + * alpha-opc.c (alpha_opcodes): Add bugchk, rduniq, wruniq, gentrap + PAL entry points. + +2003-01-16 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2003-01-08 Klee Dienes <kdienes@apple.com> + + * Makefile.am (ALL_MACHINES): Add msp430-dis.lo. + * Makefile.in: Regenerate. + +2003-01-08 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c (powerpc_macros <extrwi>): Accept a shift of 32. + +2002-01-02 Ben Elliston <bje@redhat.com> + Jeff Johnston <jjohnstn@redhat.com> + + * iq2000-asm.c: New file. + * iq2000-desc.c: Likewise. + * iq2000-desc.h: Likewise. + * iq2000-dis.c: Likewise. + * iq2000-ibld.c: Likewise. + * iq2000-opc.c: Likewise. + * iq2000-opc.h: Likewise. + * Makefile.am (HFILES): Add iq2000-desc.h, iq2000-opc.h. + (CFILES): Add iq2000-asm.c, iq2000-desc.c, iq2000-dis.c, + iq2000-ibld.c, iq2000-opc.c. + (ALL_MACHINES): Add iq2000-asm.lo, iq2000-desc.lo, iq2000-dis.lo, + iq2000-ibld.lo, iq2000-opc.lo. + (CLEANFILES): Add stamp-iq2000. + (IQ2000_DEPS): New macro. + (stamp-iq2000): New target. + * Makefile.in: Regenerate. + * configure.in: Handle bfd_iq2000_arch. + * configure: Regenerate. + +2003-01-02 Chris Demetriou <cgd@broadcom.com> + + * mips-dis.c (print_insn_args): Use position extracted by "+A" + to calculate size for "+B". Redo code for "+C" so it shares + the same style as "+A" and "+B" now do. + +2003-01-02 Chris Demetriou <cgd@broadcom.com> + + * mips-dis.c: Update copyright years. + (print_insn_arg): Rename to... + (print_insn_args): This, returning void. Process the whole + string of args rather than a single one. Reindent. + (print_insn_mips): Update to match the above. + +2002-12-31 Chris Demetriou <cgd@broadcom.com> + + * mips-opc.c (mips_builtin_opcodes): Move "di" into the + right order alphabetically, and make all hex constants use + lower-case letters. + +2002-12-31 Chris Demetriou <cgd@broadcom.com> + + * mips-dis.c (mips_cp0sel_name): New structure. + (mips_cp0sel_names_mips3264, mips_cp0sel_names_mips3264r2) + (mips_cp0sel_names_sb1): New arrays. + (mips_arch_choice): New structure members "cp0sel_names" and + "cp0sel_names_len". + (mips_arch_choices): Add references to new cp0sel_names arrays + as appropriate, and make all existing entries reference + appropriate mips_XXX_names_numeric arrays rather than simply + using NULL. + (mips_cp0sel_names, mips_cp0sel_names_len): New variables. + (lookup_mips_cp0sel_name): New function. + (set_default_mips_dis_options): Set mips_cp0sel_names and + mips_cp0sel_names_len as appropriate. Remove now-unnecessary + checks for NULL register name arrays. + (parse_mips_dis_option): Likewise. + (print_insn_arg): Handle "+D" operand type. + * mips-opc.c (mips_builtin_opcodes): Add new "+D" variants + of mfc0, mtc0, dmfc0, and dmtc0 to print CP0+sel register + names symbolically. + +2002-12-30 Chris Demetriou <cgd@broadcom.com> + + * mips-dis.c (mips_cp0_names_mips3264r2, mips_hwr_names_numeric) + (mips_hwr_names_mips3264r2): New arrays. + (mips_arch_choice): New "hwr_names" member. + (mips_arch_choices): Adjust for structure change, and add a new + entry for "mips32r2" ISA. + (mips_hwr_names): New variable. + (set_default_mips_dis_options): Set mips_hwr_names. + (parse_mips_dis_option): New "hwr-names" option which sets + mips_hwr_names, and adjust "reg-names=ARCH" to set mips_hwr_names. + (print_insn_arg): Change return type to "int" + and use that to indicate number of characters consumed. + Add support for "+" operand extension character, "+A", "+B", + "+C", and "K" operands. + (print_insn_mips): Adjust for changes to print_insn_arg. + (print_mips_disassembler_options): Adjust for "hwr-names" + addition and "reg-names" change. + * mips-opc (I33): New define (shorthand for INSN_ISA32R2). + (mips_builtin_opcodes): Note that "nop" and "ssnop" are special + forms of "sll". Add new MIPS32 Release 2 instructions: ehb, + di, ei, ext, ins, jr.hb, jalr.hb, mfhc1, mfhc2, mthc1, mthc2, + rdhwr, rdpgpr, seb, seh, synci, wrpgpr, wsbh. + Note that hardware rotate instructions (ror, rorv) can be + used on MIPS32 Release 2, and add the official mnemonics + for them (rotr, rotrv) and the similar "rotl" mnemonic for + left-rotate. + +2002-12-30 Dmitry Diky <diwil@mail.ru> + + * configure.in: Add msp430 target. + * configure: Regenerate. + * disassemble.c: Add entry for msp430 disassembly. + * msp430-dis.c: New file: msp430 disassembler. + +2002-12-27 Chris Demetriou <cgd@broadcom.com> + + * disassemble.c (disassembler_usage): Add invocation of + print_mips_disassembler_options. + * mips-dis.c: Include libiberty.h. + (print_mips_disassembler_options, set_default_mips_dis_options) + (parse_mips_dis_option, parse_mips_dis_options, choose_abi_by_name) + (choose_arch_by_name, choose_arch_by_number): New functions. + (mips_abi_choice, mips_arch_choice): New structures. + (mips32_reg_names, mips64_reg_names, reg_names): Remove. + (mips_gpr_names_numeric, mips_gpr_names_oldabi) + (mips_gpr_names_newabi, mips_fpr_names_numeric) + (mips_fpr_names_32, mips_fpr_names_n32, mips_fpr_names_64) + (mips_cp0_names_numeric, mips_cp0_names_mips3264) + (mips_cp0_names_sb1, mips_abi_choices, mips_arch_choices) + (mips_processor, mips_isa, mips_gpr_names, mips_fpr_names) + (mips_cp0_names): New variables. + (print_insn_args): Use new variables to print GPR, FPR, and CP0 + register names. + (mips_isa_type): Remove. + (print_insn_mips): Remove ISA and CPU setup since it is now done... + (_print_insn_mips): Here. Remove register setup code, and + call set_default_mips_dis_options and parse_mips_dis_options + instead. + (print_mips16_insn_arg): Use mips_gpr_names instead of mips32_names. + +2002-12-23 Alan Modra <amodra@bigpond.net.au> + + * Makefile.in: Regenerate. + +2002-12-19 Nick Kelsey <nickk@ubicom.com> + + * cgen-asm.c (cgen_parse_keyword): Added underscore to symbol character + check to fix false keyword trigger with names such as <keyword>_foo. + +2002-12-19 Doug Evans <dje@sebabeach.org> + + * Makefile.am (CGEN_CPUS): New variable. + (run-cgen-all): New rule. + * Makefile.in: Regenerate. + +2002-12-18 Chris Demetriou <cgd@broadcom.com> + + * mips-opc.c (mips_builtin_opcodes): Remove one "ror" and two + "dror" entries, and reorder the remaining "dror" and "ror" entries. + +2002-12-16 DJ Delorie <dj@delorie.com> + + * xstormy16-asm.c (parse_immediate16): Add prototype. + +2002-12-16 Andrew MacLeod <amacleod@redhat.com> + + * xstormy16-asm.c: Regenerate. + +2002-12-16 Alan Modra <amodra@bigpond.net.au> + + * ns32k-dis.c (print_insn_ns32k): Constify "d", remove register + keyword. + +2002-12-13 Alan Modra <amodra@bigpond.net.au> + + * h8500-opc.h (h8500_table): Add missing initializers to quiet + warnings. + * pj-dis.c (print_insn_pj): Adjust for pj_opc_info_t change. + * pj-opc.c (pj_opc_info): Add braces around union initializer. + * z8kgen.c: Include "libiberty.h". + (opt, args, toks): Fix initializer warnings. + (chewname): Make "name" a char **. Return mnemonic trimmed of + operands. + (gas): Improve emitted "DO NOT EDIT" warning. Format emitted + opcode_entry_type, and make "nicename" and "name" const. Make + z8k_table const too. Formatting. Generate idx as gas needs it. + * z8k-opc.h: Regenerate. + +2002-12-08 Stephane Carrez <stcarrez@nerim.fr> + + * m68hc11-dis.c (print_indexed_operand): Fix PC-relative address + for 9 and 16-bit PC-relative addressing mode. + +2002-12-05 Aldy Hernandez <aldyh@redhat.com> + + * ppc-opc.c: Delete evsabs, evsnabs, evsneg, evsadd, evssub, + evsmul, evsdiv, evscmpgt, evsgmplt, evststgt, evtstlt, evststeq, + evscfui, evscfsi, evscfuf, evscfsf, evsctui, evsctuiz, evsctsi, + evsctsiz, evsctuf, evsctsf, evmwhssfaa, evmwhssmaa, evmwhsmfaa, + evmwhsmiaa, evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian, + evmwhsmfan, evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa, + evmwhgsmfaa, evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan, + evmwhgsmian, evmwhgumian. + (mftb): Add to opcode table. + (mtspefscr): Change RT to RS in opcode table. + +2002-12-05 Aldy Hernandez <aldyh@redhat.com> + + * ppc-opc.c: Move mbar and msync up. Change mask for mbar and + msync. + +2002-12-04 David Mosberger <davidm@hpl.hp.com> + + * ia64-opc-d.c (ia64_opcodes_d): Add "hint" instruction. + * ia64-opc-b.c: Add "hint.b" instruction. + * ia64-opc-f.c: Add "hint.f" instruction. + * ia64-opc-i.c: Add "hint.i" instruction. + * ia64-opc-m.c: Add "hint.m", "fc.i", "ld16", "st16", and + "cmp8xchg16" instructions. + * ia64-opc-x.c: Add "hint.x" instruction. + + * ia64-opc.h (AR_CSD): New macro. + + * ia64-ic.tbl: Update according to SDM2.1. + * ia64-raw.tbl: Ditto. + * ia64-waw.tbl: Ditto. + + * ia64-gen.c (in_iclass): Handle "hint" like "nop". + (lookup_regindex): Recognize AR[FCR], AR[EFLAG], AR[CSD], + AR[SSD], AR[CFLG], AR[FSR], AR[FIR], and AR[FDR]. + * ia64-asmtab.c: Regenerate. + +2002-11-25 Aldy Hernandez <aldyh@redhat.com> + + * ppc-opc.c: Remove evmwlssf, evmwlssfa, evmwlsmf, evmwlsmfa, + evmwlssfaaw, evmwlsmfaaw, evmwlssfanw, evmwlsfanw. + +2002-12-04 Aldy Hernandez <aldyh@redhat.com> + + * ppc-opc.c (PMRN): Remove. + (RA): Set to NB + 1. + (powerpc_opcodes): Change PMRN to SPR. + Change all RD to RS. + Change mftb to look like mftbl. + Move mftb before mftbl. + Add mfbbtar. + Add mtbbtar. + Change mfpmr to use PMR. + Change mtpmr to use PMR. + (RD): Remove. + (insert_ev2): Fix mask and shift. + (extract_ev2): Same. + (insert_ev4): Same. + (extract_ev4): Same. + (PMR): Define. + (extract_pmrn): Remove. + (insert_pmrn): Remove. + +2002-12-03 Richard Henderson <rth@redhat.com> + + * ia64-opc-m.c: Add ld8.mov. + * ia64-asmtab.c: Regenerate. + +2002-12-02 Alan Modra <amodra@bigpond.net.au> + + * arm-dis.c (print_insn_arm): Constify "insn". Formatting. + (print_insn_thumb): Likewise. + * h8500-dis.c (print_insn_h8500): Constify "opcode". + * mcore-dis.c (print_insn_mcore): Constify "op". Formatting. + * ns32k-dis.c (print_insn_arg <case 'F'>): Use a union to avoid + type-punned pointer warnings. + <case 'L'>: Likewise. Fix error message too. + * pdp11-dis.c (print_reg): Warning fix. + * sh-dis.c (print_movxy): Constify "op" param. + (print_insn_ddt): Constify sh_opcode_info vars. + (print_insn_ppi): Likewise. + (print_insn_sh): Likewise. + * tic30-dis.c (cnvt_tmsfloat_ieee): Use a union to avoid + type-punned pointer warnings. + * w65-dis.c (print_insn_w65): Constify "op". + +2002-12-01 Stephane Carrez <stcarrez@nerim.fr> + + * m68hc11-dis.c (PC_REGNUM): Define. + (print_indexed_operand): Need an adjustment for some PC-relative + operand modes; print the final address of PC-relative modes. + (print_insn): Take into account movw/movb to adjust the PC-relative + operand addresses. + +2002-11-30 Alan Modra <amodra@bigpond.net.au> + + *arm-dis.c, cris-dis.c, h8300-dis.c, mips-dis.c, mmix-dis.c, sh-dis.c, + sh64-dis.c, v850-dis.c: Replace boolean with bfd_boolean, true with + TRUE, false with FALSE. Simplify comparisons of bfd_boolean vars + with TRUE/FALSE. Formatting. + +2002-11-25 DJ Delorie <dj@redhat.com> + + * xstormy16-opc.c: Regenerate. + +2002-11-25 Jim Wilson <wilson@redhat.com> + + * ia64-dis.c (print_insn_ia64): Correct handling of IA64_OPND_TGT64. + +2002-11-15 DJ Delorie <dj@redhat.com> + + * xstormy16-desc.c: Regenerate. + * xstormy16-opc.c: Regenerate. + * xstormy16-opc.h: Regenerate. + +2002-11-18 Klee Dienes <kdienes@apple.com> + + * avr-dis.c: Include libiberty.h (for xmalloc). + (struct avr_opcodes_s): Remove 'bin_mask' field (it's + automatically computed in the init routine). + (AVR_INSN): No longer provide bin_mask field in initializer. + (avr_opcodes_s): Declare as const. + (print_insn_avr): Store the bin_mask field in a separate table + (allocated with xmalloc); iterate through it at the same time as + we iterate through the opcodes. + +2002-11-18 Klee Dienes <kdienes@apple.com> + + * h8300-dis.c: Include libiberty.h (for xmalloc). + (struct h8_instruction): New type, used to wrap h8_opcodes with a + length field (computed at run-time). + (h8_instructions): New variable. + (bfd_h8_disassemble_init): Allocate the storage for + h8_instructions. Fill h8_instructions with pointers to the + appropriate opcode and the correct value for the length field. + (bfd_h8_disassemble): Iterate through h8_instructions instead of + h8_opcodes. + +2002-11-18 Klee Dienes <kdienes@apple.com> + + * arc-opc.c (arc_ext_opcodes): Define. + (arc_ext_operands): Define. + * i386-dis.c (Suffix3DNow): Declare as const. + * arm-opc.h (arm_opcodes): Declare as const. + (thumb_opcodes): Declare as const. + * h8500-opc.h (h8500_table): Declare as const. + (h8500_table): Use a NULL for the opcode in the terminator, so + that code testing (opcode->name) behaves correctly. + * mcore-opc.h (mcore_table): Declare as const. + * sh-opc.h (sh_table): Declare as const. + * w65-opc.h (optable): Declare as const. + * z8k-opc.h (z8k_table): Declare as const. + +2002-11-18 Svein E. Seldal <Svein.Seldal@solidas.com> + + * tic4x-dis.c: Added support for enhanced and special insn. + (c4x_print_op): Added insn class 'i' and 'j' + (c4x_hash_opcode_special): Add to support special insn + (c4x_hash_opcode): Update to support the new opcode-list + format. Add support for the new special insns. + (c4x_disassemble): New opcode-list support. + +2002-11-16 Klee Dienes <kdienes@apple.com> + + * m88k-dis.c: Include libiberty.h (for xmalloc). + (HASHTAB): New type, used to build instruction hash tables. + Contains a pointer to an INSTAB and a pointer to the next hash + chain entry. + (instructions): Move definition from m88k.h; remove initialization + of 'next' field. + (hashtable): Now an aray of pointer-to-HASHTAB, not INSTAB. + (printop): Mark pointer to OPSPEC as const. + (install): Remove; fold into init_disasm. + (m88kdis): Update to ihashtab_initialized to 1 after calling + init_disasm. entry_ptr now iterates through HASHTABs, not + INSTABs. + (init_disasm): Iterate through the instructions and add to + hashtable[]. + +2002-11-16 Svein E. Seldal <Svein.Seldal@solidas.com> + + * tic4x-dis.c: (c4x_print_op): Add support for the new argument + format. Fix bug in 'N' register printer. + +2002-11-12 Segher Boessenkool <segher@koffie.nl> + + * ppc-dis.c (print_insn_powerpc): Correct condition register display. + +2002-11-07 Aldy Hernandez <aldyh@redhat.com> + + * ppc-opc.c (EVUIMM_4): Change bit size to 32. + (EVUIMM_2): Same. + (EVUIMM_8): Same. + +2002-11-07 Klee Dienes <kdienes@apple.com> + + * Makefile.am (ia64-asmtab.c): Update to use the new '--srcdir' + argument to ia64-gen. + Regenerate dependencies for ia64-len.lo. + * Makefile.in: Regenerate. + * ia64-gen.c: Convert to use getopt(). Add the standard GNU + options, as well as '--srcdir', which controls the directory in + which ia64-gen looks for the sources it uses to generate the + output table. Add a 'const' to the declaration of the final + output table. Call xmalloc_set_program_name to set the program + name. + * ia64-asmtab.c: Regenerate. + +2002-11-07 Nick Clifton <nickc@redhat.com> + + * ia64-gen.c: Fix comment formatting and compile time warnings. + * ia64-opc-a.c: Fix compile time warnings. + * ia64-opc-b.c: Likewise. + * ia64-opc-d.c: Likewise. + * ia64-opc-f.c: Likewise. + * ia64-opc-i.c: Likewise. + * ia64-opc-m.c: Likewise. + * ia64-opc-x.c: Likewise. + +2002-11-06 Aldy Hernandez <aldyh@redhat.com> + + * ppc-opc.c: Change RD to RS for evmerge*. + +2002-10-07 Nathan Tallent <eraxxon@alumni.rice.edu> + + * sparc-opc.c (sparc_opcodes) <fb, fba, fbe, fbz, fbg, fbge, + fbl, fble, fblg, fbn, fbne, fbnz, fbo, fbu, fbue, fbug, fbuge, + fbul, fbule>: Add conditional/unconditional branch + classification. + +2002-10-13 Stephane Carrez <stcarrez@nerim.fr> + + * m68hc11-dis.c (print_insn): Treat bitmask and branch operands + at the end. + +2002-09-30 Gavin Romig-Koch <gavin@redhat.com> + Ken Raeburn <raeburn@cygnus.com> + Aldy Hernandez <aldyh@redhat.com> + Eric Christopher <echristo@redhat.com> + Richard Sandiford <rsandifo@redhat.com> + + * mips-dis.c (print_insn_arg): Handle '[', ']', 'e' and '%'. + (mips_isa_type): Handle bfd_mach_mips4120, bfd_mach_mips5400 + and bfd_mach_mips5500. + * mips-opc.c (V1): Include INSN_4111 and INSN_4120. + (N411, N412, N5, N54, N55): New convenience defines. + (mips_builtin_opcodes): Add vr4120, vr5400 and vr5500 opcodes. + Change dmadd16 and madd16 from V1 to N411. + +2002-09-26 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips-dis.c (print_insn_mips): Always allow disassembly of + 32-bit jalx opcode. + +2002-09-24 Nick Clifton <nickc@redhat.com> + + * po/de.po: Updated German translation. + +2002-09-21 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2002-09-20 Nick Clifton <nickc@redhat.com> + + * ppc-opc.c (CRFD, CRFS): Add PPC_OPERAND_CR flag so that cr + register names are accepted. + +2002-09-17 Svein E. Seldal <Svein.Seldal@solidas.com> + + * tic4x-dis.c: Add function declarations and ATTRIBUTE_UNUSED. + Convert functions to K&R format. + +2002-09-13 Nick Clifton <nickc@redhat.com> + + * ppc-opc.c (MFDEC2): Include Book-E. + (PPCCHLK64): New opcode mask. + (evsubw, evsubiw, evmr, evnot, isellt, iselgt, iseleq, mfpid, + mfcsrr0, mfcsrr1, mfdear, mfesr, mfivpr, mfusprg0, mftbl, + mftbu, mfpir, mfdbsr, mfdbcr0, mfdbcr1, mfdbcr2, mfiac1, + mfiac2, mfiac3, mfiac4, mfdac1, mfdac2, mfdvc1, mfdvc2, mftsr, + mftcr, mfivor0, mfivor1, mfivor2, mfivor3, mfivor4, mfivor5, + mfivor6, mfivor7, mfivor8, mfivor9, mfivor10, mfivor11, + mfivor12, mfivor13, mfivor14, mfivor15, mfbbear, mfmcsrr0, + mfmcsrr1, mfmcsr, mtpid, mtdecar, mtcsrr0, mtcsrr1, mtdear, + mtesr, mtivpr, mtusprg0, mtsprg4, mtsprg5, mtsprg6, mtsprg7, + mtdbsr, mtdbcr0, mtdbcr1, mtdbcr2, mtiac1, mtiac2, mtiac3, + mtiac4, mtdac1, mtdac2, mtdvc1, mtdvc2, mttsr, mttcr, mtivor0, + mtivor1, mtivor2, mtivor3, mtivor4, mtivor5, mtivor6, mtivor7, + mtivor8, mtivor9, mtivor10, mtivor11, mtivor12, mtivor13, + mtivor14, mtivor15, mtbbear, mtmcsrr0, mtmcsrr1, mtmcsr): New + Book-E instructions. + (evfsneg): Fix opcode value. + (dcbtstlse, dcbtlse, icblce, dcblce, icbtsle): Use PPCCHLK64 + mask. + (mcrxr64, tlbivaxe, tlbsxe, tlbsxe.): Restrict to 64-bit + Book-E. + (extsw): Restrict to 64-bit PPC instruction sets. + (extsw.): Does not exist in 64-bit Book-E. + (powerpc_macro): Remove mftbl, mftbu and mftb Book-E macros as + they are no longer needed. + +2002-09-12 Gary Hade <garyhade@us.ibm.com> + + * ppc-dis.c (powerpc_dialect): Add missing PPC_OPCODE_CLASSIC. + +2002-09-11 Nick Clifton <nickc@redhat.com> + + * po/da.po: Updated Danish translation file. + +2002-09-04 Nick Clifton <nickc@redhat.com> + + * ppc-opc.c (extsw, extsw.): Do not allow for the BookE32. + +2002-09-04 Nick Clifton <nickc@redhat.com> + + * disassemble.c (disassembler_usage): Add invocation of + print_ppc_disassembler_options. + * ppc-dis.c (print_ppc_disassembler_options): New function. + +2002-09-04 Nick Clifton <nickc@redhat.com> + + * ppc-opc.c: The BookE implementations of the TLBWE and TLBRE + instructions do not take any arguments. + +2002-09-02 Nick Clifton <nickc@redhat.com> + + * v850-opc.c: Remove redundant references to V850EA architecture. + +2002-09-02 Alan Modra <amodra@bigpond.net.au> + + * arc-opc.c: Include bfd.h. + (arc_get_opcode_mach): Subtract off base bfd_mach value. + +2002-08-30 Alan Modra <amodra@bigpond.net.au> + + * v850-dis.c (disassemble): Remove bfd_mach_v850ea case. + + * mips-dis.c (_print_insn_mips): Don't use hard-coded mach constants. + +2002-08-28 Svein E. Seldal <Svein.Seldal@solidas.com> + + * configure.in: Added bfd_tic4x_arch. + * configure: Regenerate. + * Makefile.am: Added tic4x-dis.o target. + * Makefile.in: Regenerate. + +2002-08-28 Michael Hayes <m.hayes@elec.canterbury.ac.nz> + + * disassemble.c: Added tic4x target and c4x + disassembler routine. + * tic4x-dis.c: New file. + +2002-08-16 Christian Groessler <chris@groessler.org> + + * z8k-dis.c (unparse_instr): case CLASS_BA: Designate hex + values as those. + * z8kgen.c (opt): Fix definition of "in rd,imm16" opcode. + * z8k-opc.h: Regenerated with new z8kgen.c. + +2002-08-19 Elena Zannoni <ezannoni@redhat.com> + + From matthew green <mrg@redhat.com> + + * ppc-dis.c (powerpc_dialect): Support `-m500', `-m500x2' and + `-mefs'. Turn off AltiVec for E500 and efs. + (print_insn_powerpc): Don't print an AltiVec instruction if the + dialect is not efs. + + * ppc-opc.c (insert_pmrn, extract_pmrn, insert_ev2, extract_ev2, + insert_ev4, extract_ev4, insert_ev8, extract_ev8): New functions + for extracting pmrn/evld/evstd/etc operands. + (CRB, CRFD, CRFS, DC, RD): New instruction fields. + (CT): Make this equal to RD + 1. + (PMRN): New operand. + (RA): Update. + (EVUIMM, EVUIMM_2, EVUIMM_4, EVUIMM_8): New operands. + (WS): Update. + (EVSEL, EVSEL_MASK): New instruction form and mask for EVSEL. + (ISEL, ISEL_MASK): New instruction form and mask for ISEL. + (XISEL, XISEL_MASK): New instruction form and mask for ISEL. + (CTX, CTX_MASK): New instruction form and mask for context cache + instructions. + (UCTX, UCTX_MASK): New instruction form and mask for user context + cache instructions. + (XC, XC_MASK, XUC, XUC_MASK): New instruction forms. + (CLASSIC): New define. + (PPCESPE): New define. + (PPCISEL, , PPCBRLK, PPCPMR, PPCCHLK, PPCRFMI): New + defines for integer select, cache control, branch + locking, power management, cache locking and machine check + APU instructions, respectively. + (efsabs, efsnabs, efsneg, efsadd, efssub, efsmul, + efsdiv, efscmpgt, efscmplt, efscmpeq, efststgt, efststlt, + efststeq, efscfui, efsctuiz, efscfsi, efscfuf, efscfsf, + efsctui, efsctsi, efsctsiz, efsctuf, efsctsf, + evaddw, evaddiw, evsubfw, evsubifw, evabs, evneg, evextsb, + evextsh, evrndw, evcntlzw, evcntlsw, brinc, evand, evandc, evor, + evorc, evxor, eveqv, evnand, evnor, evrlw, evrlwi, evslw, evslwi, + evsrws, evsrwu, evsrwis, evsrwiu, evsplati, evsplatfi, evmergehi, + evmergelo, evmergehilo, evmergelohi, evcmpgts, evcmpgtu, evcmplts, + evcmpltu, evcmpeq, evsel, evldd, evlddx, evldw, evldwx, evldh, + evldhx, evlwhe, evlwhex, evlwhou, evlwhoux, evlwhos, evlwhosx, + evlwwsplat, evlwwsplatx, evlwhsplat, evlwhsplatx, evlhhesplat, + evlhhesplatx, evlhousplat, evlhousplatx, evlhossplat, evlhossplatx, + evstdd, evstddx, evstdw, evstdwx, evstdh, evstdhx, evstwwe, + evstwwex, evstwwo, evstwwox, evstwhe, evstwhex, evstwho, evstwhox, + evfsabs, evfsnabs, evfsneg, evfsadd, evfssub, evfsmul, evfsdiv, + evfscmpgt, evfscmplt, evfscmpeq, evfststgt, evfststlt, evfststeq, + evfscfui, evfsctuiz, evfscfsi, evfscfuf, evfscfsf, evfsctui, + evfsctsi, evfsctsiz, evfsctuf, evfsctsf, evsabs, evsnabs, evsneg, + evsadd, evssub, evsmul, evsdiv, evscmpgt, evsgmplt, evsgmpeq, + evststgt, evststlt, evststeq, evscfui, evscfsi, evscfuf, evscfsf, + evsctui, evsctuiz, evsctsi, evsctsiz, evsctuf, evsctsf, evmhossf, + evmhossfa, evmhosmf, evmhosmfa, evmhosmi, evmhosmia, evmhoumi, + evmhoumia, evmhessf, evmhessfa, evmhesmf, evmhesmfa, evmhesmi, + evmhesmia, evmheumi, evmheumia, evmhossfaaw, evmhossiaaw, + evmhosmfaaw, evmhosmiaaw, evmhousiaaw, evmhoumiaaw, evmhessfaaw, + evmhessiaaw, evmhesmfaaw, evmhesmiaaw, evmheusiaaw, evmheumiaaw, + evmhossfanw, evmhossianw, evmhosmfanw, evmhosmianw, evmhousianw, + evmhoumianw, evmhessfanw, evmhessianw, evmhesmfanw, evmhesmianw, + evmheusianw, evmheumianw, evmhogsmfaa, evmhogsmiaa, evmhogumiaa, + evmhegsmfaa, evmhegsmiaa, evmhegumiaa, evmhogsmfan, evmhogsmian, + evmhogumian, evmhegsmfan, evmhegsmian, evmhegumian, evmwhssf, + evmwhssfa, evmwhssfaa, evmwhssmaa, evmwhsmfaa, evmwhsmiaa, + evmwhusiaa, evmwhumiaa, evmwhssfan, evmwhssian, evmwhsmfan, + evmwhsmian, evmwhusian, evmwhumian, evmwhgssfaa, evmwhgsmfaa, + evmwhgsmiaa, evmwhgumiaa, evmwhgssfan, evmwhgsmfan, evmwhgsmian, + evmwhgumian, evmwhsmf, evmwhsmfa, evmshsmi, evmshsmia, evmshumi, + evmshumia, evmmlssf, evmmlssfa, evmwlsmf, evmwlsmfa, evmwlumi, + evmwlumia, evmwlssfaaw, evmwlssiaaw, evmwlsmfaaw, evmwlsmiaaw, + evmwlusiaaw, evmwlumiaaw, evmwissfanw, evmwissianw, evmwlsmfanw, + evmwlsmianw, evmwlusianw, evmwlumianw, evmwssf, evmwssfa, + evmwsmf, evmwsmfa, evmwsmi, evmwsmia, evmwumi, evmwumia, + evmwssfaa, evmwsmfaa, evmwsmiaa, evmwumiaa, evmwssfan, evmwsmfan, + evmwsmian, evmwumian, evaddssiaaw, evaddsmiaaw, evaddusiaaw, + evaddumiaaw, evsubfssiaaw, evsubfsmiaaw, evsubfusiaaw, + evsubfumiaaw, evmra, evdivws, evdivws): New e500x2 Core Complex + instructions. + (rfmci): New machine check APU instruction. + (isel): New integer select APU instructino. + (icbtls, icbtlse, icblc, icblce, dcbtls, dcbtlse, dcbtstls, + dcbtstlse, dcblc, dcblce): New cache control APU instructions. + (mtspefscr, mfspefscr): New instructions. + (mfpmr, mtpmr): New performance monitor APU instructions. + (savecontext): New context cache APU instructions. + (bblels, bbelr): New branch locking APU instructions. + (bblels, bbelr): New instructions. + (mftbl, mftbu, mftb): Set as CLASSIC instructions. Add BOOKE alias. + +2002-08-13 Stephane Carrez <stcarrez@nerim.fr> + + * m68hc11-opc.c: Update call operand to accept the page definition. + Identify instructions that are branches and calls to generate a + RL_JUMP relocation. + +2002-08-13 Stephane Carrez <stcarrez@nerim.fr> + + * m68hc11-dis.c (print_insn): Take into account 68HC12 memory + banks and fix disassembling of call instruction. + (print_indexed_operand): New param to tell whether + it was an indirect addressing operand (for disassembling call). + +2002-08-09 Nick Clifton <nickc@redhat.com> + + * po/sv.po: Updated Swedish translation. + +2002-08-08 Maciej W. Rozycki <macro@ds2.pg.gda.pl> + + * mips-opc.c (mips_builtin_opcodes): Remove "dla" and "la" as + aliases to "daddiu" and "addiu". + +2002-07-30 Nick Clifton <nickc@redhat.com> + + * po/sv.po: Updated Swedish translation. + +2002-07-25 Nick Clifton <nickc@redhat.com> + + * po/sv.po: Updated Swedish translation. + * po/es.po: Updated Spanish translation. + * po/pr_BR.po: Updated Brazilian Portuguese translation. + * po/tr.po: Updated Turkish translation. + * po/fr.po: Updated French translation. + +2002-07-24 Nick Clifton <nickc@redhat.com> + + * po/sv.po: Updated Swedish translation. + * po/es.po: Updated Spanish translation. + * po/pr_BR.po: Updated Brazilian Portuguese translation. + +2002-07-23 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2002-07-23 Nick Clifton <nickc@redhat.com> + + * po/fr.po: Updated French translation. + * po/pr_BR.po: New Brazilian Portuguese translation. + * po/id.po: Updated Indonesian translation. + * configure.in (LINGUAS): Add pr_BR. + * configure: Regenerate. + +2002-07-18 Denis Chertykov <denisc@overta.ru> + Frank Ch. Eigler <fche@redhat.com> + Alan Lehotsky <alehotsky@cygnus.com> + matthew green <mrg@redhat.com> + + * configure.in: Add support for ip2k. + * configure: Regenerate. + * Makefile.am: Add support for ip2k. + * Makefile.in: Regenerate. + * disassemble.c: Add support for ip2k. + * ip2k-asm.c: New generated file. + * ip2k-desc.c: New generated file. + * ip2k-desc.h: New generated file. + * ip2k-dis.c: New generated file. + * ip2k-ibld.c: New generated file. + * ip2k-opc.c: New generated file. + * ip2k-opc.h: New generated file. + +2002-07-17 David Mosberger <davidm@hpl.hp.com> + + * ia64-opc-b.c (bWhc): New macro. + (mWhc): Ditto. + (OpPaWhcD): Ditto. + (ia64_opcodes_b): Correct patterns for indirect call + instructions to use 3-bit "wh" field. + * ia64-asmtab.c: Regnerate. + +2002-07-09 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips-dis.c (mips_isa_type): Add MIPS16 insn handling. + * mips-opc.c (I16): New define. + (mips_builtin_opcodes): Make jalx an I16 insn. + +2002-06-18 Dave Brolley <brolley@redhat.com> + + * po/POTFILES.in: Add frv-*.[ch]. + * disassemble.c (ARCH_frv): New macro. + (disassembler): Handle bfd_arch_frv. + * configure.in: Support frv_bfd_arch. + * Makefile.am (HFILES): Add frv-*.h. + (CFILES): Add frv-*.c + (ALL_MACHINES): Add frv-*.lo. + (CLEANFILES): Add stamp-frv. + (FRV_DEPS): New variable. + (stamp-frv): New target. + (frv-asm.lo): New target. + (frv-desc.lo): New target. + (frv-dis.lo): New target. + (frv-ibld.lo): New target. + (frv-opc.lo): New target. + (frv-*.[ch]): New files. + +2002-06-18 Ben Elliston <bje@redhat.com> + + * Makefile.am (CGENDEPS): Remove unnecessary stamp-cgen. + * Makefile.in: Regenerate. + +2002-06-08 Alan Modra <amodra@bigpond.net.au> + + * a29k-dis.c: Replace CONST with const. + * h8300-dis.c: Likewise. + * m68k-dis.c: Likewise. + * or32-dis.c: Likewise. + * sparc-dis.c: Likewise. + +2002-06-04 Jason Thorpe <thorpej@wasabisystems.com> + + * configure.in: Add "sh5*-*" to list of targets which include + sh64 support. + * configure: Regenerate. + +2002-05-31 Chris G. Demetriou <cgd@broadcom.com> + + * mips-opc.c: Clean up a few whitespace issues, and sort a + few entries understanding that 'x' follows 'w' in the alphabet. + +2002-05-31 Chris G. Demetriou <cgd@broadcom.com> + Ed Satterthwaite <ehs@broadcom.com> + + * mips-opc.c: Add support for SB-1 MDMX subset and extensions. + +2002-05-31 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2002-05-30 Chris G. Demetriou <cgd@broadcom.com> + Ed Satterthwaite <ehs@broadcom.com> + + * mips-dis.c (print_insn_arg): Add support for 'O', 'Q', 'X', 'Y', + and 'Z' formats, for MDMX. + (mips_isa_type): Add MDMX instructions to the ISA + bit mask for bfd_mach_mipsisa64. + * mips-opc.c: Add support for MDMX instructions. + (MX): New definition. + + * mips-dis.c: Update copyright years to include 2002. + +2002-05-30 Diego Novillo <dnovillo@redhat.com> + + * d10v-opc.c (d10v_opcodes): `btsti' does not modify its + arguments. + +2002-05-28 Kuang Hwa Lin <kuang@sbcglobal.net> + + * configure.in: Add DLX configuraton support. + * configure: Regenerate. + * Makefile.am: Add DLX configuraton support. + * Makefile.in: Regenerate. + * disassemble.c: Add DLX support. + * dlx-dis.c: New file. + +2002-05-25 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am (sh-dis.lo): Don't put make commands in deps. + * Makefile.in: Regenerate. + * arc-dis.c: Use #include "" instead of <> for local header files. + * m68k-dis.c: Likewise. + +2002-05-22 J"orn Rennecke <joern.rennecke@superh.com> + + * Makefile.am (sh-dis.lo): Compile with @archdefs@. + * Makefile.in: regenerate. + + * sh-dis.c (print_insn_sh): If coff and bfd_mach_sh, use arch_sh4 + for disassembly. + +2002-05-22 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips-opc.c (mips_builtin_opcodes): Add drol, dror macros. + +2002-05-17 J"orn Rennecke <joern.rennecke@superh.com> + + * disassemble.c (disassembler): Just use print_insn_sh for bfd_arch_sh. + * sh-dis.c (LITTLE_BIT): Delete. + (print_insn_sh, print_insn_shl): Deleted. + (print_insn_shx): Renamed to + (print_insn_sh). No longer static. Handle SHmedia instructions. + Use info->endian to determine endianness. + * sh64-dis.c (print_insn_sh64, print_insn_sh64l): Delete. + (print_insn_sh64x): No longer static. Renamed to + (print_insn_sh64). Removed pfun_compact and endian arguments. + If we got an uneven address to indicate SHmedia, adjust it. + Return -2 for SHcompact instructions. + +2002-05-17 Alan Modra <amodra@bigpond.net.au> + + * acinclude.m4 (AM_INSTALL_LIBBFD): Fake to fool autotools. + * configure.in: Invoke AM_INSTALL_LIBBFD. + * Makefile.am (install-data-local): Move to.. + (install_libopcodes): .. New target. + (uninstall_libopcodes): Likewise. + (install-bfdlibLTLIBRARIES): Likewise. + (uninstall-bfdlibLTLIBRARIES): Likewise. + (bfdlibdir): New. + (bfdincludedir): New. + (lib_LTLIBRARIES): Rename to bfdlib_LTLIBRARIES. + * aclocal.m4: Regenerate. + * configure: Regenerate. + * Makefile.in: Regenerate. + +2002-05-15 Nick Clifton <nickc@cambridge.redhat.com> + + * fr30-asm.c: Regenerate. + * fr30-desc.c: Regenerate. + * fr30-dis.c: Regenerate. + * m32r-asm.c: Regenerate. + * m32r-desc.c: Regenerate. + * m32r-dis.c: Regenerate. + * openrisc-asm.c: Regenerate. + * openrisc-desc.c: Regenerate. + * openrisc-dis.c: Regenerate. + * xstormy16-asm.c: Regenerate. + * xstormy16-desc.c: Regenerate. + * xstormy16-dis.c: Regenerate. + +2002-05-15 Thiemo Seufer <seufer@csv.ica.uni-stuttgart.de> + + * mips-dis.c (is_newabi): EABI is not a NewABI. + +2002-05-13 Jason Thorpe <thorpej@wasabisystems.com> + + * configure.in (shle-*-*elf*): Include sh64 support. + * configure: Regenerate. + +2002-04-28 Jason Thorpe <thorpej@wasabisystems.com> + + * vax-dis.c (print_insn_arg): Pass the insn info to print_insn_mode. + (print_insn_mode): Print some basic info about floating point values. + +2002-05-09 Anton Blanchard <anton@samba.org> + + * ppc-opc.c: Add "tlbiel" for POWER4. + +2002-05-07 Graydon Hoare <graydon@redhat.com> + + * cgen-dis.in: (print_insn_@arch@): Cache list of opened CPUs rather + than just most-recently-opened. + +2002-05-01 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c: Add "tlbsx." and "tlbsxe." for booke. + +2002-04-24 Christian Groessler <chris@groessler.org> + + * z8k-dis.c (print_insn_z8k): Set disassemble_info to 2 + bytes_per_chunk, 6 bytes_per_line for nicer display of the hex + codes. + (z8k_lookup_instr): CLASS_IGNORE case added. + (output_instr): Don't print hex codes, they are already + printed. + (unpack_instr): ARG_NIM4 case added. ARG_NIM8 case + fixed. Support CLASS_BIT_1OR2 and CLASS_IGNORE cases. + (unparse_instr): Fix base and indexed addressing disassembly: + The index is inside the brackets. + * z8kgen.c (gas): Add ARG_NIM4 and CLASS_IGNORE defines. + (opt): Fix shift left/right arithmetic/logical byte defines: + The high byte of the immediate word is ignored by the + processor. + Fix n parameter of ldm opcodes: The opcode contains (n-1). + (args): Fix "n" entry. + (toks): Add "nim4" and "iiii" entries. + * z8k-opc.h: Regenerated with new z8kgen.c. + +2002-04-24 Nick Clifton <nickc@cambridge.redhat.com> + + * po/id.po: New Indonesian translation. + * configure.in (ALL_LIGUAS): Add id.po + * configure: Regenerate. + +2002-04-17 matthew green <mrg@redhat.com> + + * ppc-opc.c (powerpc_opcode): Fix dssall operand list. + +2002-04-04 Alan Modra <amodra@bigpond.net.au> + + * dep-in.sed: Cope with absolute paths. + * Makefile.am (dep.sed): Subst TOPDIR. + Run "make dep-am". + * Makefile.in: Regenerate. + * ppc-opc.c: Whitespace. + * s390-dis.c: Fix copyright date. + +2002-03-23 matthew green <mrg@redhat.com> + + * ppc-opc.c (vmaddfp): Fix operand order. + +2002-03-21 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + +2002-03-21 Anton Blanchard <anton@samba.org> + + * ppc-opc.c: Add optional field to mtmsrd. + (MTMSRD_L, XRLARB_MASK): Define. + +2002-03-18 Jan Hubicka <jh@suse.cz> + + * i386-dis.c (prefix_name): Fix handling of 32bit address prefix + in 64bit mode. + (print_insn) Likewise. + (putop): Fix handling of 'E' + (OP_E, OP_OFF): handle 32bit addressing mode in 64bit. + (ptr_reg): Likewise. + +2002-03-18 Nick Clifton <nickc@cambridge.redhat.com> + + * po/fr.po: Updated version. + +2002-03-16 Chris Demetriou <cgd@broadcom.com> + + * mips-opc.c (M3D): Tweak comment. + (mips_builtin_op): Add comment indicating that opcodes of the + same name must be placed together in the table, and sort + the "recip.fmt", "recip1.fmt", "recip2.fmt", "rsqrt.fmt", + "rsqrt1.fmt", and "rsqrt2.fmt" opcodes by name. + +2002-03-16 Nick Clifton <nickc@cambridge.redhat.com> + + * Makefile.am: Tidy up sh64 rules. + * Makefile.in: Regenerate. + +2002-03-15 Chris G. Demetriou <cgd@broadcom.com> + + * mips-dis.c: Update copyright years. + +2002-03-15 Chris G. Demetriou <cgd@broadcom.com> + + * mips-dis.c (mips_isa_type): Add MIPS3D instructions to the ISA + bit masks for bfd_mach_mips_sb1 and bfd_mach_mipsisa64. Add + comments for bfd_mach_mipsisa32 and bfd_mach_mipsisa64 that + indicate that they should dissassemble all applicable + MIPS-specified ASEs. + * mips-opc.c: Add support for MIPS-3D instructions. + (M3D): New definition. + + * mips-opc.c: Update copyright years. + +2002-03-15 Chris G. Demetriou <cgd@broadcom.com> + + * mips-opc.c (mips_builtin_opcodes): Sort bc<N> opcodes by name. + +2002-03-15 Chris Demetriou <cgd@broadcom.com> + + * mips-dis.c (is_newabi): Fix ABI decoding. + +2002-03-14 Chris G. Demetriou <cgd@broadcom.com> + + * mips-dis.c (mips_isa_type): Fix formatting of bfd_mach_mipsisa32 + and bfd_mach_mipsisa64 cases to match the rest. + +2002-03-13 Nick Clifton <nickc@cambridge.redhat.com> + + * po/fr.po: Updated version. + +2002-03-13 Alan Modra <amodra@bigpond.net.au> + + * ppc-opc.c: Add optional `L' field to tlbie. + (XRTLRA_MASK): Define. + +2002-03-06 Chris Demetriou <cgd@broadcom.com> + + * mips-opc.c (mips_builtin_opcodes): Mark "pref" as being + present on I4. + + * mips-opc.c (mips_builtin_opcodes): Add "movn.ps" and "movz.ps". + +2002-03-05 Paul Koning <pkoning@equallogic.com> + + * pdp11-opc.c: Fix "mark" operand type. Fix operand types + for float opcodes that take float operands. Add alternate + names (xxxD vs. xxxF) for float opcodes. + * pdp11-dis.c (print_operand): Clean up formatting for mode 67. + (print_foperand): New function to handle float opcode operands. + (print_insn_pdp11): Use print_foperand to disassemble float ops. + +2002-02-27 Nick Clifton <nickc@cambridge.redhat.com> + + * po/de.po: Updated. + +2002-02-26 Brian Gaeke <brg@dgate.org> + + * Makefile.am (install-data-local): Install dis-asm.h. + +2002-02-26 Nick Clifton <nickc@cambridge.redhat.com> + + * configure.in (LINGUAS): Add de.po. + * configure: Regenerate. + * po/de.po: New file. + +2002-02-25 Alan Modra <amodra@bigpond.net.au> + + * ppc-dis.c (powerpc_dialect): Handle power4 option. + * ppc-opc.c (insert_bdm): Correct description of "at" branch + hints. Test PPC_OPCODE_POWER4 to determine branch hint flavour. + (extract_bdm, insert_bdp, extract_bdp, valid_bo): Likewise. + (BOFM64, BOFP64, BOTM64, BOFP64): Rename to BOFM4, BOFP4 etc. + (BODNZM64, BODNZP64, BODZM64, BODZP64): Likewise. + (PPCCOM32, PPCCOM64): Delete. + (NOPOWER4, POWER4): Define. + (powerpc_opcodes): Replace occurences of PPCCOM32 with NOPOWER4, + and PPCCOM4 with POWER4 so that "at" style branch hint opcodes + are enabled for power4 rather than ppc64. + +2002-02-20 Tom Rix <trix@redhat.com> + + * ppc-opc.c (powerpc_operands): Add WS field. Use for tlbre, tlbwe. + +2002-02-19 Martin Schwidefsky <schwidefsky@de.ibm.com> + + * s390-dis.c (init_disasm): Use renamed architecture defines. + +2002-02-19 matthew green <mrg@redhat.com> + + * ppc-opc.c (powerpc_dialect): Fix comment; BookE is not Motorola + specific. + +2002-02-18 Nick Clifton <nickc@cambridge.redhat.com> + + * po/tr.po: Updated translation. + +2002-02-15 Richard Henderson <rth@redhat.com> + + * alpha-opc.c (alpha_opcodes): Fix thinko in ret pseudo + disassembly mask. + +2002-02-15 Richard Henderson <rth@redhat.com> + + * alpha-opc.c (alpha_opcodes): Add simple pseudos for + lda, ldah, jmp, ret. + +2002-02-14 Nick Clifton <nickc@cambridge.redhat.com> + + * po/da.po: Updated translation. + +2002-02-12 Graydon Hoare <graydon@redhat.com> + + * cgen-asm.in (parse_insn_normal): Change call from + @arch@_cgen_parse_operand to cd->parse_operand, to + facilitate CGEN_ASM_INIT_HOOK doing useful work. + +2002-02-11 Alexandre Oliva <aoliva@redhat.com> + + * sparc-dis.c (print_insn_sparc): Make sure 0xFFFFFFFF is not + sign-extended. + +2002-02-11 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: "make dep-am". + * Makefile.in: Regenerate. + * aclocal.m4: Regenerate. + * config.in: Regenerate. + * configure: Regenerate. + +2002-02-10 Hans-Peter Nilsson <hp@bitrange.com> + + * configure.in <bfd_sh_arc>: For sh-* and shl-*, enable sh64 + support only for sh-*-*elf*, shl-*-*elf*, sh-*-linux* and + shl-*-linux*. + * configure: Regenerate. + +2002-02-10 Daniel Jacobowitz <drow@mvista.com> + + * cgen-dis.c: Add prototypes for count_decodable_bits + and add_insn_to_hash_chain. + +2002-02-08 Alexandre Oliva <aoliva@redhat.com> + + * configure.in <bfd_sh_arc>: Enable sh64 support on sh-*. + * configure: Rebuilt. + +2002-02-08 Ivan Guzvinec <ivang@opencores.org> + + * or32-opc.c: Fix compile time warning messages. + * or32-dis.c: Fix compile time warning messages. + +2002-02-08 Alexandre Oliva <aoliva@redhat.com> + + Contribute sh64-elf. + 2001-10-08 Nick Clifton <nickc@cambridge.redhat.com> + * sh64-opc.c: Regenerate. + 2001-03-13 DJ Delorie <dj@redhat.com> + * sh64-opc.h: Rename A_RESV_Fx to A_REUSE_PREV so that its + purpose is more obvious. + * sh64-opc.c (shmedia_table): Ditto. + * sh64-dis.c (initialize_shmedia_opcode_mask_table): Ditto. + (print_insn_shmedia): Ditto. + 2001-03-12 DJ Delorie <dj@redhat.com> + * sh64-opc.c: Adjust comments to reflect reality: replace bits + 3:0 with zeros (not "reserved"), replace "rrrrrr" with + "gggggg" for two-operand floating point opcodes. Remove + "fsina". + 2001-01-08 Hans-Peter Nilsson <hpn@cygnus.com> + * sh64-dis.c (print_insn_shmedia) <failing read_memory_func>: + Correct printing of .byte:s. Return number of printed bytes or + -1; never 0. + (print_insn_sh64x) <not CRT_SH5_ISA16>: Ditto. Print as .byte:s + to next four-byte-alignment if insn or data is not aligned. + 2001-01-06 Hans-Peter Nilsson <hpn@cygnus.com> + * sh64-dis.c: Update comments and fix comment formatting. + (initialize_shmedia_opcode_mask_table) <case A_IMMM>: + Abort instead of setting length to 0. + (crange_qsort_cmpb, crange_qsort_cmpl, crange_bsearch_cmpb, + crange_bsearch_cmpl, sh64_get_contents_type, + sh64_address_in_cranges): Move to bfd/elf32-sh64.c. + 2001-01-05 Hans-Peter Nilsson <hpn@cygnus.com> + * sh64-opc.c: Remove #if 0:d entries for instructions not found in + SH-5/ST50-023-04: fcosa.s, fsrra.s and prefo. + 2000-12-30 Hans-Peter Nilsson <hpn@cygnus.com> + * sh64-dis.c (print_insn_shmedia): Display MOVI/SHORI-formed + address with same prefix as SHcompact. + In the disassembler, use a .cranges section for linked executables. + * sh64-dis.c (SAVED_MOVI_R, SAVED_MOVI_IMM): Move to head of file + and update for using structure in info->private_data. + (struct sh64_disassemble_info): New. + (is_shmedia_p): Delete. + (crange_qsort_cmpb): New function. + (crange_qsort_cmpl, crange_bsearch_cmpb): New functions. + (crange_bsearch_cmpl, sh64_address_in_cranges): New functions. + (init_sh64_disasm_info, sh64_get_contents_type_disasm): New functions. + (sh64_get_contents_type, sh64_address_is_shmedia): New functions. + (print_insn_shmedia): Correct displaying of address after MOVI/SHORI + pair. Display addresses for linked executables only. + (print_insn_sh64x_media): Initialize info->private_data by calling + init_sh64_disasm_info. + (print_insn_sh64x): Ditto. Find out type of contents by calling + sh64_contents_type_disasm. Display data regions using ".long" and + ".byte" similar to unrecognized opcodes. + 2000-12-19 Hans-Peter Nilsson <hpn@cygnus.com> + * sh64-dis.c (is_shmedia_p): Check info->section and look for ISA + information in section flags before considering symbols. Don't + assume an info->mach setting of bfd_mach_sh5 means SHmedia code. + * configure.in (bfd_sh_arch): Check presence of sh64 insns by + matching $target $canon_targets instead of looking at the + now-removed -DINCLUDE_SHMEDIA in $targ_cflags. + * configure: Regenerate. + 2000-11-25 Hans-Peter Nilsson <hpn@cygnus.com> + * sh64-opc.c (shmedia_creg_table): New. + * sh64-opc.h (shmedia_creg_info): New type. + (shmedia_creg_table): Declare. + * sh64-dis.c (creg_name): New function. + (print_insn_shmedia): Use it. + * disassemble.c (disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map + bfd_mach_sh5 to print_insn_sh64 if big-endian and to + print_insn_sh64l if little-endian. + * sh64-dis.c (print_insn_shmedia): Make r unsigned. + (print_insn_sh64l): New. + (print_insn_sh64x): New. + (print_insn_sh64x_media): New. + (print_insn_sh64): Break out code to print_insn_sh64x and + print_insn_sh64x_media. + 2000-11-24 Hans-Peter Nilsson <hpn@cygnus.com> + * sh64-opc.h: New file + * sh64-opc.c: New file + * sh64-dis.c: New file + * Makefile.am: Add sh64 targets. + (HFILES): Add sh64-opc.h. + (CFILES): Add sh64-opc.c and sh64-dis.c. + (ALL_MACHINES): Add sh64 files. + * Makefile.in: Regenerate. + * configure.in: Add support for sh64 to bfd_sh_arch. + * configure: Regenerate. + * disassemble.c [ARCH_all] (INCLUDE_SHMEDIA): Define. + (disassembler) [ARCH_sh, INCLUDE_SHMEDIA]: Map bfd_mach_sh5 to + print_insn_sh64. + * sh-dis.c (print_insn_shx): Handle bfd_mach_sh5 as arch_sh4. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2002-02-04 Frank Ch. Eigler <fche@redhat.com> + + * cgen-dis.in (print_insn_@arch@): Support disassemble_info.insn_sets. + +2002-02-04 Alexandre Oliva <aoliva@redhat.com> + + * sh-opc.h (sh_arg_type): Added A_DISP_PC_ABS. + +2002-02-01 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am" + * Makefile.in: Regenerate. + +2002-01-31 Ivan Guzvinec <ivang@opencores.org> + + * or32-dis.c: New file. + * or32-opc.c: New file. + * configure.in: Add support for or32. + * configure: Regenerate. + * Makefile.am: Add support for or32. + * Makefile.in: Regenerate. + * disassemble.c: Add support for or32. + * po/POTFILES.in: Regenerate. + * po/opcodes.pot: Regenerate. + +2002-01-27 Daniel Jacobowitz <drow@mvista.com> + + * configure: Regenerated. + +2002-01-26 Nick Clifton <nickc@cambridge.redhat.com> + + * po/fr.po: Updated version. + +2002-01-25 Nick Clifton <nickc@cambridge.redhat.com> + + * po/es.po: Updated version. + +2002-01-24 Nick Clifton <nickc@cambridge.redhat.com> + + * po/da.po: New version. + +2002-01-23 Nick Clifton <nickc@cambridge.redhat.com> + + * po/da.po: New file: Spanish translation. + * configure.in (ALL_LINGUAS): Add da. + * configure: Regenerate. + +2002-01-22 Graydon Hoare <graydon@redhat.com> + + * fr30-asm.c: Regenerate. + * fr30-desc.c: Likewise. + * fr30-desc.h: Likewise. + * fr30-dis.c: Likewise. + * fr30-ibld.c: Likewise. + * fr30-opc.c: Likewise. + * fr30-opc.h: Likewise. + * m32r-asm.c: Likewise. + * m32r-desc.c: Likewise. + * m32r-desc.h: Likewise. + * m32r-dis.c: Likewise. + * m32r-ibld.c: Likewise. + * m32r-opc.c: Likewise. + * m32r-opc.h: Likewise. + * m32r-opinst.c: Likewise. + * openrisc-asm.c: Likewise. + * openrisc-desc.c: Likewise. + * openrisc-desc.h: Likewise. + * openrisc-dis.c: Likewise. + * openrisc-ibld.c: Likewise. + * openrisc-opc.c: Likewise. + * openrisc-opc.h: Likewise. + * xstormy16-desc.c: Likewise. + +2002-01-22 Richard Henderson <rth@redhat.com> + + * alpha-dis.c (print_insn_alpha): Also mask the base opcode for + comparison. + +2002-01-22 Alan Modra <amodra@bigpond.net.au> + + * Makefile.am: Run "make dep-am". + * Makefile.in: Regenerate. + * po/POTFILES.in: Regenerate. + +2002-01-19 Richard Earnshaw <rearnsha@arm.com> + + * arm-opc.h (arm_opcodes): Use generic rule %5?hb instead of %h. + * arm-dis.c (print_insn_arm): Don't handle 'h' case. + +2002-01-18 Keith Walker <keith.walker@arm.com> + + * arm-opc.h (arm_opcodes): Add bxj instruction. + +2002-01-17 Nick Clifton <nickc@cambridge.redhat.com> + + * po/opcodes.pot: Regenerate. + * po/fr.po: Regenerate. + * po/sv.po: Regenerate. + * po/tr.po: Regenerate. + +2002-01-16 Nick Clifton <nickc@cambridge.redhat.com> + + * po/tr.po: Import new version. + +2002-01-15 Richard Earnshaw <rearnsha@arm.com> + + * arm-opc.h (arm_opcodes): Add patterns for VFP instructions. + * arm-dis.c (print_insn_arm): Support new disassembly qualifiers for + VFP bitfields. + +2002-01-10 matthew green <mrg@redhat.com> + + * xstormy16-asm.c: Regenerate. + * xstormy16-desc.c: Likewise. + * xstormy16-desc.h: Likewise. + * xstormy16-dis.c: Likewise. + * xstormy16-opc.c: Likewise. + * xstormy16-opc.h: Likewise. + +2002-01-07 Nick Clifton <nickc@cambridge.redhat.com> + + * po/es.po: New file: Spanish translation. + * configure.in (ALL_LINGUAS): Add es. + * configure: Regenerate. + +For older changes see ChangeLog-0001 + +Local Variables: +mode: change-log +left-margin: 8 +fill-column: 74 +version-control: never +End: diff --git a/contrib/binutils/opcodes/Makefile.am b/contrib/binutils/opcodes/Makefile.am index bafdb57..ea621f2 100644 --- a/contrib/binutils/opcodes/Makefile.am +++ b/contrib/binutils/opcodes/Makefile.am @@ -30,6 +30,8 @@ HFILES = \ h8500-opc.h \ ia64-asmtab.h \ ia64-opc.h \ + ip2k-desc.h ip2k-opc.h \ + iq2000-desc.h iq2000-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ openrisc-desc.h openrisc-opc.h \ @@ -61,6 +63,7 @@ CFILES = \ d30v-opc.c \ dlx-dis.c \ dis-buf.c \ + dis-init.c \ disassemble.c \ fr30-asm.c \ fr30-desc.c \ @@ -90,6 +93,16 @@ CFILES = \ ia64-opc.c \ ia64-gen.c \ ia64-asmtab.c \ + ip2k-asm.c \ + ip2k-desc.c \ + ip2k-dis.c \ + ip2k-ibld.c \ + ip2k-opc.c \ + iq2000-asm.c \ + iq2000-desc.c \ + iq2000-dis.c \ + iq2000-ibld.c \ + iq2000-opc.c \ m32r-asm.c \ m32r-desc.c \ m32r-dis.c \ @@ -134,6 +147,7 @@ CFILES = \ sparc-dis.c \ sparc-opc.c \ tic30-dis.c \ + tic4x-dis.c \ tic54x-dis.c \ tic54x-opc.c \ tic80-dis.c \ @@ -147,6 +161,7 @@ CFILES = \ xstormy16-dis.c \ xstormy16-ibld.c \ xstormy16-opc.c \ + xtensa-dis.c \ z8k-dis.c \ z8kgen.c @@ -189,6 +204,16 @@ ALL_MACHINES = \ i960-dis.lo \ ia64-dis.lo \ ia64-opc.lo \ + ip2k-asm.lo \ + ip2k-desc.lo \ + ip2k-dis.lo \ + ip2k-ibld.lo \ + ip2k-opc.lo \ + iq2000-asm.lo \ + iq2000-desc.lo \ + iq2000-dis.lo \ + iq2000-ibld.lo \ + iq2000-opc.lo \ m32r-asm.lo \ m32r-desc.lo \ m32r-dis.lo \ @@ -210,6 +235,7 @@ ALL_MACHINES = \ mips16-opc.lo \ mmix-dis.lo \ mmix-opc.lo \ + msp430-dis.lo \ ns32k-dis.lo \ openrisc-asm.lo \ openrisc-desc.lo \ @@ -232,6 +258,7 @@ ALL_MACHINES = \ sparc-dis.lo \ sparc-opc.lo \ tic30-dis.lo \ + tic4x-dis.lo \ tic54x-dis.lo \ tic54x-opc.lo \ tic80-dis.lo \ @@ -245,6 +272,7 @@ ALL_MACHINES = \ xstormy16-dis.lo \ xstormy16-ibld.lo \ xstormy16-opc.lo \ + xtensa-dis.lo \ z8k-dis.lo OFILES = @BFD_MACHINES@ @@ -254,7 +282,12 @@ INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFI disassemble.lo: disassemble.c $(INCDIR)/dis-asm.h $(LIBTOOL) --mode=compile $(COMPILE) -c @archdefs@ $(srcdir)/disassemble.c -libopcodes_la_SOURCES = dis-buf.c disassemble.c +libopcodes_la_SOURCES = dis-buf.c disassemble.c dis-init.c +# It's desirable to list ../bfd/libbfd.la in DEPENDENCIES and LIBADD. +# Unfortunately this causes libtool to add -L$(libdir), referring to the +# planned install directory of libbfd. This can cause us to pick up an +# old version of libbfd, or to pick up libbfd for the wrong architecture +# if host != build. libopcodes_la_DEPENDENCIES = $(OFILES) libopcodes_la_LIBADD = $(OFILES) @WIN32LIBADD@ libopcodes_la_LDFLAGS = -release $(VERSION) @WIN32LDFLAGS@ @@ -279,7 +312,7 @@ libopcodes.a: stamp-lib ; @true POTFILES = $(HFILES) $(CFILES) po/POTFILES.in: @MAINT@ Makefile - for file in $(POTFILES); do echo $$file; done | sort > tmp \ + for f in $(POTFILES); do echo $$f; done | LC_COLLATE= sort > tmp \ && mv tmp $(srcdir)/po/POTFILES.in # We should reconfigure whenever bfd/configure.in changes, because @@ -312,8 +345,8 @@ uninstall_libopcodes: rm -f $(DESTDIR)$(bfdincludedir)/dis-asm.h CLEANFILES = \ - stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ - stamp-xstormy16 \ + stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ + stamp-iq2000 stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -329,52 +362,86 @@ CGENDEPS = \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in +CGEN_CPUS = fr30 frv ip2k m32r openrisc xstormy16 + if CGEN_MAINT +IP2K_DEPS = stamp-ip2k M32R_DEPS = stamp-m32r FR30_DEPS = stamp-fr30 FRV_DEPS = stamp-frv OPENRISC_DEPS = stamp-openrisc +IQ2000_DEPS = stamp-iq2000 XSTORMY16_DEPS = stamp-xstormy16 else +IP2K_DEPS = M32R_DEPS = FR30_DEPS = FRV_DEPS = OPENRISC_DEPS = +IQ2000_DEPS = XSTORMY16_DEPS = endif run-cgen: $(SHELL) $(srcdir)/cgen.sh opcodes $(srcdir) $(CGEN) \ - $(CGENDIR) "$(CGENFLAGS)" $(arch) $(prefix) \ - "$(options)" $(extrafiles) + $(CGENDIR) "$(CGENFLAGS)" $(arch) $(prefix) $(archfile) $(opcfile) \ + "$(options)" "$(extrafiles)" touch stamp-${prefix} .PHONY: run-cgen +# Maintainer utility rule to regenerate all cgen files. +run-cgen-all: + for c in $(CGEN_CPUS) ; \ + do \ + $(MAKE) stamp-$$c || exit 1 ; \ + done +.PHONY: run-cgen-all + # For now, require developers to configure with --enable-cgen-maint. +$(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS) + @true +stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc + $(MAKE) run-cgen arch=ip2k prefix=ip2k options= \ + archfile=$(CPUDIR)/ip2k.cpu opcfile=$(CPUDIR)/ip2k.opc extrafiles= + $(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) @true stamp-m32r: $(CGENDEPS) $(CPUDIR)/m32r.cpu $(CPUDIR)/m32r.opc - $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst extrafiles=opinst + $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst \ + archfile=$(CPUDIR)/m32r.cpu opcfile=$(CPUDIR)/m32r.opc extrafiles=opinst $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS) @true stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc - $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= + $(MAKE) run-cgen arch=fr30 prefix=fr30 options= \ + archfile=$(CPUDIR)/fr30.cpu opcfile=$(CPUDIR)/fr30.opc extrafiles= $(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS) @true -stamp-frv: $(CGENDEPS) $(CPUDIR)/frv.cpu $(CPUDIR)/frv.opc - $(MAKE) run-cgen arch=frv prefix=frv options= extrafiles= +# .cpu and .opc files for frv are kept in a different directory, but cgen has no switch to specify that location, so +# copy those file to the regular place. +stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc + $(MAKE) run-cgen arch=frv prefix=frv options= \ + archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles= $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc - $(MAKE) run-cgen arch=openrisc prefix=openrisc options= extrafiles= + $(MAKE) run-cgen arch=openrisc prefix=openrisc options= \ + archfile=$(CPUDIR)/openrisc.cpu opcfile=$(CPUDIR)/openrisc.opc extrafiles= + +$(srcdir)/iq2000-desc.h $(srcdir)/iq2000-desc.c $(srcdir)/iq2000-opc.h $(srcdir)/iq2000-opc.c $(srcdir)/iq2000-ibld.c $(srcdir)/iq2000-asm.c $(srcdir)/iq2000-dis.c: $(IQ2000_DEPS) + @true +stamp-iq2000: $(CGENDEPS) $(CPUDIR)/iq2000.cpu $(CPUDIR)/iq2000.opc \ + $(CPUDIR)/iq2000m.cpu $(CPUDIR)/iq10.cpu + $(MAKE) run-cgen arch=iq2000 prefix=iq2000 options= \ + archfile=$(CPUDIR)/iq2000.cpu opcfile=$(CPUDIR)/iq2000.opc extrafiles= $(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS) @true stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc - $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= extrafiles= + $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= \ + archfile=$(CPUDIR)/xstormy16.cpu opcfile=$(CPUDIR)/xstormy16.opc extrafiles= ia64-gen: ia64-gen.o $(LINK) ia64-gen.o $(LIBIBERTY) @@ -383,7 +450,7 @@ ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \ ia64-opc-i.c ia64-opc-m.c ia64-opc-d.c ia64-opc.h ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl - here=`pwd`; cd $(srcdir); $$here/ia64-gen > ia64-asmtab.c + ./ia64-gen --srcdir $(srcdir) > $(srcdir)/ia64-asmtab.c s390-mkopc: s390-mkopc.c $(CC_FOR_BUILD) -o s390-mkopc $(srcdir)/s390-mkopc.c @@ -457,18 +524,18 @@ arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \ $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/arc.h + $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h arc-ext.h $(INCDIR)/libiberty.h arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h arm-opc.h \ $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \ - opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ - $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/arm.h \ - $(INCDIR)/elf/reloc-macros.h + opintl.h $(INCDIR)/safe-ctype.h $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ + $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h \ - $(INCDIR)/opcode/avr.h + $(INCDIR)/libiberty.h $(INCDIR)/opcode/avr.h cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h opintl.h @@ -495,6 +562,8 @@ dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/dlx.h dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h +dis-init.lo: dis-init.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ @@ -503,36 +572,38 @@ fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h fr30-desc.lo: fr30-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ - fr30-opc.h opintl.h $(INCDIR)/libiberty.h + fr30-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h \ - $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + fr30-desc.h $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h \ $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h $(INCDIR)/safe-ctype.h fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ fr30-opc.h $(INCDIR)/libiberty.h -frv-asm.lo: frv-asm.c sysdep.h config.h $(BFD_H) \ - $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ - $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h -frv-desc.lo: frv-desc.c sysdep.h config.h $(BFD_H) \ - $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ - $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h -frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \ - $(BFD_H) $(INCDIR)/ansidecl.h \ - $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ - frv-opc.h opintl.h -frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/dis-asm.h \ - $(BFD_H) $(INCDIR)/ansidecl.h \ - $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ - frv-opc.h opintl.h -frv-opc.lo: frv-opc.c sysdep.h config.h $(BFD_H) \ - $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ - $(INCDIR)/opcode/cgen.h frv-opc.h +frv-asm.lo: frv-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +frv-desc.lo: frv-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h +frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + frv-desc.h $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h +frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h $(INCDIR)/safe-ctype.h +frv-opc.lo: frv-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h $(INCDIR)/libiberty.h $(INCDIR)/elf/frv.h \ + $(INCDIR)/elf/reloc-macros.h h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/symcat.h opintl.h + $(INCDIR)/symcat.h opintl.h $(INCDIR)/libiberty.h h8500-dis.lo: h8500-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ opintl.h @@ -567,21 +638,57 @@ ia64-opc.lo: ia64-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ sysdep.h config.h ia64-asmtab.h $(INCDIR)/opcode/ia64.h \ $(BFD_H) $(INCDIR)/symcat.h ia64-asmtab.c ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ - $(INCDIR)/safe-ctype.h sysdep.h config.h ia64-opc.h \ - $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/symcat.h \ + $(INCDIR)/safe-ctype.h sysdep.h config.h $(INCDIR)/getopt.h \ + ia64-opc.h $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/symcat.h \ ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c \ ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c ia64-asmtab.lo: ia64-asmtab.c +ip2k-asm.lo: ip2k-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ + ip2k-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +ip2k-desc.lo: ip2k-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ + ip2k-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h +ip2k-dis.lo: ip2k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + ip2k-desc.h $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h +ip2k-ibld.lo: ip2k-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h \ + $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h $(INCDIR)/safe-ctype.h +ip2k-opc.lo: ip2k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ + ip2k-opc.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +iq2000-asm.lo: iq2000-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen.h \ + iq2000-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +iq2000-desc.lo: iq2000-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen.h \ + iq2000-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h +iq2000-dis.lo: iq2000-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + iq2000-desc.h $(INCDIR)/opcode/cgen.h iq2000-opc.h \ + opintl.h +iq2000-ibld.lo: iq2000-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h \ + $(INCDIR)/opcode/cgen.h iq2000-opc.h opintl.h $(INCDIR)/safe-ctype.h +iq2000-opc.lo: iq2000-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen.h \ + iq2000-opc.h $(INCDIR)/libiberty.h m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h m32r-desc.lo: m32r-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ - m32r-opc.h opintl.h $(INCDIR)/libiberty.h + m32r-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h m32r-dis.lo: m32r-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h \ - $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + m32r-desc.h $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h m32r-ibld.lo: m32r-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h \ $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h $(INCDIR)/safe-ctype.h @@ -603,14 +710,14 @@ m68k-opc.lo: m68k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/m68k.h m88k-dis.lo: m88k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/m88k.h \ - opintl.h + opintl.h $(INCDIR)/libiberty.h mcore-dis.lo: mcore-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ mcore-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/mips.h \ - opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ - $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \ - $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + $(INCDIR)/opcode/mips.h opintl.h $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ + $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h mips-opc.lo: mips-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/mips.h mips16-opc.lo: mips16-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ @@ -638,10 +745,12 @@ openrisc-asm.lo: openrisc-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h openrisc-desc.lo: openrisc-desc.c sysdep.h config.h \ $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h \ - $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h $(INCDIR)/libiberty.h + $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h $(INCDIR)/libiberty.h \ + $(INCDIR)/xregex.h $(INCDIR)/xregex2.h openrisc-dis.lo: openrisc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h \ - $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + openrisc-desc.h $(INCDIR)/opcode/cgen.h openrisc-opc.h \ + opintl.h openrisc-ibld.lo: openrisc-ibld.c sysdep.h config.h \ $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ openrisc-desc.h $(INCDIR)/opcode/cgen.h openrisc-opc.h \ @@ -678,7 +787,8 @@ sh64-dis.lo: sh64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ sh64-opc.h $(INCDIR)/libiberty.h $(BFDDIR)/elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ - $(INCDIR)/bfdlink.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h + $(INCDIR)/bfdlink.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \ + $(BFDDIR)/elf32-sh64.h sh64-opc.lo: sh64-opc.c sh64-opc.h sparc-dis.lo: sparc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/sparc.h $(INCDIR)/dis-asm.h $(BFD_H) \ @@ -687,6 +797,8 @@ sparc-opc.lo: sparc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/sparc.h tic30-dis.lo: tic30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic30.h +tic4x-dis.lo: tic4x-dis.c $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic4x.h tic54x-dis.lo: tic54x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic54x.h \ $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h @@ -713,11 +825,12 @@ xstormy16-asm.lo: xstormy16-asm.c sysdep.h config.h \ $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h xstormy16-desc.lo: xstormy16-desc.c sysdep.h config.h \ $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ - $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/libiberty.h + $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/libiberty.h \ + $(INCDIR)/xregex.h $(INCDIR)/xregex2.h xstormy16-dis.lo: xstormy16-dis.c sysdep.h config.h \ $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ - xstormy16-desc.h $(INCDIR)/opcode/cgen.h xstormy16-opc.h \ - opintl.h + $(INCDIR)/libiberty.h xstormy16-desc.h $(INCDIR)/opcode/cgen.h \ + xstormy16-opc.h opintl.h xstormy16-ibld.lo: xstormy16-ibld.c sysdep.h config.h \ $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ xstormy16-desc.h $(INCDIR)/opcode/cgen.h xstormy16-opc.h \ @@ -725,7 +838,11 @@ xstormy16-ibld.lo: xstormy16-ibld.c sysdep.h config.h \ xstormy16-opc.lo: xstormy16-opc.c sysdep.h config.h \ $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ $(INCDIR)/opcode/cgen.h xstormy16-opc.h $(INCDIR)/libiberty.h +xtensa-dis.lo: xtensa-dis.c $(INCDIR)/xtensa-isa.h \ + $(INCDIR)/ansidecl.h sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/symcat.h z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h z8k-opc.h -z8kgen.lo: z8kgen.c sysdep.h config.h $(INCDIR)/ansidecl.h +z8kgen.lo: z8kgen.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h # IF YOU PUT ANYTHING HERE IT WILL GO AWAY diff --git a/contrib/binutils/opcodes/Makefile.in b/contrib/binutils/opcodes/Makefile.in index b1b7ae1..559194d 100644 --- a/contrib/binutils/opcodes/Makefile.in +++ b/contrib/binutils/opcodes/Makefile.in @@ -1,6 +1,6 @@ -# Makefile.in generated automatically by automake 1.4-p5 from Makefile.am +# Makefile.in generated automatically by automake 1.4 from Makefile.am -# Copyright (C) 1994, 1995-8, 1999, 2001 Free Software Foundation, Inc. +# Copyright (C) 1994, 1995-8, 1999 Free Software Foundation, Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. @@ -140,6 +140,8 @@ HFILES = \ h8500-opc.h \ ia64-asmtab.h \ ia64-opc.h \ + ip2k-desc.h ip2k-opc.h \ + iq2000-desc.h iq2000-opc.h \ m32r-desc.h m32r-opc.h \ mcore-opc.h \ openrisc-desc.h openrisc-opc.h \ @@ -172,6 +174,7 @@ CFILES = \ d30v-opc.c \ dlx-dis.c \ dis-buf.c \ + dis-init.c \ disassemble.c \ fr30-asm.c \ fr30-desc.c \ @@ -201,6 +204,16 @@ CFILES = \ ia64-opc.c \ ia64-gen.c \ ia64-asmtab.c \ + ip2k-asm.c \ + ip2k-desc.c \ + ip2k-dis.c \ + ip2k-ibld.c \ + ip2k-opc.c \ + iq2000-asm.c \ + iq2000-desc.c \ + iq2000-dis.c \ + iq2000-ibld.c \ + iq2000-opc.c \ m32r-asm.c \ m32r-desc.c \ m32r-dis.c \ @@ -245,6 +258,7 @@ CFILES = \ sparc-dis.c \ sparc-opc.c \ tic30-dis.c \ + tic4x-dis.c \ tic54x-dis.c \ tic54x-opc.c \ tic80-dis.c \ @@ -258,6 +272,7 @@ CFILES = \ xstormy16-dis.c \ xstormy16-ibld.c \ xstormy16-opc.c \ + xtensa-dis.c \ z8k-dis.c \ z8kgen.c @@ -301,6 +316,16 @@ ALL_MACHINES = \ i960-dis.lo \ ia64-dis.lo \ ia64-opc.lo \ + ip2k-asm.lo \ + ip2k-desc.lo \ + ip2k-dis.lo \ + ip2k-ibld.lo \ + ip2k-opc.lo \ + iq2000-asm.lo \ + iq2000-desc.lo \ + iq2000-dis.lo \ + iq2000-ibld.lo \ + iq2000-opc.lo \ m32r-asm.lo \ m32r-desc.lo \ m32r-dis.lo \ @@ -322,6 +347,7 @@ ALL_MACHINES = \ mips16-opc.lo \ mmix-dis.lo \ mmix-opc.lo \ + msp430-dis.lo \ ns32k-dis.lo \ openrisc-asm.lo \ openrisc-desc.lo \ @@ -344,6 +370,7 @@ ALL_MACHINES = \ sparc-dis.lo \ sparc-opc.lo \ tic30-dis.lo \ + tic4x-dis.lo \ tic54x-dis.lo \ tic54x-opc.lo \ tic80-dis.lo \ @@ -357,6 +384,7 @@ ALL_MACHINES = \ xstormy16-dis.lo \ xstormy16-ibld.lo \ xstormy16-opc.lo \ + xtensa-dis.lo \ z8k-dis.lo @@ -364,7 +392,12 @@ OFILES = @BFD_MACHINES@ INCLUDES = -D_GNU_SOURCE -I. -I$(srcdir) -I../bfd -I$(INCDIR) -I$(BFDDIR) @HDEFINES@ -I$(srcdir)/../intl -I../intl -libopcodes_la_SOURCES = dis-buf.c disassemble.c +libopcodes_la_SOURCES = dis-buf.c disassemble.c dis-init.c +# It's desirable to list ../bfd/libbfd.la in DEPENDENCIES and LIBADD. +# Unfortunately this causes libtool to add -L$(libdir), referring to the +# planned install directory of libbfd. This can cause us to pick up an +# old version of libbfd, or to pick up libbfd for the wrong architecture +# if host != build. libopcodes_la_DEPENDENCIES = $(OFILES) libopcodes_la_LIBADD = $(OFILES) @WIN32LIBADD@ libopcodes_la_LDFLAGS = -release $(VERSION) @WIN32LDFLAGS@ @@ -379,8 +412,8 @@ noinst_LIBRARIES = libopcodes.a POTFILES = $(HFILES) $(CFILES) CLEANFILES = \ - stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ - stamp-xstormy16 \ + stamp-ip2k stamp-m32r stamp-fr30 stamp-frv stamp-openrisc \ + stamp-iq2000 stamp-xstormy16 \ libopcodes.a stamp-lib dep.sed DEP DEPA DEP1 DEP2 @@ -396,6 +429,10 @@ CGENDEPS = \ $(CGENDIR)/opc-opinst.scm \ cgen-asm.in cgen-dis.in cgen-ibld.in + +CGEN_CPUS = fr30 frv ip2k m32r openrisc xstormy16 +@CGEN_MAINT_TRUE@IP2K_DEPS = @CGEN_MAINT_TRUE@stamp-ip2k +@CGEN_MAINT_FALSE@IP2K_DEPS = @CGEN_MAINT_TRUE@M32R_DEPS = @CGEN_MAINT_TRUE@stamp-m32r @CGEN_MAINT_FALSE@M32R_DEPS = @CGEN_MAINT_TRUE@FR30_DEPS = @CGEN_MAINT_TRUE@stamp-fr30 @@ -404,6 +441,8 @@ CGENDEPS = \ @CGEN_MAINT_FALSE@FRV_DEPS = @CGEN_MAINT_TRUE@OPENRISC_DEPS = @CGEN_MAINT_TRUE@stamp-openrisc @CGEN_MAINT_FALSE@OPENRISC_DEPS = +@CGEN_MAINT_TRUE@IQ2000_DEPS = @CGEN_MAINT_TRUE@stamp-iq2000 +@CGEN_MAINT_FALSE@IQ2000_DEPS = @CGEN_MAINT_TRUE@XSTORMY16_DEPS = @CGEN_MAINT_TRUE@stamp-xstormy16 @CGEN_MAINT_FALSE@XSTORMY16_DEPS = ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 @@ -422,7 +461,7 @@ libopcodes_a_SOURCES = libopcodes.a.c libopcodes_a_OBJECTS = libopcodes.a.$(OBJEXT) LTLIBRARIES = $(bfdlib_LTLIBRARIES) -libopcodes_la_OBJECTS = dis-buf.lo disassemble.lo +libopcodes_la_OBJECTS = dis-buf.lo disassemble.lo dis-init.lo CFLAGS = @CFLAGS@ COMPILE = $(CC) $(DEFS) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) LTCOMPILE = $(LIBTOOL) --mode=compile $(CC) $(DEFS) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) @@ -583,7 +622,7 @@ maintainer-clean-recursive: dot_seen=no; \ rev=''; list='$(SUBDIRS)'; for subdir in $$list; do \ rev="$$subdir $$rev"; \ - test "$$subdir" != "." || dot_seen=yes; \ + test "$$subdir" = "." && dot_seen=yes; \ done; \ test "$$dot_seen" = "no" && rev=". $$rev"; \ target=`echo $@ | sed s/-recursive//`; \ @@ -807,7 +846,7 @@ stamp-lib: libopcodes.la libopcodes.a: stamp-lib ; @true po/POTFILES.in: @MAINT@ Makefile - for file in $(POTFILES); do echo $$file; done | sort > tmp \ + for f in $(POTFILES); do echo $$f; done | LC_COLLATE= sort > tmp \ && mv tmp $(srcdir)/po/POTFILES.in # We should reconfigure whenever bfd/configure.in changes, because @@ -841,36 +880,64 @@ uninstall_libopcodes: run-cgen: $(SHELL) $(srcdir)/cgen.sh opcodes $(srcdir) $(CGEN) \ - $(CGENDIR) "$(CGENFLAGS)" $(arch) $(prefix) \ - "$(options)" $(extrafiles) + $(CGENDIR) "$(CGENFLAGS)" $(arch) $(prefix) $(archfile) $(opcfile) \ + "$(options)" "$(extrafiles)" touch stamp-${prefix} .PHONY: run-cgen +# Maintainer utility rule to regenerate all cgen files. +run-cgen-all: + for c in $(CGEN_CPUS) ; \ + do \ + $(MAKE) stamp-$$c || exit 1 ; \ + done +.PHONY: run-cgen-all + # For now, require developers to configure with --enable-cgen-maint. +$(srcdir)/ip2k-desc.h $(srcdir)/ip2k-desc.c $(srcdir)/ip2k-opc.h $(srcdir)/ip2k-opc.c $(srcdir)/ip2k-ibld.c $(srcdir)/ip2k-asm.c $(srcdir)/ip2k-dis.c: $(IP2K_DEPS) + @true +stamp-ip2k: $(CGENDEPS) $(CPUDIR)/ip2k.cpu $(CPUDIR)/ip2k.opc + $(MAKE) run-cgen arch=ip2k prefix=ip2k options= \ + archfile=$(CPUDIR)/ip2k.cpu opcfile=$(CPUDIR)/ip2k.opc extrafiles= + $(srcdir)/m32r-desc.h $(srcdir)/m32r-desc.c $(srcdir)/m32r-opc.h $(srcdir)/m32r-opc.c $(srcdir)/m32r-ibld.c $(srcdir)/m32r-opinst.c $(srcdir)/m32r-asm.c $(srcdir)/m32r-dis.c: $(M32R_DEPS) @true stamp-m32r: $(CGENDEPS) $(CPUDIR)/m32r.cpu $(CPUDIR)/m32r.opc - $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst extrafiles=opinst + $(MAKE) run-cgen arch=m32r prefix=m32r options=opinst \ + archfile=$(CPUDIR)/m32r.cpu opcfile=$(CPUDIR)/m32r.opc extrafiles=opinst $(srcdir)/fr30-desc.h $(srcdir)/fr30-desc.c $(srcdir)/fr30-opc.h $(srcdir)/fr30-opc.c $(srcdir)/fr30-ibld.c $(srcdir)/fr30-asm.c $(srcdir)/fr30-dis.c: $(FR30_DEPS) @true stamp-fr30: $(CGENDEPS) $(CPUDIR)/fr30.cpu $(CPUDIR)/fr30.opc - $(MAKE) run-cgen arch=fr30 prefix=fr30 options= extrafiles= + $(MAKE) run-cgen arch=fr30 prefix=fr30 options= \ + archfile=$(CPUDIR)/fr30.cpu opcfile=$(CPUDIR)/fr30.opc extrafiles= $(srcdir)/frv-desc.h $(srcdir)/frv-desc.c $(srcdir)/frv-opc.h $(srcdir)/frv-opc.c $(srcdir)/frv-ibld.c $(srcdir)/frv-asm.c $(srcdir)/frv-dis.c: $(FRV_DEPS) @true -stamp-frv: $(CGENDEPS) $(CPUDIR)/frv.cpu $(CPUDIR)/frv.opc - $(MAKE) run-cgen arch=frv prefix=frv options= extrafiles= +# .cpu and .opc files for frv are kept in a different directory, but cgen has no switch to specify that location, so +# copy those file to the regular place. +stamp-frv: $(CGENDEPS) $(srcdir)/../cpu/frv.cpu $(srcdir)/../cpu/frv.opc + $(MAKE) run-cgen arch=frv prefix=frv options= \ + archfile=$(srcdir)/../cpu/frv.cpu opcfile=$(srcdir)/../cpu/frv.opc extrafiles= $(srcdir)/openrisc-desc.h $(srcdir)/openrisc-desc.c $(srcdir)/openrisc-opc.h $(srcdir)/openrisc-opc.c $(srcdir)/openrisc-ibld.c $(srcdir)/openrisc-asm.c $(srcdir)/openrisc-dis.c: $(OPENRISC_DEPS) @true stamp-openrisc: $(CGENDEPS) $(CPUDIR)/openrisc.cpu $(CPUDIR)/openrisc.opc - $(MAKE) run-cgen arch=openrisc prefix=openrisc options= extrafiles= + $(MAKE) run-cgen arch=openrisc prefix=openrisc options= \ + archfile=$(CPUDIR)/openrisc.cpu opcfile=$(CPUDIR)/openrisc.opc extrafiles= + +$(srcdir)/iq2000-desc.h $(srcdir)/iq2000-desc.c $(srcdir)/iq2000-opc.h $(srcdir)/iq2000-opc.c $(srcdir)/iq2000-ibld.c $(srcdir)/iq2000-asm.c $(srcdir)/iq2000-dis.c: $(IQ2000_DEPS) + @true +stamp-iq2000: $(CGENDEPS) $(CPUDIR)/iq2000.cpu $(CPUDIR)/iq2000.opc \ + $(CPUDIR)/iq2000m.cpu $(CPUDIR)/iq10.cpu + $(MAKE) run-cgen arch=iq2000 prefix=iq2000 options= \ + archfile=$(CPUDIR)/iq2000.cpu opcfile=$(CPUDIR)/iq2000.opc extrafiles= $(srcdir)/xstormy16-desc.h $(srcdir)/xstormy16-desc.c $(srcdir)/xstormy16-opc.h $(srcdir)/xstormy16-opc.c $(srcdir)/xstormy16-ibld.c $(srcdir)/xstormy16-asm.c $(srcdir)/xstormy16-dis.c: $(XSTORMY16_DEPS) @true stamp-xstormy16: $(CGENDEPS) $(CPUDIR)/xstormy16.cpu $(CPUDIR)/xstormy16.opc - $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= extrafiles= + $(MAKE) run-cgen arch=xstormy16 prefix=xstormy16 options= \ + archfile=$(CPUDIR)/xstormy16.cpu opcfile=$(CPUDIR)/xstormy16.opc extrafiles= ia64-gen: ia64-gen.o $(LINK) ia64-gen.o $(LIBIBERTY) @@ -879,7 +946,7 @@ ia64-gen.o: ia64-gen.c ia64-opc.c ia64-opc-a.c ia64-opc-b.c ia64-opc-f.c \ ia64-opc-i.c ia64-opc-m.c ia64-opc-d.c ia64-opc.h ia64-asmtab.c: @MAINT@ ia64-gen ia64-ic.tbl ia64-raw.tbl ia64-waw.tbl ia64-war.tbl - here=`pwd`; cd $(srcdir); $$here/ia64-gen > ia64-asmtab.c + ./ia64-gen --srcdir $(srcdir) > $(srcdir)/ia64-asmtab.c s390-mkopc: s390-mkopc.c $(CC_FOR_BUILD) -o s390-mkopc $(srcdir)/s390-mkopc.c @@ -953,18 +1020,18 @@ arc-dis.lo: arc-dis.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h $(INCDIR)/elf/arc.h \ $(INCDIR)/elf/reloc-macros.h opintl.h arc-dis.h arc-ext.h arc-opc.lo: arc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/opcode/arc.h + $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/arc.h arc-ext.lo: arc-ext.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h arc-ext.h $(INCDIR)/libiberty.h arm-dis.lo: arm-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h arm-opc.h \ $(INCDIR)/coff/internal.h $(BFDDIR)/libcoff.h $(INCDIR)/bfdlink.h \ - opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ - $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/elf/arm.h \ - $(INCDIR)/elf/reloc-macros.h + opintl.h $(INCDIR)/safe-ctype.h $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ + $(INCDIR)/elf/arm.h $(INCDIR)/elf/reloc-macros.h avr-dis.lo: avr-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h \ - $(INCDIR)/opcode/avr.h + $(INCDIR)/libiberty.h $(INCDIR)/opcode/avr.h cgen-asm.lo: cgen-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h $(BFD_H) \ $(INCDIR)/symcat.h $(INCDIR)/opcode/cgen.h opintl.h @@ -991,6 +1058,8 @@ dlx-dis.lo: dlx-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/dlx.h dis-buf.lo: dis-buf.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h opintl.h +dis-init.lo: dis-init.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h disassemble.lo: disassemble.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ @@ -999,36 +1068,38 @@ fr30-asm.lo: fr30-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h fr30-desc.lo: fr30-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ - fr30-opc.h opintl.h $(INCDIR)/libiberty.h + fr30-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h fr30-dis.lo: fr30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h \ - $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + fr30-desc.h $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h fr30-ibld.lo: fr30-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h \ $(INCDIR)/opcode/cgen.h fr30-opc.h opintl.h $(INCDIR)/safe-ctype.h fr30-opc.lo: fr30-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h fr30-desc.h $(INCDIR)/opcode/cgen.h \ fr30-opc.h $(INCDIR)/libiberty.h -frv-asm.lo: frv-asm.c sysdep.h config.h $(BFD_H) \ - $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ - $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h -frv-desc.lo: frv-desc.c sysdep.h config.h $(BFD_H) \ - $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ - $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h -frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/dis-asm.h \ - $(BFD_H) $(INCDIR)/ansidecl.h \ - $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ - frv-opc.h opintl.h -frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/dis-asm.h \ - $(BFD_H) $(INCDIR)/ansidecl.h \ - $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ - frv-opc.h opintl.h -frv-opc.lo: frv-opc.c sysdep.h config.h $(BFD_H) \ - $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h frv-desc.h \ - $(INCDIR)/opcode/cgen.h frv-opc.h +frv-asm.lo: frv-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +frv-desc.lo: frv-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h +frv-dis.lo: frv-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + frv-desc.h $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h +frv-ibld.lo: frv-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h frv-desc.h \ + $(INCDIR)/opcode/cgen.h frv-opc.h opintl.h $(INCDIR)/safe-ctype.h +frv-opc.lo: frv-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h frv-desc.h $(INCDIR)/opcode/cgen.h \ + frv-opc.h $(INCDIR)/libiberty.h $(INCDIR)/elf/frv.h \ + $(INCDIR)/elf/reloc-macros.h h8300-dis.lo: h8300-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/h8300.h $(INCDIR)/dis-asm.h $(BFD_H) \ - $(INCDIR)/symcat.h opintl.h + $(INCDIR)/symcat.h opintl.h $(INCDIR)/libiberty.h h8500-dis.lo: h8500-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ h8500-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ opintl.h @@ -1063,21 +1134,57 @@ ia64-opc.lo: ia64-opc.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ sysdep.h config.h ia64-asmtab.h $(INCDIR)/opcode/ia64.h \ $(BFD_H) $(INCDIR)/symcat.h ia64-asmtab.c ia64-gen.lo: ia64-gen.c $(INCDIR)/ansidecl.h $(INCDIR)/libiberty.h \ - $(INCDIR)/safe-ctype.h sysdep.h config.h ia64-opc.h \ - $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/symcat.h \ + $(INCDIR)/safe-ctype.h sysdep.h config.h $(INCDIR)/getopt.h \ + ia64-opc.h $(INCDIR)/opcode/ia64.h $(BFD_H) $(INCDIR)/symcat.h \ ia64-opc-a.c ia64-opc-i.c ia64-opc-m.c ia64-opc-b.c \ ia64-opc-f.c ia64-opc-x.c ia64-opc-d.c ia64-asmtab.lo: ia64-asmtab.c +ip2k-asm.lo: ip2k-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ + ip2k-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +ip2k-desc.lo: ip2k-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ + ip2k-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h +ip2k-dis.lo: ip2k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + ip2k-desc.h $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h +ip2k-ibld.lo: ip2k-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h \ + $(INCDIR)/opcode/cgen.h ip2k-opc.h opintl.h $(INCDIR)/safe-ctype.h +ip2k-opc.lo: ip2k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h ip2k-desc.h $(INCDIR)/opcode/cgen.h \ + ip2k-opc.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +iq2000-asm.lo: iq2000-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen.h \ + iq2000-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ + $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h +iq2000-desc.lo: iq2000-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen.h \ + iq2000-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h +iq2000-dis.lo: iq2000-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + iq2000-desc.h $(INCDIR)/opcode/cgen.h iq2000-opc.h \ + opintl.h +iq2000-ibld.lo: iq2000-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h \ + $(INCDIR)/opcode/cgen.h iq2000-opc.h opintl.h $(INCDIR)/safe-ctype.h +iq2000-opc.lo: iq2000-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(BFD_H) $(INCDIR)/symcat.h iq2000-desc.h $(INCDIR)/opcode/cgen.h \ + iq2000-opc.h $(INCDIR)/libiberty.h m32r-asm.lo: m32r-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ m32r-opc.h opintl.h $(INCDIR)/xregex.h $(INCDIR)/xregex2.h \ $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h m32r-desc.lo: m32r-desc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h $(INCDIR)/opcode/cgen.h \ - m32r-opc.h opintl.h $(INCDIR)/libiberty.h + m32r-opc.h opintl.h $(INCDIR)/libiberty.h $(INCDIR)/xregex.h \ + $(INCDIR)/xregex2.h m32r-dis.lo: m32r-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h \ - $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + m32r-desc.h $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h m32r-ibld.lo: m32r-ibld.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h m32r-desc.h \ $(INCDIR)/opcode/cgen.h m32r-opc.h opintl.h $(INCDIR)/safe-ctype.h @@ -1099,14 +1206,14 @@ m68k-opc.lo: m68k-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/m68k.h m88k-dis.lo: m88k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/m88k.h \ - opintl.h + opintl.h $(INCDIR)/libiberty.h mcore-dis.lo: mcore-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ mcore-opc.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h mips-dis.lo: mips-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/mips.h \ - opintl.h $(BFDDIR)/elf-bfd.h $(INCDIR)/elf/common.h \ - $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h $(INCDIR)/bfdlink.h \ - $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + $(INCDIR)/opcode/mips.h opintl.h $(BFDDIR)/elf-bfd.h \ + $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ + $(INCDIR)/bfdlink.h $(INCDIR)/elf/mips.h $(INCDIR)/elf/reloc-macros.h mips-opc.lo: mips-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/mips.h mips16-opc.lo: mips16-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ @@ -1134,10 +1241,12 @@ openrisc-asm.lo: openrisc-asm.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h openrisc-desc.lo: openrisc-desc.c sysdep.h config.h \ $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h \ - $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h $(INCDIR)/libiberty.h + $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h $(INCDIR)/libiberty.h \ + $(INCDIR)/xregex.h $(INCDIR)/xregex2.h openrisc-dis.lo: openrisc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ - $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h openrisc-desc.h \ - $(INCDIR)/opcode/cgen.h openrisc-opc.h opintl.h + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/libiberty.h \ + openrisc-desc.h $(INCDIR)/opcode/cgen.h openrisc-opc.h \ + opintl.h openrisc-ibld.lo: openrisc-ibld.c sysdep.h config.h \ $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ openrisc-desc.h $(INCDIR)/opcode/cgen.h openrisc-opc.h \ @@ -1174,7 +1283,8 @@ sh64-dis.lo: sh64-dis.c $(INCDIR)/dis-asm.h $(BFD_H) \ $(INCDIR)/ansidecl.h $(INCDIR)/symcat.h sysdep.h config.h \ sh64-opc.h $(INCDIR)/libiberty.h $(BFDDIR)/elf-bfd.h \ $(INCDIR)/elf/common.h $(INCDIR)/elf/internal.h $(INCDIR)/elf/external.h \ - $(INCDIR)/bfdlink.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h + $(INCDIR)/bfdlink.h $(INCDIR)/elf/sh.h $(INCDIR)/elf/reloc-macros.h \ + $(BFDDIR)/elf32-sh64.h sh64-opc.lo: sh64-opc.c sh64-opc.h sparc-dis.lo: sparc-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/sparc.h $(INCDIR)/dis-asm.h $(BFD_H) \ @@ -1183,6 +1293,8 @@ sparc-opc.lo: sparc-opc.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/opcode/sparc.h tic30-dis.lo: tic30-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic30.h +tic4x-dis.lo: tic4x-dis.c $(INCDIR)/libiberty.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic4x.h tic54x-dis.lo: tic54x-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h $(INCDIR)/opcode/tic54x.h \ $(INCDIR)/coff/tic54x.h $(INCDIR)/coff/ti.h @@ -1209,11 +1321,12 @@ xstormy16-asm.lo: xstormy16-asm.c sysdep.h config.h \ $(INCDIR)/xregex2.h $(INCDIR)/libiberty.h $(INCDIR)/safe-ctype.h xstormy16-desc.lo: xstormy16-desc.c sysdep.h config.h \ $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ - $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/libiberty.h + $(INCDIR)/opcode/cgen.h xstormy16-opc.h opintl.h $(INCDIR)/libiberty.h \ + $(INCDIR)/xregex.h $(INCDIR)/xregex2.h xstormy16-dis.lo: xstormy16-dis.c sysdep.h config.h \ $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ - xstormy16-desc.h $(INCDIR)/opcode/cgen.h xstormy16-opc.h \ - opintl.h + $(INCDIR)/libiberty.h xstormy16-desc.h $(INCDIR)/opcode/cgen.h \ + xstormy16-opc.h opintl.h xstormy16-ibld.lo: xstormy16-ibld.c sysdep.h config.h \ $(INCDIR)/ansidecl.h $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h \ xstormy16-desc.h $(INCDIR)/opcode/cgen.h xstormy16-opc.h \ @@ -1221,9 +1334,13 @@ xstormy16-ibld.lo: xstormy16-ibld.c sysdep.h config.h \ xstormy16-opc.lo: xstormy16-opc.c sysdep.h config.h \ $(INCDIR)/ansidecl.h $(BFD_H) $(INCDIR)/symcat.h xstormy16-desc.h \ $(INCDIR)/opcode/cgen.h xstormy16-opc.h $(INCDIR)/libiberty.h +xtensa-dis.lo: xtensa-dis.c $(INCDIR)/xtensa-isa.h \ + $(INCDIR)/ansidecl.h sysdep.h config.h $(INCDIR)/dis-asm.h \ + $(BFD_H) $(INCDIR)/symcat.h z8k-dis.lo: z8k-dis.c sysdep.h config.h $(INCDIR)/ansidecl.h \ $(INCDIR)/dis-asm.h $(BFD_H) $(INCDIR)/symcat.h z8k-opc.h -z8kgen.lo: z8kgen.c sysdep.h config.h $(INCDIR)/ansidecl.h +z8kgen.lo: z8kgen.c sysdep.h config.h $(INCDIR)/ansidecl.h \ + $(INCDIR)/libiberty.h # IF YOU PUT ANYTHING HERE IT WILL GO AWAY # Tell versions [3.59,3.63) of GNU make to not export all variables. diff --git a/contrib/binutils/opcodes/aclocal.m4 b/contrib/binutils/opcodes/aclocal.m4 index 184bf36..92732d3 100644 --- a/contrib/binutils/opcodes/aclocal.m4 +++ b/contrib/binutils/opcodes/aclocal.m4 @@ -35,6 +35,24 @@ AC_SUBST(bfdlibdir) AC_SUBST(bfdincludedir) ]) +#serial 1 +# This test replaces the one in autoconf. +# Currently this macro should have the same name as the autoconf macro +# because gettext's gettext.m4 (distributed in the automake package) +# still uses it. Otherwise, the use in gettext.m4 makes autoheader +# give these diagnostics: +# configure.in:556: AC_TRY_COMPILE was called before AC_ISC_POSIX +# configure.in:556: AC_TRY_RUN was called before AC_ISC_POSIX + +undefine([AC_ISC_POSIX]) + +AC_DEFUN([AC_ISC_POSIX], + [ + dnl This test replaces the obsolescent AC_ISC_POSIX kludge. + AC_CHECK_LIB(cposix, strerror, [LIBS="$LIBS -lcposix"]) + ] +) + # Do all the work for Automake. This macro actually does too much -- # some checks are only needed if your package does certain things. # But this isn't really a big deal. diff --git a/contrib/binutils/opcodes/alpha-opc.c b/contrib/binutils/opcodes/alpha-opc.c index 6cf7d4c..5371597 100644 --- a/contrib/binutils/opcodes/alpha-opc.c +++ b/contrib/binutils/opcodes/alpha-opc.c @@ -1,5 +1,5 @@ /* alpha-opc.c -- Alpha AXP opcode list - Copyright 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2000, 2003 Free Software Foundation, Inc. Contributed by Richard Henderson <rth@cygnus.com>, patterned after the PPC opcode handling written by Ian Lance Taylor. @@ -214,7 +214,6 @@ const unsigned alpha_num_operands = sizeof(alpha_operands)/sizeof(*alpha_operand the RA field into the RB field, and the extraction function just checks that the fields are the same. */ -/*ARGSUSED*/ static unsigned insert_rba(insn, value, errmsg) unsigned insn; @@ -238,7 +237,6 @@ extract_rba(insn, invalid) /* The same for the RC field */ -/*ARGSUSED*/ static unsigned insert_rca(insn, value, errmsg) unsigned insn; @@ -262,7 +260,6 @@ extract_rca(insn, invalid) /* Fake arguments in which the registers must be set to ZERO */ -/*ARGSUSED*/ static unsigned insert_za(insn, value, errmsg) unsigned insn; @@ -282,7 +279,6 @@ extract_za(insn, invalid) return 0; } -/*ARGSUSED*/ static unsigned insert_zb(insn, value, errmsg) unsigned insn; @@ -302,7 +298,6 @@ extract_zb(insn, invalid) return 0; } -/*ARGSUSED*/ static unsigned insert_zc(insn, value, errmsg) unsigned insn; @@ -336,7 +331,6 @@ insert_bdisp(insn, value, errmsg) return insn | ((value / 4) & 0x1FFFFF); } -/*ARGSUSED*/ static int extract_bdisp(insn, invalid) unsigned insn; @@ -359,7 +353,6 @@ insert_jhint(insn, value, errmsg) return insn | ((value / 4) & 0x3FFF); } -/*ARGSUSED*/ static int extract_jhint(insn, invalid) unsigned insn; @@ -381,7 +374,6 @@ insert_ev6hwjhint(insn, value, errmsg) return insn | ((value / 4) & 0x1FFF); } -/*ARGSUSED*/ static int extract_ev6hwjhint(insn, invalid) unsigned insn; @@ -533,9 +525,13 @@ const struct alpha_opcode alpha_opcodes[] = { { "halt", SPCD(0x00,0x0000), BASE, ARG_NONE }, { "draina", SPCD(0x00,0x0002), BASE, ARG_NONE }, { "bpt", SPCD(0x00,0x0080), BASE, ARG_NONE }, + { "bugchk", SPCD(0x00,0x0081), BASE, ARG_NONE }, { "callsys", SPCD(0x00,0x0083), BASE, ARG_NONE }, { "chmk", SPCD(0x00,0x0083), BASE, ARG_NONE }, { "imb", SPCD(0x00,0x0086), BASE, ARG_NONE }, + { "rduniq", SPCD(0x00,0x009e), BASE, ARG_NONE }, + { "wruniq", SPCD(0x00,0x009f), BASE, ARG_NONE }, + { "gentrap", SPCD(0x00,0x00aa), BASE, ARG_NONE }, { "call_pal", PCD(0x00), BASE, ARG_PCD }, { "pal", PCD(0x00), BASE, ARG_PCD }, /* alias */ @@ -1101,7 +1097,8 @@ const struct alpha_opcode alpha_opcodes[] = { { "wmb", MFC(0x18,0x4400), BASE, ARG_NONE }, { "fetch", MFC(0x18,0x8000), BASE, { ZA, PRB } }, { "fetch_m", MFC(0x18,0xA000), BASE, { ZA, PRB } }, - { "rpcc", MFC(0x18,0xC000), BASE, { RA } }, + { "rpcc", MFC(0x18,0xC000), BASE, { RA, ZB } }, + { "rpcc", MFC(0x18,0xC000), BASE, { RA, RB } }, /* ev6 una */ { "rc", MFC(0x18,0xE000), BASE, { RA } }, { "ecb", MFC(0x18,0xE800), BASE, { ZA, PRB } }, /* ev56 una */ { "rs", MFC(0x18,0xF000), BASE, { RA } }, diff --git a/contrib/binutils/opcodes/arc-opc.c b/contrib/binutils/opcodes/arc-opc.c index b7afb86..614fff0 100644 --- a/contrib/binutils/opcodes/arc-opc.c +++ b/contrib/binutils/opcodes/arc-opc.c @@ -20,6 +20,7 @@ #include "sysdep.h" #include <stdio.h> #include "ansidecl.h" +#include "bfd.h" #include "opcode/arc.h" #define INSERT_FN(fn) \ @@ -65,6 +66,9 @@ enum operand {OP_NONE,OP_REG,OP_SHIMM,OP_LIMM}; enum operand ls_operand[OPERANDS]; +struct arc_opcode *arc_ext_opcodes; +struct arc_ext_operand_value *arc_ext_operands; + #define LS_VALUE 0 #define LS_DEST 0 #define LS_BASE 1 @@ -513,7 +517,7 @@ arc_get_opcode_mach (bfd_mach, big_p) ARC_MACH_7, ARC_MACH_8 }; - return mach_type_map[bfd_mach] | (big_p ? ARC_MACH_BIG : 0); + return mach_type_map[bfd_mach - bfd_mach_arc_5] | (big_p ? ARC_MACH_BIG : 0); } /* Initialize any tables that need it. diff --git a/contrib/binutils/opcodes/arm-dis.c b/contrib/binutils/opcodes/arm-dis.c index f3785f2..e918daf 100644 --- a/contrib/binutils/opcodes/arm-dis.c +++ b/contrib/binutils/opcodes/arm-dis.c @@ -1,24 +1,24 @@ /* Instruction printing code for the ARM - Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002 + Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. Contributed by Richard Earnshaw (rwe@pegasus.esprit.ec.org) Modification by James G. Smith (jsmith@cygnus.co.uk) -This file is part of libopcodes. + This file is part of libopcodes. -This program is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free -Software Foundation; either version 2 of the License, or (at your option) -any later version. + This program is free software; you can redistribute it and/or modify it under + the terms of the GNU General Public License as published by the Free + Software Foundation; either version 2 of the License, or (at your option) + any later version. -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -more details. + This program is distributed in the hope that it will be useful, but WITHOUT + ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "sysdep.h" #include "dis-asm.h" @@ -27,6 +27,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "coff/internal.h" #include "libcoff.h" #include "opintl.h" +#include "safe-ctype.h" /* FIXME: This shouldn't be done here. */ #include "elf-bfd.h" @@ -70,7 +71,21 @@ static arm_regname regnames[] = { "atpcs", "Select register names used in the ATPCS", { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "IP", "SP", "LR", "PC" }}, { "special-atpcs", "Select special register names used in the ATPCS", - { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }} + { "a1", "a2", "a3", "a4", "v1", "v2", "v3", "WR", "v5", "SB", "SL", "FP", "IP", "SP", "LR", "PC" }}, + { "iwmmxt_regnames", "Select register names used on the Intel Wireless MMX technology coprocessor", + { "wr0", "wr1", "wr2", "wr3", "wr4", "wr5", "wr6", "wr7", "wr8", "wr9", "wr10", "wr11", "wr12", "wr13", "wr14", "wr15"}}, + { "iwmmxt_Cregnames", "Select control register names used on the Intel Wireless MMX technology coprocessor", + {"wcid", "wcon", "wcssf", "wcasf", "reserved", "reserved", "reserved", "reserved", "wcgr0", "wcgr1", "wcgr2", "wcgr3", "reserved", "reserved", "reserved", "reserved"}} +}; + +static char * iwmmxt_wwnames[] = +{"b", "h", "w", "d"}; + +static char * iwmmxt_wwssnames[] = +{"b", "bus", "b", "bss", + "h", "hus", "h", "hss", + "w", "wus", "w", "wss", + "d", "dus", "d", "dss" }; /* Default to GCC register name set. */ @@ -79,25 +94,34 @@ static unsigned int regname_selected = 1; #define NUM_ARM_REGNAMES NUM_ELEM (regnames) #define arm_regnames regnames[regname_selected].reg_names -static boolean force_thumb = false; +static bfd_boolean force_thumb = FALSE; static char * arm_fp_const[] = {"0.0", "1.0", "2.0", "3.0", "4.0", "5.0", "0.5", "10.0"}; -static char * arm_shift[] = +static char * arm_shift[] = {"lsl", "lsr", "asr", "ror"}; /* Forward declarations. */ -static void arm_decode_shift PARAMS ((long, fprintf_ftype, void *)); -static int print_insn_arm PARAMS ((bfd_vma, struct disassemble_info *, long)); -static int print_insn_thumb PARAMS ((bfd_vma, struct disassemble_info *, long)); -static void parse_disassembler_options PARAMS ((char *)); -static int print_insn PARAMS ((bfd_vma, struct disassemble_info *, boolean)); -int get_arm_regname_num_options (void); -int set_arm_regname_option (int option); -int get_arm_regnames (int option, const char **setname, - const char **setdescription, - const char ***register_names); +static void arm_decode_shift + PARAMS ((long, fprintf_ftype, void *)); +static int print_insn_arm + PARAMS ((bfd_vma, struct disassemble_info *, long)); +static int print_insn_thumb + PARAMS ((bfd_vma, struct disassemble_info *, long)); +static void parse_disassembler_options + PARAMS ((char *)); +static int print_insn + PARAMS ((bfd_vma, struct disassemble_info *, bfd_boolean)); +static int set_iwmmxt_regnames + PARAMS ((void)); + +int get_arm_regname_num_options + PARAMS ((void)); +int set_arm_regname_option + PARAMS ((int)); +int get_arm_regnames + PARAMS ((int, const char **, const char **, const char ***)); /* Functions. */ int @@ -135,14 +159,14 @@ arm_decode_shift (given, func, stream) void * stream; { func (stream, "%s", arm_regnames[given & 0xf]); - + if ((given & 0xff0) != 0) { if ((given & 0x10) == 0) { int amount = (given & 0xf80) >> 7; int shift = (given & 0x60) >> 5; - + if (amount == 0) { if (shift == 3) @@ -150,10 +174,10 @@ arm_decode_shift (given, func, stream) func (stream, ", rrx"); return; } - + amount = 32; } - + func (stream, ", %s #%d", arm_shift[shift], amount); } else @@ -162,25 +186,49 @@ arm_decode_shift (given, func, stream) } } +static int +set_iwmmxt_regnames () +{ + const char * setname; + const char * setdesc; + const char ** regnames; + int iwmmxt_regnames = 0; + int num_regnames = get_arm_regname_num_options (); + + get_arm_regnames (iwmmxt_regnames, &setname, + &setdesc, ®names); + while ((strcmp ("iwmmxt_regnames", setname)) + && (iwmmxt_regnames < num_regnames)) + get_arm_regnames (++iwmmxt_regnames, &setname, &setdesc, ®names); + + return iwmmxt_regnames; +} + /* Print one instruction from PC on INFO->STREAM. Return the size of the instruction (always 4 on ARM). */ static int print_insn_arm (pc, info, given) - bfd_vma pc; - struct disassemble_info * info; - long given; + bfd_vma pc; + struct disassemble_info *info; + long given; { - struct arm_opcode * insn; - void * stream = info->stream; - fprintf_ftype func = info->fprintf_func; + const struct arm_opcode *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; + static int iwmmxt_regnames = 0; for (insn = arm_opcodes; insn->assembler; insn++) { + if (insn->value == FIRST_IWMMXT_INSN + && info->mach != bfd_mach_arm_XScale + && info->mach != bfd_mach_arm_iWMMXt) + insn = insn + IWMMXT_INSN_COUNT; + if ((given & insn->mask) == insn->value) { char * c; - + for (c = insn->assembler; *c; c++) { if (*c == '%') @@ -196,14 +244,14 @@ print_insn_arm (pc, info, given) && ((given & 0x02000000) == 0)) { int offset = given & 0xfff; - + func (stream, "[pc"); - + if (given & 0x01000000) { if ((given & 0x00800000) == 0) offset = - offset; - + /* Pre-indexed. */ func (stream, ", #%d]", offset); @@ -224,13 +272,13 @@ print_insn_arm (pc, info, given) /* ie ignore the offset. */ offset = pc + 8; } - + func (stream, "\t; "); info->print_address_func (offset, info); } else { - func (stream, "[%s", + func (stream, "[%s", arm_regnames[(given >> 16) & 0xf]); if ((given & 0x01000000) != 0) { @@ -238,7 +286,7 @@ print_insn_arm (pc, info, given) { int offset = given & 0xfff; if (offset) - func (stream, ", %s#%d", + func (stream, ", #%s%d", (((given & 0x00800000) == 0) ? "-" : ""), offset); } @@ -250,7 +298,7 @@ print_insn_arm (pc, info, given) arm_decode_shift (given, func, stream); } - func (stream, "]%s", + func (stream, "]%s", ((given & 0x00200000) != 0) ? "!" : ""); } else @@ -259,16 +307,16 @@ print_insn_arm (pc, info, given) { int offset = given & 0xfff; if (offset) - func (stream, "], %s#%d", + func (stream, "], #%s%d", (((given & 0x00800000) == 0) ? "-" : ""), offset); - else + else func (stream, "]"); } else { func (stream, "], %s", - (((given & 0x00800000) == 0) + (((given & 0x00800000) == 0) ? "-" : "")); arm_decode_shift (given, func, stream); } @@ -281,18 +329,18 @@ print_insn_arm (pc, info, given) { /* PC relative with immediate offset. */ int offset = ((given & 0xf00) >> 4) | (given & 0xf); - + if ((given & 0x00800000) == 0) offset = -offset; - + func (stream, "[pc, #%d]\t; ", offset); - + (*info->print_address_func) (offset + pc + 8, info); } else { - func (stream, "[%s", + func (stream, "[%s", arm_regnames[(given >> 16) & 0xf]); if ((given & 0x01000000) != 0) { @@ -302,7 +350,7 @@ print_insn_arm (pc, info, given) /* Immediate. */ int offset = ((given & 0xf00) >> 4) | (given & 0xf); if (offset) - func (stream, ", %s#%d", + func (stream, ", #%s%d", (((given & 0x00800000) == 0) ? "-" : ""), offset); } @@ -315,7 +363,7 @@ print_insn_arm (pc, info, given) arm_regnames[given & 0xf]); } - func (stream, "]%s", + func (stream, "]%s", ((given & 0x00200000) != 0) ? "!" : ""); } else @@ -326,10 +374,10 @@ print_insn_arm (pc, info, given) /* Immediate. */ int offset = ((given & 0xf00) >> 4) | (given & 0xf); if (offset) - func (stream, "], %s#%d", + func (stream, "], #%s%d", (((given & 0x00800000) == 0) ? "-" : ""), offset); - else + else func (stream, "]"); } else @@ -343,7 +391,7 @@ print_insn_arm (pc, info, given) } } break; - + case 'b': (*info->print_address_func) (BDISP (given) * 4 + pc + 8, info); @@ -397,11 +445,13 @@ print_insn_arm (pc, info, given) case 'A': func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); - if ((given & 0x01000000) != 0) + + if ((given & (1 << 24)) != 0) { int offset = given & 0xff; + if (offset) - func (stream, ", %s#%d]%s", + func (stream, ", #%s%d]%s", ((given & 0x00800000) == 0 ? "-" : ""), offset * 4, ((given & 0x00200000) != 0 ? "!" : "")); @@ -411,12 +461,18 @@ print_insn_arm (pc, info, given) else { int offset = given & 0xff; - if (offset) - func (stream, "], %s#%d", - ((given & 0x00800000) == 0 ? "-" : ""), - offset * 4); + + func (stream, "]"); + + if (given & (1 << 21)) + { + if (offset) + func (stream, ", #%s%d", + ((given & 0x00800000) == 0 ? "-" : ""), + offset * 4); + } else - func (stream, "]"); + func (stream, ", {%d}", offset); } break; @@ -425,7 +481,7 @@ print_insn_arm (pc, info, given) { bfd_vma address; bfd_vma offset = 0; - + if (given & 0x00800000) /* Is signed, hi bits should be ones. */ offset = (-1) ^ 0x00ffffff; @@ -434,7 +490,7 @@ print_insn_arm (pc, info, given) offset += given & 0x00ffffff; offset <<= 2; address = offset + pc + 8; - + if (given & 0x01000000) /* H bit allows addressing to 2-byte boundaries. */ address += 2; @@ -490,7 +546,7 @@ print_insn_arm (pc, info, given) func (stream, "3"); } break; - + case 'P': switch (given & 0x00080080) { @@ -542,7 +598,7 @@ print_insn_arm (pc, info, given) } break; - case '0': case '1': case '2': case '3': case '4': + case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { int bitstart = *c++ - '0'; @@ -554,44 +610,54 @@ print_insn_arm (pc, info, given) { case '-': c++; - + while (*c >= '0' && *c <= '9') bitend = (bitend * 10) + *c++ - '0'; - + if (!bitend) abort (); - + switch (*c) { case 'r': { long reg; - + reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - + func (stream, "%s", arm_regnames[reg]); } break; case 'd': { long reg; - + reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - + func (stream, "%d", reg); } break; - case 'x': + case 'W': { long reg; reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; + func (stream, "%d", reg + 1); + } + break; + case 'x': + { + long reg; + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + func (stream, "0x%08x", reg); - + /* Some SWI instructions have special meanings. */ if ((given & 0x0fffffff) == 0x0FF00000) @@ -603,20 +669,20 @@ print_insn_arm (pc, info, given) case 'X': { long reg; - + reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - + func (stream, "%01x", reg & 0xf); } break; case 'f': { long reg; - + reg = given >> bitstart; reg &= (2 << (bitend - bitstart)) - 1; - + if (reg > 7) func (stream, "#%s", arm_fp_const[reg & 7]); @@ -624,6 +690,63 @@ print_insn_arm (pc, info, given) func (stream, "f%d", reg); } break; + + case 'w': + { + long reg; + + if (bitstart != bitend) + { + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + if (bitend - bitstart == 1) + func (stream, "%s", iwmmxt_wwnames[reg]); + else + func (stream, "%s", iwmmxt_wwssnames[reg]); + } + else + { + reg = (((given >> 8) & 0x1) | + ((given >> 22) & 0x1)); + func (stream, "%s", iwmmxt_wwnames[reg]); + } + } + break; + + case 'g': + { + long reg; + int current_regnames; + + if (! iwmmxt_regnames) + iwmmxt_regnames = set_iwmmxt_regnames (); + current_regnames = set_arm_regname_option + (iwmmxt_regnames); + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + func (stream, "%s", arm_regnames[reg]); + set_arm_regname_option (current_regnames); + } + break; + + case 'G': + { + long reg; + int current_regnames; + + if (! iwmmxt_regnames) + iwmmxt_regnames = set_iwmmxt_regnames (); + current_regnames = set_arm_regname_option + (iwmmxt_regnames + 1); + + reg = given >> bitstart; + reg &= (2 << (bitend - bitstart)) - 1; + func (stream, "%s", arm_regnames[reg]); + set_arm_regname_option (current_regnames); + } + break; + default: abort (); } @@ -677,7 +800,7 @@ print_insn_arm (pc, info, given) } break; - + default: abort (); } @@ -729,6 +852,54 @@ print_insn_arm (pc, info, given) } break; + case 'L': + switch (given & 0x00400100) + { + case 0x00000000: func (stream, "b"); break; + case 0x00400000: func (stream, "h"); break; + case 0x00000100: func (stream, "w"); break; + case 0x00400100: func (stream, "d"); break; + default: + break; + } + break; + + case 'Z': + { + int value; + /* given (20, 23) | given (0, 3) */ + value = ((given >> 16) & 0xf0) | (given & 0xf); + func (stream, "%d", value); + } + break; + + case 'l': + /* This is like the 'A' operator, except that if + the width field "M" is zero, then the offset is + *not* multiplied by four. */ + { + int offset = given & 0xff; + int multiplier = (given & 0x00000100) ? 4 : 1; + + func (stream, "[%s", arm_regnames [(given >> 16) & 0xf]); + + if (offset) + { + if ((given & 0x01000000) != 0) + func (stream, ", #%s%d]%s", + ((given & 0x00800000) == 0 ? "-" : ""), + offset * multiplier, + ((given & 0x00200000) != 0 ? "!" : "")); + else + func (stream, "], #%s%d", + ((given & 0x00800000) == 0 ? "-" : ""), + offset * multiplier); + } + else + func (stream, "]"); + } + break; + default: abort (); } @@ -748,13 +919,13 @@ print_insn_arm (pc, info, given) static int print_insn_thumb (pc, info, given) - bfd_vma pc; - struct disassemble_info * info; - long given; + bfd_vma pc; + struct disassemble_info *info; + long given; { - struct thumb_opcode * insn; - void * stream = info->stream; - fprintf_ftype func = info->fprintf_func; + const struct thumb_opcode *insn; + void *stream = info->stream; + fprintf_ftype func = info->fprintf_func; for (insn = thumb_opcodes; insn->assembler; insn++) { @@ -766,7 +937,7 @@ print_insn_thumb (pc, info, given) if (!*c) /* Check for empty (not NULL) assembler string. */ { long offset; - + info->bytes_per_chunk = 4; info->bytes_per_line = 4; @@ -788,16 +959,16 @@ print_insn_thumb (pc, info, given) { info->bytes_per_chunk = 2; info->bytes_per_line = 4; - + given &= 0xffff; - + for (; *c; c++) { if (*c == '%') { int domaskpc = 0; int domasklr = 0; - + switch (*++c) { case '%': @@ -807,11 +978,11 @@ print_insn_thumb (pc, info, given) case 'S': { long reg; - + reg = (given >> 3) & 0x7; if (given & (1 << 6)) reg += 8; - + func (stream, "%s", arm_regnames[reg]); } break; @@ -819,11 +990,11 @@ print_insn_thumb (pc, info, given) case 'D': { long reg; - + reg = given & 0x7; if (given & (1 << 7)) reg += 8; - + func (stream, "%s", arm_regnames[reg]); } break; @@ -845,9 +1016,9 @@ print_insn_thumb (pc, info, given) { int started = 0; int reg; - + func (stream, "{"); - + /* It would be nice if we could spot ranges, and generate the rS-rE format: */ for (reg = 0; (reg < 8); reg++) @@ -879,12 +1050,12 @@ print_insn_thumb (pc, info, given) break; - case '0': case '1': case '2': case '3': case '4': + case '0': case '1': case '2': case '3': case '4': case '5': case '6': case '7': case '8': case '9': { int bitstart = *c++ - '0'; int bitend = 0; - + while (*c >= '0' && *c <= '9') bitstart = (bitstart * 10) + *c++ - '0'; @@ -893,7 +1064,7 @@ print_insn_thumb (pc, info, given) case '-': { long reg; - + c++; while (*c >= '0' && *c <= '9') bitend = (bitend * 10) + *c++ - '0'; @@ -984,6 +1155,23 @@ print_insn_thumb (pc, info, given) abort (); } +/* Disallow mapping symbols ($a, $b, $d, $t etc) from + being displayed in symbol relative addresses. */ + +bfd_boolean +arm_symbol_is_valid (asymbol * sym, + struct disassemble_info * info ATTRIBUTE_UNUSED) +{ + const char * name; + + if (sym == NULL) + return FALSE; + + name = bfd_asymbol_name (sym); + + return (name && *name != '$'); +} + /* Parse an individual disassembler option. */ void @@ -992,59 +1180,56 @@ parse_arm_disassembler_option (option) { if (option == NULL) return; - + if (strneq (option, "reg-names-", 10)) { int i; - + option += 10; for (i = NUM_ARM_REGNAMES; i--;) - if (streq (option, regnames[i].name)) + if (strneq (option, regnames[i].name, strlen (regnames[i].name))) { regname_selected = i; break; } - + if (i < 0) + /* XXX - should break 'option' at following delimiter. */ fprintf (stderr, _("Unrecognised register name set: %s\n"), option); } - else if (streq (option, "force-thumb")) + else if (strneq (option, "force-thumb", 11)) force_thumb = 1; - else if (streq (option, "no-force-thumb")) + else if (strneq (option, "no-force-thumb", 14)) force_thumb = 0; else + /* XXX - should break 'option' at following delimiter. */ fprintf (stderr, _("Unrecognised disassembler option: %s\n"), option); - + return; } -/* Parse the string of disassembler options, spliting it at whitespaces. */ +/* Parse the string of disassembler options, spliting it at whitespaces + or commas. (Whitespace separators supported for backwards compatibility). */ static void parse_disassembler_options (options) char * options; { - char * space; - if (options == NULL) return; - do + while (*options) { - space = strchr (options, ' '); - - if (space) - { - * space = '\0'; - parse_arm_disassembler_option (options); - * space = ' '; - options = space + 1; - } - else - parse_arm_disassembler_option (options); + parse_arm_disassembler_option (options); + + /* Skip forward to next seperator. */ + while ((*options) && (! ISSPACE (*options)) && (*options != ',')) + ++ options; + /* Skip forward past seperators. */ + while (ISSPACE (*options) || (*options == ',')) + ++ options; } - while (space); } /* NOTE: There are no checks in these routines that @@ -1054,7 +1239,7 @@ static int print_insn (pc, info, little) bfd_vma pc; struct disassemble_info * info; - boolean little; + bfd_boolean little; { unsigned char b[4]; long given; @@ -1064,19 +1249,19 @@ print_insn (pc, info, little) if (info->disassembler_options) { parse_disassembler_options (info->disassembler_options); - + /* To avoid repeated parsing of these options, we remove them here. */ info->disassembler_options = NULL; } - + is_thumb = force_thumb; - + if (!is_thumb && info->symbols != NULL) { if (bfd_asymbol_flavour (*info->symbols) == bfd_target_coff_flavour) { coff_symbol_type * cs; - + cs = coffsymbol (*info->symbols); is_thumb = ( cs->native->u.syment.n_sclass == C_THUMBEXT || cs->native->u.syment.n_sclass == C_THUMBSTAT @@ -1088,14 +1273,14 @@ print_insn (pc, info, little) { elf_symbol_type * es; unsigned int type; - + es = *(elf_symbol_type **)(info->symbols); type = ELF_ST_TYPE (es->internal_elf_sym.st_info); - + is_thumb = (type == STT_ARM_TFUNC) || (type == STT_ARM_16BIT); } } - + info->bytes_per_chunk = 4; info->display_endian = little ? BFD_ENDIAN_LITTLE : BFD_ENDIAN_BIG; @@ -1105,17 +1290,17 @@ print_insn (pc, info, little) if (status != 0 && is_thumb) { info->bytes_per_chunk = 2; - + status = info->read_memory_func (pc, (bfd_byte *) b, 2, info); b[3] = b[2] = 0; } - + if (status != 0) { info->memory_error_func (status, pc, info); return -1; } - + given = (b[0]) | (b[1] << 8) | (b[2] << 16) | (b[3] << 24); } else @@ -1127,13 +1312,13 @@ print_insn (pc, info, little) info->memory_error_func (status, pc, info); return -1; } - + if (is_thumb) { if (pc & 0x2) { given = (b[2] << 8) | b[3]; - + status = info->read_memory_func ((pc + 4) & ~ 0x3, (bfd_byte *) b, 4, info); if (status != 0) @@ -1141,7 +1326,7 @@ print_insn (pc, info, little) info->memory_error_func (status, pc + 4, info); return -1; } - + given |= (b[0] << 24) | (b[1] << 16); } else @@ -1150,7 +1335,7 @@ print_insn (pc, info, little) else given = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | (b[3]); } - + if (info->flags & INSN_HAS_RELOC) /* If the instruction has a reloc associated with it, then the offset field in the instruction will actually be the @@ -1158,7 +1343,7 @@ print_insn (pc, info, little) In such cases, we can ignore the pc when computing addresses, since the addend is not currently pc-relative. */ pc = 0; - + if (is_thumb) status = print_insn_thumb (pc, info, given); else @@ -1172,7 +1357,7 @@ print_insn_big_arm (pc, info) bfd_vma pc; struct disassemble_info * info; { - return print_insn (pc, info, false); + return print_insn (pc, info, FALSE); } int @@ -1180,7 +1365,7 @@ print_insn_little_arm (pc, info) bfd_vma pc; struct disassemble_info * info; { - return print_insn (pc, info, true); + return print_insn (pc, info, TRUE); } void @@ -1191,7 +1376,7 @@ print_arm_disassembler_options (FILE * stream) fprintf (stream, _("\n\ The following ARM specific disassembler options are supported for use with\n\ the -M switch:\n")); - + for (i = NUM_ARM_REGNAMES; i--;) fprintf (stream, " reg-names-%s %*c%s\n", regnames[i].name, diff --git a/contrib/binutils/opcodes/arm-opc.h b/contrib/binutils/opcodes/arm-opc.h index 85f611d..574bc1f 100644 --- a/contrib/binutils/opcodes/arm-opc.h +++ b/contrib/binutils/opcodes/arm-opc.h @@ -1,6 +1,6 @@ /* Opcode table for the ARM. - Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000 + Copyright 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2003 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -35,6 +35,7 @@ struct thumb_opcode %<bitfield>d print the bitfield in decimal %<bitfield>x print the bitfield in hex %<bitfield>X print the bitfield as 1 hex digit without leading "0x" + %<bitfield>w print the bitfield plus one in decimal %<bitfield>r print as an ARM register %<bitfield>f print a floating point constant if >7 else a floating point register @@ -60,6 +61,13 @@ struct thumb_opcode %m print register mask for ldm/stm instruction %C print the PSR sub type. %F print the COUNT field of a LFM/SFM instruction. +IWMMXT specific format options: + %<bitfield>g print as an iWMMXt 64-bit register + %<bitfield>G print as an iWMMXt general purpose or control register + %<bitfield>w print as an iWMMXt width field - [bhwd]ss/us + %Z print the Immediate of a WSHUFH instruction. + %L print as an iWMMXt N/M width field. + %l like 'A' except use byte offsets for 'B' & 'H' versions Thumb specific format options: %D print Thumb register (bits 0..2 as high number if bit 7 set) %S print Thumb register (bits 3..5 as high number if bit 6 set) @@ -79,7 +87,7 @@ Thumb specific format options: /* Note: There is a partial ordering in this table - it must be searched from the top to obtain a correct match. */ -static struct arm_opcode arm_opcodes[] = +static const struct arm_opcode arm_opcodes[] = { /* ARM instructions. */ {0xe1a00000, 0xffffffff, "nop\t\t\t(mov r0,r0)"}, @@ -90,6 +98,132 @@ static struct arm_opcode arm_opcodes[] = {0x00800090, 0x0fa000f0, "%22?sumull%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, {0x00a00090, 0x0fa000f0, "%22?sumlal%c%20's\t%12-15r, %16-19r, %0-3r, %8-11r"}, + /* ARM V6 instructions. */ + {0xfc500000, 0xfff00000, "mrrc2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + {0xfc400000, 0xfff00000, "mcrr2\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + {0xf1080000, 0xfffdfe3f, "cpsie\t%8'a%7'i%6'f"}, + {0xf1080000, 0xfffdfe20, "cpsie\t%8'a%7'i%6'f,#%0-4d"}, + {0xf10C0000, 0xfffdfe3f, "cpsid\t%8'a%7'i%6'f"}, + {0xf10C0000, 0xfffdfe20, "cpsid\t%8'a%7'i%6'f,#%0-4d"}, + {0xf1000000, 0xfff1fe20, "cps\t#%0-4d"}, + {0x06800010, 0x0ff00ff0, "pkhbt%c\t%12-15r, %16-19r, %0-3r"}, + {0x06800010, 0x0ff00070, "pkhbt%c\t%12-15r, %16-19r, %0-3r, LSL #%7-11d"}, + {0x06800050, 0x0ff00ff0, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #32"}, + {0x06800050, 0x0ff00070, "pkhtb%c\t%12-15r, %16-19r, %0-3r, ASR #%7-11d"}, + {0x01900f9f, 0x0ff00fff, "ldrex%c\tr%12-15d, [%16-19r]"}, + {0x06200f10, 0x0ff00ff0, "qadd16%c\t%12-15r, %16-19r, %0-3r"}, + {0x06200f90, 0x0ff00ff0, "qadd8%c\t%12-15r, %16-19r, %0-3r"}, + {0x06200f30, 0x0ff00ff0, "qaddsubx%c\t%12-15r, %16-19r, %0-3r"}, + {0x06200f70, 0x0ff00ff0, "qsub16%c\t%12-15r, %16-19r, %0-3r"}, + {0x06200ff0, 0x0ff00ff0, "qsub8%c\t%12-15r, %16-19r, %0-3r"}, + {0x06200f50, 0x0ff00ff0, "qsubaddx%c\t%12-15r, %16-19r, %0-3r"}, + {0x06100f10, 0x0ff00ff0, "sadd16%c\t%12-15r, %16-19r, %0-3r"}, + {0x06100f90, 0x0ff00ff0, "sadd8%c\t%12-15r, %16-19r, %0-3r"}, + {0x06100f30, 0x0ff00ff0, "saddaddx%c\t%12-15r, %16-19r, %0-3r"}, + {0x06300f10, 0x0ff00ff0, "shadd16%c\t%12-15r, %16-19r, %0-3r"}, + {0x06300f90, 0x0ff00ff0, "shadd8%c\t%12-15r, %16-19r, %0-3r"}, + {0x06300f30, 0x0ff00ff0, "shaddsubx%c\t%12-15r, %16-19r, %0-3r"}, + {0x06300f70, 0x0ff00ff0, "shsub16%c\t%12-15r, %16-19r, %0-3r"}, + {0x06300ff0, 0x0ff00ff0, "shsub8%c\t%12-15r, %16-19r, %0-3r"}, + {0x06300f50, 0x0ff00ff0, "shsubaddx%c\t%12-15r, %16-19r, %0-3r"}, + {0x06100f70, 0x0ff00ff0, "ssub16%c\t%12-15r, %16-19r, %0-3r"}, + {0x06100ff0, 0x0ff00ff0, "ssub8%c\t%12-15r, %16-19r, %0-3r"}, + {0x06100f50, 0x0ff00ff0, "ssubaddx%c\t%12-15r, %16-19r, %0-3r"}, + {0x06500f10, 0x0ff00ff0, "uadd16%c\t%12-15r, %16-19r, %0-3r"}, + {0x06500f90, 0x0ff00ff0, "uadd8%c\t%12-15r, %16-19r, %0-3r"}, + {0x06500f30, 0x0ff00ff0, "uaddsubx%c\t%12-15r, %16-19r, %0-3r"}, + {0x06700f10, 0x0ff00ff0, "uhadd16%c\t%12-15r, %16-19r, %0-3r"}, + {0x06700f90, 0x0ff00ff0, "uhadd8%c\t%12-15r, %16-19r, %0-3r"}, + {0x06700f30, 0x0ff00ff0, "uhaddsubx%c\t%12-15r, %16-19r, %0-3r"}, + {0x06700f70, 0x0ff00ff0, "uhsub16%c\t%12-15r, %16-19r, %0-3r"}, + {0x06700ff0, 0x0ff00ff0, "uhsub8%c\t%12-15r, %16-19r, %0-3r"}, + {0x06700f50, 0x0ff00ff0, "uhsubaddx%c\t%12-15r, %16-19r, %0-3r"}, + {0x06600f10, 0x0ff00ff0, "uqadd16%c\t%12-15r, %16-19r, %0-3r"}, + {0x06600f90, 0x0ff00ff0, "uqadd8%c\t%12-15r, %16-19r, %0-3r"}, + {0x06600f30, 0x0ff00ff0, "uqaddsubx%c\t%12-15r, %16-19r, %0-3r"}, + {0x06600f70, 0x0ff00ff0, "uqsub16%c\t%12-15r, %16-19r, %0-3r"}, + {0x06600ff0, 0x0ff00ff0, "uqsub8%c\t%12-15r, %16-19r, %0-3r"}, + {0x06600f50, 0x0ff00ff0, "uqsubaddx%c\t%12-15r, %16-19r, %0-3r"}, + {0x06500f70, 0x0ff00ff0, "usub16%c\t%12-15r, %16-19r, %0-3r"}, + {0x06500ff0, 0x0ff00ff0, "usub8%c\t%12-15r, %16-19r, %0-3r"}, + {0x06500f50, 0x0ff00ff0, "usubaddx%c\t%12-15r, %16-19r, %0-3r"}, + {0x06bf0f30, 0x0fff0ff0, "rev%c\t\%12-15r, %0-3r"}, + {0x06bf0fb0, 0x0fff0ff0, "rev16%c\t\%12-15r, %0-3r"}, + {0x06ff0fb0, 0x0fff0ff0, "revsh%c\t\%12-15r, %0-3r"}, + {0xf8100a00, 0xfe50ffff, "rfe%23?id%24?ba\t\%16-19r%21'!"}, + {0x06bf0070, 0x0fff0ff0, "sxth%c %12-15r,%0-3r"}, + {0x06bf0470, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #8"}, + {0x06bf0870, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #16"}, + {0x06bf0c70, 0x0fff0ff0, "sxth%c %12-15r,%0-3r, ROR #24"}, + {0x068f0070, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r"}, + {0x068f0470, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #8"}, + {0x068f0870, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #16"}, + {0x068f0c70, 0x0fff0ff0, "sxtb16%c %12-15r,%0-3r, ROR #24"}, + {0x06af0070, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r"}, + {0x06af0470, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #8"}, + {0x06af0870, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #16"}, + {0x06af0c70, 0x0fff0ff0, "sxtb%c %12-15r,%0-3r, ROR #24"}, + {0x06ff0070, 0x0fff0ff0, "uxth%c %12-15r,%0-3r"}, + {0x06ff0470, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #8"}, + {0x06ff0870, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #16"}, + {0x06ff0c70, 0x0fff0ff0, "uxth%c %12-15r,%0-3r, ROR #24"}, + {0x06cf0070, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r"}, + {0x06cf0470, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #8"}, + {0x06cf0870, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #16"}, + {0x06cf0c70, 0x0fff0ff0, "uxtb16%c %12-15r,%0-3r, ROR #24"}, + {0x06ef0070, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r"}, + {0x06ef0470, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #8"}, + {0x06ef0870, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #16"}, + {0x06ef0c70, 0x0fff0ff0, "uxtb%c %12-15r,%0-3r, ROR #24"}, + {0x06b00070, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r"}, + {0x06b00470, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, + {0x06b00870, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, + {0x06b00c70, 0x0ff00ff0, "sxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {0x06800070, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r"}, + {0x06800470, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, + {0x06800870, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, + {0x06800c70, 0x0ff00ff0, "sxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {0x06a00070, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r"}, + {0x06a00470, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, + {0x06a00870, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, + {0x06a00c70, 0x0ff00ff0, "sxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {0x06f00070, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r"}, + {0x06f00470, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, + {0x06f00870, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, + {0x06f00c70, 0x0ff00ff0, "uxtah%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {0x06c00070, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r"}, + {0x06c00470, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, + {0x06c00870, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, + {0x06c00c70, 0x0ff00ff0, "uxtab16%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {0x06e00070, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r"}, + {0x06e00470, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #8"}, + {0x06e00870, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #16"}, + {0x06e00c70, 0x0ff00ff0, "uxtab%c\t%12-15r, %16-19r, %0-3r, ROR #24"}, + {0x068000b0, 0x0ff00ff0, "sel%c\t%12-15r, %16-19r, %0-3r"}, + {0xf1010000, 0xfffffc00, "setend\t%9?ble"}, + {0x0700f010, 0x0ff0f0d0, "smuad%5'x%c\t%16-19r, %0-3r, %8-11r"}, + {0x0700f050, 0x0ff0f0d0, "smusd%5'x%c\t%16-19r, %0-3r, %8-11r"}, + {0x07000010, 0x0ff000d0, "smlad%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0x07400010, 0x0ff000d0, "smlald%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {0x07000050, 0x0ff000d0, "smlsd%5'x%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0x07400050, 0x0ff000d0, "smlsld%5'x%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {0x0750f010, 0x0ff0f0d0, "smmul%5'r%c\t%16-19r, %0-3r, %8-11r"}, + {0x07500010, 0x0ff000d0, "smmla%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0x075000d0, 0x0ff000d0, "smmls%5'r%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0xf84d0500, 0xfe5fffe0, "srs%23?id%24?ba\t#%0-4d%21'!"}, + {0x06a00010, 0x0fe00ff0, "ssat%c\t%12-15r, #%16-20W, %0-3r"}, + {0x06a00010, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, LSL #%7-11d"}, + {0x06a00050, 0x0fe00070, "ssat%c\t%12-15r, #%16-20W, %0-3r, ASR #%7-11d"}, + {0x06a00f30, 0x0ff00ff0, "ssat16%c\t%12-15r, #%16-19W, %0-3r"}, + {0x01800f90, 0x0ff00ff0, "strex%c\t%12-15r, %0-3r, [%16-19r]"}, + {0x00400090, 0x0ff000f0, "umaal%c\t%12-15r, %16-19r, %0-3r, %8-11r"}, + {0x0780f010, 0x0ff0f0f0, "usad8%c\t%16-19r, %0-3r, %8-11r"}, + {0x07800010, 0x0ff000f0, "usada8%c\t%16-19r, %0-3r, %8-11r, %12-15r"}, + {0x06e00010, 0x0fe00ff0, "usat%c\t%12-15r, #%16-20d, %0-3r"}, + {0x06e00010, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, LSL #%7-11d"}, + {0x06e00050, 0x0fe00070, "usat%c\t%12-15r, #%16-20d, %0-3r, ASR #%7-11d"}, + {0x06e00f30, 0x0ff00ff0, "usat16%c\t%12-15r, #%16-19d, %0-3r"}, + /* V5J instruction. */ {0x012fff20, 0x0ffffff0, "bxj%c\t%0-3r"}, @@ -101,6 +235,59 @@ static struct arm_opcode arm_opcodes[] = {0x0c500000, 0x0ff00fff, "mra%c\t%12-15r, %16-19r, acc0"}, {0xf450f000, 0xfc70f000, "pld\t%a"}, + /* Intel Wireless MMX technology instructions. */ +#define FIRST_IWMMXT_INSN 0x0e130130 +#define IWMMXT_INSN_COUNT 47 + {0x0e130130, 0x0f3f0fff, "tandc%22-23w%c\t%12-15r"}, + {0x0e400010, 0x0ff00f3f, "tbcst%6-7w%c\t%16-19g, %12-15r"}, + {0x0e130170, 0x0f3f0ff8, "textrc%22-23w%c\t%12-15r, #%0-2d"}, + {0x0e100070, 0x0f300ff0, "textrm%3?su%22-23w%c\t%12-15r, %16-19g, #%0-2d"}, + {0x0e600010, 0x0ff00f38, "tinsr%6-7w%c\t%16-19g, %12-15r, #%0-2d"}, + {0x0e000110, 0x0ff00fff, "tmcr%c\t%16-19G, %12-15r"}, + {0x0c400000, 0x0ff00ff0, "tmcrr%c\t%0-3g, %12-15r, %16-19r"}, + {0x0e2c0010, 0x0ffc0e10, "tmia%17?tb%16?tb%c\t%5-8g, %0-3r, %12-15r"}, + {0x0e200010, 0x0fff0e10, "tmia%c\t%5-8g, %0-3r, %12-15r"}, + {0x0e280010, 0x0fff0e10, "tmiaph%c\t%5-8g, %0-3r, %12-15r"}, + {0x0e100030, 0x0f300fff, "tmovmsk%22-23w%c\t%12-15r, %16-19g"}, + {0x0e100110, 0x0ff00ff0, "tmrc%c\t%12-15r, %16-19G"}, + {0x0c500000, 0x0ff00ff0, "tmrrc%c\t%12-15r, %16-19r, %0-3g"}, + {0x0e130150, 0x0f3f0fff, "torc%22-23w%c\t%12-15r"}, + {0x0e0001c0, 0x0f300fff, "wacc%22-23w%c\t%12-15g, %16-19g"}, + {0x0e000180, 0x0f000ff0, "wadd%20-23w%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e000020, 0x0f800ff0, "waligni%c\t%12-15g, %16-19g, %0-3g, #%20-22d"}, + {0x0e800020, 0x0fc00ff0, "walignr%20-21d%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e200000, 0x0fe00ff0, "wand%20'n%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e800000, 0x0fa00ff0, "wavg2%22?hb%20'r%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e000060, 0x0f300ff0, "wcmpeq%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e100060, 0x0f100ff0, "wcmpgt%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {0xfc100100, 0xfe500f00, "wldrw\t%12-15G, %A"}, + {0x0c100000, 0x0e100e00, "wldr%L%c\t%12-15g, %l"}, + {0x0e400100, 0x0fc00ff0, "wmac%21?su%20'z%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e800100, 0x0fd00ff0, "wmadd%21?su%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e000160, 0x0f100ff0, "wmax%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e100160, 0x0f100ff0, "wmin%21?su%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e000100, 0x0fc00ff0, "wmul%21?su%20?ml%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e000000, 0x0ff00ff0, "wor%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e000080, 0x0f000ff0, "wpack%20-23w%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e300040, 0x0f300ff0, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e300148, 0x0f300ffc, "wror%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {0x0e000120, 0x0fa00ff0, "wsad%22?hb%20'z%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e0001e0, 0x0f000ff0, "wshufh%c\t%12-15g, %16-19g, #%Z"}, + {0x0e100040, 0x0f300ff0, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e100148, 0x0f300ffc, "wsll%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {0x0e000040, 0x0f300ff0, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e000148, 0x0f300ffc, "wsra%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {0x0e200040, 0x0f300ff0, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e200148, 0x0f300ffc, "wsrl%22-23w%8'g%c\t%12-15g, %16-19g, %0-3G"}, + {0xfc000100, 0xfe500f00, "wstrw\t%12-15G, %A"}, + {0x0c000000, 0x0e100e00, "wstr%L%c\t%12-15g, %l"}, + {0x0e0001a0, 0x0f000ff0, "wsub%20-23w%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e0000c0, 0x0f100fff, "wunpckeh%21?su%22-23w%c\t%12-15g, %16-19g"}, + {0x0e0000e0, 0x0f100fff, "wunpckel%21?su%22-23w%c\t%12-15g, %16-19g"}, + {0x0e1000c0, 0x0f300ff0, "wunpckih%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e1000e0, 0x0f300ff0, "wunpckil%22-23w%c\t%12-15g, %16-19g, %0-3g"}, + {0x0e100000, 0x0ff00ff0, "wxor%c\t%12-15g, %16-19g, %0-3g"}, + /* V5 Instructions. */ {0xe1200070, 0xfff000f0, "bkpt\t0x%16-19X%12-15X%8-11X%0-3X"}, {0xfa000000, 0xfe000000, "blx\t%B"}, @@ -141,9 +328,6 @@ static struct arm_opcode arm_opcodes[] = {0x01200050, 0x0ff00ff0, "qsub%c\t%12-15r, %0-3r, %16-19r"}, {0x01600050, 0x0ff00ff0, "qdsub%c\t%12-15r, %0-3r, %16-19r"}, - {0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, - {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, - /* ARM Instructions. */ {0x00000090, 0x0e100090, "str%c%6's%5?hb\t%12-15r, %s"}, {0x00100090, 0x0e100090, "ldr%c%6's%5?hb\t%12-15r, %s"}, @@ -322,18 +506,18 @@ static struct arm_opcode arm_opcodes[] = {0x0e100510, 0x0ff00fff, "cfmvr64l%c\t%12-15r, mvdx%16-19d"}, {0x0e000530, 0x0ff00fff, "cfmv64hr%c\tmvdx%16-19d, %12-15r"}, {0x0e100530, 0x0ff00fff, "cfmvr64h%c\t%12-15r, mvdx%16-19d"}, - {0x0e100610, 0x0ff0fff0, "cfmval32%c\tmvax%0-3d, mvfx%16-19d"}, - {0x0e000610, 0x0ff0fff0, "cfmv32al%c\tmvfx%0-3d, mvax%16-19d"}, - {0x0e100630, 0x0ff0fff0, "cfmvam32%c\tmvax%0-3d, mvfx%16-19d"}, - {0x0e000630, 0x0ff0fff0, "cfmv32am%c\tmvfx%0-3d, mvax%16-19d"}, - {0x0e100650, 0x0ff0fff0, "cfmvah32%c\tmvax%0-3d, mvfx%16-19d"}, - {0x0e000650, 0x0ff0fff0, "cfmv32ah%c\tmvfx%0-3d, mvax%16-19d"}, - {0x0e000670, 0x0ff0fff0, "cfmv32a%c\tmvfx%0-3d, mvax%16-19d"}, - {0x0e100670, 0x0ff0fff0, "cfmva32%c\tmvax%0-3d, mvfx%16-19d"}, - {0x0e000690, 0x0ff0fff0, "cfmv64a%c\tmvdx%0-3d, mvax%16-19d"}, - {0x0e100690, 0x0ff0fff0, "cfmva64%c\tmvax%0-3d, mvdx%16-19d"}, - {0x0e1006b0, 0x0ff0fff0, "cfmvsc32%c\tdspsc, mvfx%16-19d"}, - {0x0e0006b0, 0x0ff0fff0, "cfmv32sc%c\tmvfx%0-3d, dspsc"}, + {0x0e200440, 0x0ff00fff, "cfmval32%c\tmvax%12-15d, mvfx%16-19d"}, + {0x0e100440, 0x0ff00fff, "cfmv32al%c\tmvfx%12-15d, mvax%16-19d"}, + {0x0e200460, 0x0ff00fff, "cfmvam32%c\tmvax%12-15d, mvfx%16-19d"}, + {0x0e100460, 0x0ff00fff, "cfmv32am%c\tmvfx%12-15d, mvax%16-19d"}, + {0x0e200480, 0x0ff00fff, "cfmvah32%c\tmvax%12-15d, mvfx%16-19d"}, + {0x0e100480, 0x0ff00fff, "cfmv32ah%c\tmvfx%12-15d, mvax%16-19d"}, + {0x0e2004a0, 0x0ff00fff, "cfmva32%c\tmvax%12-15d, mvfx%16-19d"}, + {0x0e1004a0, 0x0ff00fff, "cfmv32a%c\tmvfx%12-15d, mvax%16-19d"}, + {0x0e2004c0, 0x0ff00fff, "cfmva64%c\tmvax%12-15d, mvdx%16-19d"}, + {0x0e1004c0, 0x0ff00fff, "cfmv64a%c\tmvdx%12-15d, mvax%16-19d"}, + {0x0e2004e0, 0x0fff0fff, "cfmvsc32%c\tdspsc, mvdx%12-15d"}, + {0x0e1004e0, 0x0fff0fff, "cfmv32sc%c\tmvdx%12-15d, dspsc"}, {0x0e000400, 0x0ff00fff, "cfcpys%c\tmvf%12-15d, mvf%16-19d"}, {0x0e000420, 0x0ff00fff, "cfcpyd%c\tmvd%12-15d, mvd%16-19d"}, {0x0e000460, 0x0ff00fff, "cfcvtsd%c\tmvd%12-15d, mvf%16-19d"}, @@ -382,6 +566,8 @@ static struct arm_opcode arm_opcodes[] = {0x0e300600, 0x0ff00f00, "cfmsuba32%c\tmvax%5-7d, mvax%12-15d, mvfx%16-19d, mvfx%0-3d"}, /* Generic coprocessor instructions */ + {0x0c400000, 0x0ff00000, "mcrr%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, + {0x0c500000, 0x0ff00000, "mrrc%c\t%8-11d, %4-7d, %12-15r, %16-19r, cr%0-3d"}, {0x0e000000, 0x0f000010, "cdp%c\t%8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}"}, {0x0e100010, 0x0f100010, "mrc%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, {0x0e000010, 0x0f100010, "mcr%c\t%8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}"}, @@ -395,10 +581,23 @@ static struct arm_opcode arm_opcodes[] = #define BDISP(x) ((((x) & 0xffffff) ^ 0x800000) - 0x800000) /* 26 bit */ -static struct thumb_opcode thumb_opcodes[] = +static const struct thumb_opcode thumb_opcodes[] = { /* Thumb instructions. */ + /* ARM V6. */ + {0xb660, 0xfff8, "cpsie\t%2'a%1'i%0'f"}, + {0xb670, 0xfff8, "cpsid\t%2'a%1'i%0'f"}, + {0x4600, 0xffc0, "cpy\t%0-2r, %3-5r"}, + {0xba00, 0xffc0, "rev\t%0-2r, %3-5r"}, + {0xba40, 0xffc0, "rev16\t%0-2r, %3-5r"}, + {0xbac0, 0xffc0, "revsh\t%0-2r, %3-5r"}, + {0xb650, 0xfff7, "setend\t%3?ble\t"}, + {0xb200, 0xffc0, "sxth\t%0-2r, %3-5r"}, + {0xb240, 0xffc0, "sxtb\t%0-2r, %3-5r"}, + {0xb280, 0xffc0, "uxth\t%0-2r, %3-5r"}, + {0xb2c0, 0xffc0, "uxtb\t%0-2r, %3-5r"}, + /* ARM V5 ISA extends Thumb. */ {0xbe00, 0xff00, "bkpt\t%0-7x"}, {0x4780, 0xff87, "blx\t%3-6r"}, /* note: 4 bit register number. */ diff --git a/contrib/binutils/opcodes/cgen-asm.c b/contrib/binutils/opcodes/cgen-asm.c index 05b62bf..7231e2d 100644 --- a/contrib/binutils/opcodes/cgen-asm.c +++ b/contrib/binutils/opcodes/cgen-asm.c @@ -28,16 +28,14 @@ #include "opcode/cgen.h" #include "opintl.h" -static CGEN_INSN_LIST * hash_insn_array PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); -static CGEN_INSN_LIST * hash_insn_list PARAMS ((CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); -static void build_asm_hash_table PARAMS ((CGEN_CPU_DESC)); +static CGEN_INSN_LIST * hash_insn_array (CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *); +static CGEN_INSN_LIST * hash_insn_list (CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *); +static void build_asm_hash_table (CGEN_CPU_DESC); /* Set the cgen_parse_operand_fn callback. */ void -cgen_set_parse_operand_fn (cd, fn) - CGEN_CPU_DESC cd; - cgen_parse_operand_fn fn; +cgen_set_parse_operand_fn (CGEN_CPU_DESC cd, cgen_parse_operand_fn fn) { cd->parse_operand_fn = fn; } @@ -45,8 +43,7 @@ cgen_set_parse_operand_fn (cd, fn) /* Called whenever starting to parse an insn. */ void -cgen_init_parse_operand (cd) - CGEN_CPU_DESC cd; +cgen_init_parse_operand (CGEN_CPU_DESC cd) { /* This tells the callback to re-initialize. */ (void) (* cd->parse_operand_fn) @@ -66,13 +63,12 @@ cgen_init_parse_operand (cd) list and we want earlier ones to be prefered. */ static CGEN_INSN_LIST * -hash_insn_array (cd, insns, count, entsize, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN *insns; - int count; - int entsize ATTRIBUTE_UNUSED; - CGEN_INSN_LIST **htable; - CGEN_INSN_LIST *hentbuf; +hash_insn_array (CGEN_CPU_DESC cd, + const CGEN_INSN *insns, + int count, + int entsize ATTRIBUTE_UNUSED, + CGEN_INSN_LIST **htable, + CGEN_INSN_LIST *hentbuf) { int i; @@ -97,11 +93,10 @@ hash_insn_array (cd, insns, count, entsize, htable, hentbuf) in a list. */ static CGEN_INSN_LIST * -hash_insn_list (cd, insns, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN_LIST *insns; - CGEN_INSN_LIST **htable; - CGEN_INSN_LIST *hentbuf; +hash_insn_list (CGEN_CPU_DESC cd, + const CGEN_INSN_LIST *insns, + CGEN_INSN_LIST **htable, + CGEN_INSN_LIST *hentbuf) { const CGEN_INSN_LIST *ilist; @@ -123,8 +118,7 @@ hash_insn_list (cd, insns, htable, hentbuf) /* Build the assembler instruction hash table. */ static void -build_asm_hash_table (cd) - CGEN_CPU_DESC cd; +build_asm_hash_table (CGEN_CPU_DESC cd) { int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd); CGEN_INSN_TABLE *insn_table = &cd->insn_table; @@ -179,9 +173,7 @@ build_asm_hash_table (cd) /* Return the first entry in the hash list for INSN. */ CGEN_INSN_LIST * -cgen_asm_lookup_insn (cd, insn) - CGEN_CPU_DESC cd; - const char *insn; +cgen_asm_lookup_insn (CGEN_CPU_DESC cd, const char *insn) { unsigned int hash; @@ -201,11 +193,10 @@ cgen_asm_lookup_insn (cd, insn) recording something in the keyword table]. */ const char * -cgen_parse_keyword (cd, strp, keyword_table, valuep) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - const char **strp; - CGEN_KEYWORD *keyword_table; - long *valuep; +cgen_parse_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + const char **strp, + CGEN_KEYWORD *keyword_table, + long *valuep) { const CGEN_KEYWORD_ENTRY *ke; char buf[256]; @@ -225,7 +216,9 @@ cgen_parse_keyword (cd, strp, keyword_table, valuep) /* Allow letters, digits, and any special characters. */ while (((p - start) < (int) sizeof (buf)) && *p - && (ISALNUM (*p) || strchr (keyword_table->nonalpha_chars, *p))) + && (ISALNUM (*p) + || *p == '_' + || strchr (keyword_table->nonalpha_chars, *p))) ++p; if (p - start >= (int) sizeof (buf)) @@ -260,11 +253,10 @@ cgen_parse_keyword (cd, strp, keyword_table, valuep) cgen_parse_address. */ const char * -cgen_parse_signed_integer (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - long *valuep; +cgen_parse_signed_integer (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + long *valuep) { bfd_vma value; enum cgen_parse_operand_result result; @@ -285,11 +277,10 @@ cgen_parse_signed_integer (cd, strp, opindex, valuep) cgen_parse_address. */ const char * -cgen_parse_unsigned_integer (cd, strp, opindex, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - unsigned long *valuep; +cgen_parse_unsigned_integer (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + unsigned long *valuep) { bfd_vma value; enum cgen_parse_operand_result result; @@ -307,13 +298,12 @@ cgen_parse_unsigned_integer (cd, strp, opindex, valuep) /* Address parser. */ const char * -cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep) - CGEN_CPU_DESC cd; - const char **strp; - int opindex; - int opinfo; - enum cgen_parse_operand_result *resultp; - bfd_vma *valuep; +cgen_parse_address (CGEN_CPU_DESC cd, + const char **strp, + int opindex, + int opinfo, + enum cgen_parse_operand_result *resultp, + bfd_vma *valuep) { bfd_vma value; enum cgen_parse_operand_result result_type; @@ -335,8 +325,7 @@ cgen_parse_address (cd, strp, opindex, opinfo, resultp, valuep) /* Signed integer validation routine. */ const char * -cgen_validate_signed_integer (value, min, max) - long value, min, max; +cgen_validate_signed_integer (long value, long min, long max) { if (value < min || value > max) { @@ -356,8 +345,9 @@ cgen_validate_signed_integer (value, min, max) cases where min != 0 (and max > LONG_MAX). */ const char * -cgen_validate_unsigned_integer (value, min, max) - unsigned long value, min, max; +cgen_validate_unsigned_integer (unsigned long value, + unsigned long min, + unsigned long max) { if (value < min || value > max) { diff --git a/contrib/binutils/opcodes/cgen-asm.in b/contrib/binutils/opcodes/cgen-asm.in index 525177c..420f640 100644 --- a/contrib/binutils/opcodes/cgen-asm.in +++ b/contrib/binutils/opcodes/cgen-asm.in @@ -43,7 +43,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define max(a,b) ((a) > (b) ? (a) : (b)) static const char * parse_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *)); + (CGEN_CPU_DESC, const CGEN_INSN *, const char **, CGEN_FIELDS *); /* -- assembler routines inserted here. */ @@ -60,8 +60,7 @@ static const char * parse_insn_normal Returns NULL for success, an error message for failure. */ char * -@arch@_cgen_build_insn_regex (insn) - CGEN_INSN *insn; +@arch@_cgen_build_insn_regex (CGEN_INSN *insn) { CGEN_OPCODE *opc = (CGEN_OPCODE *) CGEN_INSN_OPCODE (insn); const char *mnem = CGEN_INSN_MNEMONIC (insn); @@ -184,11 +183,10 @@ char * Returns NULL for success, an error message for failure. */ static const char * -parse_insn_normal (cd, insn, strp, fields) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - const char **strp; - CGEN_FIELDS *fields; +parse_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const char **strp, + CGEN_FIELDS *fields) { /* ??? Runtime added insns not handled yet. */ const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); @@ -326,12 +324,11 @@ parse_insn_normal (cd, insn, strp, fields) mind helps keep the design clean. */ const CGEN_INSN * -@arch@_cgen_assemble_insn (cd, str, fields, buf, errmsg) - CGEN_CPU_DESC cd; - const char *str; - CGEN_FIELDS *fields; - CGEN_INSN_BYTES_PTR buf; - char **errmsg; +@arch@_cgen_assemble_insn (CGEN_CPU_DESC cd, + const char *str, + CGEN_FIELDS *fields, + CGEN_INSN_BYTES_PTR buf, + char **errmsg) { const char *start; CGEN_INSN_LIST *ilist; @@ -361,10 +358,10 @@ const CGEN_INSN * if (! @arch@_cgen_insn_supported (cd, insn)) continue; #endif - /* If the RELAX attribute is set, this is an insn that shouldn't be + /* If the RELAXED attribute is set, this is an insn that shouldn't be chosen immediately. Instead, it is used during assembler/linker relaxation if possible. */ - if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAX) != 0) + if (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_RELAXED) != 0) continue; str = start; @@ -435,9 +432,7 @@ const CGEN_INSN * FIXME: Not currently used. */ void -@arch@_cgen_asm_hash_keywords (cd, opvals) - CGEN_CPU_DESC cd; - CGEN_KEYWORD *opvals; +@arch@_cgen_asm_hash_keywords (CGEN_CPU_DESC cd, CGEN_KEYWORD *opvals) { CGEN_KEYWORD_SEARCH search = cgen_keyword_search_init (opvals, NULL); const CGEN_KEYWORD_ENTRY * ke; diff --git a/contrib/binutils/opcodes/cgen-dis.c b/contrib/binutils/opcodes/cgen-dis.c index 881ee14..ca621de 100644 --- a/contrib/binutils/opcodes/cgen-dis.c +++ b/contrib/binutils/opcodes/cgen-dis.c @@ -27,19 +27,18 @@ #include "symcat.h" #include "opcode/cgen.h" -static CGEN_INSN_LIST * hash_insn_array PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); -static CGEN_INSN_LIST * hash_insn_list PARAMS ((CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *)); -static void build_dis_hash_table PARAMS ((CGEN_CPU_DESC)); -static int count_decodable_bits PARAMS ((const CGEN_INSN *)); -static void add_insn_to_hash_chain PARAMS ((CGEN_INSN_LIST *, - const CGEN_INSN *, - CGEN_INSN_LIST **, - unsigned int)); +static CGEN_INSN_LIST * hash_insn_array (CGEN_CPU_DESC, const CGEN_INSN *, int, int, CGEN_INSN_LIST **, CGEN_INSN_LIST *); +static CGEN_INSN_LIST * hash_insn_list (CGEN_CPU_DESC, const CGEN_INSN_LIST *, CGEN_INSN_LIST **, CGEN_INSN_LIST *); +static void build_dis_hash_table (CGEN_CPU_DESC); +static int count_decodable_bits (const CGEN_INSN *); +static void add_insn_to_hash_chain (CGEN_INSN_LIST *, + const CGEN_INSN *, + CGEN_INSN_LIST **, + unsigned int); /* Return the number of decodable bits in this insn. */ static int -count_decodable_bits (insn) - const CGEN_INSN *insn; +count_decodable_bits (const CGEN_INSN *insn) { unsigned mask = CGEN_INSN_BASE_MASK (insn); int bits = 0; @@ -54,11 +53,10 @@ count_decodable_bits (insn) /* Add an instruction to the hash chain. */ static void -add_insn_to_hash_chain (hentbuf, insn, htable, hash) - CGEN_INSN_LIST *hentbuf; - const CGEN_INSN *insn; - CGEN_INSN_LIST **htable; - unsigned int hash; +add_insn_to_hash_chain (CGEN_INSN_LIST *hentbuf, + const CGEN_INSN *insn, + CGEN_INSN_LIST **htable, + unsigned int hash) { CGEN_INSN_LIST *current_buf; CGEN_INSN_LIST *previous_buf; @@ -100,13 +98,12 @@ add_insn_to_hash_chain (hentbuf, insn, htable, hash) list and we want earlier ones to be prefered. */ static CGEN_INSN_LIST * -hash_insn_array (cd, insns, count, entsize, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN * insns; - int count; - int entsize ATTRIBUTE_UNUSED; - CGEN_INSN_LIST ** htable; - CGEN_INSN_LIST * hentbuf; +hash_insn_array (CGEN_CPU_DESC cd, + const CGEN_INSN * insns, + int count, + int entsize ATTRIBUTE_UNUSED, + CGEN_INSN_LIST ** htable, + CGEN_INSN_LIST * hentbuf) { int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG; int i; @@ -141,11 +138,10 @@ hash_insn_array (cd, insns, count, entsize, htable, hentbuf) in a list. */ static CGEN_INSN_LIST * -hash_insn_list (cd, insns, htable, hentbuf) - CGEN_CPU_DESC cd; - const CGEN_INSN_LIST *insns; - CGEN_INSN_LIST **htable; - CGEN_INSN_LIST *hentbuf; +hash_insn_list (CGEN_CPU_DESC cd, + const CGEN_INSN_LIST *insns, + CGEN_INSN_LIST **htable, + CGEN_INSN_LIST *hentbuf) { int big_p = CGEN_CPU_ENDIAN (cd) == CGEN_ENDIAN_BIG; const CGEN_INSN_LIST *ilist; @@ -177,8 +173,7 @@ hash_insn_list (cd, insns, htable, hentbuf) /* Build the disassembler instruction hash table. */ static void -build_dis_hash_table (cd) - CGEN_CPU_DESC cd; +build_dis_hash_table (CGEN_CPU_DESC cd) { int count = cgen_insn_count (cd) + cgen_macro_insn_count (cd); CGEN_INSN_TABLE *insn_table = & cd->insn_table; @@ -233,10 +228,7 @@ build_dis_hash_table (cd) /* Return the first entry in the hash list for INSN. */ CGEN_INSN_LIST * -cgen_dis_lookup_insn (cd, buf, value) - CGEN_CPU_DESC cd; - const char * buf; - CGEN_INSN_INT value; +cgen_dis_lookup_insn (CGEN_CPU_DESC cd, const char * buf, CGEN_INSN_INT value) { unsigned int hash; diff --git a/contrib/binutils/opcodes/cgen-dis.in b/contrib/binutils/opcodes/cgen-dis.in index 7c59340..1a3c0fa 100644 --- a/contrib/binutils/opcodes/cgen-dis.in +++ b/contrib/binutils/opcodes/cgen-dis.in @@ -4,7 +4,8 @@ THIS FILE IS MACHINE GENERATED WITH CGEN. - the resultant file is machine generated, cgen-dis.in isn't -Copyright 1996, 1997, 1998, 1999, 2000, 2001 Free Software Foundation, Inc. +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 +Free Software Foundation, Inc. This file is part of the GNU Binutils and GDB, the GNU debugger. @@ -31,6 +32,7 @@ along with this program; if not, write to the Free Software Foundation, Inc., #include "dis-asm.h" #include "bfd.h" #include "symcat.h" +#include "libiberty.h" #include "@prefix@-desc.h" #include "@prefix@-opc.h" #include "opintl.h" @@ -39,34 +41,32 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define UNKNOWN_INSN_MSG _("*unknown*") static void print_normal - PARAMS ((CGEN_CPU_DESC, PTR, long, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); static void print_address - PARAMS ((CGEN_CPU_DESC, PTR, bfd_vma, unsigned int, bfd_vma, int)); + (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int); static void print_keyword - PARAMS ((CGEN_CPU_DESC, PTR, CGEN_KEYWORD *, long, unsigned int)); + (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int); static void print_insn_normal - PARAMS ((CGEN_CPU_DESC, PTR, const CGEN_INSN *, CGEN_FIELDS *, - bfd_vma, int)); + (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); static int print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, unsigned); static int default_print_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *); static int read_insn - PARAMS ((CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, - CGEN_EXTRACT_INFO *, unsigned long *)); + (CGEN_CPU_DESC, bfd_vma, disassemble_info *, char *, int, CGEN_EXTRACT_INFO *, + unsigned long *); /* -- disassembler routines inserted here */ /* Default print handler. */ static void -print_normal (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - long value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + long value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -86,13 +86,12 @@ print_normal (cd, dis_info, value, attrs, pc, length) /* Default address handler. */ static void -print_address (cd, dis_info, value, attrs, pc, length) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - bfd_vma value; - unsigned int attrs; - bfd_vma pc ATTRIBUTE_UNUSED; - int length ATTRIBUTE_UNUSED; +print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + bfd_vma value, + unsigned int attrs, + bfd_vma pc ATTRIBUTE_UNUSED, + int length ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; @@ -116,12 +115,11 @@ print_address (cd, dis_info, value, attrs, pc, length) /* Keyword print handler. */ static void -print_keyword (cd, dis_info, keyword_table, value, attrs) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - PTR dis_info; - CGEN_KEYWORD *keyword_table; - long value; - unsigned int attrs ATTRIBUTE_UNUSED; +print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + void *dis_info, + CGEN_KEYWORD *keyword_table, + long value, + unsigned int attrs ATTRIBUTE_UNUSED) { disassemble_info *info = (disassemble_info *) dis_info; const CGEN_KEYWORD_ENTRY *ke; @@ -135,17 +133,16 @@ print_keyword (cd, dis_info, keyword_table, value, attrs) /* Default insn printer. - DIS_INFO is defined as `PTR' so the disassembler needn't know anything + DIS_INFO is defined as `void *' so the disassembler needn't know anything about disassemble_info. */ static void -print_insn_normal (cd, dis_info, insn, fields, pc, length) - CGEN_CPU_DESC cd; - PTR dis_info; - const CGEN_INSN *insn; - CGEN_FIELDS *fields; - bfd_vma pc; - int length; +print_insn_normal (CGEN_CPU_DESC cd, + void *dis_info, + const CGEN_INSN *insn, + CGEN_FIELDS *fields, + bfd_vma pc, + int length) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); disassemble_info *info = (disassemble_info *) dis_info; @@ -177,14 +174,13 @@ print_insn_normal (cd, dis_info, insn, fields, pc, length) Returns 0 if all is well, non-zero otherwise. */ static int -read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - bfd_vma pc; - disassemble_info *info; - char *buf; - int buflen; - CGEN_EXTRACT_INFO *ex_info; - unsigned long *insn_value; +read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + bfd_vma pc, + disassemble_info *info, + char *buf, + int buflen, + CGEN_EXTRACT_INFO *ex_info, + unsigned long *insn_value) { int status = (*info->read_memory_func) (pc, buf, buflen, info); if (status != 0) @@ -208,12 +204,11 @@ read_insn (cd, pc, info, buf, buflen, ex_info, insn_value) been called). */ static int -print_insn (cd, pc, info, buf, buflen) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; - char *buf; - unsigned int buflen; +print_insn (CGEN_CPU_DESC cd, + bfd_vma pc, + disassemble_info *info, + char *buf, + unsigned int buflen) { CGEN_INSN_INT insn_value; const CGEN_INSN_LIST *insn_list; @@ -318,10 +313,7 @@ print_insn (cd, pc, info, buf, buflen) #endif static int -default_print_insn (cd, pc, info) - CGEN_CPU_DESC cd; - bfd_vma pc; - disassemble_info *info; +default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) { char buf[CGEN_MAX_INSN_SIZE]; int buflen; @@ -360,9 +352,7 @@ typedef struct cpu_desc_list { } cpu_desc_list; int -print_insn_@arch@ (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_@arch@ (bfd_vma pc, disassemble_info *info) { static cpu_desc_list *cd_list = 0; cpu_desc_list *cl = 0; diff --git a/contrib/binutils/opcodes/cgen-ibld.in b/contrib/binutils/opcodes/cgen-ibld.in index d2bfd02..316f183 100644 --- a/contrib/binutils/opcodes/cgen-ibld.in +++ b/contrib/binutils/opcodes/cgen-ibld.in @@ -44,30 +44,29 @@ along with this program; if not, write to the Free Software Foundation, Inc., #define FLD(f) (fields->f) static const char * insert_normal - PARAMS ((CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR)); + (CGEN_CPU_DESC, long, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, unsigned int, CGEN_INSN_BYTES_PTR); static const char * insert_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, - CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, + CGEN_FIELDS *, CGEN_INSN_BYTES_PTR, bfd_vma); static int extract_normal - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, - unsigned int, unsigned int, unsigned int, unsigned int, - unsigned int, unsigned int, bfd_vma, long *)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, CGEN_INSN_INT, + unsigned int, unsigned int, unsigned int, unsigned int, + unsigned int, unsigned int, bfd_vma, long *); static int extract_insn_normal - PARAMS ((CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, - CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma)); + (CGEN_CPU_DESC, const CGEN_INSN *, CGEN_EXTRACT_INFO *, + CGEN_INSN_INT, CGEN_FIELDS *, bfd_vma); #if CGEN_INT_INSN_P static void put_insn_int_value - PARAMS ((CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT)); + (CGEN_CPU_DESC, CGEN_INSN_BYTES_PTR, int, int, CGEN_INSN_INT); #endif #if ! CGEN_INT_INSN_P static CGEN_INLINE void insert_1 - PARAMS ((CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *)); + (CGEN_CPU_DESC, unsigned long, int, int, int, unsigned char *); static CGEN_INLINE int fill_cache - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, bfd_vma); static CGEN_INLINE long extract_1 - PARAMS ((CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, - unsigned char *, bfd_vma)); + (CGEN_CPU_DESC, CGEN_EXTRACT_INFO *, int, int, int, unsigned char *, bfd_vma); #endif /* Operand insertion. */ @@ -77,11 +76,12 @@ static CGEN_INLINE long extract_1 /* Subroutine of insert_normal. */ static CGEN_INLINE void -insert_1 (cd, value, start, length, word_length, bufp) - CGEN_CPU_DESC cd; - unsigned long value; - int start,length,word_length; - unsigned char *bufp; +insert_1 (CGEN_CPU_DESC cd, + unsigned long value, + int start, + int length, + int word_length, + unsigned char *bufp) { unsigned long x,mask; int shift; @@ -118,13 +118,15 @@ insert_1 (cd, value, start, length, word_length, bufp) necessary. */ static const char * -insert_normal (cd, value, attrs, word_offset, start, length, word_length, - total_length, buffer) - CGEN_CPU_DESC cd; - long value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; - CGEN_INSN_BYTES_PTR buffer; +insert_normal (CGEN_CPU_DESC cd, + long value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, + CGEN_INSN_BYTES_PTR buffer) { static char errbuf[100]; /* Written this way to avoid undefined behaviour. */ @@ -232,12 +234,11 @@ insert_normal (cd, value, attrs, word_offset, start, length, word_length, The result is an error message or NULL if success. */ static const char * -insert_insn_normal (cd, insn, fields, buffer, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN * insn; - CGEN_FIELDS * fields; - CGEN_INSN_BYTES_PTR buffer; - bfd_vma pc; +insert_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN * insn, + CGEN_FIELDS * fields, + CGEN_INSN_BYTES_PTR buffer, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); unsigned long value; @@ -288,12 +289,11 @@ insert_insn_normal (cd, insn, fields, buffer, pc) because it needs <prefix>-desc.h for CGEN_INT_INSN_P. */ static void -put_insn_int_value (cd, buf, length, insn_length, value) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_INSN_BYTES_PTR buf; - int length; - int insn_length; - CGEN_INSN_INT value; +put_insn_int_value (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_INSN_BYTES_PTR buf, + int length, + int insn_length, + CGEN_INSN_INT value) { /* For architectures with insns smaller than the base-insn-bitsize, length may be too big. */ @@ -320,11 +320,11 @@ put_insn_int_value (cd, buf, length, insn_length, value) Returns 1 for success, 0 for failure. */ static CGEN_INLINE int -fill_cache (cd, ex_info, offset, bytes, pc) - CGEN_CPU_DESC cd ATTRIBUTE_UNUSED; - CGEN_EXTRACT_INFO *ex_info; - int offset, bytes; - bfd_vma pc; +fill_cache (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, + CGEN_EXTRACT_INFO *ex_info, + int offset, + int bytes, + bfd_vma pc) { /* It's doubtful that the middle part has already been fetched so we don't optimize that case. kiss. */ @@ -364,12 +364,13 @@ fill_cache (cd, ex_info, offset, bytes, pc) /* Subroutine of extract_normal. */ static CGEN_INLINE long -extract_1 (cd, ex_info, start, length, word_length, bufp, pc) - CGEN_CPU_DESC cd; - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; - int start,length,word_length; - unsigned char *bufp; - bfd_vma pc ATTRIBUTE_UNUSED; +extract_1 (CGEN_CPU_DESC cd, + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, + int start, + int length, + int word_length, + unsigned char *bufp, + bfd_vma pc ATTRIBUTE_UNUSED) { unsigned long x; int shift; @@ -408,23 +409,25 @@ extract_1 (cd, ex_info, start, length, word_length, bufp, pc) necessary. */ static int -extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, - word_length, total_length, pc, valuep) - CGEN_CPU_DESC cd; +extract_normal (CGEN_CPU_DESC cd, #if ! CGEN_INT_INSN_P - CGEN_EXTRACT_INFO *ex_info; + CGEN_EXTRACT_INFO *ex_info, #else - CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED; + CGEN_EXTRACT_INFO *ex_info ATTRIBUTE_UNUSED, #endif - CGEN_INSN_INT insn_value; - unsigned int attrs; - unsigned int word_offset, start, length, word_length, total_length; + CGEN_INSN_INT insn_value, + unsigned int attrs, + unsigned int word_offset, + unsigned int start, + unsigned int length, + unsigned int word_length, + unsigned int total_length, #if ! CGEN_INT_INSN_P - bfd_vma pc; + bfd_vma pc, #else - bfd_vma pc ATTRIBUTE_UNUSED; + bfd_vma pc ATTRIBUTE_UNUSED, #endif - long *valuep; + long *valuep) { long value, mask; @@ -505,13 +508,12 @@ extract_normal (cd, ex_info, insn_value, attrs, word_offset, start, length, been called). */ static int -extract_insn_normal (cd, insn, ex_info, insn_value, fields, pc) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_EXTRACT_INFO *ex_info; - CGEN_INSN_INT insn_value; - CGEN_FIELDS *fields; - bfd_vma pc; +extract_insn_normal (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_EXTRACT_INFO *ex_info, + CGEN_INSN_INT insn_value, + CGEN_FIELDS *fields, + bfd_vma pc) { const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); const CGEN_SYNTAX_CHAR_TYPE *syn; diff --git a/contrib/binutils/opcodes/cgen-opc.c b/contrib/binutils/opcodes/cgen-opc.c index 06544ca..882b348 100644 --- a/contrib/binutils/opcodes/cgen-opc.c +++ b/contrib/binutils/opcodes/cgen-opc.c @@ -33,11 +33,11 @@ #endif static unsigned int hash_keyword_name - PARAMS ((const CGEN_KEYWORD *, const char *, int)); + (const CGEN_KEYWORD *, const char *, int); static unsigned int hash_keyword_value - PARAMS ((const CGEN_KEYWORD *, unsigned int)); + (const CGEN_KEYWORD *, unsigned int); static void build_keyword_hash_tables - PARAMS ((CGEN_KEYWORD *)); + (CGEN_KEYWORD *); /* Return number of hash table entries to use for N elements. */ #define KEYWORD_HASH_SIZE(n) ((n) <= 31 ? 17 : 31) @@ -46,9 +46,7 @@ static void build_keyword_hash_tables The result is the keyword entry or NULL if not found. */ const CGEN_KEYWORD_ENTRY * -cgen_keyword_lookup_name (kt, name) - CGEN_KEYWORD *kt; - const char *name; +cgen_keyword_lookup_name (CGEN_KEYWORD *kt, const char *name) { const CGEN_KEYWORD_ENTRY *ke; const char *p,*n; @@ -87,9 +85,7 @@ cgen_keyword_lookup_name (kt, name) The result is the keyword entry or NULL if not found. */ const CGEN_KEYWORD_ENTRY * -cgen_keyword_lookup_value (kt, value) - CGEN_KEYWORD *kt; - int value; +cgen_keyword_lookup_value (CGEN_KEYWORD *kt, int value) { const CGEN_KEYWORD_ENTRY *ke; @@ -111,9 +107,7 @@ cgen_keyword_lookup_value (kt, value) /* Add an entry to a keyword table. */ void -cgen_keyword_add (kt, ke) - CGEN_KEYWORD *kt; - CGEN_KEYWORD_ENTRY *ke; +cgen_keyword_add (CGEN_KEYWORD *kt, CGEN_KEYWORD_ENTRY *ke) { unsigned int hash; size_t i; @@ -159,9 +153,7 @@ cgen_keyword_add (kt, ke) It is passed to each call to cgen_keyword_search_next. */ CGEN_KEYWORD_SEARCH -cgen_keyword_search_init (kt, spec) - CGEN_KEYWORD *kt; - const char *spec; +cgen_keyword_search_init (CGEN_KEYWORD *kt, const char *spec) { CGEN_KEYWORD_SEARCH search; @@ -183,8 +175,7 @@ cgen_keyword_search_init (kt, spec) The result is the next entry or NULL if there are no more. */ const CGEN_KEYWORD_ENTRY * -cgen_keyword_search_next (search) - CGEN_KEYWORD_SEARCH *search; +cgen_keyword_search_next (CGEN_KEYWORD_SEARCH *search) { /* Has search finished? */ if (search->current_hash == search->table->hash_table_size) @@ -218,10 +209,9 @@ cgen_keyword_search_next (search) If CASE_SENSITIVE_P is non-zero, return a case sensitive hash. */ static unsigned int -hash_keyword_name (kt, name, case_sensitive_p) - const CGEN_KEYWORD *kt; - const char *name; - int case_sensitive_p; +hash_keyword_name (const CGEN_KEYWORD *kt, + const char *name, + int case_sensitive_p) { unsigned int hash; @@ -237,9 +227,7 @@ hash_keyword_name (kt, name, case_sensitive_p) /* Return first entry in hash chain for VALUE. */ static unsigned int -hash_keyword_value (kt, value) - const CGEN_KEYWORD *kt; - unsigned int value; +hash_keyword_value (const CGEN_KEYWORD *kt, unsigned int value) { return value % kt->hash_table_size; } @@ -249,8 +237,7 @@ hash_keyword_value (kt, value) we're using the disassembler, but we keep things simple. */ static void -build_keyword_hash_tables (kt) - CGEN_KEYWORD *kt; +build_keyword_hash_tables (CGEN_KEYWORD *kt) { int i; /* Use the number of compiled in entries as an estimate for the @@ -278,9 +265,7 @@ build_keyword_hash_tables (kt) mach/isa. */ const CGEN_HW_ENTRY * -cgen_hw_lookup_by_name (cd, name) - CGEN_CPU_DESC cd; - const char *name; +cgen_hw_lookup_by_name (CGEN_CPU_DESC cd, const char *name) { unsigned int i; const CGEN_HW_ENTRY **hw = cd->hw_table.entries; @@ -298,9 +283,7 @@ cgen_hw_lookup_by_name (cd, name) Returns NULL if HWNUM is not supported by the currently selected mach. */ const CGEN_HW_ENTRY * -cgen_hw_lookup_by_num (cd, hwnum) - CGEN_CPU_DESC cd; - unsigned int hwnum; +cgen_hw_lookup_by_num (CGEN_CPU_DESC cd, unsigned int hwnum) { unsigned int i; const CGEN_HW_ENTRY **hw = cd->hw_table.entries; @@ -320,9 +303,7 @@ cgen_hw_lookup_by_num (cd, hwnum) mach/isa. */ const CGEN_OPERAND * -cgen_operand_lookup_by_name (cd, name) - CGEN_CPU_DESC cd; - const char *name; +cgen_operand_lookup_by_name (CGEN_CPU_DESC cd, const char *name) { unsigned int i; const CGEN_OPERAND **op = cd->operand_table.entries; @@ -341,9 +322,7 @@ cgen_operand_lookup_by_name (cd, name) mach/isa. */ const CGEN_OPERAND * -cgen_operand_lookup_by_num (cd, opnum) - CGEN_CPU_DESC cd; - int opnum; +cgen_operand_lookup_by_num (CGEN_CPU_DESC cd, int opnum) { return cd->operand_table.entries[opnum]; } @@ -353,8 +332,7 @@ cgen_operand_lookup_by_num (cd, opnum) /* Return number of instructions. This includes any added at runtime. */ int -cgen_insn_count (cd) - CGEN_CPU_DESC cd; +cgen_insn_count (CGEN_CPU_DESC cd) { int count = cd->insn_table.num_init_entries; CGEN_INSN_LIST *rt_insns = cd->insn_table.new_entries; @@ -369,8 +347,7 @@ cgen_insn_count (cd) This includes any added at runtime. */ int -cgen_macro_insn_count (cd) - CGEN_CPU_DESC cd; +cgen_macro_insn_count (CGEN_CPU_DESC cd) { int count = cd->macro_insn_table.num_init_entries; CGEN_INSN_LIST *rt_insns = cd->macro_insn_table.new_entries; @@ -384,10 +361,7 @@ cgen_macro_insn_count (cd) /* Cover function to read and properly byteswap an insn value. */ CGEN_INSN_INT -cgen_get_insn_value (cd, buf, length) - CGEN_CPU_DESC cd; - unsigned char *buf; - int length; +cgen_get_insn_value (CGEN_CPU_DESC cd, unsigned char *buf, int length) { int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); int insn_chunk_bitsize = cd->insn_chunk_bitsize; @@ -423,11 +397,10 @@ cgen_get_insn_value (cd, buf, length) /* Cover function to store an insn value properly byteswapped. */ void -cgen_put_insn_value (cd, buf, length, value) - CGEN_CPU_DESC cd; - unsigned char *buf; - int length; - CGEN_INSN_INT value; +cgen_put_insn_value (CGEN_CPU_DESC cd, + unsigned char *buf, + int length, + CGEN_INSN_INT value) { int big_p = (cd->insn_endian == CGEN_ENDIAN_BIG); int insn_chunk_bitsize = cd->insn_chunk_bitsize; @@ -472,16 +445,14 @@ cgen_put_insn_value (cd, buf, length, value) /* ??? Will need to be revisited for VLIW architectures. */ const CGEN_INSN * -cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value, length, fields, - alias_p) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_INSN_INT insn_int_value; - /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ - unsigned char *insn_bytes_value; - int length; - CGEN_FIELDS *fields; - int alias_p; +cgen_lookup_insn (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_INSN_INT insn_int_value, + /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ + unsigned char *insn_bytes_value, + int length, + CGEN_FIELDS *fields, + int alias_p) { unsigned char *buf; CGEN_INSN_INT base_insn; @@ -571,11 +542,10 @@ cgen_lookup_insn (cd, insn, insn_int_value, insn_bytes_value, length, fields, in. */ void -cgen_get_insn_operands (cd, insn, fields, indices) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - const CGEN_FIELDS *fields; - int *indices; +cgen_get_insn_operands (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + const CGEN_FIELDS *fields, + int *indices) { const CGEN_OPINST *opinst; int i; @@ -603,16 +573,14 @@ cgen_get_insn_operands (cd, insn, fields, indices) recognized. */ const CGEN_INSN * -cgen_lookup_get_insn_operands (cd, insn, insn_int_value, insn_bytes_value, - length, indices, fields) - CGEN_CPU_DESC cd; - const CGEN_INSN *insn; - CGEN_INSN_INT insn_int_value; - /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ - unsigned char *insn_bytes_value; - int length; - int *indices; - CGEN_FIELDS *fields; +cgen_lookup_get_insn_operands (CGEN_CPU_DESC cd, + const CGEN_INSN *insn, + CGEN_INSN_INT insn_int_value, + /* ??? CGEN_INSN_BYTES would be a nice type name to use here. */ + unsigned char *insn_bytes_value, + int length, + int *indices, + CGEN_FIELDS *fields) { /* Pass non-zero for ALIAS_P only if INSN != NULL. If INSN == NULL, we want a real insn. */ @@ -627,24 +595,21 @@ cgen_lookup_get_insn_operands (cd, insn, insn_int_value, insn_bytes_value, /* Allow signed overflow of instruction fields. */ void -cgen_set_signed_overflow_ok (cd) - CGEN_CPU_DESC cd; +cgen_set_signed_overflow_ok (CGEN_CPU_DESC cd) { cd->signed_overflow_ok_p = 1; } /* Generate an error message if a signed field in an instruction overflows. */ void -cgen_clear_signed_overflow_ok (cd) - CGEN_CPU_DESC cd; +cgen_clear_signed_overflow_ok (CGEN_CPU_DESC cd) { cd->signed_overflow_ok_p = 0; } /* Will an error message be generated if a signed field in an instruction overflows ? */ unsigned int -cgen_signed_overflow_ok_p (cd) - CGEN_CPU_DESC cd; +cgen_signed_overflow_ok_p (CGEN_CPU_DESC cd) { return cd->signed_overflow_ok_p; } diff --git a/contrib/binutils/opcodes/cgen.sh b/contrib/binutils/opcodes/cgen.sh index a9483bd..5a340b6 100644 --- a/contrib/binutils/opcodes/cgen.sh +++ b/contrib/binutils/opcodes/cgen.sh @@ -23,11 +23,19 @@ # arch-asm.c, arch-dis.c, arch-opinst.c, arch-ibld.[ch]. # # Usage: -# cgen.sh action srcdir cgen cgendir cgenflags arch prefix options +# cgen.sh action srcdir cgen cgendir cgenflags arch prefix \ +# arch-file opc-file options [extrafiles] # # ACTION is currently always "opcodes". It exists to be consistent with the # simulator. -# OPTIONS is comma separated list of options: +# ARCH is the name of the architecture. +# It is substituted into @arch@ and @ARCH@ in the generated files. +# PREFIX is both the generated file prefix and is substituted into +# @prefix@ in the generated files. +# ARCH-FILE is the name of the .cpu file (including path). +# OPC-FILE is the name of the .opc file (including path). +# OPTIONS is comma separated list of options (???). +# EXTRAFILES is a space separated list (1 arg still) of extra files to build: # - opinst - arch-opinst.c is being made, causes semantic analysis # # We store the generated files in the source directory until we decide to @@ -44,11 +52,13 @@ cgendir=$4 cgenflags=$5 arch=$6 prefix=$7 -options=$8 +archfile=$8 +opcfile=$9 +shift ; options=$9 # List of extra files to build. # Values: opinst (only 1 extra file at present) -extrafiles=$9 +shift ; extrafiles=$9 rootdir=${srcdir}/.. @@ -88,7 +98,8 @@ opcodes) ${cgenflags} \ -f "${options}" \ -m all \ - -a ${arch} \ + -a ${archfile} \ + -OPC ${opcfile} \ -H tmp-desc.h1 \ -C tmp-desc.c1 \ -O tmp-opc.h1 \ diff --git a/contrib/binutils/opcodes/config.in b/contrib/binutils/opcodes/config.in index 6355be0..5caef55 100644 --- a/contrib/binutils/opcodes/config.in +++ b/contrib/binutils/opcodes/config.in @@ -25,9 +25,6 @@ /* Define to `long' if <sys/types.h> doesn't define. */ #undef off_t -/* Define if you need to in order for stat and other things to work. */ -#undef _POSIX_SOURCE - /* Define to `unsigned' if <sys/types.h> doesn't define. */ #undef size_t @@ -109,12 +106,6 @@ /* Define if you have the <sys/param.h> header file. */ #undef HAVE_SYS_PARAM_H -/* Define if you have the <sys/stat.h> header file. */ -#undef HAVE_SYS_STAT_H - -/* Define if you have the <sys/types.h> header file. */ -#undef HAVE_SYS_TYPES_H - /* Define if you have the <unistd.h> header file. */ #undef HAVE_UNISTD_H diff --git a/contrib/binutils/opcodes/configure b/contrib/binutils/opcodes/configure index 93dc228..4a95a9a 100755 --- a/contrib/binutils/opcodes/configure +++ b/contrib/binutils/opcodes/configure @@ -33,7 +33,7 @@ ac_help="$ac_help --enable-maintainer-mode enable make rules and dependencies not useful (and sometimes confusing) to the casual installer" ac_help="$ac_help - --install-libbfd controls installation of libbfd and related headers" + --enable-install-libbfd controls installation of libbfd and related headers" ac_help="$ac_help --disable-nls do not use Native Language Support" ac_help="$ac_help @@ -57,6 +57,7 @@ program_suffix=NONE program_transform_name=s,x,x, silent= site= +sitefile= srcdir= target=NONE verbose= @@ -171,6 +172,7 @@ Configuration: --help print this message --no-create do not create output files --quiet, --silent do not print \`checking...' messages + --site-file=FILE use FILE as the site file --version print the version of autoconf that created configure Directory and file names: --prefix=PREFIX install architecture-independent files in PREFIX @@ -341,6 +343,11 @@ EOF -site=* | --site=* | --sit=*) site="$ac_optarg" ;; + -site-file | --site-file | --site-fil | --site-fi | --site-f) + ac_prev=sitefile ;; + -site-file=* | --site-file=* | --site-fil=* | --site-fi=* | --site-f=*) + sitefile="$ac_optarg" ;; + -srcdir | --srcdir | --srcdi | --srcd | --src | --sr) ac_prev=srcdir ;; -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*) @@ -506,12 +513,16 @@ fi srcdir=`echo "${srcdir}" | sed 's%\([^/]\)/*$%\1%'` # Prefer explicitly selected file to automatically selected ones. -if test -z "$CONFIG_SITE"; then - if test "x$prefix" != xNONE; then - CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site" - else - CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site" +if test -z "$sitefile"; then + if test -z "$CONFIG_SITE"; then + if test "x$prefix" != xNONE; then + CONFIG_SITE="$prefix/share/config.site $prefix/etc/config.site" + else + CONFIG_SITE="$ac_default_prefix/share/config.site $ac_default_prefix/etc/config.site" + fi fi +else + CONFIG_SITE="$sitefile" fi for ac_site_file in $CONFIG_SITE; do if test -r "$ac_site_file"; then @@ -550,12 +561,12 @@ else fi echo $ac_n "checking for Cygwin environment""... $ac_c" 1>&6 -echo "configure:554: checking for Cygwin environment" >&5 +echo "configure:565: checking for Cygwin environment" >&5 if eval "test \"`echo '$''{'ac_cv_cygwin'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 559 "configure" +#line 570 "configure" #include "confdefs.h" int main() { @@ -566,7 +577,7 @@ int main() { return __CYGWIN__; ; return 0; } EOF -if { (eval echo configure:570: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:581: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_cygwin=yes else @@ -583,19 +594,19 @@ echo "$ac_t""$ac_cv_cygwin" 1>&6 CYGWIN= test "$ac_cv_cygwin" = yes && CYGWIN=yes echo $ac_n "checking for mingw32 environment""... $ac_c" 1>&6 -echo "configure:587: checking for mingw32 environment" >&5 +echo "configure:598: checking for mingw32 environment" >&5 if eval "test \"`echo '$''{'ac_cv_mingw32'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 592 "configure" +#line 603 "configure" #include "confdefs.h" int main() { return __MINGW32__; ; return 0; } EOF -if { (eval echo configure:599: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:610: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_mingw32=yes else @@ -660,7 +671,7 @@ else { echo "configure: error: can not run $ac_config_sub" 1>&2; exit 1; } fi echo $ac_n "checking host system type""... $ac_c" 1>&6 -echo "configure:664: checking host system type" >&5 +echo "configure:675: checking host system type" >&5 host_alias=$host case "$host_alias" in @@ -681,7 +692,7 @@ host_os=`echo $host | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` echo "$ac_t""$host" 1>&6 echo $ac_n "checking target system type""... $ac_c" 1>&6 -echo "configure:685: checking target system type" >&5 +echo "configure:696: checking target system type" >&5 target_alias=$target case "$target_alias" in @@ -699,7 +710,7 @@ target_os=`echo $target | sed 's/^\([^-]*\)-\([^-]*\)-\(.*\)$/\3/'` echo "$ac_t""$target" 1>&6 echo $ac_n "checking build system type""... $ac_c" 1>&6 -echo "configure:703: checking build system type" >&5 +echo "configure:714: checking build system type" >&5 build_alias=$build case "$build_alias" in @@ -721,249 +732,49 @@ test "$host_alias" != "$target_alias" && NONENONEs,x,x, && program_prefix=${target_alias}- -# Extract the first word of "gcc", so it can be a program name with args. -set dummy gcc; ac_word=$2 -echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:728: checking for $ac_word" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then - echo $ac_n "(cached) $ac_c" 1>&6 -else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - ac_dummy="$PATH" - for ac_dir in $ac_dummy; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/$ac_word; then - ac_cv_prog_CC="gcc" - break - fi - done - IFS="$ac_save_ifs" -fi -fi -CC="$ac_cv_prog_CC" -if test -n "$CC"; then - echo "$ac_t""$CC" 1>&6 -else - echo "$ac_t""no" 1>&6 -fi - -if test -z "$CC"; then - # Extract the first word of "cc", so it can be a program name with args. -set dummy cc; ac_word=$2 -echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:758: checking for $ac_word" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then - echo $ac_n "(cached) $ac_c" 1>&6 -else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - ac_prog_rejected=no - ac_dummy="$PATH" - for ac_dir in $ac_dummy; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/$ac_word; then - if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then - ac_prog_rejected=yes - continue - fi - ac_cv_prog_CC="cc" - break - fi - done - IFS="$ac_save_ifs" -if test $ac_prog_rejected = yes; then - # We found a bogon in the path, so make sure we never use it. - set dummy $ac_cv_prog_CC - shift - if test $# -gt 0; then - # We chose a different compiler from the bogus one. - # However, it has the same basename, so the bogon will be chosen - # first if we set CC to just the basename; use the full file name. - shift - set dummy "$ac_dir/$ac_word" "$@" - shift - ac_cv_prog_CC="$@" - fi -fi -fi -fi -CC="$ac_cv_prog_CC" -if test -n "$CC"; then - echo "$ac_t""$CC" 1>&6 -else - echo "$ac_t""no" 1>&6 -fi - if test -z "$CC"; then - case "`uname -s`" in - *win32* | *WIN32*) - # Extract the first word of "cl", so it can be a program name with args. -set dummy cl; ac_word=$2 -echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:809: checking for $ac_word" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "checking for strerror in -lcposix""... $ac_c" 1>&6 +echo "configure:738: checking for strerror in -lcposix" >&5 +ac_lib_var=`echo cposix'_'strerror | sed 'y%./+-%__p_%'` +if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else - if test -n "$CC"; then - ac_cv_prog_CC="$CC" # Let the user override the test. -else - IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" - ac_dummy="$PATH" - for ac_dir in $ac_dummy; do - test -z "$ac_dir" && ac_dir=. - if test -f $ac_dir/$ac_word; then - ac_cv_prog_CC="cl" - break - fi - done - IFS="$ac_save_ifs" -fi -fi -CC="$ac_cv_prog_CC" -if test -n "$CC"; then - echo "$ac_t""$CC" 1>&6 -else - echo "$ac_t""no" 1>&6 -fi - ;; - esac - fi - test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; } -fi - -echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 -echo "configure:841: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 - -ac_ext=c -# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. -ac_cpp='$CPP $CPPFLAGS' -ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' -ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' -cross_compiling=$ac_cv_prog_cc_cross - -cat > conftest.$ac_ext << EOF - -#line 852 "configure" + ac_save_LIBS="$LIBS" +LIBS="-lcposix $LIBS" +cat > conftest.$ac_ext <<EOF +#line 746 "configure" #include "confdefs.h" +/* Override any gcc2 internal prototype to avoid an error. */ +/* We use char because int might match the return type of a gcc2 + builtin and then its argument prototype would still apply. */ +char strerror(); -main(){return(0);} +int main() { +strerror() +; return 0; } EOF -if { (eval echo configure:857: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then - ac_cv_prog_cc_works=yes - # If we can't run a trivial program, we are probably using a cross compiler. - if (./conftest; exit) 2>/dev/null; then - ac_cv_prog_cc_cross=no - else - ac_cv_prog_cc_cross=yes - fi +if { (eval echo configure:757: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=yes" else echo "configure: failed program was:" >&5 cat conftest.$ac_ext >&5 - ac_cv_prog_cc_works=no -fi -rm -fr conftest* -ac_ext=c -# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. -ac_cpp='$CPP $CPPFLAGS' -ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' -ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' -cross_compiling=$ac_cv_prog_cc_cross - -echo "$ac_t""$ac_cv_prog_cc_works" 1>&6 -if test $ac_cv_prog_cc_works = no; then - { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } -fi -echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 -echo "configure:883: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 -echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 -cross_compiling=$ac_cv_prog_cc_cross - -echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 -echo "configure:888: checking whether we are using GNU C" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then - echo $ac_n "(cached) $ac_c" 1>&6 -else - cat > conftest.c <<EOF -#ifdef __GNUC__ - yes; -#endif -EOF -if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:897: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then - ac_cv_prog_gcc=yes -else - ac_cv_prog_gcc=no -fi -fi - -echo "$ac_t""$ac_cv_prog_gcc" 1>&6 - -if test $ac_cv_prog_gcc = yes; then - GCC=yes -else - GCC= -fi - -ac_test_CFLAGS="${CFLAGS+set}" -ac_save_CFLAGS="$CFLAGS" -CFLAGS= -echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 -echo "configure:916: checking whether ${CC-cc} accepts -g" >&5 -if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then - echo $ac_n "(cached) $ac_c" 1>&6 -else - echo 'void f(){}' > conftest.c -if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then - ac_cv_prog_cc_g=yes -else - ac_cv_prog_cc_g=no + rm -rf conftest* + eval "ac_cv_lib_$ac_lib_var=no" fi rm -f conftest* +LIBS="$ac_save_LIBS" fi - -echo "$ac_t""$ac_cv_prog_cc_g" 1>&6 -if test "$ac_test_CFLAGS" = set; then - CFLAGS="$ac_save_CFLAGS" -elif test $ac_cv_prog_cc_g = yes; then - if test "$GCC" = yes; then - CFLAGS="-g -O2" - else - CFLAGS="-g" - fi -else - if test "$GCC" = yes; then - CFLAGS="-O2" - else - CFLAGS= - fi -fi - -echo $ac_n "checking for POSIXized ISC""... $ac_c" 1>&6 -echo "configure:948: checking for POSIXized ISC" >&5 -if test -d /etc/conf/kconfig.d && - grep _POSIX_VERSION /usr/include/sys/unistd.h >/dev/null 2>&1 -then +if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then echo "$ac_t""yes" 1>&6 - ISC=yes # If later tests want to check for ISC. - cat >> confdefs.h <<\EOF -#define _POSIX_SOURCE 1 -EOF - - if test "$GCC" = yes; then - CC="$CC -posix" - else - CC="$CC -Xp" - fi + LIBS="$LIBS -lcposix" else echo "$ac_t""no" 1>&6 - ISC= fi + + # We currently only use the version number for the name of any shared # library. For user convenience, we always use the same version @@ -982,7 +793,7 @@ BFD_VERSION=`sed -n -e 's/^.._INIT_AUTOMAKE.*,[ ]*\([^ ]*\)[ ]*).*/\1/p' < ${ # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # ./install, which can be erroneously created by make from ./install.sh. echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 -echo "configure:986: checking for a BSD compatible install" >&5 +echo "configure:797: checking for a BSD compatible install" >&5 if test -z "$INSTALL"; then if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -1035,7 +846,7 @@ test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL_PROGRAM}' test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' echo $ac_n "checking whether build environment is sane""... $ac_c" 1>&6 -echo "configure:1039: checking whether build environment is sane" >&5 +echo "configure:850: checking whether build environment is sane" >&5 # Just in case sleep 1 echo timestamp > conftestfile @@ -1092,7 +903,7 @@ test "$program_suffix" != NONE && test "$program_transform_name" = "" && program_transform_name="s,x,x," echo $ac_n "checking whether ${MAKE-make} sets \${MAKE}""... $ac_c" 1>&6 -echo "configure:1096: checking whether ${MAKE-make} sets \${MAKE}" >&5 +echo "configure:907: checking whether ${MAKE-make} sets \${MAKE}" >&5 set dummy ${MAKE-make}; ac_make=`echo "$2" | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_prog_make_${ac_make}_set'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -1138,7 +949,7 @@ EOF missing_dir=`cd $ac_aux_dir && pwd` echo $ac_n "checking for working aclocal""... $ac_c" 1>&6 -echo "configure:1142: checking for working aclocal" >&5 +echo "configure:953: checking for working aclocal" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1151,7 +962,7 @@ else fi echo $ac_n "checking for working autoconf""... $ac_c" 1>&6 -echo "configure:1155: checking for working autoconf" >&5 +echo "configure:966: checking for working autoconf" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1164,7 +975,7 @@ else fi echo $ac_n "checking for working automake""... $ac_c" 1>&6 -echo "configure:1168: checking for working automake" >&5 +echo "configure:979: checking for working automake" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1177,7 +988,7 @@ else fi echo $ac_n "checking for working autoheader""... $ac_c" 1>&6 -echo "configure:1181: checking for working autoheader" >&5 +echo "configure:992: checking for working autoheader" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1190,7 +1001,7 @@ else fi echo $ac_n "checking for working makeinfo""... $ac_c" 1>&6 -echo "configure:1194: checking for working makeinfo" >&5 +echo "configure:1005: checking for working makeinfo" >&5 # Run test in a subshell; some versions of sh will print an error if # an executable is not found, even if stderr is redirected. # Redirect stdin to placate older versions of autoconf. Sigh. @@ -1213,7 +1024,7 @@ fi # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. set dummy ${ac_tool_prefix}ar; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1217: checking for $ac_word" >&5 +echo "configure:1028: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_AR'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1245,7 +1056,7 @@ fi # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ac_tool_prefix}ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1249: checking for $ac_word" >&5 +echo "configure:1060: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1277,7 +1088,7 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1281: checking for $ac_word" >&5 +echo "configure:1092: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1380,6 +1191,228 @@ else enable_fast_install=yes fi +# Extract the first word of "gcc", so it can be a program name with args. +set dummy gcc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1198: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="gcc" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + +if test -z "$CC"; then + # Extract the first word of "cc", so it can be a program name with args. +set dummy cc; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1228: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_prog_rejected=no + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + if test "$ac_dir/$ac_word" = "/usr/ucb/cc"; then + ac_prog_rejected=yes + continue + fi + ac_cv_prog_CC="cc" + break + fi + done + IFS="$ac_save_ifs" +if test $ac_prog_rejected = yes; then + # We found a bogon in the path, so make sure we never use it. + set dummy $ac_cv_prog_CC + shift + if test $# -gt 0; then + # We chose a different compiler from the bogus one. + # However, it has the same basename, so the bogon will be chosen + # first if we set CC to just the basename; use the full file name. + shift + set dummy "$ac_dir/$ac_word" "$@" + shift + ac_cv_prog_CC="$@" + fi +fi +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + + if test -z "$CC"; then + case "`uname -s`" in + *win32* | *WIN32*) + # Extract the first word of "cl", so it can be a program name with args. +set dummy cl; ac_word=$2 +echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 +echo "configure:1279: checking for $ac_word" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + if test -n "$CC"; then + ac_cv_prog_CC="$CC" # Let the user override the test. +else + IFS="${IFS= }"; ac_save_ifs="$IFS"; IFS=":" + ac_dummy="$PATH" + for ac_dir in $ac_dummy; do + test -z "$ac_dir" && ac_dir=. + if test -f $ac_dir/$ac_word; then + ac_cv_prog_CC="cl" + break + fi + done + IFS="$ac_save_ifs" +fi +fi +CC="$ac_cv_prog_CC" +if test -n "$CC"; then + echo "$ac_t""$CC" 1>&6 +else + echo "$ac_t""no" 1>&6 +fi + ;; + esac + fi + test -z "$CC" && { echo "configure: error: no acceptable cc found in \$PATH" 1>&2; exit 1; } +fi + +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 +echo "configure:1311: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 + +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +cat > conftest.$ac_ext << EOF + +#line 1322 "configure" +#include "confdefs.h" + +main(){return(0);} +EOF +if { (eval echo configure:1327: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then + ac_cv_prog_cc_works=yes + # If we can't run a trivial program, we are probably using a cross compiler. + if (./conftest; exit) 2>/dev/null; then + ac_cv_prog_cc_cross=no + else + ac_cv_prog_cc_cross=yes + fi +else + echo "configure: failed program was:" >&5 + cat conftest.$ac_ext >&5 + ac_cv_prog_cc_works=no +fi +rm -fr conftest* +ac_ext=c +# CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. +ac_cpp='$CPP $CPPFLAGS' +ac_compile='${CC-cc} -c $CFLAGS $CPPFLAGS conftest.$ac_ext 1>&5' +ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS 1>&5' +cross_compiling=$ac_cv_prog_cc_cross + +echo "$ac_t""$ac_cv_prog_cc_works" 1>&6 +if test $ac_cv_prog_cc_works = no; then + { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } +fi +echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 +echo "configure:1353: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 +cross_compiling=$ac_cv_prog_cc_cross + +echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 +echo "configure:1358: checking whether we are using GNU C" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + cat > conftest.c <<EOF +#ifdef __GNUC__ + yes; +#endif +EOF +if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:1367: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then + ac_cv_prog_gcc=yes +else + ac_cv_prog_gcc=no +fi +fi + +echo "$ac_t""$ac_cv_prog_gcc" 1>&6 + +if test $ac_cv_prog_gcc = yes; then + GCC=yes +else + GCC= +fi + +ac_test_CFLAGS="${CFLAGS+set}" +ac_save_CFLAGS="$CFLAGS" +CFLAGS= +echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 +echo "configure:1386: checking whether ${CC-cc} accepts -g" >&5 +if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then + echo $ac_n "(cached) $ac_c" 1>&6 +else + echo 'void f(){}' > conftest.c +if test -z "`${CC-cc} -g -c conftest.c 2>&1`"; then + ac_cv_prog_cc_g=yes +else + ac_cv_prog_cc_g=no +fi +rm -f conftest* + +fi + +echo "$ac_t""$ac_cv_prog_cc_g" 1>&6 +if test "$ac_test_CFLAGS" = set; then + CFLAGS="$ac_save_CFLAGS" +elif test $ac_cv_prog_cc_g = yes; then + if test "$GCC" = yes; then + CFLAGS="-g -O2" + else + CFLAGS="-g" + fi +else + if test "$GCC" = yes; then + CFLAGS="-O2" + else + CFLAGS= + fi +fi + # Check whether --with-gnu-ld or --without-gnu-ld was given. if test "${with_gnu_ld+set}" = set; then withval="$with_gnu_ld" @@ -1392,7 +1425,7 @@ ac_prog=ld if test "$GCC" = yes; then # Check if gcc -print-prog-name=ld gives a path. echo $ac_n "checking for ld used by GCC""... $ac_c" 1>&6 -echo "configure:1396: checking for ld used by GCC" >&5 +echo "configure:1429: checking for ld used by GCC" >&5 case $host in *-*-mingw*) # gcc leaves a trailing carriage return which upsets mingw @@ -1422,10 +1455,10 @@ echo "configure:1396: checking for ld used by GCC" >&5 esac elif test "$with_gnu_ld" = yes; then echo $ac_n "checking for GNU ld""... $ac_c" 1>&6 -echo "configure:1426: checking for GNU ld" >&5 +echo "configure:1459: checking for GNU ld" >&5 else echo $ac_n "checking for non-GNU ld""... $ac_c" 1>&6 -echo "configure:1429: checking for non-GNU ld" >&5 +echo "configure:1462: checking for non-GNU ld" >&5 fi if eval "test \"`echo '$''{'lt_cv_path_LD'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -1460,7 +1493,7 @@ else fi test -z "$LD" && { echo "configure: error: no acceptable ld found in \$PATH" 1>&2; exit 1; } echo $ac_n "checking if the linker ($LD) is GNU ld""... $ac_c" 1>&6 -echo "configure:1464: checking if the linker ($LD) is GNU ld" >&5 +echo "configure:1497: checking if the linker ($LD) is GNU ld" >&5 if eval "test \"`echo '$''{'lt_cv_prog_gnu_ld'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1477,7 +1510,7 @@ with_gnu_ld=$lt_cv_prog_gnu_ld echo $ac_n "checking for $LD option to reload object files""... $ac_c" 1>&6 -echo "configure:1481: checking for $LD option to reload object files" >&5 +echo "configure:1514: checking for $LD option to reload object files" >&5 if eval "test \"`echo '$''{'lt_cv_ld_reload_flag'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1489,7 +1522,7 @@ reload_flag=$lt_cv_ld_reload_flag test -n "$reload_flag" && reload_flag=" $reload_flag" echo $ac_n "checking for BSD-compatible nm""... $ac_c" 1>&6 -echo "configure:1493: checking for BSD-compatible nm" >&5 +echo "configure:1526: checking for BSD-compatible nm" >&5 if eval "test \"`echo '$''{'lt_cv_path_NM'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1527,7 +1560,7 @@ NM="$lt_cv_path_NM" echo "$ac_t""$NM" 1>&6 echo $ac_n "checking whether ln -s works""... $ac_c" 1>&6 -echo "configure:1531: checking whether ln -s works" >&5 +echo "configure:1564: checking whether ln -s works" >&5 if eval "test \"`echo '$''{'ac_cv_prog_LN_S'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1548,7 +1581,7 @@ else fi echo $ac_n "checking how to recognise dependant libraries""... $ac_c" 1>&6 -echo "configure:1552: checking how to recognise dependant libraries" >&5 +echo "configure:1585: checking how to recognise dependant libraries" >&5 if eval "test \"`echo '$''{'lt_cv_deplibs_check_method'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1658,7 +1691,7 @@ irix5* | irix6*) # This must be Linux ELF. linux-gnu*) case $host_cpu in - alpha* | hppa* | i*86 | powerpc* | sparc* | ia64* ) + alpha* | mips* | hppa* | i*86 | powerpc* | sparc* | ia64* ) lt_cv_deplibs_check_method=pass_all ;; *) # glibc up to 2.1.1 does not perform some relocations on ARM @@ -1721,13 +1754,13 @@ file_magic_cmd=$lt_cv_file_magic_cmd deplibs_check_method=$lt_cv_deplibs_check_method echo $ac_n "checking for object suffix""... $ac_c" 1>&6 -echo "configure:1725: checking for object suffix" >&5 +echo "configure:1758: checking for object suffix" >&5 if eval "test \"`echo '$''{'ac_cv_objext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else rm -f conftest* echo 'int i = 1;' > conftest.$ac_ext -if { (eval echo configure:1731: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:1764: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then for ac_file in conftest.*; do case $ac_file in *.c) ;; @@ -1747,7 +1780,7 @@ ac_objext=$ac_cv_objext echo $ac_n "checking for executable suffix""... $ac_c" 1>&6 -echo "configure:1751: checking for executable suffix" >&5 +echo "configure:1784: checking for executable suffix" >&5 if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1757,10 +1790,10 @@ else rm -f conftest* echo 'int main () { return 0; }' > conftest.$ac_ext ac_cv_exeext= - if { (eval echo configure:1761: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then + if { (eval echo configure:1794: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then for file in conftest.*; do case $file in - *.c | *.o | *.obj) ;; + *.c | *.o | *.obj | *.ilk | *.pdb) ;; *) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;; esac done @@ -1784,7 +1817,7 @@ case $deplibs_check_method in file_magic*) if test "$file_magic_cmd" = '$MAGIC_CMD'; then echo $ac_n "checking for ${ac_tool_prefix}file""... $ac_c" 1>&6 -echo "configure:1788: checking for ${ac_tool_prefix}file" >&5 +echo "configure:1821: checking for ${ac_tool_prefix}file" >&5 if eval "test \"`echo '$''{'lt_cv_path_MAGIC_CMD'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1846,7 +1879,7 @@ fi if test -z "$lt_cv_path_MAGIC_CMD"; then if test -n "$ac_tool_prefix"; then echo $ac_n "checking for file""... $ac_c" 1>&6 -echo "configure:1850: checking for file" >&5 +echo "configure:1883: checking for file" >&5 if eval "test \"`echo '$''{'lt_cv_path_MAGIC_CMD'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1917,7 +1950,7 @@ esac # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ac_tool_prefix}ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1921: checking for $ac_word" >&5 +echo "configure:1954: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1949,7 +1982,7 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1953: checking for $ac_word" >&5 +echo "configure:1986: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -1984,7 +2017,7 @@ fi # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. set dummy ${ac_tool_prefix}strip; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:1988: checking for $ac_word" >&5 +echo "configure:2021: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_STRIP'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2016,7 +2049,7 @@ if test -n "$ac_tool_prefix"; then # Extract the first word of "strip", so it can be a program name with args. set dummy strip; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2020: checking for $ac_word" >&5 +echo "configure:2053: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_STRIP'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2083,8 +2116,21 @@ test x"$pic_mode" = xno && libtool_flags="$libtool_flags --prefer-non-pic" case $host in *-*-irix6*) # Find out which ABI we are using. - echo '#line 2087 "configure"' > conftest.$ac_ext - if { (eval echo configure:2088: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + echo '#line 2120 "configure"' > conftest.$ac_ext + if { (eval echo configure:2121: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + if test "$lt_cv_prog_gnu_ld" = yes; then + case `/usr/bin/file conftest.$ac_objext` in + *32-bit*) + LD="${LD-ld} -melf32bsmip" + ;; + *N32*) + LD="${LD-ld} -melf32bmipn32" + ;; + *64-bit*) + LD="${LD-ld} -melf64bmip" + ;; + esac + else case `/usr/bin/file conftest.$ac_objext` in *32-bit*) LD="${LD-ld} -32" @@ -2096,6 +2142,7 @@ case $host in LD="${LD-ld} -64" ;; esac + fi fi rm -rf conftest* ;; @@ -2103,7 +2150,7 @@ case $host in ia64-*-hpux*) # Find out which ABI we are using. echo 'int i;' > conftest.$ac_ext - if { (eval echo configure:2107: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then + if { (eval echo configure:2154: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then case "`/usr/bin/file conftest.o`" in *ELF-32*) HPUX_IA64_MODE="32" @@ -2121,7 +2168,7 @@ ia64-*-hpux*) SAVE_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS -belf" echo $ac_n "checking whether the C compiler needs -belf""... $ac_c" 1>&6 -echo "configure:2125: checking whether the C compiler needs -belf" >&5 +echo "configure:2172: checking whether the C compiler needs -belf" >&5 if eval "test \"`echo '$''{'lt_cv_cc_needs_belf'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2134,14 +2181,14 @@ ac_link='${CC-cc} -o conftest${ac_exeext} $CFLAGS $CPPFLAGS $LDFLAGS conftest.$a cross_compiling=$ac_cv_prog_cc_cross cat > conftest.$ac_ext <<EOF -#line 2138 "configure" +#line 2185 "configure" #include "confdefs.h" int main() { ; return 0; } EOF -if { (eval echo configure:2145: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2192: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* lt_cv_cc_needs_belf=yes else @@ -2309,7 +2356,7 @@ if test -z "$target" ; then fi echo $ac_n "checking whether to enable maintainer-specific portions of Makefiles""... $ac_c" 1>&6 -echo "configure:2313: checking whether to enable maintainer-specific portions of Makefiles" >&5 +echo "configure:2360: checking whether to enable maintainer-specific portions of Makefiles" >&5 # Check whether --enable-maintainer-mode or --disable-maintainer-mode was given. if test "${enable_maintainer_mode+set}" = set; then enableval="$enable_maintainer_mode" @@ -2332,13 +2379,13 @@ fi echo $ac_n "checking whether to install libbfd""... $ac_c" 1>&6 -echo "configure:2336: checking whether to install libbfd" >&5 +echo "configure:2383: checking whether to install libbfd" >&5 # Check whether --enable-install-libbfd or --disable-install-libbfd was given. if test "${enable_install_libbfd+set}" = set; then enableval="$enable_install_libbfd" install_libbfd_p=$enableval else - if test "${host}" = "${target}" -o "$enable_shared" = "yes"; then + if test "${host}" = "${target}" || test "$enable_shared" = "yes"; then install_libbfd_p=yes else install_libbfd_p=no @@ -2369,7 +2416,7 @@ fi echo $ac_n "checking for executable suffix""... $ac_c" 1>&6 -echo "configure:2373: checking for executable suffix" >&5 +echo "configure:2420: checking for executable suffix" >&5 if eval "test \"`echo '$''{'ac_cv_exeext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2379,10 +2426,10 @@ else rm -f conftest* echo 'int main () { return 0; }' > conftest.$ac_ext ac_cv_exeext= - if { (eval echo configure:2383: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then + if { (eval echo configure:2430: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; }; then for file in conftest.*; do case $file in - *.c | *.o | *.obj) ;; + *.c | *.o | *.obj | *.ilk | *.pdb) ;; *) ac_cv_exeext=`echo $file | sed -e s/conftest//` ;; esac done @@ -2405,7 +2452,7 @@ ac_exeext=$EXEEXT # Extract the first word of "gcc", so it can be a program name with args. set dummy gcc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2409: checking for $ac_word" >&5 +echo "configure:2456: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2435,7 +2482,7 @@ if test -z "$CC"; then # Extract the first word of "cc", so it can be a program name with args. set dummy cc; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2439: checking for $ac_word" >&5 +echo "configure:2486: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2486,7 +2533,7 @@ fi # Extract the first word of "cl", so it can be a program name with args. set dummy cl; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2490: checking for $ac_word" >&5 +echo "configure:2537: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_CC'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2518,7 +2565,7 @@ fi fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works""... $ac_c" 1>&6 -echo "configure:2522: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 +echo "configure:2569: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) works" >&5 ac_ext=c # CFLAGS is not in ac_cpp because -g, -O, etc. are not valid cpp options. @@ -2529,12 +2576,12 @@ cross_compiling=$ac_cv_prog_cc_cross cat > conftest.$ac_ext << EOF -#line 2533 "configure" +#line 2580 "configure" #include "confdefs.h" main(){return(0);} EOF -if { (eval echo configure:2538: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:2585: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then ac_cv_prog_cc_works=yes # If we can't run a trivial program, we are probably using a cross compiler. if (./conftest; exit) 2>/dev/null; then @@ -2560,12 +2607,12 @@ if test $ac_cv_prog_cc_works = no; then { echo "configure: error: installation or configuration problem: C compiler cannot create executables." 1>&2; exit 1; } fi echo $ac_n "checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler""... $ac_c" 1>&6 -echo "configure:2564: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 +echo "configure:2611: checking whether the C compiler ($CC $CFLAGS $LDFLAGS) is a cross-compiler" >&5 echo "$ac_t""$ac_cv_prog_cc_cross" 1>&6 cross_compiling=$ac_cv_prog_cc_cross echo $ac_n "checking whether we are using GNU C""... $ac_c" 1>&6 -echo "configure:2569: checking whether we are using GNU C" >&5 +echo "configure:2616: checking whether we are using GNU C" >&5 if eval "test \"`echo '$''{'ac_cv_prog_gcc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2574,7 +2621,7 @@ else yes; #endif EOF -if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:2578: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then +if { ac_try='${CC-cc} -E conftest.c'; { (eval echo configure:2625: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; }; } | egrep yes >/dev/null 2>&1; then ac_cv_prog_gcc=yes else ac_cv_prog_gcc=no @@ -2593,7 +2640,7 @@ ac_test_CFLAGS="${CFLAGS+set}" ac_save_CFLAGS="$CFLAGS" CFLAGS= echo $ac_n "checking whether ${CC-cc} accepts -g""... $ac_c" 1>&6 -echo "configure:2597: checking whether ${CC-cc} accepts -g" >&5 +echo "configure:2644: checking whether ${CC-cc} accepts -g" >&5 if eval "test \"`echo '$''{'ac_cv_prog_cc_g'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2625,9 +2672,9 @@ else fi -ALL_LINGUAS="fr sv tr es da de id pt_BR" +ALL_LINGUAS="fr sv tr es da de id pt_BR ro nl" echo $ac_n "checking how to run the C preprocessor""... $ac_c" 1>&6 -echo "configure:2631: checking how to run the C preprocessor" >&5 +echo "configure:2678: checking how to run the C preprocessor" >&5 # On Suns, sometimes $CPP names a directory. if test -n "$CPP" && test -d "$CPP"; then CPP= @@ -2642,13 +2689,13 @@ else # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. cat > conftest.$ac_ext <<EOF -#line 2646 "configure" +#line 2693 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2652: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2699: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -2659,13 +2706,13 @@ else rm -rf conftest* CPP="${CC-cc} -E -traditional-cpp" cat > conftest.$ac_ext <<EOF -#line 2663 "configure" +#line 2710 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2669: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2716: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -2676,13 +2723,13 @@ else rm -rf conftest* CPP="${CC-cc} -nologo -E" cat > conftest.$ac_ext <<EOF -#line 2680 "configure" +#line 2727 "configure" #include "confdefs.h" #include <assert.h> Syntax Error EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2686: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2733: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then : @@ -2709,7 +2756,7 @@ echo "$ac_t""$CPP" 1>&6 # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:2713: checking for $ac_word" >&5 +echo "configure:2760: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_prog_RANLIB'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -2737,12 +2784,12 @@ else fi echo $ac_n "checking for ANSI C header files""... $ac_c" 1>&6 -echo "configure:2741: checking for ANSI C header files" >&5 +echo "configure:2788: checking for ANSI C header files" >&5 if eval "test \"`echo '$''{'ac_cv_header_stdc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2746 "configure" +#line 2793 "configure" #include "confdefs.h" #include <stdlib.h> #include <stdarg.h> @@ -2750,7 +2797,7 @@ else #include <float.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:2754: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:2801: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -2767,7 +2814,7 @@ rm -f conftest* if test $ac_cv_header_stdc = yes; then # SunOS 4.x string.h does not declare mem*, contrary to ANSI. cat > conftest.$ac_ext <<EOF -#line 2771 "configure" +#line 2818 "configure" #include "confdefs.h" #include <string.h> EOF @@ -2785,7 +2832,7 @@ fi if test $ac_cv_header_stdc = yes; then # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. cat > conftest.$ac_ext <<EOF -#line 2789 "configure" +#line 2836 "configure" #include "confdefs.h" #include <stdlib.h> EOF @@ -2806,7 +2853,7 @@ if test "$cross_compiling" = yes; then : else cat > conftest.$ac_ext <<EOF -#line 2810 "configure" +#line 2857 "configure" #include "confdefs.h" #include <ctype.h> #define ISLOWER(c) ('a' <= (c) && (c) <= 'z') @@ -2817,7 +2864,7 @@ if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) exit(2); exit (0); } EOF -if { (eval echo configure:2821: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:2868: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then : else @@ -2841,12 +2888,12 @@ EOF fi echo $ac_n "checking for working const""... $ac_c" 1>&6 -echo "configure:2845: checking for working const" >&5 +echo "configure:2892: checking for working const" >&5 if eval "test \"`echo '$''{'ac_cv_c_const'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2850 "configure" +#line 2897 "configure" #include "confdefs.h" int main() { @@ -2895,7 +2942,7 @@ ccp = (char const *const *) p; ; return 0; } EOF -if { (eval echo configure:2899: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:2946: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_c_const=yes else @@ -2916,21 +2963,21 @@ EOF fi echo $ac_n "checking for inline""... $ac_c" 1>&6 -echo "configure:2920: checking for inline" >&5 +echo "configure:2967: checking for inline" >&5 if eval "test \"`echo '$''{'ac_cv_c_inline'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else ac_cv_c_inline=no for ac_kw in inline __inline__ __inline; do cat > conftest.$ac_ext <<EOF -#line 2927 "configure" +#line 2974 "configure" #include "confdefs.h" int main() { } $ac_kw foo() { ; return 0; } EOF -if { (eval echo configure:2934: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then +if { (eval echo configure:2981: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>&5; }; then rm -rf conftest* ac_cv_c_inline=$ac_kw; break else @@ -2956,12 +3003,12 @@ EOF esac echo $ac_n "checking for off_t""... $ac_c" 1>&6 -echo "configure:2960: checking for off_t" >&5 +echo "configure:3007: checking for off_t" >&5 if eval "test \"`echo '$''{'ac_cv_type_off_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2965 "configure" +#line 3012 "configure" #include "confdefs.h" #include <sys/types.h> #if STDC_HEADERS @@ -2989,12 +3036,12 @@ EOF fi echo $ac_n "checking for size_t""... $ac_c" 1>&6 -echo "configure:2993: checking for size_t" >&5 +echo "configure:3040: checking for size_t" >&5 if eval "test \"`echo '$''{'ac_cv_type_size_t'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 2998 "configure" +#line 3045 "configure" #include "confdefs.h" #include <sys/types.h> #if STDC_HEADERS @@ -3024,19 +3071,19 @@ fi # The Ultrix 4.2 mips builtin alloca declared by alloca.h only works # for constant arguments. Useless! echo $ac_n "checking for working alloca.h""... $ac_c" 1>&6 -echo "configure:3028: checking for working alloca.h" >&5 +echo "configure:3075: checking for working alloca.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_alloca_h'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3033 "configure" +#line 3080 "configure" #include "confdefs.h" #include <alloca.h> int main() { char *p = alloca(2 * sizeof(int)); ; return 0; } EOF -if { (eval echo configure:3040: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3087: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* ac_cv_header_alloca_h=yes else @@ -3057,12 +3104,12 @@ EOF fi echo $ac_n "checking for alloca""... $ac_c" 1>&6 -echo "configure:3061: checking for alloca" >&5 +echo "configure:3108: checking for alloca" >&5 if eval "test \"`echo '$''{'ac_cv_func_alloca_works'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3066 "configure" +#line 3113 "configure" #include "confdefs.h" #ifdef __GNUC__ @@ -3090,7 +3137,7 @@ int main() { char *p = (char *) alloca(1); ; return 0; } EOF -if { (eval echo configure:3094: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3141: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* ac_cv_func_alloca_works=yes else @@ -3122,12 +3169,12 @@ EOF echo $ac_n "checking whether alloca needs Cray hooks""... $ac_c" 1>&6 -echo "configure:3126: checking whether alloca needs Cray hooks" >&5 +echo "configure:3173: checking whether alloca needs Cray hooks" >&5 if eval "test \"`echo '$''{'ac_cv_os_cray'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3131 "configure" +#line 3178 "configure" #include "confdefs.h" #if defined(CRAY) && ! defined(CRAY2) webecray @@ -3152,12 +3199,12 @@ echo "$ac_t""$ac_cv_os_cray" 1>&6 if test $ac_cv_os_cray = yes; then for ac_func in _getb67 GETB67 getb67; do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3156: checking for $ac_func" >&5 +echo "configure:3203: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3161 "configure" +#line 3208 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3180,7 +3227,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3184: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3231: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3207,7 +3254,7 @@ done fi echo $ac_n "checking stack direction for C alloca""... $ac_c" 1>&6 -echo "configure:3211: checking stack direction for C alloca" >&5 +echo "configure:3258: checking stack direction for C alloca" >&5 if eval "test \"`echo '$''{'ac_cv_c_stack_direction'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3215,7 +3262,7 @@ else ac_cv_c_stack_direction=0 else cat > conftest.$ac_ext <<EOF -#line 3219 "configure" +#line 3266 "configure" #include "confdefs.h" find_stack_direction () { @@ -3234,7 +3281,7 @@ main () exit (find_stack_direction() < 0); } EOF -if { (eval echo configure:3238: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:3285: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_c_stack_direction=1 else @@ -3255,21 +3302,21 @@ EOF fi -for ac_hdr in stdlib.h unistd.h sys/stat.h sys/types.h +for ac_hdr in unistd.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:3263: checking for $ac_hdr" >&5 +echo "configure:3310: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3268 "configure" +#line 3315 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3273: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3320: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3298,12 +3345,12 @@ done for ac_func in getpagesize do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3302: checking for $ac_func" >&5 +echo "configure:3349: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3307 "configure" +#line 3354 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3326,7 +3373,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3330: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3377: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3351,7 +3398,7 @@ fi done echo $ac_n "checking for working mmap""... $ac_c" 1>&6 -echo "configure:3355: checking for working mmap" >&5 +echo "configure:3402: checking for working mmap" >&5 if eval "test \"`echo '$''{'ac_cv_func_mmap_fixed_mapped'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3359,7 +3406,7 @@ else ac_cv_func_mmap_fixed_mapped=no else cat > conftest.$ac_ext <<EOF -#line 3363 "configure" +#line 3410 "configure" #include "confdefs.h" /* Thanks to Mike Haertel and Jim Avera for this test. @@ -3387,24 +3434,11 @@ else #include <fcntl.h> #include <sys/mman.h> -#if HAVE_SYS_TYPES_H -# include <sys/types.h> -#endif - -#if HAVE_STDLIB_H -# include <stdlib.h> -#endif - -#if HAVE_SYS_STAT_H -# include <sys/stat.h> -#endif - -#if HAVE_UNISTD_H -# include <unistd.h> -#endif - /* This mess was copied from the GNU getpagesize.h. */ #ifndef HAVE_GETPAGESIZE +# ifdef HAVE_UNISTD_H +# include <unistd.h> +# endif /* Assume that all systems that can run configure have sys/param.h. */ # ifndef HAVE_SYS_PARAM_H @@ -3512,7 +3546,7 @@ main() } EOF -if { (eval echo configure:3516: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null +if { (eval echo configure:3550: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext} && (./conftest; exit) 2>/dev/null then ac_cv_func_mmap_fixed_mapped=yes else @@ -3540,17 +3574,17 @@ unistd.h values.h sys/param.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:3544: checking for $ac_hdr" >&5 +echo "configure:3578: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3549 "configure" +#line 3583 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3554: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3588: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3580,12 +3614,12 @@ done __argz_count __argz_stringify __argz_next do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3584: checking for $ac_func" >&5 +echo "configure:3618: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3589 "configure" +#line 3623 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3608,7 +3642,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3612: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3646: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3637,12 +3671,12 @@ done for ac_func in stpcpy do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3641: checking for $ac_func" >&5 +echo "configure:3675: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3646 "configure" +#line 3680 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3665,7 +3699,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3669: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3703: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3699,19 +3733,19 @@ EOF if test $ac_cv_header_locale_h = yes; then echo $ac_n "checking for LC_MESSAGES""... $ac_c" 1>&6 -echo "configure:3703: checking for LC_MESSAGES" >&5 +echo "configure:3737: checking for LC_MESSAGES" >&5 if eval "test \"`echo '$''{'am_cv_val_LC_MESSAGES'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3708 "configure" +#line 3742 "configure" #include "confdefs.h" #include <locale.h> int main() { return LC_MESSAGES ; return 0; } EOF -if { (eval echo configure:3715: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3749: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* am_cv_val_LC_MESSAGES=yes else @@ -3732,7 +3766,7 @@ EOF fi fi echo $ac_n "checking whether NLS is requested""... $ac_c" 1>&6 -echo "configure:3736: checking whether NLS is requested" >&5 +echo "configure:3770: checking whether NLS is requested" >&5 # Check whether --enable-nls or --disable-nls was given. if test "${enable_nls+set}" = set; then enableval="$enable_nls" @@ -3752,7 +3786,7 @@ fi EOF echo $ac_n "checking whether included gettext is requested""... $ac_c" 1>&6 -echo "configure:3756: checking whether included gettext is requested" >&5 +echo "configure:3790: checking whether included gettext is requested" >&5 # Check whether --with-included-gettext or --without-included-gettext was given. if test "${with_included_gettext+set}" = set; then withval="$with_included_gettext" @@ -3771,17 +3805,17 @@ fi ac_safe=`echo "libintl.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for libintl.h""... $ac_c" 1>&6 -echo "configure:3775: checking for libintl.h" >&5 +echo "configure:3809: checking for libintl.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3780 "configure" +#line 3814 "configure" #include "confdefs.h" #include <libintl.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:3785: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:3819: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -3798,19 +3832,19 @@ fi if eval "test \"`echo '$ac_cv_header_'$ac_safe`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libc""... $ac_c" 1>&6 -echo "configure:3802: checking for gettext in libc" >&5 +echo "configure:3836: checking for gettext in libc" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libc'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3807 "configure" +#line 3841 "configure" #include "confdefs.h" #include <libintl.h> int main() { return (int) gettext ("") ; return 0; } EOF -if { (eval echo configure:3814: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3848: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libc=yes else @@ -3826,7 +3860,7 @@ echo "$ac_t""$gt_cv_func_gettext_libc" 1>&6 if test "$gt_cv_func_gettext_libc" != "yes"; then echo $ac_n "checking for bindtextdomain in -lintl""... $ac_c" 1>&6 -echo "configure:3830: checking for bindtextdomain in -lintl" >&5 +echo "configure:3864: checking for bindtextdomain in -lintl" >&5 ac_lib_var=`echo intl'_'bindtextdomain | sed 'y%./+-%__p_%'` if eval "test \"`echo '$''{'ac_cv_lib_$ac_lib_var'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -3834,7 +3868,7 @@ else ac_save_LIBS="$LIBS" LIBS="-lintl $LIBS" cat > conftest.$ac_ext <<EOF -#line 3838 "configure" +#line 3872 "configure" #include "confdefs.h" /* Override any gcc2 internal prototype to avoid an error. */ /* We use char because int might match the return type of a gcc2 @@ -3845,7 +3879,7 @@ int main() { bindtextdomain() ; return 0; } EOF -if { (eval echo configure:3849: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3883: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_lib_$ac_lib_var=yes" else @@ -3861,19 +3895,19 @@ fi if eval "test \"`echo '$ac_cv_lib_'$ac_lib_var`\" = yes"; then echo "$ac_t""yes" 1>&6 echo $ac_n "checking for gettext in libintl""... $ac_c" 1>&6 -echo "configure:3865: checking for gettext in libintl" >&5 +echo "configure:3899: checking for gettext in libintl" >&5 if eval "test \"`echo '$''{'gt_cv_func_gettext_libintl'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3870 "configure" +#line 3904 "configure" #include "confdefs.h" int main() { return (int) gettext ("") ; return 0; } EOF -if { (eval echo configure:3877: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:3911: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* gt_cv_func_gettext_libintl=yes else @@ -3901,7 +3935,7 @@ EOF # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3905: checking for $ac_word" >&5 +echo "configure:3939: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -3935,12 +3969,12 @@ fi for ac_func in dcgettext do echo $ac_n "checking for $ac_func""... $ac_c" 1>&6 -echo "configure:3939: checking for $ac_func" >&5 +echo "configure:3973: checking for $ac_func" >&5 if eval "test \"`echo '$''{'ac_cv_func_$ac_func'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 3944 "configure" +#line 3978 "configure" #include "confdefs.h" /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $ac_func(); below. */ @@ -3963,7 +3997,7 @@ $ac_func(); ; return 0; } EOF -if { (eval echo configure:3967: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4001: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* eval "ac_cv_func_$ac_func=yes" else @@ -3990,7 +4024,7 @@ done # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:3994: checking for $ac_word" >&5 +echo "configure:4028: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4026,7 +4060,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4030: checking for $ac_word" >&5 +echo "configure:4064: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4058,7 +4092,7 @@ else fi cat > conftest.$ac_ext <<EOF -#line 4062 "configure" +#line 4096 "configure" #include "confdefs.h" int main() { @@ -4066,7 +4100,7 @@ extern int _nl_msg_cat_cntr; return _nl_msg_cat_cntr ; return 0; } EOF -if { (eval echo configure:4070: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then +if { (eval echo configure:4104: \"$ac_link\") 1>&5; (eval $ac_link) 2>&5; } && test -s conftest${ac_exeext}; then rm -rf conftest* CATOBJEXT=.gmo DATADIRNAME=share @@ -4098,7 +4132,7 @@ fi # Extract the first word of "msgfmt", so it can be a program name with args. set dummy msgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4102: checking for $ac_word" >&5 +echo "configure:4136: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_MSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4132,7 +4166,7 @@ fi # Extract the first word of "gmsgfmt", so it can be a program name with args. set dummy gmsgfmt; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4136: checking for $ac_word" >&5 +echo "configure:4170: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_GMSGFMT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4168,7 +4202,7 @@ fi # Extract the first word of "xgettext", so it can be a program name with args. set dummy xgettext; ac_word=$2 echo $ac_n "checking for $ac_word""... $ac_c" 1>&6 -echo "configure:4172: checking for $ac_word" >&5 +echo "configure:4206: checking for $ac_word" >&5 if eval "test \"`echo '$''{'ac_cv_path_XGETTEXT'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4258,7 +4292,7 @@ fi LINGUAS= else echo $ac_n "checking for catalogs to be installed""... $ac_c" 1>&6 -echo "configure:4262: checking for catalogs to be installed" >&5 +echo "configure:4296: checking for catalogs to be installed" >&5 NEW_LINGUAS= for lang in ${LINGUAS=$ALL_LINGUAS}; do case "$ALL_LINGUAS" in @@ -4286,17 +4320,17 @@ echo "configure:4262: checking for catalogs to be installed" >&5 if test "$CATOBJEXT" = ".cat"; then ac_safe=`echo "linux/version.h" | sed 'y%./+-%__p_%'` echo $ac_n "checking for linux/version.h""... $ac_c" 1>&6 -echo "configure:4290: checking for linux/version.h" >&5 +echo "configure:4324: checking for linux/version.h" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4295 "configure" +#line 4329 "configure" #include "confdefs.h" #include <linux/version.h> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4300: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4334: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4374,7 +4408,7 @@ if test "x$cross_compiling" = "xno"; then EXEEXT_FOR_BUILD='$(EXEEXT)' else echo $ac_n "checking for build system executable suffix""... $ac_c" 1>&6 -echo "configure:4378: checking for build system executable suffix" >&5 +echo "configure:4412: checking for build system executable suffix" >&5 if eval "test \"`echo '$''{'bfd_cv_build_exeext'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else @@ -4411,7 +4445,7 @@ fi # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # ./install, which can be erroneously created by make from ./install.sh. echo $ac_n "checking for a BSD compatible install""... $ac_c" 1>&6 -echo "configure:4415: checking for a BSD compatible install" >&5 +echo "configure:4449: checking for a BSD compatible install" >&5 if test -z "$INSTALL"; then if eval "test \"`echo '$''{'ac_cv_path_install'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 @@ -4468,17 +4502,17 @@ for ac_hdr in string.h strings.h stdlib.h do ac_safe=`echo "$ac_hdr" | sed 'y%./+-%__p_%'` echo $ac_n "checking for $ac_hdr""... $ac_c" 1>&6 -echo "configure:4472: checking for $ac_hdr" >&5 +echo "configure:4506: checking for $ac_hdr" >&5 if eval "test \"`echo '$''{'ac_cv_header_$ac_safe'+set}'`\" = set"; then echo $ac_n "(cached) $ac_c" 1>&6 else cat > conftest.$ac_ext <<EOF -#line 4477 "configure" +#line 4511 "configure" #include "confdefs.h" #include <$ac_hdr> EOF ac_try="$ac_cpp conftest.$ac_ext >/dev/null 2>conftest.out" -{ (eval echo configure:4482: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } +{ (eval echo configure:4516: \"$ac_try\") 1>&5; (eval $ac_try) 2>&5; } ac_err=`grep -v '^ *+' conftest.out | grep -v "^conftest.${ac_ext}\$"` if test -z "$ac_err"; then rm -rf conftest* @@ -4614,6 +4648,8 @@ if test x${all_targets} = xfalse ; then bfd_i860_arch) ta="$ta i860-dis.lo" ;; bfd_i960_arch) ta="$ta i960-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; + bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; + bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;; bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; @@ -4624,6 +4660,7 @@ if test x${all_targets} = xfalse ; then bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; + bfd_msp430_arch) ta="$ta msp430-dis.lo" ;; bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; bfd_or32_arch) ta="$ta or32-dis.lo or32-opc.lo" using_cgen=yes ;; @@ -4653,6 +4690,7 @@ if test x${all_targets} = xfalse ; then bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; bfd_tahoe_arch) ;; bfd_tic30_arch) ta="$ta tic30-dis.lo" ;; + bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;; bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;; bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; @@ -4662,6 +4700,7 @@ if test x${all_targets} = xfalse ; then bfd_w65_arch) ta="$ta w65-dis.lo" ;; bfd_we32k_arch) ;; bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; + bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;; bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; @@ -4852,7 +4891,6 @@ s%@build_alias@%$build_alias%g s%@build_cpu@%$build_cpu%g s%@build_vendor@%$build_vendor%g s%@build_os@%$build_os%g -s%@CC@%$CC%g s%@INSTALL_PROGRAM@%$INSTALL_PROGRAM%g s%@INSTALL_SCRIPT@%$INSTALL_SCRIPT%g s%@INSTALL_DATA@%$INSTALL_DATA%g @@ -4866,6 +4904,7 @@ s%@MAKEINFO@%$MAKEINFO%g s%@SET_MAKE@%$SET_MAKE%g s%@AR@%$AR%g s%@RANLIB@%$RANLIB%g +s%@CC@%$CC%g s%@LN_S@%$LN_S%g s%@OBJEXT@%$OBJEXT%g s%@EXEEXT@%$EXEEXT%g diff --git a/contrib/binutils/opcodes/configure.in b/contrib/binutils/opcodes/configure.in index 3183bc7..8919924 100644 --- a/contrib/binutils/opcodes/configure.in +++ b/contrib/binutils/opcodes/configure.in @@ -78,7 +78,7 @@ AC_EXEEXT AC_PROG_CC -ALL_LINGUAS="fr sv tr es da de id pt_BR" +ALL_LINGUAS="fr sv tr es da de id pt_BR ro nl" CY_GNU_GETTEXT . ${srcdir}/../bfd/configure.host @@ -189,6 +189,8 @@ if test x${all_targets} = xfalse ; then bfd_i860_arch) ta="$ta i860-dis.lo" ;; bfd_i960_arch) ta="$ta i960-dis.lo" ;; bfd_ia64_arch) ta="$ta ia64-dis.lo ia64-opc.lo" ;; + bfd_ip2k_arch) ta="$ta ip2k-asm.lo ip2k-desc.lo ip2k-dis.lo ip2k-ibld.lo ip2k-opc.lo" using_cgen=yes ;; + bfd_iq2000_arch) ta="$ta iq2000-asm.lo iq2000-desc.lo iq2000-dis.lo iq2000-ibld.lo iq2000-opc.lo" using_cgen=yes ;; bfd_m32r_arch) ta="$ta m32r-asm.lo m32r-desc.lo m32r-dis.lo m32r-ibld.lo m32r-opc.lo m32r-opinst.lo" using_cgen=yes ;; bfd_m68hc11_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; bfd_m68hc12_arch) ta="$ta m68hc11-dis.lo m68hc11-opc.lo" ;; @@ -199,6 +201,7 @@ if test x${all_targets} = xfalse ; then bfd_mmix_arch) ta="$ta mmix-dis.lo mmix-opc.lo" ;; bfd_mn10200_arch) ta="$ta m10200-dis.lo m10200-opc.lo" ;; bfd_mn10300_arch) ta="$ta m10300-dis.lo m10300-opc.lo" ;; + bfd_msp430_arch) ta="$ta msp430-dis.lo" ;; bfd_ns32k_arch) ta="$ta ns32k-dis.lo" ;; bfd_openrisc_arch) ta="$ta openrisc-asm.lo openrisc-desc.lo openrisc-dis.lo openrisc-ibld.lo openrisc-opc.lo" using_cgen=yes ;; bfd_or32_arch) ta="$ta or32-dis.lo or32-opc.lo" using_cgen=yes ;; @@ -228,6 +231,7 @@ if test x${all_targets} = xfalse ; then bfd_sparc_arch) ta="$ta sparc-dis.lo sparc-opc.lo" ;; bfd_tahoe_arch) ;; bfd_tic30_arch) ta="$ta tic30-dis.lo" ;; + bfd_tic4x_arch) ta="$ta tic4x-dis.lo" ;; bfd_tic54x_arch) ta="$ta tic54x-dis.lo tic54x-opc.lo" ;; bfd_tic80_arch) ta="$ta tic80-dis.lo tic80-opc.lo" ;; bfd_v850_arch) ta="$ta v850-opc.lo v850-dis.lo" ;; @@ -237,6 +241,7 @@ if test x${all_targets} = xfalse ; then bfd_w65_arch) ta="$ta w65-dis.lo" ;; bfd_we32k_arch) ;; bfd_xstormy16_arch) ta="$ta xstormy16-asm.lo xstormy16-desc.lo xstormy16-dis.lo xstormy16-ibld.lo xstormy16-opc.lo" using_cgen=yes ;; + bfd_xtensa_arch) ta="$ta xtensa-dis.lo" ;; bfd_z8k_arch) ta="$ta z8k-dis.lo" ;; bfd_frv_arch) ta="$ta frv-asm.lo frv-desc.lo frv-dis.lo frv-ibld.lo frv-opc.lo" using_cgen=yes ;; diff --git a/contrib/binutils/opcodes/dep-in.sed b/contrib/binutils/opcodes/dep-in.sed index e373d4c..94da2ad 100644 --- a/contrib/binutils/opcodes/dep-in.sed +++ b/contrib/binutils/opcodes/dep-in.sed @@ -10,6 +10,7 @@ s!@TOPDIR@/include!$(INCDIR)!g s!@BFDDIR@!$(BFDDIR)!g s!@TOPDIR@/bfd!$(BFDDIR)!g s!@SRCDIR@/!!g +s! \.\./intl/libintl\.h!!g s/\\\n */ /g diff --git a/contrib/binutils/opcodes/dis-buf.c b/contrib/binutils/opcodes/dis-buf.c index 8f846a9..83fbfbd 100644 --- a/contrib/binutils/opcodes/dis-buf.c +++ b/contrib/binutils/opcodes/dis-buf.c @@ -107,7 +107,7 @@ generic_strcat_address (addr, buf, len) } #endif -/* Just return the given address. */ +/* Just return true. */ int generic_symbol_at_address (addr, info) @@ -116,3 +116,12 @@ generic_symbol_at_address (addr, info) { return 1; } + +/* Just return TRUE. */ + +bfd_boolean +generic_symbol_is_valid (asymbol * sym ATTRIBUTE_UNUSED, + struct disassemble_info *info ATTRIBUTE_UNUSED) +{ + return TRUE; +} diff --git a/contrib/binutils/opcodes/dis-init.c b/contrib/binutils/opcodes/dis-init.c new file mode 100644 index 0000000..35a5ee7 --- /dev/null +++ b/contrib/binutils/opcodes/dis-init.c @@ -0,0 +1,43 @@ +/* Initialize "struct disassemble_info". + + Copyright 2003 Free Software Foundation, Inc. + + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2 of the + License, or (at your option) any later version. + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +#include "sysdep.h" +#include "dis-asm.h" +#include "bfd.h" + +void +init_disassemble_info (struct disassemble_info *info, void *stream, + fprintf_ftype fprintf_func) +{ + memset (info, 0, sizeof (*info)); + + info->flavour = bfd_target_unknown_flavour; + info->arch = bfd_arch_unknown; + info->endian = BFD_ENDIAN_UNKNOWN; + info->octets_per_byte = 1; + info->fprintf_func = fprintf_func; + info->stream = stream; + info->read_memory_func = buffer_read_memory; + info->memory_error_func = perror_memory; + info->print_address_func = generic_print_address; + info->symbol_at_address_func = generic_symbol_at_address; + info->symbol_is_valid = generic_symbol_is_valid; + info->display_endian = BFD_ENDIAN_UNKNOWN; +} + diff --git a/contrib/binutils/opcodes/disassemble.c b/contrib/binutils/opcodes/disassemble.c index 7c586c7..d5b17be 100644 --- a/contrib/binutils/opcodes/disassemble.c +++ b/contrib/binutils/opcodes/disassemble.c @@ -36,6 +36,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ARCH_i386 #define ARCH_i860 #define ARCH_i960 +#define ARCH_ip2k #define ARCH_ia64 #define ARCH_fr30 #define ARCH_m32r @@ -48,6 +49,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ARCH_mmix #define ARCH_mn10200 #define ARCH_mn10300 +#define ARCH_msp430 #define ARCH_ns32k #define ARCH_openrisc #define ARCH_or32 @@ -59,14 +61,17 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define ARCH_sh #define ARCH_sparc #define ARCH_tic30 +#define ARCH_tic4x #define ARCH_tic54x #define ARCH_tic80 #define ARCH_v850 #define ARCH_vax #define ARCH_w65 #define ARCH_xstormy16 +#define ARCH_xtensa #define ARCH_z8k #define ARCH_frv +#define ARCH_iq2000 #define INCLUDE_SHMEDIA #endif @@ -136,9 +141,12 @@ disassembler (abfd) #endif #ifdef ARCH_h8300 case bfd_arch_h8300: - if (bfd_get_mach(abfd) == bfd_mach_h8300h) + if (bfd_get_mach (abfd) == bfd_mach_h8300h + || bfd_get_mach (abfd) == bfd_mach_h8300hn) disassemble = print_insn_h8300h; - else if (bfd_get_mach(abfd) == bfd_mach_h8300s) + else if (bfd_get_mach (abfd) == bfd_mach_h8300s + || bfd_get_mach (abfd) == bfd_mach_h8300sn + || bfd_get_mach (abfd) == bfd_mach_h8300sx) disassemble = print_insn_h8300s; else disassemble = print_insn_h8300; @@ -179,6 +187,11 @@ disassembler (abfd) disassemble = print_insn_ia64; break; #endif +#ifdef ARCH_ip2k + case bfd_arch_ip2k: + disassemble = print_insn_ip2k; + break; +#endif #ifdef ARCH_fr30 case bfd_arch_fr30: disassemble = print_insn_fr30; @@ -207,6 +220,11 @@ disassembler (abfd) disassemble = print_insn_m88k; break; #endif +#ifdef ARCH_msp430 + case bfd_arch_msp430: + disassemble = print_insn_msp430; + break; +#endif #ifdef ARCH_ns32k case bfd_arch_ns32k: disassemble = print_insn_ns32k; @@ -299,6 +317,11 @@ disassembler (abfd) disassemble = print_insn_tic30; break; #endif +#ifdef ARCH_tic4x + case bfd_arch_tic4x: + disassemble = print_insn_tic4x; + break; +#endif #ifdef ARCH_tic54x case bfd_arch_tic54x: disassemble = print_insn_tic54x; @@ -324,6 +347,11 @@ disassembler (abfd) disassemble = print_insn_xstormy16; break; #endif +#ifdef ARCH_xtensa + case bfd_arch_xtensa: + disassemble = print_insn_xtensa; + break; +#endif #ifdef ARCH_z8k case bfd_arch_z8k: if (bfd_get_mach(abfd) == bfd_mach_z8001) @@ -342,6 +370,11 @@ disassembler (abfd) disassemble = print_insn_frv; break; #endif +#ifdef ARCH_iq2000 + case bfd_arch_iq2000: + disassemble = print_insn_iq2000; + break; +#endif default: return 0; } @@ -355,9 +388,30 @@ disassembler_usage (stream) #ifdef ARCH_arm print_arm_disassembler_options (stream); #endif +#ifdef ARCH_mips + print_mips_disassembler_options (stream); +#endif #ifdef ARCH_powerpc print_ppc_disassembler_options (stream); #endif return; } + +void +disassemble_init_for_target (struct disassemble_info * info) +{ + if (info == NULL) + return; + + switch (info->arch) + { +#ifdef ARCH_arm + case bfd_arch_arm: + info->symbol_is_valid = arm_symbol_is_valid; + break; +#endif + default: + break; + } +} diff --git a/contrib/binutils/opcodes/i386-dis.c b/contrib/binutils/opcodes/i386-dis.c index d2271d8..a71eb0c 100644 --- a/contrib/binutils/opcodes/i386-dis.c +++ b/contrib/binutils/opcodes/i386-dis.c @@ -1,7 +1,6 @@ /* Print i386 instructions for GDB, the GNU debugger. Copyright 1988, 1989, 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2001 - Free Software Foundation, Inc. + 2001, 2002, 2003, 2004 Free Software Foundation, Inc. This file is part of GDB. @@ -24,6 +23,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ * July 1988 * modified by John Hassey (hassey@dg-rtp.dg.com) * x86-64 support added by Jan Hubicka (jh@suse.cz) + * VIA PadLock support by Michal Ludvig (mludvig@suse.cz) */ /* @@ -49,52 +49,58 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define UNIXWARE_COMPAT 1 #endif -static int fetch_data PARAMS ((struct disassemble_info *, bfd_byte *)); -static void ckprefix PARAMS ((void)); -static const char *prefix_name PARAMS ((int, int)); -static int print_insn PARAMS ((bfd_vma, disassemble_info *)); -static void dofloat PARAMS ((int)); -static void OP_ST PARAMS ((int, int)); -static void OP_STi PARAMS ((int, int)); -static int putop PARAMS ((const char *, int)); -static void oappend PARAMS ((const char *)); -static void append_seg PARAMS ((void)); -static void OP_indirE PARAMS ((int, int)); -static void print_operand_value PARAMS ((char *, int, bfd_vma)); -static void OP_E PARAMS ((int, int)); -static void OP_G PARAMS ((int, int)); -static bfd_vma get64 PARAMS ((void)); -static bfd_signed_vma get32 PARAMS ((void)); -static bfd_signed_vma get32s PARAMS ((void)); -static int get16 PARAMS ((void)); -static void set_op PARAMS ((bfd_vma, int)); -static void OP_REG PARAMS ((int, int)); -static void OP_IMREG PARAMS ((int, int)); -static void OP_I PARAMS ((int, int)); -static void OP_I64 PARAMS ((int, int)); -static void OP_sI PARAMS ((int, int)); -static void OP_J PARAMS ((int, int)); -static void OP_SEG PARAMS ((int, int)); -static void OP_DIR PARAMS ((int, int)); -static void OP_OFF PARAMS ((int, int)); -static void OP_OFF64 PARAMS ((int, int)); -static void ptr_reg PARAMS ((int, int)); -static void OP_ESreg PARAMS ((int, int)); -static void OP_DSreg PARAMS ((int, int)); -static void OP_C PARAMS ((int, int)); -static void OP_D PARAMS ((int, int)); -static void OP_T PARAMS ((int, int)); -static void OP_Rd PARAMS ((int, int)); -static void OP_MMX PARAMS ((int, int)); -static void OP_XMM PARAMS ((int, int)); -static void OP_EM PARAMS ((int, int)); -static void OP_EX PARAMS ((int, int)); -static void OP_MS PARAMS ((int, int)); -static void OP_XS PARAMS ((int, int)); -static void OP_3DNowSuffix PARAMS ((int, int)); -static void OP_SIMD_Suffix PARAMS ((int, int)); -static void SIMD_Fixup PARAMS ((int, int)); -static void BadOp PARAMS ((void)); +static int fetch_data (struct disassemble_info *, bfd_byte *); +static void ckprefix (void); +static const char *prefix_name (int, int); +static int print_insn (bfd_vma, disassemble_info *); +static void dofloat (int); +static void OP_ST (int, int); +static void OP_STi (int, int); +static int putop (const char *, int); +static void oappend (const char *); +static void append_seg (void); +static void OP_indirE (int, int); +static void print_operand_value (char *, int, bfd_vma); +static void OP_E (int, int); +static void OP_G (int, int); +static bfd_vma get64 (void); +static bfd_signed_vma get32 (void); +static bfd_signed_vma get32s (void); +static int get16 (void); +static void set_op (bfd_vma, int); +static void OP_REG (int, int); +static void OP_IMREG (int, int); +static void OP_I (int, int); +static void OP_I64 (int, int); +static void OP_sI (int, int); +static void OP_J (int, int); +static void OP_SEG (int, int); +static void OP_DIR (int, int); +static void OP_OFF (int, int); +static void OP_OFF64 (int, int); +static void ptr_reg (int, int); +static void OP_ESreg (int, int); +static void OP_DSreg (int, int); +static void OP_C (int, int); +static void OP_D (int, int); +static void OP_T (int, int); +static void OP_Rd (int, int); +static void OP_MMX (int, int); +static void OP_XMM (int, int); +static void OP_EM (int, int); +static void OP_EX (int, int); +static void OP_MS (int, int); +static void OP_XS (int, int); +static void OP_M (int, int); +static void OP_0fae (int, int); +static void OP_0f07 (int, int); +static void NOP_Fixup (int, int); +static void OP_3DNowSuffix (int, int); +static void OP_SIMD_Suffix (int, int); +static void SIMD_Fixup (int, int); +static void PNI_Fixup (int, int); +static void INVLPG_Fixup (int, int); +static void BadOp (void); struct dis_private { /* Points to first byte not fetched. */ @@ -161,9 +167,7 @@ static int used_prefixes; ? 1 : fetch_data ((info), (addr))) static int -fetch_data (info, addr) - struct disassemble_info *info; - bfd_byte *addr; +fetch_data (struct disassemble_info *info, bfd_byte *addr) { int status; struct dis_private *priv = (struct dis_private *) info->private_data; @@ -176,9 +180,9 @@ fetch_data (info, addr) if (status != 0) { /* If we did manage to read at least one byte, then - print_insn_i386 will do something sensible. Otherwise, print - an error. We do that here because this is where we know - STATUS. */ + print_insn_i386 will do something sensible. Otherwise, print + an error. We do that here because this is where we know + STATUS. */ if (priv->max_fetched == priv->the_buffer) (*info->memory_error_func) (status, start, info); longjmp (priv->bailout, 1); @@ -193,12 +197,13 @@ fetch_data (info, addr) #define Eb OP_E, b_mode #define Ev OP_E, v_mode #define Ed OP_E, d_mode +#define Edq OP_E, dq_mode #define indirEb OP_indirE, b_mode #define indirEv OP_indirE, v_mode #define Ew OP_E, w_mode #define Ma OP_E, v_mode -#define M OP_E, 0 /* lea, lgdt, etc. */ -#define Mp OP_E, 0 /* 32 or 48 bit memory operand for LDS, LES etc */ +#define M OP_M, 0 /* lea, lgdt, etc. */ +#define Mp OP_M, 0 /* 32 or 48 bit memory operand for LDS, LES etc */ #define Gb OP_G, b_mode #define Gv OP_G, v_mode #define Gd OP_G, d_mode @@ -291,7 +296,6 @@ fetch_data (info, addr) #define EX OP_EX, v_mode #define MS OP_MS, v_mode #define XS OP_XS, v_mode -#define None OP_E, 0 #define OPSUF OP_3DNowSuffix, 0 #define OPSIMD OP_SIMD_Suffix, 0 @@ -312,6 +316,7 @@ fetch_data (info, addr) #define m_mode 7 /* d_mode in 32bit, q_mode in 64bit mode. */ #define cond_jump_mode 8 #define loop_jcxz_mode 9 +#define dq_mode 10 /* operand size depends on REX prefixes. */ #define es_reg 100 #define cs_reg 101 @@ -388,6 +393,7 @@ fetch_data (info, addr) #define GRP13 NULL, NULL, USE_GROUPS, NULL, 20, NULL, 0 #define GRP14 NULL, NULL, USE_GROUPS, NULL, 21, NULL, 0 #define GRPAMD NULL, NULL, USE_GROUPS, NULL, 22, NULL, 0 +#define GRPPADLCK NULL, NULL, USE_GROUPS, NULL, 23, NULL, 0 #define PREGRP0 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 0, NULL, 0 #define PREGRP1 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 1, NULL, 0 @@ -416,10 +422,16 @@ fetch_data (info, addr) #define PREGRP24 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 24, NULL, 0 #define PREGRP25 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 25, NULL, 0 #define PREGRP26 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 26, NULL, 0 +#define PREGRP27 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 27, NULL, 0 +#define PREGRP28 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 28, NULL, 0 +#define PREGRP29 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 29, NULL, 0 +#define PREGRP30 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 30, NULL, 0 +#define PREGRP31 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 31, NULL, 0 +#define PREGRP32 NULL, NULL, USE_PREFIX_USER_TABLE, NULL, 32, NULL, 0 #define X86_64_0 NULL, NULL, X86_64_SPECIAL, NULL, 0, NULL, 0 -typedef void (*op_rtn) PARAMS ((int bytemode, int sizeflag)); +typedef void (*op_rtn) (int bytemode, int sizeflag); struct dis386 { const char *name; @@ -625,8 +637,7 @@ static const struct dis386 dis386[] = { { "movQ", Sw, Ev, XX }, { "popU", Ev, XX, XX }, /* 90 */ - { "nop", XX, XX, XX }, - /* FIXME: NOP with REPz prefix is called PAUSE. */ + { "nop", NOP_Fixup, 0, XX, XX }, { "xchgS", RMeCX, eAX, XX }, { "xchgS", RMeDX, eAX, XX }, { "xchgS", RMeBX, eAX, XX }, @@ -735,7 +746,7 @@ static const struct dis386 dis386[] = { { "outS", indirDX, eAX, XX }, /* f0 */ { "(bad)", XX, XX, XX }, /* lock prefix */ - { "(bad)", XX, XX, XX }, + { "icebp", XX, XX, XX }, { "(bad)", XX, XX, XX }, /* repne */ { "(bad)", XX, XX, XX }, /* repz */ { "hlt", XX, XX, XX }, @@ -775,11 +786,11 @@ static const struct dis386 dis386_twobyte[] = { /* 10 */ { PREGRP8 }, { PREGRP9 }, - { "movlpX", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */ + { PREGRP30 }, { "movlpX", EX, XM, SIMD_Fixup, 'h' }, { "unpcklpX", XM, EX, XX }, { "unpckhpX", XM, EX, XX }, - { "movhpX", XM, EX, SIMD_Fixup, 'l' }, + { PREGRP31 }, { "movhpX", EX, XM, SIMD_Fixup, 'l' }, /* 18 */ { GRP14 }, @@ -878,7 +889,7 @@ static const struct dis386 dis386_twobyte[] = { { "packssdw", MX, EM, XX }, { PREGRP26 }, { PREGRP24 }, - { "movd", MX, Ed, XX }, + { "movd", MX, Edq, XX }, { PREGRP19 }, /* 70 */ { PREGRP22 }, @@ -894,8 +905,8 @@ static const struct dis386 dis386_twobyte[] = { { "(bad)", XX, XX, XX }, { "(bad)", XX, XX, XX }, { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { PREGRP28 }, + { PREGRP29 }, { PREGRP23 }, { PREGRP20 }, /* 80 */ @@ -942,7 +953,7 @@ static const struct dis386 dis386_twobyte[] = { { "shldS", Ev, Gv, Ib }, { "shldS", Ev, Gv, CL }, { "(bad)", XX, XX, XX }, - { "(bad)", XX, XX, XX }, + { GRPPADLCK }, /* a8 */ { "pushT", gs, XX, XX }, { "popT", gs, XX, XX }, @@ -989,7 +1000,7 @@ static const struct dis386 dis386_twobyte[] = { { "bswap", RMeSI, XX, XX }, { "bswap", RMeDI, XX, XX }, /* d0 */ - { "(bad)", XX, XX, XX }, + { PREGRP27 }, { "psrlw", MX, EM, XX }, { "psrld", MX, EM, XX }, { "psrlq", MX, EM, XX }, @@ -1025,7 +1036,7 @@ static const struct dis386 dis386_twobyte[] = { { "pmaxsw", MX, EM, XX }, { "pxor", MX, EM, XX }, /* f0 */ - { "(bad)", XX, XX, XX }, + { PREGRP32 }, { "psllw", MX, EM, XX }, { "pslld", MX, EM, XX }, { "psllq", MX, EM, XX }, @@ -1077,15 +1088,15 @@ static const unsigned char twobyte_has_modrm[256] = { /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ - /* 70 */ 1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,1, /* 7f */ + /* 70 */ 1,1,1,1,1,1,1,0,0,0,0,0,1,1,1,1, /* 7f */ /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ - /* a0 */ 0,0,0,1,1,1,0,0,0,0,0,1,1,1,1,1, /* af */ + /* a0 */ 0,0,0,1,1,1,0,1,0,0,0,1,1,1,1,1, /* af */ /* b0 */ 1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1, /* bf */ /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ - /* d0 */ 0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ + /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ - /* f0 */ 0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ + /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -1094,21 +1105,21 @@ static const unsigned char twobyte_uses_SSE_prefix[256] = { /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ /* ------------------------------- */ /* 00 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 0f */ - /* 10 */ 1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 1f */ + /* 10 */ 1,1,1,0,0,0,1,0,0,0,0,0,0,0,0,0, /* 1f */ /* 20 */ 0,0,0,0,0,0,0,0,0,0,1,0,1,1,0,0, /* 2f */ /* 30 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 3f */ /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 4f */ /* 50 */ 0,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* 5f */ /* 60 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,1,0,1, /* 6f */ - /* 70 */ 1,0,0,0,0,0,0,0,0,0,0,0,0,0,1,1, /* 7f */ + /* 70 */ 1,0,0,0,0,0,0,0,0,0,0,0,1,1,1,1, /* 7f */ /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 9f */ /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* af */ /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* bf */ /* c0 */ 0,0,1,0,0,0,0,0,0,0,0,0,0,0,0,0, /* cf */ - /* d0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */ + /* d0 */ 1,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* df */ /* e0 */ 0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0, /* ef */ - /* f0 */ 0,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0 /* ff */ + /* f0 */ 1,0,0,0,0,0,0,1,0,0,0,0,0,0,0,0 /* ff */ /* ------------------------------- */ /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ }; @@ -1348,13 +1359,13 @@ static const struct dis386 grps[][8] = { /* GRP7 */ { { "sgdtQ", M, XX, XX }, - { "sidtQ", M, XX, XX }, + { "sidtQ", PNI_Fixup, 0, XX, XX }, { "lgdtQ", M, XX, XX }, { "lidtQ", M, XX, XX }, { "smswQ", Ev, XX, XX }, { "(bad)", XX, XX, XX }, { "lmsw", Ew, XX, XX }, - { "invlpg", Ew, XX, XX }, + { "invlpg", INVLPG_Fixup, w_mode, XX, XX }, }, /* GRP8 */ { @@ -1418,10 +1429,9 @@ static const struct dis386 grps[][8] = { { "ldmxcsr", Ev, XX, XX }, { "stmxcsr", Ev, XX, XX }, { "(bad)", XX, XX, XX }, - { "lfence", None, XX, XX }, - { "mfence", None, XX, XX }, - { "sfence", None, XX, XX }, - /* FIXME: the sfence with memory operand is clflush! */ + { "lfence", OP_0fae, 0, XX, XX }, + { "mfence", OP_0fae, 0, XX, XX }, + { "clflush", OP_0fae, 0, XX, XX }, }, /* GRP14 */ { @@ -1444,6 +1454,17 @@ static const struct dis386 grps[][8] = { { "(bad)", XX, XX, XX }, { "(bad)", XX, XX, XX }, { "(bad)", XX, XX, XX }, + }, + /* GRPPADLCK */ + { + { "xstorerng", OP_0f07, 0, XX, XX }, + { "xcryptecb", OP_0f07, 0, XX, XX }, + { "xcryptcbc", OP_0f07, 0, XX, XX }, + { "(bad)", OP_0f07, 0, XX, XX }, + { "xcryptcfb", OP_0f07, 0, XX, XX }, + { "xcryptofb", OP_0f07, 0, XX, XX }, + { "(bad)", OP_0f07, 0, XX, XX }, + { "(bad)", OP_0f07, 0, XX, XX }, } }; @@ -1611,9 +1632,9 @@ static const struct dis386 prefix_user_table[][4] = { }, /* PREGRP23 */ { - { "movd", Ed, MX, XX }, + { "movd", Edq, MX, XX }, { "movq", XM, EX, XX }, - { "movd", Ed, XM, XX }, + { "movd", Edq, XM, XX }, { "(bad)", Ed, XM, XX }, }, /* PREGRP24 */ @@ -1637,6 +1658,48 @@ static const struct dis386 prefix_user_table[][4] = { { "punpcklqdq", XM, EX, XX }, { "(bad)", XM, EX, XX }, }, + /* PREGRP27 */ + { + { "(bad)", MX, EX, XX }, + { "(bad)", XM, EX, XX }, + { "addsubpd", XM, EX, XX }, + { "addsubps", XM, EX, XX }, + }, + /* PREGRP28 */ + { + { "(bad)", MX, EX, XX }, + { "(bad)", XM, EX, XX }, + { "haddpd", XM, EX, XX }, + { "haddps", XM, EX, XX }, + }, + /* PREGRP29 */ + { + { "(bad)", MX, EX, XX }, + { "(bad)", XM, EX, XX }, + { "hsubpd", XM, EX, XX }, + { "hsubps", XM, EX, XX }, + }, + /* PREGRP30 */ + { + { "movlpX", XM, EX, SIMD_Fixup, 'h' }, /* really only 2 operands */ + { "movsldup", XM, EX, XX }, + { "movlpd", XM, EX, XX }, + { "movddup", XM, EX, XX }, + }, + /* PREGRP31 */ + { + { "movhpX", XM, EX, SIMD_Fixup, 'l' }, + { "movshdup", XM, EX, XX }, + { "movhpd", XM, EX, XX }, + { "(bad)", XM, EX, XX }, + }, + /* PREGRP32 */ + { + { "(bad)", XM, EX, XX }, + { "(bad)", XM, EX, XX }, + { "(bad)", XM, EX, XX }, + { "lddqu", XM, M, XX }, + }, }; static const struct dis386 x86_64_table[][2] = { @@ -1649,7 +1712,7 @@ static const struct dis386 x86_64_table[][2] = { #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") static void -ckprefix () +ckprefix (void) { int newrex; rex = 0; @@ -1747,9 +1810,7 @@ ckprefix () prefix byte. */ static const char * -prefix_name (pref, sizeflag) - int pref; - int sizeflag; +prefix_name (int pref, int sizeflag) { switch (pref) { @@ -1808,9 +1869,9 @@ prefix_name (pref, sizeflag) return (sizeflag & DFLAG) ? "data16" : "data32"; case 0x67: if (mode_64bit) - return (sizeflag & AFLAG) ? "addr32" : "addr64"; + return (sizeflag & AFLAG) ? "addr32" : "addr64"; else - return ((sizeflag & AFLAG) && !mode_64bit) ? "addr16" : "addr32"; + return ((sizeflag & AFLAG) && !mode_64bit) ? "addr16" : "addr32"; case FWAIT_OPCODE: return "fwait"; default: @@ -1843,9 +1904,7 @@ static char scale_char; print_insn_i386_att and print_insn_i386_intel these functions can disappear, and print_insn_i386 be merged into print_insn. */ int -print_insn_i386_att (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_i386_att (bfd_vma pc, disassemble_info *info) { intel_syntax = 0; @@ -1853,9 +1912,7 @@ print_insn_i386_att (pc, info) } int -print_insn_i386_intel (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_i386_intel (bfd_vma pc, disassemble_info *info) { intel_syntax = 1; @@ -1863,9 +1920,7 @@ print_insn_i386_intel (pc, info) } int -print_insn_i386 (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn_i386 (bfd_vma pc, disassemble_info *info) { intel_syntax = -1; @@ -1873,9 +1928,7 @@ print_insn_i386 (pc, info) } static int -print_insn (pc, info) - bfd_vma pc; - disassemble_info *info; +print_insn (bfd_vma pc, disassemble_info *info) { const struct dis386 *dp; int i; @@ -1890,7 +1943,7 @@ print_insn (pc, info) mode_64bit = (info->mach == bfd_mach_x86_64_intel_syntax || info->mach == bfd_mach_x86_64); - if (intel_syntax == -1) + if (intel_syntax == (char) -1) intel_syntax = (info->mach == bfd_mach_i386_i386_intel_syntax || info->mach == bfd_mach_x86_64_intel_syntax); @@ -1984,7 +2037,7 @@ print_insn (pc, info) puts most long word instructions on a single line. */ info->bytes_per_line = 7; - info->private_data = (PTR) &priv; + info->private_data = &priv; priv.max_fetched = priv.the_buffer; priv.insn_start = pc; @@ -2040,7 +2093,7 @@ print_insn (pc, info) const char *name; /* fwait not followed by floating point instruction. Print the - first prefix, which is probably fwait itself. */ + first prefix, which is probably fwait itself. */ name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); if (name == NULL) name = INTERNAL_DISASSEMBLER_ERROR; @@ -2273,7 +2326,7 @@ static const char *float_mem[] = { "fsubr{s||s|}", "fdiv{s||s|}", "fdivr{s||s|}", - /* d9 */ + /* d9 */ "fld{s||s|}", "(bad)", "fst{s||s|}", @@ -2293,7 +2346,7 @@ static const char *float_mem[] = { "fidivr{l||l|}", /* db */ "fild{l||l|}", - "(bad)", + "fisttp{l||l|}", "fist{l||l|}", "fistp{l||l|}", "(bad)", @@ -2311,7 +2364,7 @@ static const char *float_mem[] = { "fdivr{l||l|}", /* dd */ "fld{l||l|}", - "(bad)", + "fisttpll", "fst{l||l|}", "fstp{l||l|}", "frstor", @@ -2329,7 +2382,7 @@ static const char *float_mem[] = { "fidivr", /* df */ "fild", - "(bad)", + "fisttp", "fist", "fistp", "fbld", @@ -2505,8 +2558,7 @@ static char *fgrps[][8] = { }; static void -dofloat (sizeflag) - int sizeflag; +dofloat (int sizeflag) { const struct dis386 *dp; unsigned char floatop; @@ -2518,11 +2570,11 @@ dofloat (sizeflag) putop (float_mem[(floatop - 0xd8) * 8 + reg], sizeflag); obufp = op1out; if (floatop == 0xdb) - OP_E (x_mode, sizeflag); + OP_E (x_mode, sizeflag); else if (floatop == 0xdd) - OP_E (d_mode, sizeflag); + OP_E (d_mode, sizeflag); else - OP_E (v_mode, sizeflag); + OP_E (v_mode, sizeflag); return; } /* Skip mod/rm byte. */ @@ -2552,17 +2604,13 @@ dofloat (sizeflag) } static void -OP_ST (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { oappend ("%st"); } static void -OP_STi (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { sprintf (scratchbuf, "%%st(%d)", rm); oappend (scratchbuf + intel_syntax); @@ -2570,9 +2618,7 @@ OP_STi (bytemode, sizeflag) /* Capital letters in template are macros. */ static int -putop (template, sizeflag) - const char *template; - int sizeflag; +putop (const char *template, int sizeflag) { const char *p; int alt; @@ -2617,14 +2663,14 @@ putop (template, sizeflag) case '}': break; case 'A': - if (intel_syntax) - break; + if (intel_syntax) + break; if (mod != 3 || (sizeflag & SUFFIX_ALWAYS)) *obufp++ = 'b'; break; case 'B': - if (intel_syntax) - break; + if (intel_syntax) + break; if (sizeflag & SUFFIX_ALWAYS) *obufp++ = 'b'; break; @@ -2642,8 +2688,8 @@ putop (template, sizeflag) used_prefixes |= (prefixes & PREFIX_ADDR); break; case 'F': - if (intel_syntax) - break; + if (intel_syntax) + break; if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) { if (sizeflag & AFLAG) @@ -2654,8 +2700,8 @@ putop (template, sizeflag) } break; case 'H': - if (intel_syntax) - break; + if (intel_syntax) + break; if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) { @@ -2669,8 +2715,8 @@ putop (template, sizeflag) } break; case 'L': - if (intel_syntax) - break; + if (intel_syntax) + break; if (sizeflag & SUFFIX_ALWAYS) *obufp++ = 'l'; break; @@ -2688,8 +2734,8 @@ putop (template, sizeflag) *obufp++ = 'd'; break; case 'T': - if (intel_syntax) - break; + if (intel_syntax) + break; if (mode_64bit) { *obufp++ = 'q'; @@ -2697,8 +2743,8 @@ putop (template, sizeflag) } /* Fall through. */ case 'P': - if (intel_syntax) - break; + if (intel_syntax) + break; if ((prefixes & PREFIX_DATA) || (rex & REX_MODE64) || (sizeflag & SUFFIX_ALWAYS)) @@ -2717,8 +2763,8 @@ putop (template, sizeflag) } break; case 'U': - if (intel_syntax) - break; + if (intel_syntax) + break; if (mode_64bit) { *obufp++ = 'q'; @@ -2726,8 +2772,8 @@ putop (template, sizeflag) } /* Fall through. */ case 'Q': - if (intel_syntax) - break; + if (intel_syntax) + break; USED_REX (REX_MODE64); if (mod != 3 || (sizeflag & SUFFIX_ALWAYS)) { @@ -2745,7 +2791,7 @@ putop (template, sizeflag) break; case 'R': USED_REX (REX_MODE64); - if (intel_syntax) + if (intel_syntax) { if (rex & REX_MODE64) { @@ -2776,8 +2822,8 @@ putop (template, sizeflag) used_prefixes |= (prefixes & PREFIX_DATA); break; case 'S': - if (intel_syntax) - break; + if (intel_syntax) + break; if (sizeflag & SUFFIX_ALWAYS) { if (rex & REX_MODE64) @@ -2797,11 +2843,11 @@ putop (template, sizeflag) *obufp++ = 'd'; else *obufp++ = 's'; - used_prefixes |= (prefixes & PREFIX_DATA); + used_prefixes |= (prefixes & PREFIX_DATA); break; case 'Y': - if (intel_syntax) - break; + if (intel_syntax) + break; if (rex & REX_MODE64) { USED_REX (REX_MODE64); @@ -2818,7 +2864,7 @@ putop (template, sizeflag) *obufp++ = 'w'; else *obufp++ = 'b'; - if (intel_syntax) + if (intel_syntax) { if (rex) { @@ -2845,15 +2891,14 @@ putop (template, sizeflag) } static void -oappend (s) - const char *s; +oappend (const char *s) { strcpy (obufp, s); obufp += strlen (s); } static void -append_seg () +append_seg (void) { if (prefixes & PREFIX_CS) { @@ -2888,9 +2933,7 @@ append_seg () } static void -OP_indirE (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_indirE (int bytemode, int sizeflag) { if (!intel_syntax) oappend ("*"); @@ -2898,10 +2941,7 @@ OP_indirE (bytemode, sizeflag) } static void -print_operand_value (buf, hex, disp) - char *buf; - int hex; - bfd_vma disp; +print_operand_value (char *buf, int hex, bfd_vma disp) { if (mode_64bit) { @@ -2958,9 +2998,7 @@ print_operand_value (buf, hex, disp) } static void -OP_E (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_E (int bytemode, int sizeflag) { bfd_vma disp; int add = 0; @@ -3000,20 +3038,17 @@ OP_E (bytemode, sizeflag) oappend (names32[rm + add]); break; case v_mode: + case dq_mode: USED_REX (REX_MODE64); if (rex & REX_MODE64) oappend (names64[rm + add]); - else if (sizeflag & DFLAG) + else if ((sizeflag & DFLAG) || bytemode == dq_mode) oappend (names32[rm + add]); else oappend (names16[rm + add]); used_prefixes |= (prefixes & PREFIX_DATA); break; case 0: - if (!(codep[-2] == 0xAE && codep[-1] == 0xF8 /* sfence */) - && !(codep[-2] == 0xAE && codep[-1] == 0xF0 /* mfence */) - && !(codep[-2] == 0xAE && codep[-1] == 0xe8 /* lfence */)) - BadOp (); /* bad sfence,lea,lds,les,lfs,lgs,lss modrm */ break; default: oappend (INTERNAL_DISASSEMBLER_ERROR); @@ -3076,52 +3111,52 @@ OP_E (bytemode, sizeflag) } if (!intel_syntax) - if (mod != 0 || (base & 7) == 5) - { + if (mod != 0 || (base & 7) == 5) + { print_operand_value (scratchbuf, !riprel, disp); - oappend (scratchbuf); + oappend (scratchbuf); if (riprel) { set_op (disp, 1); oappend ("(%rip)"); } - } + } if (havebase || (havesib && (index != 4 || scale != 0))) { - if (intel_syntax) - { - switch (bytemode) - { - case b_mode: - oappend ("BYTE PTR "); - break; - case w_mode: - oappend ("WORD PTR "); - break; - case v_mode: - oappend ("DWORD PTR "); - break; - case d_mode: - oappend ("QWORD PTR "); - break; - case m_mode: + if (intel_syntax) + { + switch (bytemode) + { + case b_mode: + oappend ("BYTE PTR "); + break; + case w_mode: + oappend ("WORD PTR "); + break; + case v_mode: + oappend ("DWORD PTR "); + break; + case d_mode: + oappend ("QWORD PTR "); + break; + case m_mode: if (mode_64bit) oappend ("DWORD PTR "); else oappend ("QWORD PTR "); break; - case x_mode: - oappend ("XWORD PTR "); - break; - default: - break; - } - } + case x_mode: + oappend ("XWORD PTR "); + break; + default: + break; + } + } *obufp++ = open_char; if (intel_syntax && riprel) oappend ("rip + "); - *obufp = '\0'; + *obufp = '\0'; USED_REX (REX_EXTZ); if (!havesib && (rex & REX_EXTZ)) base += 8; @@ -3132,41 +3167,37 @@ OP_E (bytemode, sizeflag) { if (index != 4) { - if (intel_syntax) - { - if (havebase) - { - *obufp++ = separator_char; - *obufp = '\0'; - } - sprintf (scratchbuf, "%s", + if (intel_syntax) + { + if (havebase) + { + *obufp++ = separator_char; + *obufp = '\0'; + } + sprintf (scratchbuf, "%s", mode_64bit && (sizeflag & AFLAG) ? names64[index] : names32[index]); - } - else + } + else sprintf (scratchbuf, ",%s", mode_64bit && (sizeflag & AFLAG) ? names64[index] : names32[index]); oappend (scratchbuf); } - if (!intel_syntax - || (intel_syntax - && bytemode != b_mode - && bytemode != w_mode - && bytemode != v_mode)) - { - *obufp++ = scale_char; - *obufp = '\0'; - sprintf (scratchbuf, "%d", 1 << scale); - oappend (scratchbuf); - } + if (scale != 0 || (!intel_syntax && index != 4)) + { + *obufp++ = scale_char; + *obufp = '\0'; + sprintf (scratchbuf, "%d", 1 << scale); + oappend (scratchbuf); + } } - if (intel_syntax) - if (mod != 0 || (base & 7) == 5) - { + if (intel_syntax) + if (mod != 0 || (base & 7) == 5) + { /* Don't print zero displacements. */ - if (disp != 0) - { + if (disp != 0) + { if ((bfd_signed_vma) disp > 0) { *obufp++ = '+'; @@ -3174,17 +3205,17 @@ OP_E (bytemode, sizeflag) } print_operand_value (scratchbuf, 0, disp); - oappend (scratchbuf); - } - } + oappend (scratchbuf); + } + } *obufp++ = close_char; - *obufp = '\0'; + *obufp = '\0'; } else if (intel_syntax) - { - if (mod != 0 || (base & 7) == 5) - { + { + if (mod != 0 || (base & 7) == 5) + { if (prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES | PREFIX_FS | PREFIX_GS)) ; @@ -3194,9 +3225,9 @@ OP_E (bytemode, sizeflag) oappend (":"); } print_operand_value (scratchbuf, 1, disp); - oappend (scratchbuf); - } - } + oappend (scratchbuf); + } + } } else { /* 16 bit address mode */ @@ -3224,27 +3255,25 @@ OP_E (bytemode, sizeflag) } if (!intel_syntax) - if (mod != 0 || (rm & 7) == 6) - { + if (mod != 0 || (rm & 7) == 6) + { print_operand_value (scratchbuf, 0, disp); - oappend (scratchbuf); - } + oappend (scratchbuf); + } if (mod != 0 || (rm & 7) != 6) { *obufp++ = open_char; - *obufp = '\0'; + *obufp = '\0'; oappend (index16[rm + add]); - *obufp++ = close_char; - *obufp = '\0'; + *obufp++ = close_char; + *obufp = '\0'; } } } static void -OP_G (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_G (int bytemode, int sizeflag) { int add = 0; USED_REX (REX_EXTX); @@ -3285,7 +3314,7 @@ OP_G (bytemode, sizeflag) } static bfd_vma -get64 () +get64 (void) { bfd_vma x; #ifdef BFD64 @@ -3310,7 +3339,7 @@ get64 () } static bfd_signed_vma -get32 () +get32 (void) { bfd_signed_vma x = 0; @@ -3323,7 +3352,7 @@ get32 () } static bfd_signed_vma -get32s () +get32s (void) { bfd_signed_vma x = 0; @@ -3339,7 +3368,7 @@ get32s () } static int -get16 () +get16 (void) { int x = 0; @@ -3350,9 +3379,7 @@ get16 () } static void -set_op (op, riprel) - bfd_vma op; - int riprel; +set_op (bfd_vma op, int riprel) { op_index[op_ad] = op_ad; if (mode_64bit) @@ -3369,9 +3396,7 @@ set_op (op, riprel) } static void -OP_REG (code, sizeflag) - int code; - int sizeflag; +OP_REG (int code, int sizeflag) { const char *s; int add = 0; @@ -3383,9 +3408,9 @@ OP_REG (code, sizeflag) { case indir_dx_reg: if (intel_syntax) - s = "[dx]"; + s = "[dx]"; else - s = "(%dx)"; + s = "(%dx)"; break; case ax_reg: case cx_reg: case dx_reg: case bx_reg: case sp_reg: case bp_reg: case si_reg: case di_reg: @@ -3431,9 +3456,7 @@ OP_REG (code, sizeflag) } static void -OP_IMREG (code, sizeflag) - int code; - int sizeflag; +OP_IMREG (int code, int sizeflag) { const char *s; @@ -3441,9 +3464,9 @@ OP_IMREG (code, sizeflag) { case indir_dx_reg: if (intel_syntax) - s = "[dx]"; + s = "[dx]"; else - s = "(%dx)"; + s = "(%dx)"; break; case ax_reg: case cx_reg: case dx_reg: case bx_reg: case sp_reg: case bp_reg: case si_reg: case di_reg: @@ -3480,9 +3503,7 @@ OP_IMREG (code, sizeflag) } static void -OP_I (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_I (int bytemode, int sizeflag) { bfd_signed_vma op; bfd_signed_vma mask = -1; @@ -3534,9 +3555,7 @@ OP_I (bytemode, sizeflag) } static void -OP_I64 (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_I64 (int bytemode, int sizeflag) { bfd_signed_vma op; bfd_signed_vma mask = -1; @@ -3587,9 +3606,7 @@ OP_I64 (bytemode, sizeflag) } static void -OP_sI (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_sI (int bytemode, int sizeflag) { bfd_signed_vma op; bfd_signed_vma mask = -1; @@ -3638,9 +3655,7 @@ OP_sI (bytemode, sizeflag) } static void -OP_J (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_J (int bytemode, int sizeflag) { bfd_vma disp; bfd_vma mask = -1; @@ -3676,17 +3691,13 @@ OP_J (bytemode, sizeflag) } static void -OP_SEG (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_SEG (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { oappend (names_seg[reg]); } static void -OP_DIR (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag; +OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) { int seg, offset; @@ -3709,9 +3720,7 @@ OP_DIR (dummy, sizeflag) } static void -OP_OFF (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag; +OP_OFF (int bytemode ATTRIBUTE_UNUSED, int sizeflag) { bfd_vma off; @@ -3725,7 +3734,7 @@ OP_OFF (bytemode, sizeflag) if (intel_syntax) { if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS - | PREFIX_ES | PREFIX_FS | PREFIX_GS))) + | PREFIX_ES | PREFIX_FS | PREFIX_GS))) { oappend (names_seg[ds_reg - es_reg]); oappend (":"); @@ -3736,9 +3745,7 @@ OP_OFF (bytemode, sizeflag) } static void -OP_OFF64 (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_OFF64 (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { bfd_vma off; @@ -3755,7 +3762,7 @@ OP_OFF64 (bytemode, sizeflag) if (intel_syntax) { if (!(prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS - | PREFIX_ES | PREFIX_FS | PREFIX_GS))) + | PREFIX_ES | PREFIX_FS | PREFIX_GS))) { oappend (names_seg[ds_reg - es_reg]); oappend (":"); @@ -3766,9 +3773,7 @@ OP_OFF64 (bytemode, sizeflag) } static void -ptr_reg (code, sizeflag) - int code; - int sizeflag; +ptr_reg (int code, int sizeflag) { const char *s; if (intel_syntax) @@ -3780,9 +3785,9 @@ ptr_reg (code, sizeflag) if (rex & REX_MODE64) { if (!(sizeflag & AFLAG)) - s = names32[code - eAX_reg]; + s = names32[code - eAX_reg]; else - s = names64[code - eAX_reg]; + s = names64[code - eAX_reg]; } else if (sizeflag & AFLAG) s = names32[code - eAX_reg]; @@ -3796,18 +3801,14 @@ ptr_reg (code, sizeflag) } static void -OP_ESreg (code, sizeflag) - int code; - int sizeflag; +OP_ESreg (int code, int sizeflag) { oappend ("%es:" + intel_syntax); ptr_reg (code, sizeflag); } static void -OP_DSreg (code, sizeflag) - int code; - int sizeflag; +OP_DSreg (int code, int sizeflag) { if ((prefixes & (PREFIX_CS @@ -3822,9 +3823,7 @@ OP_DSreg (code, sizeflag) } static void -OP_C (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { int add = 0; USED_REX (REX_EXTX); @@ -3835,9 +3834,7 @@ OP_C (dummy, sizeflag) } static void -OP_D (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { int add = 0; USED_REX (REX_EXTX); @@ -3851,18 +3848,14 @@ OP_D (dummy, sizeflag) } static void -OP_T (dummy, sizeflag) - int dummy ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { sprintf (scratchbuf, "%%tr%d", reg); oappend (scratchbuf + intel_syntax); } static void -OP_Rd (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_Rd (int bytemode, int sizeflag) { if (mod == 3) OP_E (bytemode, sizeflag); @@ -3871,9 +3864,7 @@ OP_Rd (bytemode, sizeflag) } static void -OP_MMX (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { int add = 0; USED_REX (REX_EXTX); @@ -3888,9 +3879,7 @@ OP_MMX (bytemode, sizeflag) } static void -OP_XMM (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_XMM (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { int add = 0; USED_REX (REX_EXTX); @@ -3901,9 +3890,7 @@ OP_XMM (bytemode, sizeflag) } static void -OP_EM (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_EM (int bytemode, int sizeflag) { int add = 0; if (mod != 3) @@ -3927,9 +3914,7 @@ OP_EM (bytemode, sizeflag) } static void -OP_EX (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_EX (int bytemode, int sizeflag) { int add = 0; if (mod != 3) @@ -3949,9 +3934,7 @@ OP_EX (bytemode, sizeflag) } static void -OP_MS (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_MS (int bytemode, int sizeflag) { if (mod == 3) OP_EM (bytemode, sizeflag); @@ -3960,9 +3943,7 @@ OP_MS (bytemode, sizeflag) } static void -OP_XS (bytemode, sizeflag) - int bytemode; - int sizeflag; +OP_XS (int bytemode, int sizeflag) { if (mod == 3) OP_EX (bytemode, sizeflag); @@ -3970,7 +3951,56 @@ OP_XS (bytemode, sizeflag) BadOp (); } -static const char *Suffix3DNow[] = { +static void +OP_M (int bytemode, int sizeflag) +{ + if (mod == 3) + BadOp (); /* bad lea,lds,les,lfs,lgs,lss modrm */ + else + OP_E (bytemode, sizeflag); +} + +static void +OP_0f07 (int bytemode, int sizeflag) +{ + if (mod != 3 || rm != 0) + BadOp (); + else + OP_E (bytemode, sizeflag); +} + +static void +OP_0fae (int bytemode, int sizeflag) +{ + if (mod == 3) + { + if (reg == 7) + strcpy (obuf + strlen (obuf) - sizeof ("clflush") + 1, "sfence"); + + if (reg < 5 || rm != 0) + { + BadOp (); /* bad sfence, mfence, or lfence */ + return; + } + } + else if (reg != 7) + { + BadOp (); /* bad clflush */ + return; + } + + OP_E (bytemode, sizeflag); +} + +static void +NOP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) +{ + /* NOP with REPZ prefix is called PAUSE. */ + if (prefixes == PREFIX_REPZ) + strcpy (obuf, "pause"); +} + +static const char *const Suffix3DNow[] = { /* 00 */ NULL, NULL, NULL, NULL, /* 04 */ NULL, NULL, NULL, NULL, /* 08 */ NULL, NULL, NULL, NULL, @@ -4038,9 +4068,7 @@ static const char *Suffix3DNow[] = { }; static void -OP_3DNowSuffix (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { const char *mnemonic; @@ -4076,9 +4104,7 @@ static const char *simd_cmp_op[] = { }; static void -OP_SIMD_Suffix (bytemode, sizeflag) - int bytemode ATTRIBUTE_UNUSED; - int sizeflag ATTRIBUTE_UNUSED; +OP_SIMD_Suffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) { unsigned int cmp_type; @@ -4118,9 +4144,7 @@ OP_SIMD_Suffix (bytemode, sizeflag) } static void -SIMD_Fixup (extrachar, sizeflag) - int extrachar; - int sizeflag ATTRIBUTE_UNUSED; +SIMD_Fixup (int extrachar, int sizeflag ATTRIBUTE_UNUSED) { /* Change movlps/movhps to movhlps/movlhps for 2 register operand forms of these instructions. */ @@ -4136,6 +4160,46 @@ SIMD_Fixup (extrachar, sizeflag) } static void +PNI_Fixup (int extrachar ATTRIBUTE_UNUSED, int sizeflag) +{ + if (mod == 3 && reg == 1) + { + char *p = obuf + strlen (obuf); + + /* Override "sidt". */ + if (rm) + { + /* mwait %eax,%ecx */ + strcpy (p - 4, "mwait %eax,%ecx"); + } + else + { + /* monitor %eax,%ecx,%edx" */ + strcpy (p - 4, "monitor %eax,%ecx,%edx"); + } + + codep++; + } + else + OP_E (0, sizeflag); +} + +static void +INVLPG_Fixup (int bytemode, int sizeflag) +{ + if (*codep == 0xf8) + { + char *p = obuf + strlen (obuf); + + /* Override "invlpg". */ + strcpy (p - 6, "swapgs"); + codep++; + } + else + OP_E (bytemode, sizeflag); +} + +static void BadOp (void) { /* Throw away prefixes and 1st. opcode byte. */ diff --git a/contrib/binutils/opcodes/ia64-asmtab.c b/contrib/binutils/opcodes/ia64-asmtab.c index f007f71..2465d39 100644 --- a/contrib/binutils/opcodes/ia64-asmtab.c +++ b/contrib/binutils/opcodes/ia64-asmtab.c @@ -1,37 +1,37 @@ -/* This file is automatically generated by ia64-gen. Do not edit! */ -static const char *ia64_strings[] = { +/* This file is automatically generated by ia64-gen. Do not edit! */ +static const char * const ia64_strings[] = { "", "0", "1", "a", "acq", "add", "addl", "addp4", "adds", "alloc", "and", "andcm", "b", "bias", "br", "break", "brl", "brp", "bsw", "c", "call", - "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmpxchg1", - "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop", "czx1", - "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl", "exit", - "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand", "fandcm", - "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt", "fetchadd4", - "fetchadd8", "few", "fill", "flushrs", "fma", "fmax", "fmerge", "fmin", - "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma", "fnmpy", "fnorm", "for", - "fpabs", "fpack", "fpamax", "fpamin", "fpcmp", "fpcvt", "fpma", "fpmax", - "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg", "fpnegabs", "fpnma", - "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta", "fselect", "fsetc", - "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu", "g", "ga", "ge", - "getf", "geu", "gt", "gtu", "h", "hu", "i", "ia", "imp", "invala", "itc", - "itr", "l", "ld1", "ld2", "ld4", "ld8", "ldf", "ldf8", "ldfd", "ldfe", - "ldfp8", "ldfpd", "ldfps", "ldfs", "le", "leu", "lfetch", "loadrs", - "loop", "lr", "lt", "ltu", "lu", "m", "many", "mf", "mix1", "mix2", - "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne", "neq", "nge", "ngt", - "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1", "nt2", "nta", "nz", - "or", "orcm", "ord", "pack2", "pack4", "padd1", "padd2", "padd4", "pavg1", - "pavg2", "pavgsub1", "pavgsub2", "pcmp1", "pcmp2", "pcmp4", "pmax1", - "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2", "popcnt", "pr", "probe", - "psad1", "pshl2", "pshl4", "pshladd2", "pshr2", "pshr4", "pshradd2", - "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz", "rel", "ret", "rfi", - "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3", "sa", "se", "setf", - "shl", "shladd", "shladdp4", "shr", "shrp", "sig", "spill", "spnt", - "sptk", "srlz", "ssm", "sss", "st1", "st2", "st4", "st8", "stf", "stf8", - "stfd", "stfe", "stfs", "sub", "sum", "sxt1", "sxt2", "sxt4", "sync", - "tak", "tbit", "thash", "tnat", "tpa", "trunc", "ttag", "u", "unc", - "unord", "unpack1", "unpack2", "unpack4", "uss", "uus", "uuu", "w", - "wexit", "wtop", "x", "xchg1", "xchg2", "xchg4", "xchg8", "xf", "xma", - "xmpy", "xor", "xuf", "z", "zxt1", "zxt2", "zxt4", + "cexit", "chk", "cloop", "clr", "clrrrb", "cmp", "cmp4", "cmp8xchg16", + "cmpxchg1", "cmpxchg2", "cmpxchg4", "cmpxchg8", "cond", "cover", "ctop", + "czx1", "czx2", "d", "dep", "dpnt", "dptk", "e", "epc", "eq", "excl", + "exit", "exp", "extr", "f", "fabs", "fadd", "famax", "famin", "fand", + "fandcm", "fault", "fc", "fchkf", "fclass", "fclrf", "fcmp", "fcvt", + "fetchadd4", "fetchadd8", "few", "fill", "flushrs", "fma", "fmax", + "fmerge", "fmin", "fmix", "fmpy", "fms", "fneg", "fnegabs", "fnma", + "fnmpy", "fnorm", "for", "fpabs", "fpack", "fpamax", "fpamin", "fpcmp", + "fpcvt", "fpma", "fpmax", "fpmerge", "fpmin", "fpmpy", "fpms", "fpneg", + "fpnegabs", "fpnma", "fpnmpy", "fprcpa", "fprsqrta", "frcpa", "frsqrta", + "fselect", "fsetc", "fsub", "fswap", "fsxt", "fwb", "fx", "fxor", "fxu", + "g", "ga", "ge", "getf", "geu", "gt", "gtu", "h", "hint", "hu", "i", "ia", + "imp", "invala", "itc", "itr", "l", "ld1", "ld16", "ld2", "ld4", "ld8", + "ldf", "ldf8", "ldfd", "ldfe", "ldfp8", "ldfpd", "ldfps", "ldfs", "le", + "leu", "lfetch", "loadrs", "loop", "lr", "lt", "ltu", "lu", "m", "many", + "mf", "mix1", "mix2", "mix4", "mov", "movl", "mux1", "mux2", "nc", "ne", + "neq", "nge", "ngt", "nl", "nle", "nlt", "nm", "nop", "nr", "ns", "nt1", + "nt2", "nta", "nz", "or", "orcm", "ord", "pack2", "pack4", "padd1", + "padd2", "padd4", "pavg1", "pavg2", "pavgsub1", "pavgsub2", "pcmp1", + "pcmp2", "pcmp4", "pmax1", "pmax2", "pmin1", "pmin2", "pmpy2", "pmpyshr2", + "popcnt", "pr", "probe", "psad1", "pshl2", "pshl4", "pshladd2", "pshr2", + "pshr4", "pshradd2", "psub1", "psub2", "psub4", "ptc", "ptr", "r", "raz", + "rel", "ret", "rfi", "rsm", "rum", "rw", "s", "s0", "s1", "s2", "s3", + "sa", "se", "setf", "shl", "shladd", "shladdp4", "shr", "shrp", "sig", + "spill", "spnt", "sptk", "srlz", "ssm", "sss", "st1", "st16", "st2", + "st4", "st8", "stf", "stf8", "stfd", "stfe", "stfs", "sub", "sum", "sxt1", + "sxt2", "sxt4", "sync", "tak", "tbit", "thash", "tnat", "tpa", "trunc", + "ttag", "u", "unc", "unord", "unpack1", "unpack2", "unpack4", "uss", + "uus", "uuu", "w", "wexit", "wtop", "x", "xchg1", "xchg2", "xchg4", + "xchg8", "xf", "xma", "xmpy", "xor", "xuf", "z", "zxt1", "zxt2", "zxt4", }; static const struct ia64_dependency @@ -39,8 +39,14 @@ dependencies[] = { { "ALAT", 0, 0, 0, -1, NULL, }, { "AR[BSP]", 26, 0, 2, 17, NULL, }, { "AR[BSPSTORE]", 26, 0, 2, 18, NULL, }, + { "AR[CFLG]", 26, 0, 2, 27, NULL, }, { "AR[CCV]", 26, 0, 2, 32, NULL, }, + { "AR[CSD]", 26, 0, 2, 25, NULL, }, { "AR[EC]", 26, 0, 2, 66, NULL, }, + { "AR[EFLAG]", 26, 0, 2, 24, NULL, }, + { "AR[FCR]", 26, 0, 2, 21, NULL, }, + { "AR[FDR]", 26, 0, 2, 30, NULL, }, + { "AR[FIR]", 26, 0, 2, 29, NULL, }, { "AR[FPSR].sf0.controls", 30, 0, 2, -1, NULL, }, { "AR[FPSR].sf1.controls", 30, 0, 2, -1, NULL, }, { "AR[FPSR].sf2.controls", 30, 0, 2, -1, NULL, }, @@ -51,6 +57,7 @@ dependencies[] = { { "AR[FPSR].sf3.flags", 30, 0, 2, -1, NULL, }, { "AR[FPSR].traps", 30, 0, 2, -1, NULL, }, { "AR[FPSR].rv", 30, 0, 2, -1, NULL, }, + { "AR[FSR]", 26, 0, 2, 28, NULL, }, { "AR[ITC]", 26, 0, 2, 44, NULL, }, { "AR[K%], % in 0 - 7", 1, 0, 2, -1, NULL, }, { "AR[LC]", 26, 0, 2, 65, NULL, }, @@ -59,6 +66,7 @@ dependencies[] = { { "AR[PFS]", 26, 0, 0, 64, NULL, }, { "AR[RNAT]", 26, 0, 2, 19, NULL, }, { "AR[RSC]", 26, 0, 2, 16, NULL, }, + { "AR[SSD]", 26, 0, 2, 26, NULL, }, { "AR[UNAT]{%}, % in 0 - 63", 2, 0, 2, -1, NULL, }, { "AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111", 3, 0, 0, -1, NULL, }, { "AR%, % in 48-63, 112-127", 4, 0, 2, -1, NULL, }, @@ -213,7 +221,13 @@ dependencies[] = { { "AR[BSP]", 26, 1, 2, 17, NULL, }, { "AR[BSPSTORE]", 26, 1, 2, 18, NULL, }, { "AR[CCV]", 26, 1, 2, 32, NULL, }, + { "AR[CFLG]", 26, 1, 2, 27, NULL, }, + { "AR[CSD]", 26, 1, 2, 25, NULL, }, { "AR[EC]", 26, 1, 2, 66, NULL, }, + { "AR[EFLAG]", 26, 1, 2, 24, NULL, }, + { "AR[FCR]", 26, 1, 2, 21, NULL, }, + { "AR[FDR]", 26, 1, 2, 30, NULL, }, + { "AR[FIR]", 26, 1, 2, 29, NULL, }, { "AR[FPSR].sf0.controls", 30, 1, 2, -1, NULL, }, { "AR[FPSR].sf1.controls", 30, 1, 2, -1, NULL, }, { "AR[FPSR].sf2.controls", 30, 1, 2, -1, NULL, }, @@ -232,6 +246,7 @@ dependencies[] = { { "AR[FPSR].sf3.flags", 30, 1, 2, -1, NULL, }, { "AR[FPSR].rv", 30, 1, 2, -1, NULL, }, { "AR[FPSR].traps", 30, 1, 2, -1, NULL, }, + { "AR[FSR]", 26, 1, 2, 28, NULL, }, { "AR[ITC]", 26, 1, 2, 44, NULL, }, { "AR[K%], % in 0 - 7", 1, 1, 2, -1, NULL, }, { "AR[LC]", 26, 1, 2, 65, NULL, }, @@ -356,1180 +371,1223 @@ dependencies[] = { }; static const short dep0[] = { - 88, 252, 2131, 2297, + 96, 267, 2139, 2312, }; static const short dep1[] = { - 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, 4127, - 20605, + 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, 4135, + 20613, }; static const short dep2[] = { - 88, 252, 2157, 2158, 2160, 2161, 2163, 2164, 2166, 2314, 2317, 2318, 2321, - 2322, 2325, 2326, + 96, 267, 2165, 2166, 2168, 2169, 2171, 2172, 2174, 2329, 2332, 2333, 2336, + 2337, 2340, 2341, }; static const short dep3[] = { - 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2314, 2317, - 2318, 2321, 2322, 2325, 2326, 4127, 20605, + 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2329, 2332, + 2333, 2336, 2337, 2340, 2341, 4135, 20613, }; static const short dep4[] = { - 88, 252, 22637, 22638, 22640, 22641, 22643, 22644, 22646, 22794, 22797, 22798, - 22801, 22802, 22805, 22806, + 96, 267, 22645, 22646, 22648, 22649, 22651, 22652, 22654, 22809, 22812, 22813, + 22816, 22817, 22820, 22821, }; static const short dep5[] = { - 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, - 22794, 22797, 22798, 22801, 22802, 22805, 22806, + 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, + 22809, 22812, 22813, 22816, 22817, 22820, 22821, }; static const short dep6[] = { - 88, 252, 2157, 2158, 2160, 2161, 2163, 2164, 2166, 2314, 2315, 2317, 2319, - 2321, 2323, 2325, + 96, 267, 2165, 2166, 2168, 2169, 2171, 2172, 2174, 2329, 2330, 2332, 2334, + 2336, 2338, 2340, }; static const short dep7[] = { - 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2314, 2315, - 2318, 2319, 2322, 2323, 2326, 4127, 20605, + 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2329, 2330, + 2333, 2334, 2337, 2338, 2341, 4135, 20613, }; static const short dep8[] = { - 88, 252, 2157, 2158, 2160, 2161, 2163, 2164, 2166, 2314, 2316, 2318, 2320, - 2322, 2324, 2326, + 96, 267, 2165, 2166, 2168, 2169, 2171, 2172, 2174, 2329, 2331, 2333, 2335, + 2337, 2339, 2341, }; static const short dep9[] = { - 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2314, 2316, - 2317, 2320, 2321, 2324, 2325, 4127, 20605, + 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2329, 2331, + 2332, 2335, 2336, 2339, 2340, 4135, 20613, }; static const short dep10[] = { - 88, 252, 2157, 2158, 2160, 2161, 2163, 2164, 2166, 2314, 2315, 2316, 2317, - 2318, 2319, 2320, 2321, 2322, 2323, 2324, 2325, 2326, + 96, 267, 2165, 2166, 2168, 2169, 2171, 2172, 2174, 2329, 2330, 2331, 2332, + 2333, 2334, 2335, 2336, 2337, 2338, 2339, 2340, 2341, }; static const short dep11[] = { - 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2314, 2315, - 2316, 2317, 2318, 2319, 2320, 2321, 2322, 2323, 2324, 2325, 2326, 4127, 20605, + 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2329, 2330, + 2331, 2332, 2333, 2334, 2335, 2336, 2337, 2338, 2339, 2340, 2341, 4135, 20613, }; static const short dep12[] = { - 88, 252, 2364, + 96, 267, 2379, }; static const short dep13[] = { - 32, 33, 88, 148, 166, 167, 252, 2074, 2075, 2157, 2159, 2160, 2162, 2163, - 2165, 2166, 4127, + 40, 41, 96, 156, 174, 175, 267, 2082, 2083, 2165, 2167, 2168, 2170, 2171, + 2173, 2174, 4135, }; static const short dep14[] = { - 88, 147, 252, 295, 2364, 28844, 28987, + 96, 155, 267, 310, 2379, 28852, 29002, }; static const short dep15[] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, - 23, 24, 25, 32, 33, 88, 136, 148, 166, 167, 252, 295, 2074, 2075, 2157, 2159, - 2160, 2162, 2163, 2165, 2166, 4127, 28844, 28987, + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, + 22, 23, 24, 25, 26, 28, 29, 30, 31, 32, 33, 40, 41, 96, 144, 156, 174, 175, + 267, 310, 2082, 2083, 2165, 2167, 2168, 2170, 2171, 2173, 2174, 4135, 28852, + 29002, }; static const short dep16[] = { - 1, 4, 32, 88, 126, 174, 177, 211, 252, 282, 2364, 28844, 28987, + 1, 6, 40, 96, 134, 182, 187, 226, 267, 297, 2379, 28852, 29002, }; static const short dep17[] = { - 1, 18, 20, 30, 32, 33, 88, 148, 150, 151, 166, 167, 174, 177, 211, 252, 282, - 2074, 2075, 2157, 2159, 2160, 2162, 2163, 2165, 2166, 4127, 28844, 28987, + 1, 25, 27, 38, 40, 41, 96, 156, 158, 159, 174, 175, 182, 187, 226, 267, 297, + 2082, 2083, 2165, 2167, 2168, 2170, 2171, 2173, 2174, 4135, 28852, 29002, }; static const short dep18[] = { - 1, 32, 43, 88, 174, 211, 218, 252, 28844, 28987, + 1, 40, 51, 96, 182, 226, 233, 267, 28852, 29002, }; static const short dep19[] = { - 1, 30, 32, 33, 88, 145, 166, 174, 211, 218, 252, 4127, 28844, 28987, + 1, 38, 40, 41, 96, 153, 174, 182, 226, 233, 267, 4135, 28852, 29002, }; static const short dep20[] = { - 32, 88, 211, 252, + 40, 96, 226, 267, }; static const short dep21[] = { - 88, 166, 211, 252, + 96, 174, 226, 267, }; static const short dep22[] = { - 1, 32, 88, 120, 121, 123, 124, 125, 126, 127, 130, 131, 132, 133, 134, 135, - 136, 137, 138, 139, 140, 142, 143, 144, 145, 146, 147, 148, 151, 152, 153, - 154, 155, 156, 157, 158, 161, 162, 163, 164, 165, 166, 167, 168, 169, 174, - 211, 252, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, - 292, 293, 294, 295, 296, 297, 298, 300, 301, 303, 304, 305, 306, 307, 308, - 309, 310, 311, 312, 313, 28844, 28987, + 1, 40, 96, 128, 129, 131, 132, 133, 134, 135, 138, 139, 140, 141, 142, 143, + 144, 145, 146, 147, 148, 150, 151, 152, 153, 154, 155, 156, 159, 160, 161, + 162, 163, 164, 165, 166, 169, 170, 171, 172, 173, 174, 175, 176, 177, 182, + 226, 267, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, + 307, 308, 309, 310, 311, 312, 313, 315, 316, 318, 319, 320, 321, 322, 323, + 324, 325, 326, 327, 328, 28852, 29002, }; static const short dep23[] = { - 1, 30, 32, 33, 42, 43, 47, 50, 64, 88, 126, 166, 174, 211, 252, 279, 280, - 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, - 296, 297, 298, 300, 301, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, - 313, 4127, 28844, 28987, + 1, 38, 40, 41, 50, 51, 55, 58, 72, 96, 134, 174, 182, 226, 267, 294, 295, + 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, + 311, 312, 313, 315, 316, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, + 328, 4135, 28852, 29002, }; static const short dep24[] = { - 88, 125, 252, 281, + 96, 133, 267, 296, }; static const short dep25[] = { - 88, 126, 166, 252, 281, + 96, 134, 174, 267, 296, }; static const short dep26[] = { - 88, 126, 252, 282, + 96, 134, 267, 297, }; static const short dep27[] = { - 18, 19, 88, 89, 92, 96, 99, 126, 148, 166, 252, 282, + 25, 26, 96, 97, 100, 104, 107, 134, 156, 174, 267, 297, }; static const short dep28[] = { - 32, 33, 88, 166, 252, 2157, 2159, 2160, 2162, 2163, 2165, 2166, 4127, + 40, 41, 96, 174, 267, 2165, 2167, 2168, 2170, 2171, 2173, 2174, 4135, }; static const short dep29[] = { - 1, 18, 32, 88, 174, 199, 200, 211, 252, 2074, 2255, 2258, 2364, 28844, 28987, + 1, 25, 40, 96, 182, 214, 215, 226, 267, 2082, 2270, 2273, 2379, 28852, 29002, }; static const short dep30[] = { - 1, 4, 30, 32, 33, 88, 126, 148, 166, 167, 174, 199, 201, 211, 252, 2074, 2075, - 2157, 2159, 2160, 2162, 2163, 2165, 2166, 2256, 2258, 4127, 28844, 28987, + 1, 6, 38, 40, 41, 96, 134, 156, 174, 175, 182, 214, 216, 226, 267, 2082, 2083, + 2165, 2167, 2168, 2170, 2171, 2173, 2174, 2271, 2273, 4135, 28852, 29002, }; static const short dep31[] = { - 88, 252, + 96, 267, }; static const short dep32[] = { - 88, 166, 252, 2074, 2076, + 96, 174, 267, 2082, 2084, }; static const short dep33[] = { - 32, 33, 88, 148, 166, 167, 252, 2157, 2159, 2160, 2162, 2163, 2165, 2166, - 4127, + 40, 41, 96, 156, 174, 175, 267, 2165, 2167, 2168, 2170, 2171, 2173, 2174, + 4135, }; static const short dep34[] = { - 4, 29, 30, 31, 88, 116, 117, 177, 211, 252, 277, 278, 2364, + 6, 37, 38, 39, 96, 124, 125, 187, 226, 267, 292, 293, 2379, }; static const short dep35[] = { - 4, 29, 32, 33, 88, 148, 166, 167, 177, 211, 252, 277, 278, 316, 2157, 2159, - 2160, 2162, 2163, 2165, 2166, 4127, + 6, 37, 40, 41, 96, 156, 174, 175, 187, 226, 267, 292, 293, 331, 2165, 2167, + 2168, 2170, 2171, 2173, 2174, 4135, }; static const short dep36[] = { - 17, 88, 198, 252, 2364, + 24, 96, 213, 267, 2379, }; static const short dep37[] = { - 17, 32, 33, 88, 148, 166, 167, 198, 252, 2157, 2159, 2160, 2162, 2163, 2165, - 2166, 4127, + 24, 40, 41, 96, 156, 174, 175, 213, 267, 2165, 2167, 2168, 2170, 2171, 2173, + 2174, 4135, }; static const short dep38[] = { - 4, 17, 29, 30, 31, 88, 116, 117, 177, 198, 211, 252, 277, 278, 2364, + 6, 24, 37, 38, 39, 96, 124, 125, 187, 213, 226, 267, 292, 293, 2379, }; static const short dep39[] = { - 4, 17, 29, 32, 33, 88, 148, 166, 167, 177, 198, 211, 252, 277, 278, 316, 2157, - 2159, 2160, 2162, 2163, 2165, 2166, 4127, + 6, 24, 37, 40, 41, 96, 156, 174, 175, 187, 213, 226, 267, 292, 293, 331, 2165, + 2167, 2168, 2170, 2171, 2173, 2174, 4135, }; static const short dep40[] = { - 1, 4, 30, 32, 33, 88, 126, 148, 166, 167, 174, 199, 201, 211, 252, 2157, 2159, - 2160, 2162, 2163, 2165, 2166, 2256, 2258, 4127, 28844, 28987, + 1, 6, 38, 40, 41, 96, 134, 156, 174, 175, 182, 214, 216, 226, 267, 2165, 2167, + 2168, 2170, 2171, 2173, 2174, 2271, 2273, 4135, 28852, 29002, }; static const short dep41[] = { - 88, 166, 252, + 96, 174, 267, }; static const short dep42[] = { - 9, 88, 182, 183, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, - 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, - 22802, 22805, 22806, + 15, 96, 196, 197, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, + 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, 22812, 22813, 22816, + 22817, 22820, 22821, }; static const short dep43[] = { - 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 22794, 22797, - 22798, 22801, 22802, 22805, 22806, + 11, 19, 20, 40, 41, 96, 174, 196, 198, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, 22809, 22812, + 22813, 22816, 22817, 22820, 22821, }; static const short dep44[] = { - 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, 2127, 2295, - 18585, 18586, 18731, 18732, 18734, 18735, 22637, 22638, 22639, 22641, 22642, - 22644, 22645, 22794, 22797, 22798, 22801, 22802, 22805, 22806, + 15, 16, 17, 18, 96, 196, 197, 199, 200, 202, 203, 205, 206, 267, 2135, 2310, + 18593, 18594, 18746, 18747, 18749, 18750, 22645, 22646, 22647, 22649, 22650, + 22652, 22653, 22809, 22812, 22813, 22816, 22817, 22820, 22821, }; static const short dep45[] = { - 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, - 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2295, 4127, 16516, 16518, 18731, - 18733, 18734, 18736, 22794, 22797, 22798, 22801, 22802, 22805, 22806, + 11, 12, 13, 14, 19, 20, 40, 41, 96, 174, 196, 198, 199, 201, 202, 204, 205, + 207, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 2310, 4135, 16524, 16526, + 18746, 18748, 18749, 18751, 22809, 22812, 22813, 22816, 22817, 22820, 22821, + }; static const short dep46[] = { - 10, 88, 185, 186, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, - 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, - 22802, 22805, 22806, + 16, 96, 199, 200, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, + 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, 22812, 22813, 22816, + 22817, 22820, 22821, }; static const short dep47[] = { - 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 22794, 22797, - 22798, 22801, 22802, 22805, 22806, + 12, 19, 20, 40, 41, 96, 174, 199, 201, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, 22809, 22812, + 22813, 22816, 22817, 22820, 22821, }; static const short dep48[] = { - 11, 88, 188, 189, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, - 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, - 22802, 22805, 22806, + 17, 96, 202, 203, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, + 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, 22812, 22813, 22816, + 22817, 22820, 22821, }; static const short dep49[] = { - 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 22794, 22797, - 22798, 22801, 22802, 22805, 22806, + 13, 19, 20, 40, 41, 96, 174, 202, 204, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, 22809, 22812, + 22813, 22816, 22817, 22820, 22821, }; static const short dep50[] = { - 12, 88, 191, 192, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, - 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, - 22802, 22805, 22806, + 18, 96, 205, 206, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, + 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, 22812, 22813, 22816, + 22817, 22820, 22821, }; static const short dep51[] = { - 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 22794, 22797, - 22798, 22801, 22802, 22805, 22806, + 14, 19, 20, 40, 41, 96, 174, 205, 207, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, 22809, 22812, + 22813, 22816, 22817, 22820, 22821, }; static const short dep52[] = { - 9, 88, 182, 183, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 15, 96, 196, 197, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, }; static const short dep53[] = { - 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, + 11, 19, 20, 40, 41, 96, 174, 196, 198, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, }; static const short dep54[] = { - 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, 2127, 2295, - 18585, 18586, 18731, 18732, 18734, 18735, + 15, 16, 17, 18, 96, 196, 197, 199, 200, 202, 203, 205, 206, 267, 2135, 2310, + 18593, 18594, 18746, 18747, 18749, 18750, }; static const short dep55[] = { - 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, - 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2295, 4127, 16516, 16518, 18731, - 18733, 18734, 18736, + 11, 12, 13, 14, 19, 20, 40, 41, 96, 174, 196, 198, 199, 201, 202, 204, 205, + 207, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 2310, 4135, 16524, 16526, + 18746, 18748, 18749, 18751, }; static const short dep56[] = { - 10, 88, 185, 186, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 16, 96, 199, 200, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, }; static const short dep57[] = { - 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, + 12, 19, 20, 40, 41, 96, 174, 199, 201, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, }; static const short dep58[] = { - 11, 88, 188, 189, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 17, 96, 202, 203, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, }; static const short dep59[] = { - 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, + 13, 19, 20, 40, 41, 96, 174, 202, 204, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, }; static const short dep60[] = { - 12, 88, 191, 192, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 18, 96, 205, 206, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, }; static const short dep61[] = { - 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, + 14, 19, 20, 40, 41, 96, 174, 205, 207, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, }; static const short dep62[] = { - 88, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 96, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, }; static const short dep63[] = { - 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2295, 4127, - 16516, 16518, 18731, 18733, 18734, 18736, + 40, 41, 96, 174, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 2310, 4135, + 16524, 16526, 18746, 18748, 18749, 18751, }; static const short dep64[] = { - 5, 88, 178, 252, + 11, 96, 192, 267, }; static const short dep65[] = { - 5, 32, 33, 88, 166, 178, 252, 2157, 2158, 2161, 2164, 4127, + 11, 40, 41, 96, 174, 192, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep66[] = { - 5, 32, 33, 88, 166, 252, 2157, 2158, 2161, 2164, 4127, + 11, 40, 41, 96, 174, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep67[] = { - 6, 88, 179, 252, + 12, 96, 193, 267, }; static const short dep68[] = { - 5, 32, 33, 88, 166, 179, 252, 2157, 2158, 2161, 2164, 4127, + 11, 40, 41, 96, 174, 193, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep69[] = { - 7, 88, 180, 252, + 13, 96, 194, 267, }; static const short dep70[] = { - 5, 32, 33, 88, 166, 180, 252, 2157, 2158, 2161, 2164, 4127, + 11, 40, 41, 96, 174, 194, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep71[] = { - 8, 88, 181, 252, + 14, 96, 195, 267, }; static const short dep72[] = { - 5, 32, 33, 88, 166, 181, 252, 2157, 2158, 2161, 2164, 4127, + 11, 40, 41, 96, 174, 195, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep73[] = { - 9, 88, 183, 184, 252, + 15, 96, 197, 198, 267, }; static const short dep74[] = { - 32, 33, 88, 166, 183, 184, 252, 2157, 2158, 2161, 2164, 4127, + 40, 41, 96, 174, 197, 198, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep75[] = { - 32, 33, 88, 166, 252, 2157, 2158, 2161, 2164, 4127, + 40, 41, 96, 174, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep76[] = { - 10, 88, 186, 187, 252, + 16, 96, 200, 201, 267, }; static const short dep77[] = { - 32, 33, 88, 166, 186, 187, 252, 2157, 2158, 2161, 2164, 4127, + 40, 41, 96, 174, 200, 201, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep78[] = { - 11, 88, 189, 190, 252, + 17, 96, 203, 204, 267, }; static const short dep79[] = { - 32, 33, 88, 166, 189, 190, 252, 2157, 2158, 2161, 2164, 4127, + 40, 41, 96, 174, 203, 204, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep80[] = { - 12, 88, 192, 193, 252, + 18, 96, 206, 207, 267, }; static const short dep81[] = { - 32, 33, 88, 166, 192, 193, 252, 2157, 2158, 2161, 2164, 4127, + 40, 41, 96, 174, 206, 207, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep82[] = { - 9, 13, 14, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, + 15, 19, 20, 40, 41, 96, 156, 174, 175, 267, 2165, 2166, 2169, 2172, 4135, + }; static const short dep83[] = { - 9, 10, 13, 14, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, + 15, 16, 19, 20, 40, 41, 96, 156, 174, 175, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep84[] = { - 9, 11, 13, 14, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, + 15, 17, 19, 20, 40, 41, 96, 156, 174, 175, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep85[] = { - 9, 12, 13, 14, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, + 15, 18, 19, 20, 40, 41, 96, 156, 174, 175, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep86[] = { - 9, 88, 182, 183, 252, + 15, 96, 196, 197, 267, }; static const short dep87[] = { - 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2157, 2158, 2161, 2164, 4127, + 11, 19, 20, 40, 41, 96, 174, 196, 198, 267, 2165, 2166, 2169, 2172, 4135, + }; static const short dep88[] = { - 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, + 15, 16, 17, 18, 96, 196, 197, 199, 200, 202, 203, 205, 206, 267, }; static const short dep89[] = { - 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, - 252, 2157, 2158, 2161, 2164, 4127, + 11, 12, 13, 14, 19, 20, 40, 41, 96, 174, 196, 198, 199, 201, 202, 204, 205, + 207, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep90[] = { - 10, 88, 185, 186, 252, + 16, 96, 199, 200, 267, }; static const short dep91[] = { - 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2157, 2158, 2161, 2164, 4127, + 12, 19, 20, 40, 41, 96, 174, 199, 201, 267, 2165, 2166, 2169, 2172, 4135, + }; static const short dep92[] = { - 11, 88, 188, 189, 252, + 17, 96, 202, 203, 267, }; static const short dep93[] = { - 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2157, 2158, 2161, 2164, 4127, + 13, 19, 20, 40, 41, 96, 174, 202, 204, 267, 2165, 2166, 2169, 2172, 4135, + }; static const short dep94[] = { - 12, 88, 191, 192, 252, + 18, 96, 205, 206, 267, }; static const short dep95[] = { - 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2157, 2158, 2161, 2164, 4127, + 14, 19, 20, 40, 41, 96, 174, 205, 207, 267, 2165, 2166, 2169, 2172, 4135, + }; static const short dep96[] = { - 9, 88, 182, 183, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, - 2318, 2321, 2322, 2325, 2326, + 15, 96, 196, 197, 267, 2165, 2166, 2167, 2169, 2170, 2172, 2173, 2329, 2332, + 2333, 2336, 2337, 2340, 2341, }; static const short dep97[] = { - 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 2314, 2317, 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, + 11, 19, 20, 40, 41, 96, 174, 196, 198, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 2329, 2332, 2333, 2336, 2337, 2340, 2341, 4135, 16524, 16526, + }; static const short dep98[] = { - 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, 2157, 2158, - 2159, 2161, 2162, 2164, 2165, 2314, 2317, 2318, 2321, 2322, 2325, 2326, + 15, 16, 17, 18, 96, 196, 197, 199, 200, 202, 203, 205, 206, 267, 2165, 2166, + 2167, 2169, 2170, 2172, 2173, 2329, 2332, 2333, 2336, 2337, 2340, 2341, }; static const short dep99[] = { - 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, - 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2314, 2317, 2318, 2321, 2322, - 2325, 2326, 4127, 16516, 16518, + 11, 12, 13, 14, 19, 20, 40, 41, 96, 174, 196, 198, 199, 201, 202, 204, 205, + 207, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 2329, 2332, 2333, 2336, + 2337, 2340, 2341, 4135, 16524, 16526, }; static const short dep100[] = { - 10, 88, 185, 186, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, - 2318, 2321, 2322, 2325, 2326, + 16, 96, 199, 200, 267, 2165, 2166, 2167, 2169, 2170, 2172, 2173, 2329, 2332, + 2333, 2336, 2337, 2340, 2341, }; static const short dep101[] = { - 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 2314, 2317, 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, + 12, 19, 20, 40, 41, 96, 174, 199, 201, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 2329, 2332, 2333, 2336, 2337, 2340, 2341, 4135, 16524, 16526, + }; static const short dep102[] = { - 11, 88, 188, 189, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, - 2318, 2321, 2322, 2325, 2326, + 17, 96, 202, 203, 267, 2165, 2166, 2167, 2169, 2170, 2172, 2173, 2329, 2332, + 2333, 2336, 2337, 2340, 2341, }; static const short dep103[] = { - 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 2314, 2317, 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, + 13, 19, 20, 40, 41, 96, 174, 202, 204, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 2329, 2332, 2333, 2336, 2337, 2340, 2341, 4135, 16524, 16526, + }; static const short dep104[] = { - 12, 88, 191, 192, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, - 2318, 2321, 2322, 2325, 2326, + 18, 96, 205, 206, 267, 2165, 2166, 2167, 2169, 2170, 2172, 2173, 2329, 2332, + 2333, 2336, 2337, 2340, 2341, }; static const short dep105[] = { - 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 2314, 2317, 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, + 14, 19, 20, 40, 41, 96, 174, 205, 207, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 2329, 2332, 2333, 2336, 2337, 2340, 2341, 4135, 16524, 16526, + }; static const short dep106[] = { - 9, 88, 182, 183, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, - 22797, 22798, 22801, 22802, 22805, 22806, + 15, 96, 196, 197, 267, 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, + 22812, 22813, 22816, 22817, 22820, 22821, }; static const short dep107[] = { - 5, 13, 14, 32, 33, 88, 166, 182, 184, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 4127, 16516, 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, - + 11, 19, 20, 40, 41, 96, 174, 196, 198, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 4135, 16524, 16526, 22809, 22812, 22813, 22816, 22817, 22820, + 22821, }; static const short dep108[] = { - 9, 10, 11, 12, 88, 182, 183, 185, 186, 188, 189, 191, 192, 252, 22637, 22638, - 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, 22801, 22802, 22805, - 22806, + 15, 16, 17, 18, 96, 196, 197, 199, 200, 202, 203, 205, 206, 267, 22645, 22646, + 22647, 22649, 22650, 22652, 22653, 22809, 22812, 22813, 22816, 22817, 22820, + 22821, }; static const short dep109[] = { - 5, 6, 7, 8, 13, 14, 32, 33, 88, 166, 182, 184, 185, 187, 188, 190, 191, 193, - 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 4127, 16516, 16518, 22794, - 22797, 22798, 22801, 22802, 22805, 22806, + 11, 12, 13, 14, 19, 20, 40, 41, 96, 174, 196, 198, 199, 201, 202, 204, 205, + 207, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 4135, 16524, 16526, 22809, + 22812, 22813, 22816, 22817, 22820, 22821, }; static const short dep110[] = { - 10, 88, 185, 186, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, - 22797, 22798, 22801, 22802, 22805, 22806, + 16, 96, 199, 200, 267, 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, + 22812, 22813, 22816, 22817, 22820, 22821, }; static const short dep111[] = { - 6, 13, 14, 32, 33, 88, 166, 185, 187, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 4127, 16516, 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, - + 12, 19, 20, 40, 41, 96, 174, 199, 201, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 4135, 16524, 16526, 22809, 22812, 22813, 22816, 22817, 22820, + 22821, }; static const short dep112[] = { - 11, 88, 188, 189, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, - 22797, 22798, 22801, 22802, 22805, 22806, + 17, 96, 202, 203, 267, 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, + 22812, 22813, 22816, 22817, 22820, 22821, }; static const short dep113[] = { - 7, 13, 14, 32, 33, 88, 166, 188, 190, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 4127, 16516, 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, - + 13, 19, 20, 40, 41, 96, 174, 202, 204, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 4135, 16524, 16526, 22809, 22812, 22813, 22816, 22817, 22820, + 22821, }; static const short dep114[] = { - 12, 88, 191, 192, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, - 22797, 22798, 22801, 22802, 22805, 22806, + 18, 96, 205, 206, 267, 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, + 22812, 22813, 22816, 22817, 22820, 22821, }; static const short dep115[] = { - 8, 13, 14, 32, 33, 88, 166, 191, 193, 252, 2126, 2127, 2128, 2157, 2158, 2161, - 2164, 4127, 16516, 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, - + 14, 19, 20, 40, 41, 96, 174, 205, 207, 267, 2134, 2135, 2136, 2165, 2166, + 2169, 2172, 4135, 16524, 16526, 22809, 22812, 22813, 22816, 22817, 22820, + 22821, }; static const short dep116[] = { - 88, 252, 2157, 2158, 2159, 2161, 2162, 2164, 2165, 2314, 2317, 2318, 2321, - 2322, 2325, 2326, + 96, 267, 2165, 2166, 2167, 2169, 2170, 2172, 2173, 2329, 2332, 2333, 2336, + 2337, 2340, 2341, }; static const short dep117[] = { - 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2314, 2317, - 2318, 2321, 2322, 2325, 2326, 4127, 16516, 16518, + 40, 41, 96, 174, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 2329, 2332, + 2333, 2336, 2337, 2340, 2341, 4135, 16524, 16526, }; static const short dep118[] = { - 88, 252, 22637, 22638, 22639, 22641, 22642, 22644, 22645, 22794, 22797, 22798, - 22801, 22802, 22805, 22806, + 96, 267, 22645, 22646, 22647, 22649, 22650, 22652, 22653, 22809, 22812, 22813, + 22816, 22817, 22820, 22821, }; static const short dep119[] = { - 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 4127, 16516, - 16518, 22794, 22797, 22798, 22801, 22802, 22805, 22806, + 40, 41, 96, 174, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 4135, 16524, + 16526, 22809, 22812, 22813, 22816, 22817, 22820, 22821, }; static const short dep120[] = { - 13, 14, 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2295, - 4127, 16516, 16518, 18731, 18733, 18734, 18736, + 19, 20, 40, 41, 96, 174, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 2310, + 4135, 16524, 16526, 18746, 18748, 18749, 18751, }; static const short dep121[] = { - 32, 33, 88, 148, 166, 167, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, - 4127, 20605, + 40, 41, 96, 156, 174, 175, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, + 4135, 20613, }; static const short dep122[] = { - 88, 252, 2075, 2076, 2256, 2257, + 96, 267, 2083, 2084, 2271, 2272, }; static const short dep123[] = { - 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2255, 2257, - 4127, 20605, + 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2270, 2272, + 4135, 20613, }; static const short dep124[] = { - 32, 33, 88, 166, 252, 2074, 2076, 2157, 2158, 2161, 2164, 2297, 4127, 20605, + 40, 41, 96, 174, 267, 2082, 2084, 2165, 2166, 2169, 2172, 2312, 4135, 20613, }; static const short dep125[] = { - 88, 252, 14446, 14448, 14449, 14451, 14452, 14454, 14605, 14606, 14609, 14610, - 14613, 14614, + 96, 267, 14454, 14456, 14457, 14459, 14460, 14462, 14620, 14621, 14624, 14625, + 14628, 14629, }; static const short dep126[] = { - 32, 33, 88, 166, 252, 2129, 2130, 2131, 4127, 14605, 14606, 14609, 14610, - 14613, 14614, 20605, 24685, 24686, 24689, 24692, + 40, 41, 96, 174, 267, 2137, 2138, 2139, 4135, 14620, 14621, 14624, 14625, + 14628, 14629, 20613, 24693, 24694, 24697, 24700, }; static const short dep127[] = { - 88, 113, 115, 116, 118, 252, 273, 274, 277, 278, + 96, 121, 123, 124, 126, 267, 288, 289, 292, 293, }; static const short dep128[] = { - 32, 33, 88, 166, 252, 273, 274, 277, 278, 4127, 24685, 24686, 24689, 24692, + 40, 41, 96, 174, 267, 288, 289, 292, 293, 4135, 24693, 24694, 24697, 24700, }; static const short dep129[] = { - 32, 33, 88, 166, 252, 2157, 2158, 2161, 2164, 2297, 4127, 20605, + 40, 41, 96, 174, 267, 2165, 2166, 2169, 2172, 2312, 4135, 20613, }; static const short dep130[] = { - 32, 33, 88, 110, 113, 116, 166, 252, 2297, 4127, 20605, 24685, + 40, 41, 96, 118, 121, 124, 174, 267, 2312, 4135, 20613, 24693, }; static const short dep131[] = { - 4, 17, 19, 20, 88, 177, 198, 201, 252, 2073, 2254, + 6, 24, 26, 27, 96, 187, 213, 216, 267, 2081, 2269, }; static const short dep132[] = { - 32, 33, 88, 166, 177, 198, 200, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, - 2254, 4127, 20605, + 40, 41, 96, 174, 187, 213, 215, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, + 2269, 4135, 20613, }; static const short dep133[] = { - 4, 17, 18, 19, 32, 33, 88, 166, 252, 2073, 2157, 2158, 2161, 2164, 2297, 4127, - 20605, + 6, 24, 25, 26, 40, 41, 96, 174, 267, 2081, 2165, 2166, 2169, 2172, 2312, 4135, + 20613, }; static const short dep134[] = { - 0, 32, 33, 88, 148, 166, 167, 252, 2157, 2158, 2161, 2164, 4127, + 0, 40, 41, 96, 156, 174, 175, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep135[] = { - 0, 88, 173, 252, + 0, 96, 181, 267, }; static const short dep136[] = { - 0, 32, 33, 88, 148, 166, 167, 173, 252, 2157, 2158, 2161, 2164, 4127, + 0, 40, 41, 96, 156, 174, 175, 181, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep137[] = { - 32, 33, 88, 166, 173, 252, 2157, 2158, 2161, 2164, 4127, + 40, 41, 96, 174, 181, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep138[] = { - 2, 21, 88, 175, 202, 252, 28844, 28987, + 2, 28, 96, 183, 217, 267, 28852, 29002, }; static const short dep139[] = { - 1, 2, 21, 22, 88, 160, 161, 166, 175, 202, 252, 28844, 28987, + 1, 2, 28, 29, 96, 168, 169, 174, 183, 217, 267, 28852, 29002, }; static const short dep140[] = { - 1, 21, 22, 30, 32, 33, 88, 160, 161, 166, 175, 202, 252, 4127, 28844, 28987, + 1, 28, 29, 38, 40, 41, 96, 168, 169, 174, 183, 217, 267, 4135, 28852, 29002, }; static const short dep141[] = { - 0, 32, 33, 88, 166, 173, 252, 2157, 2158, 2161, 2164, 4127, + 0, 40, 41, 96, 174, 181, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep142[] = { - 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21, 22, 23, 88, 174, 175, - 176, 178, 179, 180, 181, 183, 184, 186, 187, 189, 190, 192, 193, 194, 195, - 196, 202, 203, 204, 252, 2064, 2073, 2245, 2254, 28844, 28987, + 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, + 28, 29, 30, 31, 96, 182, 183, 184, 185, 186, 188, 189, 190, 191, 192, 193, + 194, 195, 197, 198, 200, 201, 203, 204, 206, 207, 208, 209, 210, 211, 217, + 218, 219, 267, 2071, 2081, 2260, 2269, 28852, 29002, }; static const short dep143[] = { - 22, 32, 33, 88, 126, 166, 174, 175, 176, 178, 179, 180, 181, 183, 184, 186, - 187, 189, 190, 192, 193, 194, 195, 196, 202, 203, 204, 252, 2129, 2130, 2131, - 2157, 2158, 2161, 2164, 2245, 2254, 4127, 20605, 28844, 28987, + 29, 40, 41, 96, 134, 174, 182, 183, 184, 185, 186, 188, 189, 190, 191, 192, + 193, 194, 195, 197, 198, 200, 201, 203, 204, 206, 207, 208, 209, 210, 211, + 217, 218, 219, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2260, 2269, + 4135, 20613, 28852, 29002, }; static const short dep144[] = { - 88, 252, 14455, 14457, 14458, 14460, 14489, 14490, 14505, 14615, 14616, 14636, - 14637, 14639, 14640, 14649, + 96, 267, 14463, 14465, 14466, 14468, 14497, 14498, 14513, 14630, 14631, 14651, + 14652, 14654, 14655, 14664, }; static const short dep145[] = { - 32, 33, 88, 165, 166, 252, 2157, 2158, 2161, 2164, 4127, 14615, 14616, 14636, - 14637, 14639, 14640, 14649, + 40, 41, 96, 173, 174, 267, 2165, 2166, 2169, 2172, 4135, 14630, 14631, 14651, + 14652, 14654, 14655, 14664, }; static const short dep146[] = { - 14455, 14457, 14458, 14460, 14489, 14490, 14505, 14615, 14616, 14636, 14637, - 14639, 14640, 14649, + 14463, 14465, 14466, 14468, 14497, 14498, 14513, 14630, 14631, 14651, 14652, + 14654, 14655, 14664, }; static const short dep147[] = { - 165, 14615, 14616, 14636, 14637, 14639, 14640, 14649, + 173, 14630, 14631, 14651, 14652, 14654, 14655, 14664, }; static const short dep148[] = { - 88, 252, 14456, 14457, 14459, 14460, 14468, 14469, 14470, 14471, 14472, 14473, - 14474, 14475, 14477, 14480, 14481, 14489, 14490, 14491, 14492, 14493, 14498, - 14499, 14500, 14501, 14505, 14615, 14616, 14622, 14623, 14624, 14625, 14627, - 14629, 14636, 14637, 14639, 14640, 14641, 14642, 14645, 14646, 14649, + 96, 267, 14464, 14465, 14467, 14468, 14476, 14477, 14478, 14479, 14480, 14481, + 14482, 14483, 14485, 14488, 14489, 14497, 14498, 14499, 14500, 14501, 14506, + 14507, 14508, 14509, 14513, 14630, 14631, 14637, 14638, 14639, 14640, 14642, + 14644, 14651, 14652, 14654, 14655, 14656, 14657, 14660, 14661, 14664, }; static const short dep149[] = { - 32, 33, 64, 88, 126, 166, 252, 2157, 2158, 2161, 2164, 4127, 14615, 14616, - 14622, 14623, 14624, 14625, 14627, 14629, 14636, 14637, 14639, 14640, 14641, - 14642, 14645, 14646, 14649, + 40, 41, 72, 96, 134, 174, 267, 2165, 2166, 2169, 2172, 4135, 14630, 14631, + 14637, 14638, 14639, 14640, 14642, 14644, 14651, 14652, 14654, 14655, 14656, + 14657, 14660, 14661, 14664, }; static const short dep150[] = { - 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 21, 22, 23, 32, 33, 88, 126, - 163, 166, 252, 2064, 2073, 2157, 2158, 2161, 2164, 2297, 4127, 20605, 28844, - + 1, 2, 3, 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, + 28, 29, 30, 31, 40, 41, 96, 134, 171, 174, 267, 2071, 2081, 2165, 2166, 2169, + 2172, 2312, 4135, 20613, 28852, }; static const short dep151[] = { - 35, 36, 37, 38, 39, 40, 41, 42, 44, 45, 46, 47, 48, 49, 50, 52, 53, 54, 55, - 56, 57, 59, 61, 62, 63, 64, 85, 87, 88, 213, 214, 215, 216, 217, 218, 219, - 220, 221, 222, 223, 225, 226, 227, 228, 229, 231, 233, 234, 235, 251, 252, - 2108, 2280, + 43, 44, 45, 46, 47, 48, 49, 50, 52, 53, 54, 55, 56, 57, 58, 60, 61, 62, 63, + 64, 65, 67, 69, 70, 71, 72, 93, 95, 96, 228, 229, 230, 231, 232, 233, 234, + 235, 236, 237, 238, 240, 241, 242, 243, 244, 246, 248, 249, 250, 266, 267, + 2116, 2295, }; static const short dep152[] = { - 32, 33, 87, 88, 126, 145, 166, 213, 214, 215, 216, 217, 218, 219, 220, 221, - 222, 223, 225, 226, 227, 228, 229, 231, 233, 234, 235, 251, 252, 2129, 2130, - 2131, 2157, 2158, 2161, 2164, 2280, 4127, 20605, + 40, 41, 95, 96, 134, 153, 174, 228, 229, 230, 231, 232, 233, 234, 235, 236, + 237, 238, 240, 241, 242, 243, 244, 246, 248, 249, 250, 266, 267, 2137, 2138, + 2139, 2165, 2166, 2169, 2172, 2295, 4135, 20613, }; static const short dep153[] = { - 51, 86, 88, 224, 251, 252, 2131, 2297, + 59, 94, 96, 239, 266, 267, 2139, 2312, }; static const short dep154[] = { - 32, 33, 35, 36, 38, 40, 41, 43, 44, 45, 46, 48, 49, 52, 53, 55, 56, 57, 58, - 59, 61, 62, 63, 85, 86, 88, 126, 145, 166, 224, 251, 252, 2099, 2108, 2157, - 2158, 2161, 2164, 2297, 4127, 20605, + 40, 41, 43, 44, 46, 48, 49, 51, 52, 53, 54, 56, 57, 60, 61, 63, 64, 65, 66, + 67, 69, 70, 71, 93, 94, 96, 134, 153, 174, 239, 266, 267, 2107, 2116, 2165, + 2166, 2169, 2172, 2312, 4135, 20613, }; static const short dep155[] = { - 2, 21, 33, 88, 175, 202, 211, 252, 2131, 2297, 28844, 28987, + 2, 28, 41, 96, 183, 217, 226, 267, 2139, 2312, 28852, 29002, }; static const short dep156[] = { - 2, 18, 19, 21, 22, 30, 32, 33, 88, 160, 161, 166, 175, 202, 211, 252, 2297, - 4127, 20605, 28844, 28987, + 2, 25, 26, 28, 29, 38, 40, 41, 96, 168, 169, 174, 183, 217, 226, 267, 2312, + 4135, 20613, 28852, 29002, }; static const short dep157[] = { - 88, 120, 121, 123, 124, 128, 129, 132, 133, 134, 135, 136, 137, 138, 139, - 141, 144, 145, 149, 150, 153, 154, 155, 156, 157, 159, 160, 162, 163, 164, - 165, 167, 168, 169, 252, 279, 280, 284, 286, 287, 288, 289, 291, 293, 297, - 300, 301, 303, 304, 305, 306, 308, 309, 310, 312, 313, + 96, 128, 129, 131, 132, 136, 137, 140, 141, 142, 143, 144, 145, 146, 147, + 149, 152, 153, 157, 158, 161, 162, 163, 164, 165, 167, 168, 170, 171, 172, + 173, 175, 176, 177, 267, 294, 295, 299, 301, 302, 303, 304, 306, 308, 312, + 315, 316, 318, 319, 320, 321, 323, 324, 325, 327, 328, }; static const short dep158[] = { - 32, 33, 64, 88, 126, 166, 252, 279, 280, 284, 286, 287, 288, 289, 291, 293, - 297, 300, 301, 303, 304, 305, 306, 308, 309, 310, 312, 313, 2129, 2130, 2131, - 2157, 2158, 2161, 2164, 4127, 20605, + 40, 41, 72, 96, 134, 174, 267, 294, 295, 299, 301, 302, 303, 304, 306, 308, + 312, 315, 316, 318, 319, 320, 321, 323, 324, 325, 327, 328, 2137, 2138, 2139, + 2165, 2166, 2169, 2172, 4135, 20613, }; static const short dep159[] = { - 88, 119, 121, 122, 124, 153, 154, 169, 252, 279, 280, 300, 301, 303, 304, - 313, + 96, 127, 129, 130, 132, 161, 162, 177, 267, 294, 295, 315, 316, 318, 319, + 328, }; static const short dep160[] = { - 32, 33, 88, 165, 166, 252, 279, 280, 300, 301, 303, 304, 313, 2129, 2130, - 2131, 2157, 2158, 2161, 2164, 4127, 20605, + 40, 41, 96, 173, 174, 267, 294, 295, 315, 316, 318, 319, 328, 2137, 2138, + 2139, 2165, 2166, 2169, 2172, 4135, 20613, }; static const short dep161[] = { - 32, 33, 88, 121, 124, 126, 129, 130, 133, 135, 137, 139, 141, 142, 144, 148, - 149, 151, 152, 153, 154, 156, 157, 159, 161, 162, 164, 166, 168, 169, 252, - 2157, 2158, 2161, 2164, 2297, 4127, 20605, + 40, 41, 96, 129, 132, 134, 137, 138, 141, 143, 145, 147, 149, 150, 152, 156, + 157, 159, 160, 161, 162, 164, 165, 167, 169, 170, 172, 174, 176, 177, 267, + 2165, 2166, 2169, 2172, 2312, 4135, 20613, }; static const short dep162[] = { - 32, 33, 88, 121, 124, 153, 154, 166, 169, 252, 2157, 2158, 2161, 2164, 2297, - 4127, 20605, + 40, 41, 96, 129, 132, 161, 162, 174, 177, 267, 2165, 2166, 2169, 2172, 2312, + 4135, 20613, }; static const short dep163[] = { - 32, 33, 67, 68, 73, 75, 88, 102, 126, 155, 166, 170, 252, 2129, 2130, 2131, - 2157, 2158, 2161, 2164, 2297, 4127, 20605, + 40, 41, 75, 76, 81, 83, 96, 110, 134, 163, 174, 178, 267, 2137, 2138, 2139, + 2165, 2166, 2169, 2172, 2312, 4135, 20613, }; static const short dep164[] = { - 32, 33, 67, 68, 73, 75, 88, 102, 126, 127, 128, 130, 131, 155, 166, 170, 252, - 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + 40, 41, 75, 76, 81, 83, 96, 110, 134, 135, 136, 138, 139, 163, 174, 178, 267, + 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, }; static const short dep165[] = { - 68, 69, 88, 92, 93, 239, 240, 252, 254, 255, + 76, 77, 96, 100, 101, 254, 255, 267, 269, 270, }; static const short dep166[] = { - 32, 33, 39, 54, 69, 71, 77, 88, 90, 93, 126, 145, 166, 170, 239, 240, 252, - 254, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + 40, 41, 47, 62, 77, 79, 85, 96, 98, 101, 134, 153, 174, 178, 254, 255, 267, + 269, 270, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, }; static const short dep167[] = { - 32, 33, 39, 54, 69, 71, 88, 90, 93, 95, 97, 126, 145, 166, 170, 239, 240, - 252, 254, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + 40, 41, 47, 62, 77, 79, 96, 98, 101, 103, 105, 134, 153, 174, 178, 254, 255, + 267, 269, 270, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, }; static const short dep168[] = { - 88, 252, 12458, 12459, 12602, + 96, 267, 12466, 12467, 12617, }; static const short dep169[] = { - 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, - 12602, 20605, + 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, + 12617, 20613, }; static const short dep170[] = { - 88, 252, 6210, 6211, 6381, + 96, 267, 6218, 6219, 6396, }; static const short dep171[] = { - 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, - 6381, 20605, + 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, + 6396, 20613, }; static const short dep172[] = { - 88, 252, 6228, 6394, + 96, 267, 6236, 6409, }; static const short dep173[] = { - 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, - 6394, 20605, + 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, + 6409, 20613, }; static const short dep174[] = { - 88, 252, 6246, 6247, 6248, 6249, 6405, 6407, 8454, + 96, 267, 6254, 6255, 6256, 6257, 6420, 6422, 8469, }; static const short dep175[] = { - 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, - 6249, 6406, 6407, 8295, 8453, 20605, + 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, + 6257, 6421, 6422, 8303, 8468, 20613, }; static const short dep176[] = { - 88, 252, 6250, 6251, 6408, + 96, 267, 6258, 6259, 6423, }; static const short dep177[] = { - 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, - 6408, 20605, + 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, + 6423, 20613, }; static const short dep178[] = { - 88, 252, 6252, 6409, + 96, 267, 6260, 6424, }; static const short dep179[] = { - 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, - 6409, 20605, + 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, + 6424, 20613, }; static const short dep180[] = { - 88, 252, 10341, 10500, + 96, 267, 10349, 10515, }; static const short dep181[] = { - 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, - 10500, 20605, + 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, + 10515, 20613, }; static const short dep182[] = { - 68, 69, 73, 74, 88, 92, 93, 239, 240, 242, 243, 252, 254, 255, + 76, 77, 81, 82, 96, 100, 101, 254, 255, 257, 258, 267, 269, 270, }; static const short dep183[] = { - 32, 33, 39, 54, 69, 71, 74, 77, 88, 90, 93, 126, 145, 166, 170, 239, 240, - 242, 244, 252, 254, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + 40, 41, 47, 62, 77, 79, 82, 85, 96, 98, 101, 134, 153, 174, 178, 254, 255, + 257, 259, 267, 269, 270, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, }; static const short dep184[] = { - 68, 69, 88, 92, 93, 95, 96, 239, 240, 252, 254, 255, 256, 257, + 76, 77, 96, 100, 101, 103, 104, 254, 255, 267, 269, 270, 271, 272, }; static const short dep185[] = { - 32, 33, 39, 54, 69, 71, 88, 90, 93, 95, 97, 126, 145, 166, 170, 239, 240, - 252, 254, 255, 256, 257, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + 40, 41, 47, 62, 77, 79, 96, 98, 101, 103, 105, 134, 153, 174, 178, 254, 255, + 267, 269, 270, 271, 272, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, }; static const short dep186[] = { - 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, - 4127, 12459, 20605, + 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, + 4135, 12467, 20613, }; static const short dep187[] = { - 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, - 4127, 6210, 20605, + 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, + 4135, 6218, 20613, }; static const short dep188[] = { - 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, - 4127, 6228, 20605, + 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, + 4135, 6236, 20613, }; static const short dep189[] = { - 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, - 4127, 6248, 8294, 20605, + 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, + 4135, 6256, 8302, 20613, }; static const short dep190[] = { - 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, - 4127, 6250, 20605, + 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, + 4135, 6258, 20613, }; static const short dep191[] = { - 32, 33, 88, 126, 165, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, - 2297, 4127, 6251, 6252, 20605, + 40, 41, 96, 134, 173, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, + 2312, 4135, 6259, 6260, 20613, }; static const short dep192[] = { - 32, 33, 88, 126, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, - 4127, 10341, 20605, + 40, 41, 96, 134, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, + 4135, 10349, 20613, }; static const short dep193[] = { - 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, 4127, - 6178, 20605, + 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, 4135, + 6186, 20613, }; static const short dep194[] = { - 68, 70, 71, 88, 89, 90, 91, 238, 239, 252, 253, 254, + 76, 78, 79, 96, 97, 98, 99, 253, 254, 267, 268, 269, }; static const short dep195[] = { - 32, 33, 69, 70, 74, 76, 88, 91, 93, 95, 98, 126, 166, 170, 238, 240, 252, - 253, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + 40, 41, 77, 78, 82, 84, 96, 99, 101, 103, 106, 134, 174, 178, 253, 255, 267, + 268, 270, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, }; static const short dep196[] = { - 68, 70, 71, 72, 88, 89, 90, 91, 94, 238, 239, 241, 252, 253, 254, + 76, 78, 79, 80, 96, 97, 98, 99, 102, 253, 254, 256, 267, 268, 269, }; static const short dep197[] = { - 32, 33, 69, 70, 72, 74, 76, 88, 91, 93, 94, 95, 98, 126, 166, 170, 238, 240, - 241, 252, 253, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + 40, 41, 77, 78, 80, 82, 84, 96, 99, 101, 102, 103, 106, 134, 174, 178, 253, + 255, 256, 267, 268, 270, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, }; static const short dep198[] = { - 68, 70, 71, 75, 76, 77, 88, 89, 90, 91, 238, 239, 244, 245, 252, 253, 254, + 76, 78, 79, 83, 84, 85, 96, 97, 98, 99, 253, 254, 259, 260, 267, 268, 269, }; static const short dep199[] = { - 32, 33, 69, 70, 74, 76, 88, 91, 93, 126, 166, 170, 238, 240, 243, 245, 252, - 253, 255, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + 40, 41, 77, 78, 82, 84, 96, 99, 101, 134, 174, 178, 253, 255, 258, 260, 267, + 268, 270, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, }; static const short dep200[] = { - 68, 70, 71, 88, 89, 90, 91, 97, 98, 99, 238, 239, 252, 253, 254, 257, 258, + 76, 78, 79, 96, 97, 98, 99, 105, 106, 107, 253, 254, 267, 268, 269, 272, 273, }; static const short dep201[] = { - 32, 33, 69, 70, 88, 91, 93, 95, 98, 126, 166, 170, 238, 240, 252, 253, 255, - 256, 258, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 4127, 20605, + 40, 41, 77, 78, 96, 99, 101, 103, 106, 134, 174, 178, 253, 255, 267, 268, + 270, 271, 273, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 4135, 20613, }; static const short dep202[] = { - 32, 33, 38, 62, 88, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, - 2297, 4127, 20605, + 40, 41, 46, 70, 96, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, + 2312, 4135, 20613, }; static const short dep203[] = { - 32, 33, 88, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, - 4127, 20605, + 40, 41, 96, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, + 4135, 20613, }; static const short dep204[] = { - 32, 33, 68, 73, 75, 88, 126, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, - 2161, 2164, 2297, 4127, 20605, + 40, 41, 76, 81, 83, 96, 134, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, + 2169, 2172, 2312, 4135, 20613, }; static const short dep205[] = { - 32, 33, 88, 148, 166, 167, 252, 2126, 2127, 2128, 2129, 2130, 2131, 2157, - 2158, 2161, 2164, 4127, 16516, 16518, 20605, + 40, 41, 96, 156, 174, 175, 267, 2134, 2135, 2136, 2137, 2138, 2139, 2165, + 2166, 2169, 2172, 4135, 16524, 16526, 20613, }; static const short dep206[] = { - 32, 33, 68, 73, 75, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, - 4127, 20605, + 40, 41, 76, 81, 83, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, + 4135, 20613, }; static const short dep207[] = { - 32, 33, 69, 70, 88, 91, 126, 166, 238, 240, 252, 253, 255, 2129, 2130, 2131, - 2157, 2158, 2161, 2164, 4127, 20605, + 40, 41, 77, 78, 96, 99, 134, 174, 253, 255, 267, 268, 270, 2137, 2138, 2139, + 2165, 2166, 2169, 2172, 4135, 20613, }; static const short dep208[] = { - 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, 130, - 131, 138, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2297, - 4127, 20605, + 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, 138, + 139, 146, 163, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2312, + 4135, 20613, }; static const short dep209[] = { - 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, - 130, 131, 138, 140, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, - 2164, 2297, 4127, 20605, + 5, 96, 186, 267, 2139, 2312, }; static const short dep210[] = { - 0, 88, 173, 252, 2131, 2297, + 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, 138, + 139, 146, 163, 174, 178, 186, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, + 2312, 4135, 20613, }; static const short dep211[] = { - 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, - 130, 131, 138, 155, 166, 170, 173, 252, 2129, 2130, 2131, 2157, 2158, 2161, - 2164, 2297, 4127, 20605, + 40, 41, 44, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, + 138, 139, 146, 148, 163, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, 2169, + 2172, 2312, 4135, 20613, }; static const short dep212[] = { - 0, 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, - 128, 130, 131, 138, 140, 155, 166, 170, 173, 252, 2129, 2130, 2131, 2157, - 2158, 2161, 2164, 2297, 4127, 20605, + 0, 96, 181, 267, 2139, 2312, }; static const short dep213[] = { - 23, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, - 130, 131, 138, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, - 2297, 4127, 20605, + 0, 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, + 138, 139, 146, 163, 174, 178, 181, 267, 2137, 2138, 2139, 2165, 2166, 2169, + 2172, 2312, 4135, 20613, }; static const short dep214[] = { - 0, 88, 173, 252, 2297, 26706, + 0, 40, 41, 44, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, + 136, 138, 139, 146, 148, 163, 174, 178, 181, 267, 2137, 2138, 2139, 2165, + 2166, 2169, 2172, 2312, 4135, 20613, }; static const short dep215[] = { - 0, 88, 100, 173, 252, 259, + 31, 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, + 138, 139, 146, 163, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, + 2312, 4135, 20613, }; static const short dep216[] = { - 0, 32, 33, 67, 68, 73, 75, 88, 102, 119, 120, 122, 123, 126, 127, 128, 130, - 131, 138, 155, 166, 170, 173, 252, 259, 2129, 2130, 2131, 2157, 2158, 2161, - 2164, 4127, 20605, + 0, 96, 181, 267, 2312, 26714, }; static const short dep217[] = { - 0, 23, 88, 100, 173, 204, 252, 259, + 0, 96, 108, 181, 267, 274, }; static const short dep218[] = { - 0, 32, 33, 67, 68, 73, 75, 88, 102, 119, 120, 122, 123, 126, 127, 128, 130, - 131, 138, 155, 166, 170, 173, 204, 252, 259, 2129, 2130, 2131, 2157, 2158, - 2161, 2164, 4127, 20605, + 0, 40, 41, 75, 76, 81, 83, 96, 110, 127, 128, 130, 131, 134, 135, 136, 138, + 139, 146, 163, 174, 178, 181, 267, 274, 2137, 2138, 2139, 2165, 2166, 2169, + 2172, 4135, 20613, }; static const short dep219[] = { - 0, 88, 100, 173, 252, 259, 2131, 2297, + 0, 5, 40, 41, 75, 76, 81, 83, 96, 110, 127, 128, 130, 131, 134, 135, 136, + 138, 139, 146, 163, 174, 178, 181, 267, 274, 2137, 2138, 2139, 2165, 2166, + 2169, 2172, 4135, 20613, }; static const short dep220[] = { - 0, 3, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, - 128, 130, 131, 138, 155, 166, 170, 173, 252, 259, 2129, 2130, 2131, 2157, - 2158, 2161, 2164, 2297, 4127, 20605, + 0, 31, 96, 108, 181, 219, 267, 274, }; static const short dep221[] = { - 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, - 130, 131, 138, 155, 166, 170, 173, 252, 259, 2129, 2130, 2131, 2157, 2158, - 2161, 2164, 2297, 4127, 20605, + 0, 40, 41, 75, 76, 81, 83, 96, 110, 127, 128, 130, 131, 134, 135, 136, 138, + 139, 146, 163, 174, 178, 181, 219, 267, 274, 2137, 2138, 2139, 2165, 2166, + 2169, 2172, 4135, 20613, }; static const short dep222[] = { - 32, 33, 88, 166, 252, 2126, 2127, 2128, 2157, 2158, 2161, 2164, 2297, 4127, - 16516, 16518, 20605, + 0, 96, 108, 181, 267, 274, 2139, 2312, }; static const short dep223[] = { - 0, 32, 33, 67, 68, 73, 75, 88, 102, 119, 120, 122, 123, 126, 127, 128, 130, - 131, 138, 155, 166, 170, 173, 252, 259, 2129, 2130, 2131, 2157, 2158, 2161, - 2164, 2297, 4127, 20605, + 0, 4, 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, + 136, 138, 139, 146, 163, 174, 178, 181, 267, 274, 2137, 2138, 2139, 2165, + 2166, 2169, 2172, 2312, 4135, 20613, }; static const short dep224[] = { - 0, 23, 88, 100, 173, 204, 252, 259, 2131, 2297, + 0, 4, 5, 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, + 136, 138, 139, 146, 163, 174, 178, 181, 267, 274, 2137, 2138, 2139, 2165, + 2166, 2169, 2172, 2312, 4135, 20613, }; static const short dep225[] = { - 0, 32, 33, 67, 68, 73, 75, 88, 102, 119, 120, 122, 123, 126, 127, 128, 130, - 131, 138, 155, 166, 170, 173, 204, 252, 259, 2129, 2130, 2131, 2157, 2158, - 2161, 2164, 2297, 4127, 20605, + 0, 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, + 138, 139, 146, 163, 174, 178, 181, 267, 274, 2137, 2138, 2139, 2165, 2166, + 2169, 2172, 2312, 4135, 20613, }; static const short dep226[] = { - 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, 130, - 131, 138, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2295, - 4127, 16516, 16518, 18731, 18733, 18734, 18736, 20605, + 40, 41, 96, 174, 267, 2134, 2135, 2136, 2165, 2166, 2169, 2172, 2312, 4135, + 16524, 16526, 20613, }; static const short dep227[] = { - 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, - 130, 131, 138, 140, 155, 166, 170, 252, 2129, 2130, 2131, 2157, 2158, 2161, - 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 20605, + 0, 40, 41, 75, 76, 81, 83, 96, 110, 127, 128, 130, 131, 134, 135, 136, 138, + 139, 146, 163, 174, 178, 181, 267, 274, 2137, 2138, 2139, 2165, 2166, 2169, + 2172, 2312, 4135, 20613, }; static const short dep228[] = { - 0, 88, 173, 252, 2127, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 0, 31, 96, 108, 181, 219, 267, 274, 2139, 2312, }; static const short dep229[] = { - 0, 32, 33, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, 128, - 130, 131, 138, 155, 166, 170, 173, 252, 2129, 2130, 2131, 2157, 2158, 2161, - 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 20605, + 0, 40, 41, 75, 76, 81, 83, 96, 110, 127, 128, 130, 131, 134, 135, 136, 138, + 139, 146, 163, 174, 178, 181, 219, 267, 274, 2137, 2138, 2139, 2165, 2166, + 2169, 2172, 2312, 4135, 20613, }; static const short dep230[] = { - 0, 32, 33, 36, 67, 68, 73, 75, 88, 100, 102, 119, 120, 122, 123, 126, 127, - 128, 130, 131, 138, 140, 155, 166, 170, 173, 252, 2129, 2130, 2131, 2157, - 2158, 2161, 2164, 2295, 4127, 16516, 16518, 18731, 18733, 18734, 18736, 20605, - + 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, 138, + 139, 146, 163, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2310, + 4135, 16524, 16526, 18746, 18748, 18749, 18751, 20613, }; static const short dep231[] = { - 0, 88, 173, 252, 2128, 2295, 18585, 18586, 18731, 18732, 18734, 18735, + 40, 41, 44, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, + 138, 139, 146, 148, 163, 174, 178, 267, 2137, 2138, 2139, 2165, 2166, 2169, + 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, 20613, }; static const short dep232[] = { - 32, 33, 67, 88, 126, 140, 166, 252, 2157, 2158, 2161, 2164, 4127, + 0, 96, 181, 267, 2135, 2310, 18593, 18594, 18746, 18747, 18749, 18750, }; static const short dep233[] = { - 32, 33, 67, 88, 126, 127, 131, 140, 166, 252, 2157, 2158, 2161, 2164, 4127, - + 0, 40, 41, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, 136, + 138, 139, 146, 163, 174, 178, 181, 267, 2137, 2138, 2139, 2165, 2166, 2169, + 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, 20613, }; static const short dep234[] = { - 32, 33, 67, 88, 126, 140, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, - 2297, 4127, 20605, + 0, 40, 41, 44, 75, 76, 81, 83, 96, 108, 110, 127, 128, 130, 131, 134, 135, + 136, 138, 139, 146, 148, 163, 174, 178, 181, 267, 2137, 2138, 2139, 2165, + 2166, 2169, 2172, 2310, 4135, 16524, 16526, 18746, 18748, 18749, 18751, 20613, + }; static const short dep235[] = { - 32, 33, 67, 88, 126, 127, 131, 140, 166, 252, 2129, 2130, 2131, 2157, 2158, - 2161, 2164, 2297, 4127, 20605, + 0, 96, 181, 267, 2136, 2310, 18593, 18594, 18746, 18747, 18749, 18750, }; static const short dep236[] = { - 32, 33, 88, 166, 252, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2295, 4127, - 16516, 16518, 18731, 18733, 18734, 18736, 20605, + 0, 40, 41, 75, 76, 81, 83, 96, 110, 127, 128, 130, 131, 134, 135, 136, 138, + 139, 146, 163, 174, 178, 181, 267, 274, 2134, 2135, 2136, 2137, 2138, 2139, + 2165, 2166, 2169, 2172, 4135, 16524, 16526, 20613, }; static const short dep237[] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 19, 20, 21, 22, 23, - 88, 174, 175, 176, 177, 178, 179, 180, 181, 183, 184, 186, 187, 189, 190, - 192, 193, 194, 195, 196, 198, 201, 202, 203, 204, 252, 2064, 2073, 2131, 2245, - 2254, 2297, 28844, 28987, + 40, 41, 75, 96, 134, 148, 174, 267, 2165, 2166, 2169, 2172, 4135, }; static const short dep238[] = { - 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, - 32, 33, 88, 126, 163, 166, 174, 175, 176, 177, 178, 179, 180, 181, 183, 184, - 186, 187, 189, 190, 192, 193, 194, 195, 196, 198, 200, 202, 203, 204, 252, - 2064, 2073, 2129, 2130, 2131, 2157, 2158, 2161, 2164, 2245, 2254, 2297, 4127, - 20605, 28844, 28987, + 40, 41, 75, 96, 134, 135, 139, 148, 174, 267, 2165, 2166, 2169, 2172, 4135, + +}; + +static const short dep239[] = { + 40, 41, 75, 96, 134, 148, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, + 2312, 4135, 20613, +}; + +static const short dep240[] = { + 40, 41, 75, 96, 134, 135, 139, 148, 174, 267, 2137, 2138, 2139, 2165, 2166, + 2169, 2172, 2312, 4135, 20613, +}; + +static const short dep241[] = { + 40, 41, 96, 174, 267, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2310, 4135, + 16524, 16526, 18746, 18748, 18749, 18751, 20613, +}; + +static const short dep242[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, + 22, 24, 26, 27, 28, 29, 30, 31, 96, 182, 183, 184, 185, 186, 187, 188, 189, + 190, 191, 192, 193, 194, 195, 197, 198, 200, 201, 203, 204, 206, 207, 208, + 209, 210, 211, 213, 216, 217, 218, 219, 267, 2071, 2081, 2139, 2260, 2269, + 2312, 28852, 29002, +}; + +static const short dep243[] = { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, + 22, 24, 25, 26, 28, 29, 30, 31, 40, 41, 96, 134, 171, 174, 182, 183, 184, + 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 197, 198, 200, 201, + 203, 204, 206, 207, 208, 209, 210, 211, 213, 215, 217, 218, 219, 267, 2071, + 2081, 2137, 2138, 2139, 2165, 2166, 2169, 2172, 2260, 2269, 2312, 4135, 20613, + 28852, 29002, }; #define NELS(X) (sizeof(X)/sizeof(X[0])) @@ -1660,30 +1718,34 @@ op_dependencies[] = { { NELS(dep206), dep206, NELS(dep31), dep31, }, { NELS(dep207), dep207, NELS(dep194), dep194, }, { NELS(dep208), dep208, NELS(dep0), dep0, }, - { NELS(dep209), dep209, NELS(dep0), dep0, }, - { NELS(dep211), dep211, NELS(dep210), dep210, }, - { NELS(dep212), dep212, NELS(dep210), dep210, }, - { NELS(dep213), dep213, NELS(dep0), dep0, }, - { NELS(dep211), dep211, NELS(dep214), dep214, }, - { NELS(dep216), dep216, NELS(dep215), dep215, }, + { NELS(dep210), dep210, NELS(dep209), dep209, }, + { NELS(dep211), dep211, NELS(dep0), dep0, }, + { NELS(dep213), dep213, NELS(dep212), dep212, }, + { NELS(dep214), dep214, NELS(dep212), dep212, }, + { NELS(dep215), dep215, NELS(dep0), dep0, }, + { NELS(dep213), dep213, NELS(dep216), dep216, }, { NELS(dep218), dep218, NELS(dep217), dep217, }, - { NELS(dep220), dep220, NELS(dep219), dep219, }, - { NELS(dep221), dep221, NELS(dep219), dep219, }, - { NELS(dep222), dep222, NELS(dep0), dep0, }, - { NELS(dep223), dep223, NELS(dep219), dep219, }, - { NELS(dep225), dep225, NELS(dep224), dep224, }, - { NELS(dep226), dep226, NELS(dep62), dep62, }, - { NELS(dep227), dep227, NELS(dep62), dep62, }, + { NELS(dep219), dep219, NELS(dep217), dep217, }, + { NELS(dep221), dep221, NELS(dep220), dep220, }, + { NELS(dep223), dep223, NELS(dep222), dep222, }, + { NELS(dep224), dep224, NELS(dep222), dep222, }, + { NELS(dep225), dep225, NELS(dep222), dep222, }, + { NELS(dep226), dep226, NELS(dep0), dep0, }, + { NELS(dep227), dep227, NELS(dep222), dep222, }, { NELS(dep229), dep229, NELS(dep228), dep228, }, - { NELS(dep230), dep230, NELS(dep228), dep228, }, - { NELS(dep229), dep229, NELS(dep231), dep231, }, - { NELS(dep232), dep232, NELS(dep31), dep31, }, - { NELS(dep233), dep233, NELS(dep31), dep31, }, - { NELS(dep234), dep234, NELS(dep0), dep0, }, - { NELS(dep235), dep235, NELS(dep0), dep0, }, - { NELS(dep236), dep236, NELS(dep62), dep62, }, + { NELS(dep230), dep230, NELS(dep62), dep62, }, + { NELS(dep231), dep231, NELS(dep62), dep62, }, + { NELS(dep233), dep233, NELS(dep232), dep232, }, + { NELS(dep234), dep234, NELS(dep232), dep232, }, + { NELS(dep233), dep233, NELS(dep235), dep235, }, + { NELS(dep236), dep236, NELS(dep217), dep217, }, + { NELS(dep237), dep237, NELS(dep31), dep31, }, + { NELS(dep238), dep238, NELS(dep31), dep31, }, + { NELS(dep239), dep239, NELS(dep0), dep0, }, + { NELS(dep240), dep240, NELS(dep0), dep0, }, + { NELS(dep241), dep241, NELS(dep62), dep62, }, { 0, NULL, 0, NULL, }, - { NELS(dep238), dep238, NELS(dep237), dep237, }, + { NELS(dep243), dep243, NELS(dep242), dep242, }, }; static const struct ia64_completer_table @@ -1701,36 +1763,36 @@ completer_table[] = { { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 449, -1, 0, 1, 6 }, - { 0x0, 0x0, 0, 512, -1, 0, 1, 17 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 147 }, - { 0x0, 0x0, 0, 611, -1, 0, 1, 17 }, - { 0x0, 0x0, 0, 1815, -1, 0, 1, 10 }, + { 0x0, 0x0, 0, 455, -1, 0, 1, 6 }, + { 0x0, 0x0, 0, 518, -1, 0, 1, 17 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 151 }, + { 0x0, 0x0, 0, 617, -1, 0, 1, 17 }, + { 0x0, 0x0, 0, 1836, -1, 0, 1, 10 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 9 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 13 }, { 0x1, 0x1, 0, -1, -1, 13, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, 1991, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2014, -1, 0, 1, 29 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 122 }, + { 0x0, 0x0, 0, 958, -1, 0, 1, 122 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 44 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 40 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 78 }, - { 0x0, 0x0, 0, 1855, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 1878, -1, 0, 1, 29 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, 2034, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, 1859, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2057, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 1882, -1, 0, 1, 29 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, - { 0x0, 0x0, 0, 1861, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, 2043, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, 2046, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 1884, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2066, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2069, -1, 0, 1, 29 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, @@ -1739,64 +1801,66 @@ completer_table[] = { { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, 2068, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2091, -1, 0, 1, 29 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, 2071, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 2094, -1, 0, 1, 29 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 24 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 35 }, - { 0x0, 0x0, 0, 2079, -1, 0, 1, 29 }, - { 0x0, 0x0, 0, 1170, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, 2102, -1, 0, 1, 29 }, + { 0x0, 0x0, 0, 1181, -1, 0, 1, 33 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 40 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 151 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 77 }, - { 0x0, 0x0, 0, 1203, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1212, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1221, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1230, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1239, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1248, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1257, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1266, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1275, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1285, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1295, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1305, -1, 0, 1, 124 }, - { 0x0, 0x0, 0, 1314, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1320, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1326, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1332, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1338, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1344, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1350, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1356, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1362, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1368, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1374, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1380, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1386, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1392, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1398, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1404, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1410, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1416, -1, 0, 1, 137 }, - { 0x0, 0x0, 0, 1420, -1, 0, 1, 142 }, - { 0x0, 0x0, 0, 1424, -1, 0, 1, 144 }, - { 0x0, 0x0, 0, 1428, -1, 0, 1, 144 }, + { 0x0, 0x0, 0, 1216, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1225, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1234, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1236, -1, 0, 1, 125 }, + { 0x0, 0x0, 0, 1245, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1254, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1263, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1272, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1281, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1290, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1300, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1310, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1320, -1, 0, 1, 124 }, + { 0x0, 0x0, 0, 1329, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1335, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1341, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1347, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1353, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1359, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1365, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1371, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1377, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1383, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1389, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1395, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1401, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1407, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1413, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1419, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1425, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1431, -1, 0, 1, 140 }, + { 0x0, 0x0, 0, 1435, -1, 0, 1, 146 }, + { 0x0, 0x0, 0, 1439, -1, 0, 1, 148 }, + { 0x0, 0x0, 0, 1443, -1, 0, 1, 148 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 79 }, - { 0x0, 0x0, 0, 250, -1, 0, 1, 40 }, + { 0x0, 0x0, 0, 253, -1, 0, 1, 40 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 33 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 67 }, - { 0x1, 0x1, 0, 975, -1, 20, 1, 67 }, + { 0x1, 0x1, 0, 984, -1, 20, 1, 67 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 68 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 69 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 70 }, @@ -1823,25 +1887,25 @@ completer_table[] = { { 0x0, 0x0, 0, -1, -1, 0, 1, 111 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 112 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 113 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 148 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 148 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 148 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 152 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 152 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 71 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, -1, -1, 0, 1, 147 }, + { 0x0, 0x0, 0, -1, -1, 0, 1, 151 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 2371, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 2372, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2394, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2395, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 1827, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 1828, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 1848, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 1849, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 2386, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2409, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, @@ -1849,13 +1913,13 @@ completer_table[] = { { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 2387, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 2388, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 2389, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 2390, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2410, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2411, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2412, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2413, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 2373, -1, 0, 1, 0 }, - { 0x0, 0x0, 0, 2374, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2396, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2397, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 11 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 84 }, @@ -1865,25 +1929,26 @@ completer_table[] = { { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x1, 0x1, 0, -1, -1, 13, 1, 0 }, - { 0x0, 0x0, 0, 2392, -1, 0, 1, 0 }, + { 0x0, 0x0, 0, 2415, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 84 }, - { 0x0, 0x0, 0, 1692, -1, 0, 1, 130 }, - { 0x0, 0x0, 0, 1694, -1, 0, 1, 135 }, - { 0x0, 0x0, 0, 1696, -1, 0, 1, 130 }, - { 0x0, 0x0, 0, 1698, -1, 0, 1, 135 }, - { 0x0, 0x0, 0, 1700, -1, 0, 1, 130 }, - { 0x0, 0x0, 0, 1702, -1, 0, 1, 135 }, - { 0x0, 0x0, 0, 1705, -1, 0, 1, 130 }, - { 0x0, 0x0, 0, 1708, -1, 0, 1, 135 }, - { 0x0, 0x0, 0, 1711, -1, 0, 1, 130 }, - { 0x0, 0x0, 0, 1712, -1, 0, 1, 130 }, - { 0x0, 0x0, 0, 1713, -1, 0, 1, 130 }, - { 0x0, 0x0, 0, 1714, -1, 0, 1, 130 }, - { 0x0, 0x0, 0, 1715, -1, 0, 1, 130 }, - { 0x0, 0x0, 0, 1716, -1, 0, 1, 130 }, - { 0x0, 0x0, 0, 1717, -1, 0, 1, 130 }, - { 0x0, 0x0, 0, 1718, -1, 0, 1, 130 }, + { 0x0, 0x0, 0, 1711, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1713, -1, 0, 1, 138 }, + { 0x0, 0x0, 0, 1715, -1, 0, 1, 132 }, + { 0x0, 0x0, 0, 1717, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1719, -1, 0, 1, 138 }, + { 0x0, 0x0, 0, 1721, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1723, -1, 0, 1, 138 }, + { 0x0, 0x0, 0, 1726, -1, 0, 1, 131 }, + { 0x0, 0x0, 0, 1729, -1, 0, 1, 138 }, + { 0x0, 0x0, 0, 1732, -1, 0, 1, 145 }, + { 0x0, 0x0, 0, 1733, -1, 0, 1, 145 }, + { 0x0, 0x0, 0, 1734, -1, 0, 1, 145 }, + { 0x0, 0x0, 0, 1735, -1, 0, 1, 145 }, + { 0x0, 0x0, 0, 1736, -1, 0, 1, 145 }, + { 0x0, 0x0, 0, 1737, -1, 0, 1, 145 }, + { 0x0, 0x0, 0, 1738, -1, 0, 1, 145 }, + { 0x0, 0x0, 0, 1739, -1, 0, 1, 145 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, @@ -1895,116 +1960,97 @@ completer_table[] = { { 0x0, 0x0, 0, -1, -1, 0, 1, 118 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 120 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 119 }, - { 0x0, 0x0, 0, 1429, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 1430, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 1431, -1, 0, 1, 133 }, - { 0x0, 0x0, 0, 1432, -1, 0, 1, 133 }, + { 0x0, 0x0, 0, 1444, -1, 0, 1, 136 }, + { 0x0, 0x0, 0, 1445, -1, 0, 1, 136 }, + { 0x0, 0x0, 0, 1446, -1, 0, 1, 136 }, + { 0x0, 0x0, 0, 1447, -1, 0, 1, 136 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, { 0x0, 0x0, 0, -1, -1, 0, 1, 0 }, - { 0x0, 0x0, 1, 217, -1, 0, 1, 12 }, + { 0x0, 0x0, 1, 220, -1, 0, 1, 12 }, { 0x1, 0x1, 2, -1, -1, 27, 1, 12 }, - { 0x0, 0x0, 3, -1, 1112, 0, 0, -1 }, - { 0x0, 0x0, 3, -1, 1113, 0, 0, -1 }, - { 0x1, 0x1, 3, 2262, 1196, 33, 1, 126 }, - { 0x1, 0x1, 3, 2263, 1205, 33, 1, 126 }, - { 0x1, 0x1, 3, 2264, 1214, 33, 1, 126 }, - { 0x1, 0x1, 3, 2265, 1223, 33, 1, 126 }, - { 0x1, 0x1, 3, 2266, 1232, 33, 1, 126 }, - { 0x1, 0x1, 3, 2267, 1241, 33, 1, 126 }, - { 0x1, 0x1, 3, 2268, 1250, 33, 1, 126 }, - { 0x1, 0x1, 3, 2269, 1259, 33, 1, 126 }, - { 0x1, 0x1, 3, 2270, 1268, 33, 1, 126 }, - { 0x1, 0x1, 3, 2271, 1277, 33, 1, 126 }, - { 0x1, 0x1, 3, 2272, 1287, 33, 1, 126 }, - { 0x1, 0x1, 3, 2273, 1297, 33, 1, 126 }, - { 0x1, 0x1, 3, 2274, 1310, 33, 1, 139 }, - { 0x1, 0x1, 3, 2275, 1316, 33, 1, 139 }, - { 0x1, 0x1, 3, 2276, 1322, 33, 1, 139 }, - { 0x1, 0x1, 3, 2277, 1328, 33, 1, 139 }, - { 0x1, 0x1, 3, 2278, 1334, 33, 1, 139 }, - { 0x1, 0x1, 3, 2279, 1340, 33, 1, 139 }, - { 0x1, 0x1, 3, 2280, 1346, 33, 1, 139 }, - { 0x1, 0x1, 3, 2281, 1352, 33, 1, 139 }, - { 0x1, 0x1, 3, 2282, 1358, 33, 1, 139 }, - { 0x1, 0x1, 3, 2283, 1364, 33, 1, 139 }, - { 0x1, 0x1, 3, 2284, 1370, 33, 1, 139 }, - { 0x1, 0x1, 3, 2285, 1376, 33, 1, 139 }, - { 0x1, 0x1, 3, 2286, 1382, 33, 1, 139 }, - { 0x1, 0x1, 3, 2287, 1388, 33, 1, 139 }, - { 0x1, 0x1, 3, 2288, 1394, 33, 1, 139 }, - { 0x1, 0x1, 3, 2289, 1400, 33, 1, 139 }, - { 0x1, 0x1, 3, 2290, 1406, 33, 1, 139 }, - { 0x1, 0x1, 3, 2291, 1412, 33, 1, 139 }, + { 0x0, 0x0, 3, -1, 1123, 0, 0, -1 }, + { 0x0, 0x0, 3, -1, 1124, 0, 0, -1 }, + { 0x1, 0x1, 3, 2285, 1209, 33, 1, 127 }, + { 0x1, 0x1, 3, 2286, 1218, 33, 1, 127 }, + { 0x1, 0x1, 3, 2287, 1227, 33, 1, 127 }, + { 0x1, 0x1, 3, 2288, 1238, 33, 1, 127 }, + { 0x1, 0x1, 3, 2289, 1247, 33, 1, 127 }, + { 0x1, 0x1, 3, 2290, 1256, 33, 1, 127 }, + { 0x1, 0x1, 3, 2291, 1265, 33, 1, 127 }, + { 0x1, 0x1, 3, 2292, 1274, 33, 1, 127 }, + { 0x1, 0x1, 3, 2293, 1283, 33, 1, 127 }, + { 0x1, 0x1, 3, 2294, 1292, 33, 1, 127 }, + { 0x1, 0x1, 3, 2295, 1302, 33, 1, 127 }, + { 0x1, 0x1, 3, 2296, 1312, 33, 1, 127 }, + { 0x1, 0x1, 3, 2297, 1325, 33, 1, 142 }, + { 0x1, 0x1, 3, 2298, 1331, 33, 1, 142 }, + { 0x1, 0x1, 3, 2299, 1337, 33, 1, 142 }, + { 0x1, 0x1, 3, 2300, 1343, 33, 1, 142 }, + { 0x1, 0x1, 3, 2301, 1349, 33, 1, 142 }, + { 0x1, 0x1, 3, 2302, 1355, 33, 1, 142 }, + { 0x1, 0x1, 3, 2303, 1361, 33, 1, 142 }, + { 0x1, 0x1, 3, 2304, 1367, 33, 1, 142 }, + { 0x1, 0x1, 3, 2305, 1373, 33, 1, 142 }, + { 0x1, 0x1, 3, 2306, 1379, 33, 1, 142 }, + { 0x1, 0x1, 3, 2307, 1385, 33, 1, 142 }, + { 0x1, 0x1, 3, 2308, 1391, 33, 1, 142 }, + { 0x1, 0x1, 3, 2309, 1397, 33, 1, 142 }, + { 0x1, 0x1, 3, 2310, 1403, 33, 1, 142 }, + { 0x1, 0x1, 3, 2311, 1409, 33, 1, 142 }, + { 0x1, 0x1, 3, 2312, 1415, 33, 1, 142 }, + { 0x1, 0x1, 3, 2313, 1421, 33, 1, 142 }, + { 0x1, 0x1, 3, 2314, 1427, 33, 1, 142 }, { 0x1, 0x1, 3, -1, -1, 27, 1, 40 }, - { 0x0, 0x0, 4, 1829, 1183, 0, 1, 132 }, - { 0x0, 0x0, 4, 1830, 1185, 0, 1, 132 }, - { 0x0, 0x0, 4, 1831, 1187, 0, 1, 132 }, - { 0x0, 0x0, 4, 1832, 1189, 0, 1, 132 }, - { 0x0, 0x0, 4, 1833, 1191, 0, 1, 133 }, - { 0x0, 0x0, 4, 1834, 1193, 0, 1, 133 }, - { 0x1, 0x1, 4, -1, 1200, 33, 1, 129 }, - { 0x5, 0x5, 4, 407, 1199, 32, 1, 124 }, - { 0x1, 0x1, 4, -1, 1209, 33, 1, 129 }, - { 0x5, 0x5, 4, 408, 1208, 32, 1, 124 }, - { 0x1, 0x1, 4, -1, 1218, 33, 1, 129 }, - { 0x5, 0x5, 4, 409, 1217, 32, 1, 124 }, - { 0x1, 0x1, 4, -1, 1227, 33, 1, 129 }, - { 0x5, 0x5, 4, 410, 1226, 32, 1, 124 }, - { 0x1, 0x1, 4, -1, 1236, 33, 1, 129 }, - { 0x5, 0x5, 4, 411, 1235, 32, 1, 124 }, - { 0x1, 0x1, 4, -1, 1245, 33, 1, 129 }, - { 0x5, 0x5, 4, 412, 1244, 32, 1, 124 }, - { 0x1, 0x1, 4, -1, 1254, 33, 1, 129 }, - { 0x5, 0x5, 4, 413, 1253, 32, 1, 124 }, - { 0x1, 0x1, 4, -1, 1263, 33, 1, 129 }, - { 0x5, 0x5, 4, 414, 1262, 32, 1, 124 }, - { 0x1, 0x1, 4, -1, 1272, 33, 1, 129 }, - { 0x5, 0x5, 4, 415, 1271, 32, 1, 124 }, - { 0x1, 0x1, 4, -1, 1282, 33, 1, 129 }, - { 0x5, 0x5, 4, 881, 1280, 32, 1, 124 }, - { 0x1, 0x1, 4, -1, 1292, 33, 1, 129 }, - { 0x5, 0x5, 4, 882, 1290, 32, 1, 124 }, - { 0x1, 0x1, 4, -1, 1302, 33, 1, 129 }, - { 0x5, 0x5, 4, 883, 1300, 32, 1, 124 }, - { 0x1, 0x21, 10, 1727, -1, 33, 1, 3 }, - { 0x200001, 0x200001, 10, 1728, -1, 12, 1, 3 }, - { 0x0, 0x0, 10, 1729, -1, 0, 1, 3 }, - { 0x1, 0x1, 10, 1730, -1, 12, 1, 3 }, - { 0x1, 0x1, 10, 1731, -1, 33, 1, 3 }, - { 0x200001, 0x200001, 10, 1732, -1, 12, 1, 3 }, - { 0x0, 0x0, 10, 346, -1, 0, 1, 3 }, - { 0x1, 0x1, 10, 1758, -1, 12, 1, 3 }, - { 0x1, 0x1, 10, 350, -1, 33, 1, 3 }, - { 0x200001, 0x200001, 10, 1760, -1, 12, 1, 3 }, - { 0x1, 0x21, 10, 1737, -1, 33, 1, 3 }, - { 0x200001, 0x200001, 10, 1738, -1, 12, 1, 3 }, - { 0x0, 0x0, 10, -1, 1767, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1768, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1769, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1770, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1771, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1772, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1773, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1774, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1775, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1776, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1777, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1778, 0, 0, -1 }, - { 0x1, 0x21, 10, 1739, -1, 33, 1, 3 }, - { 0x200001, 0x200001, 10, 1740, -1, 12, 1, 3 }, - { 0x0, 0x0, 10, 1741, -1, 0, 1, 3 }, - { 0x1, 0x1, 10, 1742, -1, 12, 1, 3 }, - { 0x1, 0x1, 10, 1743, -1, 33, 1, 3 }, - { 0x200001, 0x200001, 10, 1744, -1, 12, 1, 3 }, - { 0x0, 0x0, 10, 370, -1, 0, 1, 3 }, - { 0x1, 0x1, 10, 1782, -1, 12, 1, 3 }, - { 0x1, 0x1, 10, 374, -1, 33, 1, 3 }, - { 0x200001, 0x200001, 10, 1784, -1, 12, 1, 3 }, - { 0x1, 0x21, 10, 1749, -1, 33, 1, 3 }, - { 0x200001, 0x200001, 10, 1750, -1, 12, 1, 3 }, + { 0x0, 0x0, 4, 1850, 1194, 0, 1, 135 }, + { 0x0, 0x0, 4, 1851, 1196, 0, 1, 134 }, + { 0x0, 0x0, 4, 1852, 1198, 0, 1, 134 }, + { 0x0, 0x0, 4, 1853, 1200, 0, 1, 134 }, + { 0x0, 0x0, 4, 1854, 1202, 0, 1, 134 }, + { 0x0, 0x0, 4, 1855, 1204, 0, 1, 136 }, + { 0x0, 0x0, 4, 1856, 1206, 0, 1, 136 }, + { 0x1, 0x1, 4, -1, 1213, 33, 1, 130 }, + { 0x5, 0x5, 4, 413, 1212, 32, 1, 124 }, + { 0x1, 0x1, 4, -1, 1222, 33, 1, 130 }, + { 0x5, 0x5, 4, 414, 1221, 32, 1, 124 }, + { 0x1, 0x1, 4, -1, 1231, 33, 1, 130 }, + { 0x5, 0x5, 4, 415, 1230, 32, 1, 124 }, + { 0x1, 0x1, 4, -1, 1235, 32, 1, 125 }, + { 0x1, 0x1, 4, -1, 1242, 33, 1, 130 }, + { 0x5, 0x5, 4, 416, 1241, 32, 1, 124 }, + { 0x1, 0x1, 4, -1, 1251, 33, 1, 130 }, + { 0x5, 0x5, 4, 417, 1250, 32, 1, 124 }, + { 0x1, 0x1, 4, -1, 1260, 33, 1, 130 }, + { 0x5, 0x5, 4, 418, 1259, 32, 1, 124 }, + { 0x1, 0x1, 4, -1, 1269, 33, 1, 130 }, + { 0x5, 0x5, 4, 419, 1268, 32, 1, 124 }, + { 0x1, 0x1, 4, -1, 1278, 33, 1, 130 }, + { 0x5, 0x5, 4, 420, 1277, 32, 1, 124 }, + { 0x1, 0x1, 4, -1, 1287, 33, 1, 130 }, + { 0x5, 0x5, 4, 421, 1286, 32, 1, 124 }, + { 0x1, 0x1, 4, -1, 1297, 33, 1, 130 }, + { 0x5, 0x5, 4, 888, 1295, 32, 1, 124 }, + { 0x1, 0x1, 4, -1, 1307, 33, 1, 130 }, + { 0x5, 0x5, 4, 889, 1305, 32, 1, 124 }, + { 0x1, 0x1, 4, -1, 1317, 33, 1, 130 }, + { 0x5, 0x5, 4, 890, 1315, 32, 1, 124 }, + { 0x1, 0x21, 10, 1748, -1, 33, 1, 3 }, + { 0x200001, 0x200001, 10, 1749, -1, 12, 1, 3 }, + { 0x0, 0x0, 10, 1750, -1, 0, 1, 3 }, + { 0x1, 0x1, 10, 1751, -1, 12, 1, 3 }, + { 0x1, 0x1, 10, 1752, -1, 33, 1, 3 }, + { 0x200001, 0x200001, 10, 1753, -1, 12, 1, 3 }, + { 0x0, 0x0, 10, 351, -1, 0, 1, 3 }, + { 0x1, 0x1, 10, 1779, -1, 12, 1, 3 }, + { 0x1, 0x1, 10, 355, -1, 33, 1, 3 }, + { 0x200001, 0x200001, 10, 1781, -1, 12, 1, 3 }, + { 0x1, 0x21, 10, 1758, -1, 33, 1, 3 }, + { 0x200001, 0x200001, 10, 1759, -1, 12, 1, 3 }, + { 0x0, 0x0, 10, -1, 1788, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1789, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1790, 0, 0, -1 }, { 0x0, 0x0, 10, -1, 1791, 0, 0, -1 }, { 0x0, 0x0, 10, -1, 1792, 0, 0, -1 }, { 0x0, 0x0, 10, -1, 1793, 0, 0, -1 }, @@ -2014,93 +2060,109 @@ completer_table[] = { { 0x0, 0x0, 10, -1, 1797, 0, 0, -1 }, { 0x0, 0x0, 10, -1, 1798, 0, 0, -1 }, { 0x0, 0x0, 10, -1, 1799, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1800, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1801, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1802, 0, 0, -1 }, - { 0x1, 0x1, 10, 1751, -1, 36, 1, 3 }, - { 0x1000001, 0x1000001, 10, 1752, -1, 12, 1, 3 }, - { 0x0, 0x0, 10, -1, 1803, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1805, 0, 0, -1 }, - { 0x1, 0x1, 10, 1753, -1, 36, 1, 3 }, - { 0x1000001, 0x1000001, 10, 1754, -1, 12, 1, 3 }, - { 0x0, 0x0, 10, -1, 1807, 0, 0, -1 }, - { 0x0, 0x0, 10, -1, 1809, 0, 0, -1 }, + { 0x1, 0x21, 10, 1760, -1, 33, 1, 3 }, + { 0x200001, 0x200001, 10, 1761, -1, 12, 1, 3 }, + { 0x0, 0x0, 10, 1762, -1, 0, 1, 3 }, + { 0x1, 0x1, 10, 1763, -1, 12, 1, 3 }, + { 0x1, 0x1, 10, 1764, -1, 33, 1, 3 }, + { 0x200001, 0x200001, 10, 1765, -1, 12, 1, 3 }, + { 0x0, 0x0, 10, 375, -1, 0, 1, 3 }, + { 0x1, 0x1, 10, 1803, -1, 12, 1, 3 }, + { 0x1, 0x1, 10, 379, -1, 33, 1, 3 }, + { 0x200001, 0x200001, 10, 1805, -1, 12, 1, 3 }, + { 0x1, 0x21, 10, 1770, -1, 33, 1, 3 }, + { 0x200001, 0x200001, 10, 1771, -1, 12, 1, 3 }, + { 0x0, 0x0, 10, -1, 1812, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1813, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1814, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1815, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1816, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1817, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1818, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1819, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1820, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1821, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1822, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1823, 0, 0, -1 }, + { 0x1, 0x1, 10, 1772, -1, 36, 1, 3 }, + { 0x1000001, 0x1000001, 10, 1773, -1, 12, 1, 3 }, + { 0x0, 0x0, 10, -1, 1824, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1826, 0, 0, -1 }, + { 0x1, 0x1, 10, 1774, -1, 36, 1, 3 }, + { 0x1000001, 0x1000001, 10, 1775, -1, 12, 1, 3 }, + { 0x0, 0x0, 10, -1, 1828, 0, 0, -1 }, + { 0x0, 0x0, 10, -1, 1830, 0, 0, -1 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, - { 0x0, 0x0, 11, 1755, -1, 0, 1, 3 }, - { 0x1, 0x1, 11, 1756, -1, 12, 1, 3 }, + { 0x0, 0x0, 11, 1776, -1, 0, 1, 3 }, + { 0x1, 0x1, 11, 1777, -1, 12, 1, 3 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, - { 0x1, 0x1, 11, 1733, -1, 12, 1, 3 }, + { 0x1, 0x1, 11, 1754, -1, 12, 1, 3 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, - { 0x0, 0x0, 11, 288, -1, 0, 1, 3 }, + { 0x0, 0x0, 11, 293, -1, 0, 1, 3 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, - { 0x200001, 0x200001, 11, 1735, -1, 12, 1, 3 }, + { 0x200001, 0x200001, 11, 1756, -1, 12, 1, 3 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, - { 0x1, 0x1, 11, 290, -1, 33, 1, 3 }, - { 0x0, 0x0, 11, 1761, -1, 0, 1, 3 }, - { 0x1, 0x1, 11, 1762, -1, 12, 1, 3 }, - { 0x1, 0x1, 11, 1763, -1, 33, 1, 3 }, - { 0x200001, 0x200001, 11, 1764, -1, 12, 1, 3 }, + { 0x1, 0x1, 11, 295, -1, 33, 1, 3 }, + { 0x0, 0x0, 11, 1782, -1, 0, 1, 3 }, + { 0x1, 0x1, 11, 1783, -1, 12, 1, 3 }, + { 0x1, 0x1, 11, 1784, -1, 33, 1, 3 }, + { 0x200001, 0x200001, 11, 1785, -1, 12, 1, 3 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, - { 0x0, 0x0, 11, 1765, -1, 0, 1, 3 }, - { 0x1, 0x1, 11, 1766, -1, 12, 1, 3 }, + { 0x0, 0x0, 11, 1786, -1, 0, 1, 3 }, + { 0x1, 0x1, 11, 1787, -1, 12, 1, 3 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, - { 0x0, 0x0, 11, 1779, -1, 0, 1, 3 }, - { 0x1, 0x1, 11, 1780, -1, 12, 1, 3 }, + { 0x0, 0x0, 11, 1800, -1, 0, 1, 3 }, + { 0x1, 0x1, 11, 1801, -1, 12, 1, 3 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, - { 0x1, 0x1, 11, 1745, -1, 12, 1, 3 }, + { 0x1, 0x1, 11, 1766, -1, 12, 1, 3 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, - { 0x0, 0x0, 11, 312, -1, 0, 1, 3 }, + { 0x0, 0x0, 11, 317, -1, 0, 1, 3 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, - { 0x200001, 0x200001, 11, 1747, -1, 12, 1, 3 }, + { 0x200001, 0x200001, 11, 1768, -1, 12, 1, 3 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, - { 0x1, 0x1, 11, 314, -1, 33, 1, 3 }, - { 0x0, 0x0, 11, 1785, -1, 0, 1, 3 }, - { 0x1, 0x1, 11, 1786, -1, 12, 1, 3 }, - { 0x1, 0x1, 11, 1787, -1, 33, 1, 3 }, - { 0x200001, 0x200001, 11, 1788, -1, 12, 1, 3 }, + { 0x1, 0x1, 11, 319, -1, 33, 1, 3 }, + { 0x0, 0x0, 11, 1806, -1, 0, 1, 3 }, + { 0x1, 0x1, 11, 1807, -1, 12, 1, 3 }, + { 0x1, 0x1, 11, 1808, -1, 33, 1, 3 }, + { 0x200001, 0x200001, 11, 1809, -1, 12, 1, 3 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, { 0x2, 0x3, 11, -1, -1, 37, 1, 5 }, - { 0x0, 0x0, 11, 1789, -1, 0, 1, 3 }, - { 0x1, 0x1, 11, 1790, -1, 12, 1, 3 }, + { 0x0, 0x0, 11, 1810, -1, 0, 1, 3 }, + { 0x1, 0x1, 11, 1811, -1, 12, 1, 3 }, { 0x1, 0x1, 11, -1, -1, 36, 1, 5 }, { 0x1, 0x1, 11, -1, -1, 36, 1, 5 }, - { 0x1, 0x1, 11, 1804, -1, 36, 1, 3 }, - { 0x1000001, 0x1000001, 11, 1806, -1, 12, 1, 3 }, + { 0x1, 0x1, 11, 1825, -1, 36, 1, 3 }, + { 0x1000001, 0x1000001, 11, 1827, -1, 12, 1, 3 }, { 0x1, 0x1, 11, -1, -1, 36, 1, 5 }, { 0x1, 0x1, 11, -1, -1, 36, 1, 5 }, - { 0x1, 0x1, 11, 1808, -1, 36, 1, 3 }, - { 0x1000001, 0x1000001, 11, 1810, -1, 12, 1, 3 }, + { 0x1, 0x1, 11, 1829, -1, 36, 1, 3 }, + { 0x1000001, 0x1000001, 11, 1831, -1, 12, 1, 3 }, + { 0x0, 0x0, 12, -1, -1, 0, 1, 14 }, { 0x0, 0x0, 12, -1, -1, 0, 1, 14 }, { 0x0, 0x0, 12, -1, -1, 0, 1, 14 }, - { 0x1, 0x1, 13, 258, 1198, 34, 1, 124 }, - { 0x1, 0x1, 13, 260, 1207, 34, 1, 124 }, - { 0x1, 0x1, 13, 262, 1216, 34, 1, 124 }, - { 0x1, 0x1, 13, 264, 1225, 34, 1, 124 }, - { 0x1, 0x1, 13, 266, 1234, 34, 1, 124 }, - { 0x1, 0x1, 13, 268, 1243, 34, 1, 124 }, - { 0x1, 0x1, 13, 270, 1252, 34, 1, 124 }, - { 0x1, 0x1, 13, 272, 1261, 34, 1, 124 }, - { 0x1, 0x1, 13, 274, 1270, 34, 1, 124 }, - { 0x1, 0x1, 13, 276, 1279, 34, 1, 124 }, - { 0x1, 0x1, 13, 278, 1289, 34, 1, 124 }, - { 0x1, 0x1, 13, 280, 1299, 34, 1, 124 }, - { 0x0, 0x0, 19, -1, 650, 0, 0, -1 }, - { 0x0, 0x0, 19, -1, 651, 0, 0, -1 }, - { 0x0, 0x0, 19, -1, 652, 0, 0, -1 }, - { 0x0, 0x0, 19, -1, 653, 0, 0, -1 }, - { 0x0, 0x0, 19, -1, 654, 0, 0, -1 }, - { 0x0, 0x0, 19, -1, 655, 0, 0, -1 }, + { 0x1, 0x1, 13, 262, 1211, 34, 1, 124 }, + { 0x1, 0x1, 13, 264, 1220, 34, 1, 124 }, + { 0x1, 0x1, 13, 266, 1229, 34, 1, 124 }, + { 0x1, 0x1, 13, 269, 1240, 34, 1, 124 }, + { 0x1, 0x1, 13, 271, 1249, 34, 1, 124 }, + { 0x1, 0x1, 13, 273, 1258, 34, 1, 124 }, + { 0x1, 0x1, 13, 275, 1267, 34, 1, 124 }, + { 0x1, 0x1, 13, 277, 1276, 34, 1, 124 }, + { 0x1, 0x1, 13, 279, 1285, 34, 1, 124 }, + { 0x1, 0x1, 13, 281, 1294, 34, 1, 124 }, + { 0x1, 0x1, 13, 283, 1304, 34, 1, 124 }, + { 0x1, 0x1, 13, 285, 1314, 34, 1, 124 }, { 0x0, 0x0, 19, -1, 656, 0, 0, -1 }, { 0x0, 0x0, 19, -1, 657, 0, 0, -1 }, { 0x0, 0x0, 19, -1, 658, 0, 0, -1 }, @@ -2125,19 +2187,25 @@ completer_table[] = { { 0x0, 0x0, 19, -1, 677, 0, 0, -1 }, { 0x0, 0x0, 19, -1, 678, 0, 0, -1 }, { 0x0, 0x0, 19, -1, 679, 0, 0, -1 }, - { 0x0, 0x0, 20, -1, 2340, 0, 0, -1 }, - { 0x0, 0x0, 20, -1, 2341, 0, 0, -1 }, - { 0x0, 0x0, 20, -1, 2356, 0, 0, -1 }, - { 0x0, 0x0, 20, -1, 2357, 0, 0, -1 }, - { 0x0, 0x0, 20, -1, 2362, 0, 0, -1 }, + { 0x0, 0x0, 19, -1, 680, 0, 0, -1 }, + { 0x0, 0x0, 19, -1, 681, 0, 0, -1 }, + { 0x0, 0x0, 19, -1, 682, 0, 0, -1 }, + { 0x0, 0x0, 19, -1, 683, 0, 0, -1 }, + { 0x0, 0x0, 19, -1, 684, 0, 0, -1 }, + { 0x0, 0x0, 19, -1, 685, 0, 0, -1 }, { 0x0, 0x0, 20, -1, 2363, 0, 0, -1 }, - { 0x0, 0x0, 21, 686, 2352, 0, 0, -1 }, - { 0x0, 0x0, 21, 687, 2354, 0, 0, -1 }, - { 0x0, 0x0, 23, -1, 2350, 0, 0, -1 }, - { 0x0, 0x0, 23, -1, 2351, 0, 0, -1 }, + { 0x0, 0x0, 20, -1, 2364, 0, 0, -1 }, + { 0x0, 0x0, 20, -1, 2379, 0, 0, -1 }, + { 0x0, 0x0, 20, -1, 2380, 0, 0, -1 }, + { 0x0, 0x0, 20, -1, 2385, 0, 0, -1 }, + { 0x0, 0x0, 20, -1, 2386, 0, 0, -1 }, + { 0x0, 0x0, 21, 692, 2375, 0, 0, -1 }, + { 0x0, 0x0, 21, 693, 2377, 0, 0, -1 }, + { 0x0, 0x0, 23, -1, 2373, 0, 0, -1 }, + { 0x0, 0x0, 23, -1, 2374, 0, 0, -1 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 6 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 6 }, - { 0x1, 0x1, 24, 1045, -1, 35, 1, 6 }, + { 0x1, 0x1, 24, 1055, -1, 35, 1, 6 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 6 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 6 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 6 }, @@ -2200,7 +2268,7 @@ completer_table[] = { { 0x1, 0x1, 24, -1, -1, 35, 1, 15 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 17 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 17 }, - { 0x1, 0x1, 24, 1066, -1, 35, 1, 17 }, + { 0x1, 0x1, 24, 1076, -1, 35, 1, 17 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 17 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 17 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 17 }, @@ -2299,7 +2367,7 @@ completer_table[] = { { 0x1, 0x1, 24, -1, -1, 35, 1, 21 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 17 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 17 }, - { 0x1, 0x1, 24, 1099, -1, 35, 1, 17 }, + { 0x1, 0x1, 24, 1109, -1, 35, 1, 17 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 17 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 17 }, { 0x1, 0x1, 24, -1, -1, 35, 1, 17 }, @@ -2338,5100 +2406,5157 @@ completer_table[] = { { 0x1, 0x1, 24, -1, -1, 35, 1, 21 }, { 0x1, 0x1, 24, -1, -1, 33, 1, 76 }, { 0x1, 0x1, 24, -1, -1, 33, 1, 76 }, - { 0x1, 0x1, 24, 1114, 1201, 35, 1, 129 }, - { 0x1, 0x1, 24, 1115, 1210, 35, 1, 129 }, - { 0x1, 0x1, 24, 1116, 1219, 35, 1, 129 }, - { 0x1, 0x1, 24, 1117, 1228, 35, 1, 129 }, - { 0x1, 0x1, 24, 1118, 1237, 35, 1, 129 }, - { 0x1, 0x1, 24, 1119, 1246, 35, 1, 129 }, - { 0x1, 0x1, 24, 1120, 1255, 35, 1, 129 }, - { 0x1, 0x1, 24, 1121, 1264, 35, 1, 129 }, - { 0x1, 0x1, 24, 1122, 1273, 35, 1, 129 }, - { 0x1, 0x1, 24, 1123, 1283, 35, 1, 129 }, - { 0x1, 0x1, 24, 1124, 1293, 35, 1, 129 }, - { 0x1, 0x1, 24, 1125, 1303, 35, 1, 129 }, - { 0x1, 0x1, 24, 1126, 1312, 35, 1, 141 }, - { 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}, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 64 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 64 }, + { 0x0, 0x0, 263, -1, 1928, 0, 0, -1 }, + { 0x0, 0x0, 263, -1, 1930, 0, 0, -1 }, + { 0x0, 0x0, 263, -1, 1932, 0, 0, -1 }, + { 0x0, 0x0, 263, -1, 1934, 0, 0, -1 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 49 }, + { 0x0, 0x0, 263, -1, 1936, 0, 0, -1 }, + { 0x0, 0x0, 263, -1, 1938, 0, 0, -1 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, + { 0x0, 0x0, 263, -1, 1940, 0, 0, -1 }, + { 0x0, 0x0, 263, -1, 1942, 0, 0, -1 }, + { 0x0, 0x0, 263, -1, 1944, 0, 0, -1 }, + { 0x0, 0x0, 263, -1, 1946, 0, 0, -1 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 49 }, + { 0x0, 0x0, 263, -1, 1948, 0, 0, -1 }, + { 0x0, 0x0, 263, -1, 1950, 0, 0, -1 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 263, -1, -1, 12, 1, 59 }, + { 0x1, 0x1, 263, 334, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, 392, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, 338, -1, 12, 1, 2 }, + { 0x1, 0x1, 263, 396, -1, 12, 1, 2 }, + { 0x0, 0x0, 264, -1, 1935, 0, 0, -1 }, + { 0x9, 0x9, 264, -1, 2465, 33, 1, 49 }, + { 0x0, 0x0, 264, 1173, 1984, 0, 0, -1 }, + { 0x3, 0x3, 264, 1174, -1, 27, 1, 49 }, + { 0x0, 0x0, 268, 2392, -1, 0, 1, 0 }, + { 0x3, 0x3, 269, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 269, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 269, -1, -1, 27, 1, 0 }, + { 0x3, 0x3, 269, -1, -1, 27, 1, 0 }, + { 0x1, 0x1, 270, 2491, -1, 28, 1, 0 }, + { 0x1, 0x1, 270, 2492, -1, 28, 1, 0 }, + { 0x1, 0x1, 270, 2493, -1, 28, 1, 0 }, + { 0x1, 0x1, 270, 2494, -1, 28, 1, 0 }, + { 0x1, 0x1, 271, -1, -1, 27, 1, 93 }, + { 0x1, 0x1, 271, -1, -1, 27, 1, 93 }, + { 0x0, 0x0, 271, -1, 820, 0, 0, -1 }, + { 0x0, 0x0, 272, 2504, 2369, 0, 0, -1 }, + { 0x0, 0x0, 272, 2505, 2371, 0, 0, -1 }, + { 0x0, 0x0, 273, -1, 2370, 0, 0, -1 }, + { 0x0, 0x0, 273, -1, 2372, 0, 0, -1 }, + { 0x0, 0x0, 274, -1, -1, 0, 1, 40 }, + { 0x0, 0x0, 274, -1, -1, 0, 1, 40 }, + { 0x0, 0x0, 274, -1, -1, 0, 1, 40 }, + { 0x0, 0x0, 279, -1, -1, 0, 1, 33 }, + { 0x0, 0x0, 283, -1, 1958, 0, 1, 29 }, + { 0x0, 0x0, 284, -1, -1, 0, 1, 0 }, + { 0x0, 0x0, 284, -1, -1, 0, 1, 71 }, + { 0x0, 0x0, 284, 1744, 2482, 0, 1, 1 }, + { 0x0, 0x0, 284, -1, 393, 0, 0, -1 }, + { 0x0, 0x0, 284, 1746, 2484, 0, 1, 1 }, + { 0x0, 0x0, 284, -1, 397, 0, 0, -1 }, }; static const struct ia64_main_table main_table[] = { - { 5, 1, 1, 0x0000010000000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 0, }, - { 5, 1, 1, 0x0000010008000000ull, 0x000001eff8000000ull, { 23, 24, 25, 3, 0 }, 0x0, 1, }, - { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 23, 65, 26, 0, 0 }, 0x0, 2, }, - { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 23, 62, 25, 0, 0 }, 0x0, 3, }, - { 6, 1, 1, 0x0000012000000000ull, 0x000001e000000000ull, { 23, 65, 26, 0, 0 }, 0x0, 4, }, - { 7, 1, 1, 0x0000010040000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 5, }, - { 7, 1, 1, 0x0000010c00000000ull, 0x000001ee00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 6, }, - { 8, 1, 1, 0x0000010800000000ull, 0x000001ee00000000ull, { 23, 62, 25, 0, 0 }, 0x0, 7, }, - { 9, 3, 1, 0x0000002c00000000ull, 0x000001ee00000000ull, { 23, 2, 51, 52, 53 }, 0x221, 8, }, - { 10, 1, 1, 0x0000010060000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 9, }, - { 10, 1, 1, 0x0000010160000000ull, 0x000001eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 10, }, - { 11, 1, 1, 0x0000010068000000ull, 0x000001eff8000000ull, { 23, 24, 25, 0, 0 }, 0x0, 11, }, - { 11, 1, 1, 0x0000010168000000ull, 0x000001eff8000000ull, { 23, 54, 25, 0, 0 }, 0x0, 12, }, - { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011ffull, { 15, 0, 0, 0, 0 }, 0x40, 814, }, - { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x0, 680, }, - { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x40, 681, }, - { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x200, 1843, }, - { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 15, 0, 0, 0, 0 }, 0x240, 1844, }, - { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 14, 15, 0, 0, 0 }, 0x0, 437, }, - { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 14, 15, 0, 0, 0 }, 0x40, 438, }, - { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011ffull, { 80, 0, 0, 0, 0 }, 0x40, 835, }, - { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x0, 682, }, - { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x40, 683, }, - { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x210, 2479, }, - { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x250, 2480, }, - { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x30, 445, }, - { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x70, 446, }, - { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x230, 443, }, - { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 80, 0, 0, 0, 0 }, 0x270, 444, }, - { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 14, 80, 0, 0, 0 }, 0x0, 439, }, - { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 14, 80, 0, 0, 0 }, 0x40, 440, }, - { 15, 4, 0, 0x0000000000000000ull, 0x000001e1f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 393, }, - { 15, 5, 0, 0x0000000000000000ull, 0x000001e3f8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 806, }, - { 15, 2, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 64, 0, 0, 0, 0 }, 0x2, 949, }, - { 15, 3, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 64, 0, 0, 0, 0 }, 0x0, 1038, }, - { 15, 6, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 68, 0, 0, 0, 0 }, 0x0, 2483, }, - { 15, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 64, 0, 0, 0, 0 }, 0x0, 15, }, - { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011ffull, { 81, 0, 0, 0, 0 }, 0x40, 868, }, - { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x0, 684, }, - { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x40, 685, }, - { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 14, 81, 0, 0, 0 }, 0x0, 441, }, - { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 14, 81, 0, 0, 0 }, 0x40, 442, }, - { 17, 4, 0, 0x0000004080000000ull, 0x000001e9f8000018ull, { 15, 76, 0, 0, 0 }, 0x20, 2365, }, - { 17, 4, 0, 0x000000e000000000ull, 0x000001e800000018ull, { 80, 76, 0, 0, 0 }, 0x20, 2366, }, - { 18, 4, 0, 0x0000000060000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x2c, 216, }, - { 22, 2, 0, 0x0000000200000000ull, 0x000001ee00000000ull, { 24, 79, 0, 0, 0 }, 0x0, 1848, }, - { 22, 3, 0, 0x0000000800000000ull, 0x000001ee00000000ull, { 23, 80, 0, 0, 0 }, 0x0, 218, }, - { 22, 3, 0, 0x0000000c00000000ull, 0x000001ee00000000ull, { 17, 80, 0, 0, 0 }, 0x0, 219, }, - { 22, 3, 0, 0x0000002200000000ull, 0x000001ee00000000ull, { 24, 79, 0, 0, 0 }, 0x0, 1849, }, - { 22, 3, 0, 0x0000002600000000ull, 0x000001ee00000000ull, { 18, 79, 0, 0, 0 }, 0x0, 1850, }, - { 22, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 79, 0, 0, 0 }, 0x0, 1851, }, + { 5, 1, 1, 0x0000010000000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 0, }, + { 5, 1, 1, 0x0000010008000000ull, 0x000001eff8000000ull, { 24, 25, 26, 4, 0 }, 0x0, 1, }, + { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 66, 27, 0, 0 }, 0x0, 2, }, + { 5, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 63, 26, 0, 0 }, 0x0, 3, }, + { 6, 1, 1, 0x0000012000000000ull, 0x000001e000000000ull, { 24, 66, 27, 0, 0 }, 0x0, 4, }, + { 7, 1, 1, 0x0000010040000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 5, }, + { 7, 1, 1, 0x0000010c00000000ull, 0x000001ee00000000ull, { 24, 63, 26, 0, 0 }, 0x0, 6, }, + { 8, 1, 1, 0x0000010800000000ull, 0x000001ee00000000ull, { 24, 63, 26, 0, 0 }, 0x0, 7, }, + { 9, 3, 1, 0x0000002c00000000ull, 0x000001ee00000000ull, { 24, 3, 52, 53, 54 }, 0x221, 8, }, + { 10, 1, 1, 0x0000010060000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 9, }, + { 10, 1, 1, 0x0000010160000000ull, 0x000001eff8000000ull, { 24, 55, 26, 0, 0 }, 0x0, 10, }, + { 11, 1, 1, 0x0000010068000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 11, }, + { 11, 1, 1, 0x0000010168000000ull, 0x000001eff8000000ull, { 24, 55, 26, 0, 0 }, 0x0, 12, }, + { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011ffull, { 16, 0, 0, 0, 0 }, 0x40, 821, }, + { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x0, 686, }, + { 14, 4, 0, 0x0000000100000000ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x40, 687, }, + { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x200, 1866, }, + { 14, 4, 0, 0x0000000108000100ull, 0x000001eff80011c0ull, { 16, 0, 0, 0, 0 }, 0x240, 1867, }, + { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 15, 16, 0, 0, 0 }, 0x0, 443, }, + { 14, 4, 1, 0x0000002100000000ull, 0x000001ef00001000ull, { 15, 16, 0, 0, 0 }, 0x40, 444, }, + { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011ffull, { 81, 0, 0, 0, 0 }, 0x40, 842, }, + { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x0, 688, }, + { 14, 4, 0, 0x0000008000000000ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x40, 689, }, + { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x210, 2502, }, + { 14, 4, 0, 0x0000008000000080ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x250, 2503, }, + { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x30, 451, }, + { 14, 4, 0, 0x0000008000000140ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x70, 452, }, + { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x230, 449, }, + { 14, 4, 0, 0x0000008000000180ull, 0x000001ee000011c0ull, { 81, 0, 0, 0, 0 }, 0x270, 450, }, + { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 15, 81, 0, 0, 0 }, 0x0, 445, }, + { 14, 4, 1, 0x000000a000000000ull, 0x000001ee00001000ull, { 15, 81, 0, 0, 0 }, 0x40, 446, }, + { 15, 4, 0, 0x0000000000000000ull, 0x000001e1f8000000ull, { 65, 0, 0, 0, 0 }, 0x0, 398, }, + { 15, 5, 0, 0x0000000000000000ull, 0x000001e3f8000000ull, { 65, 0, 0, 0, 0 }, 0x0, 812, }, + { 15, 2, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 65, 0, 0, 0, 0 }, 0x2, 956, }, + { 15, 3, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 65, 0, 0, 0, 0 }, 0x0, 1047, }, + { 15, 6, 0, 0x0000000000000000ull, 0x000001eff8000000ull, { 69, 0, 0, 0, 0 }, 0x0, 2506, }, + { 15, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 65, 0, 0, 0, 0 }, 0x0, 15, }, + { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011ffull, { 82, 0, 0, 0, 0 }, 0x40, 875, }, + { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x0, 690, }, + { 16, 6, 0, 0x0000018000000000ull, 0x000001ee000011c0ull, { 82, 0, 0, 0, 0 }, 0x40, 691, }, + { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 15, 82, 0, 0, 0 }, 0x0, 447, }, + { 16, 6, 1, 0x000001a000000000ull, 0x000001ee00001000ull, { 15, 82, 0, 0, 0 }, 0x40, 448, }, + { 17, 4, 0, 0x0000004080000000ull, 0x000001e9f8000018ull, { 16, 77, 0, 0, 0 }, 0x20, 2388, }, + { 17, 4, 0, 0x000000e000000000ull, 0x000001e800000018ull, { 81, 77, 0, 0, 0 }, 0x20, 2389, }, + { 18, 4, 0, 0x0000000060000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x2c, 219, }, + { 22, 2, 0, 0x0000000200000000ull, 0x000001ee00000000ull, { 25, 80, 0, 0, 0 }, 0x0, 1871, }, + { 22, 3, 0, 0x0000000800000000ull, 0x000001ee00000000ull, { 24, 81, 0, 0, 0 }, 0x0, 221, }, + { 22, 3, 0, 0x0000000c00000000ull, 0x000001ee00000000ull, { 18, 81, 0, 0, 0 }, 0x0, 222, }, + { 22, 3, 0, 0x0000002200000000ull, 0x000001ee00000000ull, { 25, 80, 0, 0, 0 }, 0x0, 1872, }, + { 22, 3, 0, 0x0000002600000000ull, 0x000001ee00000000ull, { 19, 80, 0, 0, 0 }, 0x0, 1873, }, + { 22, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 25, 80, 0, 0, 0 }, 0x0, 1874, }, { 25, 4, 0, 0x0000000020000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x224, 17, }, - { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 21, 22, 24, 25, 0 }, 0x0, 1014, }, - { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 21, 25, 24, 0 }, 0x0, 990, }, - { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 21, 22, 25, 24, 0 }, 0x0, 918, }, - { 26, 1, 2, 0x0000018000000000ull, 0x000001fe00001000ull, { 22, 21, 24, 25, 0 }, 0x0, 897, }, - { 26, 1, 2, 0x0000018200000000ull, 0x000001fe00001000ull, { 21, 22, 24, 25, 0 }, 0x40, 1146, }, - { 26, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 21, 22, 6, 25, 0 }, 0x0, 919, }, - { 26, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 21, 22, 25, 6, 0 }, 0x40, 1016, }, - { 26, 1, 2, 0x0000019000000000ull, 0x000001fe00001000ull, { 21, 22, 6, 25, 0 }, 0x40, 993, }, - { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 21, 22, 54, 25, 0 }, 0x0, 1018, }, - { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 21, 22, 56, 25, 0 }, 0x0, 994, }, - { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 21, 56, 25, 0 }, 0x0, 922, }, - { 26, 1, 2, 0x0000018800000000ull, 0x000001ee00001000ull, { 22, 21, 54, 25, 0 }, 0x0, 901, }, - { 26, 1, 2, 0x0000018a00000000ull, 0x000001ee00001000ull, { 21, 22, 54, 25, 0 }, 0x40, 1149, }, - { 26, 1, 2, 0x000001a800000000ull, 0x000001ee00001000ull, { 21, 22, 58, 25, 0 }, 0x0, 1009, }, - { 26, 1, 2, 0x000001a800000000ull, 0x000001ee00001000ull, { 22, 21, 58, 25, 0 }, 0x0, 939, }, - { 26, 1, 2, 0x000001c200000000ull, 0x000001fe00001000ull, { 22, 21, 24, 25, 0 }, 0x40, 1150, }, - { 26, 1, 2, 0x000001d000000000ull, 0x000001fe00001000ull, { 22, 21, 6, 25, 0 }, 0x40, 995, }, - { 26, 1, 2, 0x000001d000000000ull, 0x000001fe00001000ull, { 22, 21, 25, 6, 0 }, 0x40, 903, }, - { 26, 1, 2, 0x000001ca00000000ull, 0x000001ee00001000ull, { 22, 21, 54, 25, 0 }, 0x40, 1151, }, - { 27, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 21, 22, 24, 25, 0 }, 0x0, 1021, }, - { 27, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 22, 21, 25, 24, 0 }, 0x0, 997, }, - { 27, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 21, 22, 25, 24, 0 }, 0x0, 925, }, - { 27, 1, 2, 0x0000018400000000ull, 0x000001fe00001000ull, { 22, 21, 24, 25, 0 }, 0x0, 904, }, - { 27, 1, 2, 0x0000018600000000ull, 0x000001fe00001000ull, { 21, 22, 24, 25, 0 }, 0x40, 1154, }, - { 27, 1, 2, 0x0000019400000000ull, 0x000001fe00001000ull, { 21, 22, 6, 25, 0 }, 0x0, 926, }, - { 27, 1, 2, 0x0000019400000000ull, 0x000001fe00001000ull, { 21, 22, 25, 6, 0 }, 0x40, 1023, }, - { 27, 1, 2, 0x0000019400000000ull, 0x000001fe00001000ull, { 21, 22, 6, 25, 0 }, 0x40, 1000, }, - { 27, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 21, 22, 54, 25, 0 }, 0x0, 1025, }, - { 27, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 21, 22, 56, 25, 0 }, 0x0, 1001, }, - { 27, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 22, 21, 56, 25, 0 }, 0x0, 929, }, - { 27, 1, 2, 0x0000018c00000000ull, 0x000001ee00001000ull, { 22, 21, 54, 25, 0 }, 0x0, 908, }, - { 27, 1, 2, 0x0000018e00000000ull, 0x000001ee00001000ull, { 21, 22, 54, 25, 0 }, 0x40, 1157, }, - { 27, 1, 2, 0x000001ac00000000ull, 0x000001ee00001000ull, { 21, 22, 55, 25, 0 }, 0x0, 1035, }, - { 27, 1, 2, 0x000001ac00000000ull, 0x000001ee00001000ull, { 21, 22, 57, 25, 0 }, 0x0, 1011, }, - { 27, 1, 2, 0x000001ac00000000ull, 0x000001ee00001000ull, { 22, 21, 57, 25, 0 }, 0x0, 941, }, - { 27, 1, 2, 0x000001ac00000000ull, 0x000001ee00001000ull, { 22, 21, 55, 25, 0 }, 0x0, 917, }, - { 27, 1, 2, 0x000001c600000000ull, 0x000001fe00001000ull, { 22, 21, 24, 25, 0 }, 0x40, 1158, }, - { 27, 1, 2, 0x000001d400000000ull, 0x000001fe00001000ull, { 22, 21, 6, 25, 0 }, 0x40, 1002, }, - { 27, 1, 2, 0x000001d400000000ull, 0x000001fe00001000ull, { 22, 21, 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0x000001fff8000000ull, { 33, 0, 0, 0, 0 }, 0x0, 100, }, + { 142, 3, 0, 0x000000db00000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x400, 101, }, + { 142, 3, 0, 0x000000eb00000000ull, 0x000001eff0000000ull, { 33, 62, 0, 0, 0 }, 0x400, 102, }, + { 143, 3, 0, 0x0000000050000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x21, 103, }, + { 151, 3, 0, 0x0000000110000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 104, }, + { 152, 2, 1, 0x000000e880000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1841, }, + { 153, 2, 1, 0x000000ea80000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1842, }, + { 154, 2, 1, 0x000000f880000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1843, }, + { 155, 1, 1, 0x0000010800000000ull, 0x000001fff80fe000ull, { 24, 26, 0, 0, 0 }, 0x0, 105, }, + { 155, 1, 1, 0x0000010800000000ull, 0x000001ee07f00000ull, { 24, 63, 0, 0, 0 }, 0x40, 106, }, + { 155, 1, 1, 0x0000012000000000ull, 0x000001e000300000ull, { 24, 66, 0, 0, 0 }, 0x40, 107, }, + { 155, 5, 1, 0x0000000080000000ull, 0x000001e3f8000000ull, { 18, 20, 0, 0, 0 }, 0xc0, 108, }, + { 155, 2, 1, 0x0000000e00100000ull, 0x000001ee00f00000ull, { 15, 25, 0, 0, 0 }, 0x40, 109, }, + { 155, 2, 1, 0x0000000e00000000ull, 0x000001ee00f00000ull, { 15, 25, 78, 0, 0 }, 0x0, 2391, }, + { 155, 2, 1, 0x0000000188000000ull, 0x000001eff8000000ull, { 24, 16, 0, 0, 0 }, 0x0, 111, }, + { 155, 2, 1, 0x0000000600000000ull, 0x000001ee00000000ull, { 9, 25, 64, 0, 0 }, 0x0, 112, }, + { 155, 2, 1, 0x0000000400000000ull, 0x000001ee00000000ull, { 10, 68, 0, 0, 0 }, 0x0, 113, }, + { 155, 2, 1, 0x0000000180000000ull, 0x000001eff8000000ull, { 24, 8, 0, 0, 0 }, 0x0, 114, }, + { 155, 2, 1, 0x0000000198000000ull, 0x000001eff8000000ull, { 24, 9, 0, 0, 0 }, 0x0, 115, }, + { 155, 2, 1, 0x0000000150000000ull, 0x000001eff8000000ull, { 14, 25, 0, 0, 0 }, 0x0, 962, }, + { 155, 2, 1, 0x0000000050000000ull, 0x000001eff8000000ull, { 14, 55, 0, 0, 0 }, 0x0, 963, }, + { 155, 2, 1, 0x0000000190000000ull, 0x000001eff8000000ull, { 24, 14, 0, 0, 0 }, 0x0, 964, }, + { 155, 3, 1, 0x0000000140000000ull, 0x000001eff8000000ull, { 14, 55, 0, 0, 0 }, 0x0, 1051, }, + { 155, 3, 1, 0x0000002150000000ull, 0x000001eff8000000ull, { 14, 25, 0, 0, 0 }, 0x0, 1052, }, + { 155, 3, 1, 0x0000002110000000ull, 0x000001eff8000000ull, { 24, 14, 0, 0, 0 }, 0x0, 1053, }, + { 155, 3, 1, 0x0000002160000000ull, 0x000001eff8000000ull, { 17, 25, 0, 0, 0 }, 0x8, 116, }, + { 155, 3, 1, 0x0000002120000000ull, 0x000001eff8000000ull, { 24, 17, 0, 0, 0 }, 0x8, 117, }, + { 155, 3, 1, 0x0000002168000000ull, 0x000001eff8000000ull, { 12, 25, 0, 0, 0 }, 0x8, 118, }, + { 155, 3, 1, 0x0000002148000000ull, 0x000001eff8000000ull, { 13, 25, 0, 0, 0 }, 0x0, 119, }, + { 155, 3, 1, 0x0000002128000000ull, 0x000001eff8000000ull, { 24, 11, 0, 0, 0 }, 0x8, 120, }, + { 155, 3, 1, 0x0000002108000000ull, 0x000001eff8000000ull, { 24, 13, 0, 0, 0 }, 0x0, 121, }, + { 155, 3, 1, 0x0000002000000000ull, 0x000001eff8000000ull, { 38, 25, 0, 0, 0 }, 0x8, 122, }, + { 155, 3, 1, 0x0000002008000000ull, 0x000001eff8000000ull, { 29, 25, 0, 0, 0 }, 0x8, 123, }, + { 155, 3, 1, 0x0000002010000000ull, 0x000001eff8000000ull, { 32, 25, 0, 0, 0 }, 0x8, 124, }, + { 155, 3, 1, 0x0000002018000000ull, 0x000001eff8000000ull, { 35, 25, 0, 0, 0 }, 0x8, 125, }, + { 155, 3, 1, 0x0000002020000000ull, 0x000001eff8000000ull, { 36, 25, 0, 0, 0 }, 0x8, 126, }, + { 155, 3, 1, 0x0000002028000000ull, 0x000001eff8000000ull, { 37, 25, 0, 0, 0 }, 0x8, 127, }, + { 155, 3, 1, 0x0000002030000000ull, 0x000001eff8000000ull, { 34, 25, 0, 0, 0 }, 0x8, 128, }, + { 155, 3, 1, 0x0000002080000000ull, 0x000001eff8000000ull, { 24, 38, 0, 0, 0 }, 0x8, 129, }, + { 155, 3, 1, 0x0000002088000000ull, 0x000001eff8000000ull, { 24, 29, 0, 0, 0 }, 0x8, 130, }, + { 155, 3, 1, 0x0000002090000000ull, 0x000001eff8000000ull, { 24, 32, 0, 0, 0 }, 0x8, 131, }, + { 155, 3, 1, 0x0000002098000000ull, 0x000001eff8000000ull, { 24, 35, 0, 0, 0 }, 0x8, 132, }, + { 155, 3, 1, 0x00000020a0000000ull, 0x000001eff8000000ull, { 24, 36, 0, 0, 0 }, 0x8, 133, }, + { 155, 3, 1, 0x00000020a8000000ull, 0x000001eff8000000ull, { 24, 37, 0, 0, 0 }, 0x0, 134, }, + { 155, 3, 1, 0x00000020b0000000ull, 0x000001eff8000000ull, { 24, 34, 0, 0, 0 }, 0x8, 135, }, + { 155, 3, 1, 0x00000020b8000000ull, 0x000001eff8000000ull, { 24, 28, 0, 0, 0 }, 0x0, 136, }, + { 155, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 24, 14, 0, 0, 0 }, 0x0, 137, }, + { 155, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 14, 55, 0, 0, 0 }, 0x0, 138, }, + { 155, 7, 1, 0x0000000000000000ull, 0x0000000000000000ull, { 14, 25, 0, 0, 0 }, 0x0, 139, }, + { 156, 6, 1, 0x000000c000000000ull, 0x000001e000100000ull, { 24, 70, 0, 0, 0 }, 0x0, 140, }, + { 157, 2, 1, 0x000000eca0000000ull, 0x000001fff0000000ull, { 24, 25, 74, 0, 0 }, 0x0, 141, }, + { 158, 2, 1, 0x000000eea0000000ull, 0x000001fff0000000ull, { 24, 25, 75, 0, 0 }, 0x0, 142, }, + { 168, 4, 0, 0x0000004000000000ull, 0x000001e1f8000000ull, { 65, 0, 0, 0, 0 }, 0x0, 400, }, + { 168, 5, 0, 0x0000000008000000ull, 0x000001e3fc000000ull, { 65, 0, 0, 0, 0 }, 0x0, 814, }, + { 168, 2, 0, 0x0000000008000000ull, 0x000001effc000000ull, { 65, 0, 0, 0, 0 }, 0x2, 965, }, + { 168, 3, 0, 0x0000000008000000ull, 0x000001effc000000ull, { 65, 0, 0, 0, 0 }, 0x0, 1054, }, + { 168, 6, 0, 0x0000000008000000ull, 0x000001effc000000ull, { 69, 0, 0, 0, 0 }, 0x0, 2508, }, + { 168, 7, 0, 0x0000000000000000ull, 0x0000000000000000ull, { 65, 0, 0, 0, 0 }, 0x0, 143, }, + { 175, 1, 1, 0x0000010070000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 144, }, + { 175, 1, 1, 0x0000010170000000ull, 0x000001eff8000000ull, { 24, 55, 26, 0, 0 }, 0x0, 145, }, + { 178, 2, 1, 0x000000ea00000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 2490, }, + { 179, 2, 1, 0x000000f820000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 2393, }, + { 180, 1, 1, 0x0000010400000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 146, }, + { 181, 1, 1, 0x0000010600000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 147, }, + { 182, 1, 1, 0x0000011400000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 148, }, + { 183, 1, 1, 0x0000010450000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 149, }, + { 184, 1, 1, 0x0000010650000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 150, }, + { 185, 1, 1, 0x0000010470000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 151, }, + { 186, 1, 1, 0x0000010670000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 152, }, + { 187, 1, 1, 0x0000010520000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 800, }, + { 188, 1, 1, 0x0000010720000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 801, }, + { 189, 1, 1, 0x0000011520000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 802, }, + { 190, 2, 1, 0x000000e850000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 2407, }, + { 191, 2, 1, 0x000000ea70000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 153, }, + { 192, 2, 1, 0x000000e810000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 2408, }, + { 193, 2, 1, 0x000000ea30000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 154, }, + { 194, 2, 1, 0x000000ead0000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 1844, }, + { 195, 2, 1, 0x000000e230000000ull, 0x000001ff30000000ull, { 24, 25, 26, 42, 0 }, 0x0, 155, }, + { 196, 2, 1, 0x000000e690000000ull, 0x000001fff0000000ull, { 24, 26, 0, 0, 0 }, 0x0, 156, }, + { 198, 3, 1, 0x00000021c0000000ull, 0x000001eff8000000ull, { 24, 26, 25, 0, 0 }, 0x0, 1845, }, + { 198, 3, 1, 0x00000020c0000000ull, 0x000001eff8000000ull, { 24, 26, 49, 0, 0 }, 0x0, 1846, }, + { 198, 3, 0, 0x0000002188000000ull, 0x000001eff8000000ull, { 26, 49, 0, 0, 0 }, 0x0, 1870, }, + { 199, 2, 1, 0x000000e8b0000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 157, }, + { 200, 2, 1, 0x000000e240000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 158, }, + { 200, 2, 1, 0x000000ee50000000ull, 0x000001fff0000000ull, { 24, 25, 39, 0, 0 }, 0x0, 159, }, + { 201, 2, 1, 0x000000f040000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 160, }, + { 201, 2, 1, 0x000000fc50000000ull, 0x000001fff0000000ull, { 24, 25, 39, 0, 0 }, 0x0, 161, }, + { 202, 1, 1, 0x0000010680000000ull, 0x000001ffe0000000ull, { 24, 25, 41, 26, 0 }, 0x0, 162, }, + { 203, 2, 1, 0x000000e220000000ull, 0x000001fff0000000ull, { 24, 26, 25, 0, 0 }, 0x0, 163, }, + { 203, 2, 1, 0x000000e630000000ull, 0x000001fff0000000ull, { 24, 26, 43, 0, 0 }, 0x0, 164, }, + { 204, 2, 1, 0x000000f020000000ull, 0x000001fff0000000ull, { 24, 26, 25, 0, 0 }, 0x0, 165, }, + { 204, 2, 1, 0x000000f430000000ull, 0x000001fff0000000ull, { 24, 26, 43, 0, 0 }, 0x0, 166, }, + { 205, 1, 1, 0x00000106c0000000ull, 0x000001ffe0000000ull, { 24, 25, 41, 26, 0 }, 0x0, 167, }, + { 206, 1, 1, 0x0000010420000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 168, }, + { 207, 1, 1, 0x0000010620000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 169, }, + { 208, 1, 1, 0x0000011420000000ull, 0x000001fff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 170, }, + { 209, 3, 0, 0x0000002048000000ull, 0x000001eff8000000ull, { 26, 25, 0, 0, 0 }, 0x8, 993, }, + { 209, 3, 0, 0x0000002050000000ull, 0x000001eff8000000ull, { 26, 25, 0, 0, 0 }, 0xc, 902, }, + { 209, 3, 0, 0x00000021a0000000ull, 0x000001eff8000000ull, { 26, 0, 0, 0, 0 }, 0x8, 783, }, + { 210, 3, 0, 0x0000002060000000ull, 0x000001eff8000000ull, { 26, 25, 0, 0, 0 }, 0x8, 709, }, + { 215, 4, 0, 0x0000000040000000ull, 0x000001e1f8000000ull, { 0, 0, 0, 0, 0 }, 0x22c, 171, }, + { 216, 3, 0, 0x0000000038000000ull, 0x000001ee78000000ull, { 67, 0, 0, 0, 0 }, 0x8, 172, }, + { 217, 3, 0, 0x0000000028000000ull, 0x000001ee78000000ull, { 67, 0, 0, 0, 0 }, 0x0, 173, }, + { 226, 3, 1, 0x000000c708000000ull, 0x000001ffc8000000ull, { 18, 25, 0, 0, 0 }, 0x0, 2318, }, + { 227, 2, 1, 0x000000a600000000ull, 0x000001ee04000000ull, { 24, 25, 45, 0, 0 }, 0x140, 174, }, + { 227, 2, 1, 0x000000f240000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 175, }, + { 228, 1, 1, 0x0000010080000000ull, 0x000001efe0000000ull, { 24, 25, 40, 26, 0 }, 0x0, 176, }, + { 229, 1, 1, 0x00000100c0000000ull, 0x000001efe0000000ull, { 24, 25, 40, 26, 0 }, 0x0, 177, }, + { 230, 2, 1, 0x000000a400000000ull, 0x000001ee00002000ull, { 24, 26, 76, 0, 0 }, 0x140, 2414, }, + { 230, 2, 1, 0x000000f220000000ull, 0x000001fff0000000ull, { 24, 26, 25, 0, 0 }, 0x0, 179, }, + { 231, 2, 1, 0x000000ac00000000ull, 0x000001ee00000000ull, { 24, 25, 26, 44, 0 }, 0x0, 180, }, + { 236, 3, 0, 0x0000000180000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 711, }, + { 237, 3, 0, 0x0000000030000000ull, 0x000001ee78000000ull, { 67, 0, 0, 0, 0 }, 0x8, 181, }, + { 239, 3, 1, 0x0000008c00000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x0, 182, }, + { 239, 3, 1, 0x000000ac00000000ull, 0x000001eff0000000ull, { 33, 25, 61, 0, 0 }, 0x400, 183, }, + { 240, 3, 1, 0x0000008c08000000ull, 0x000001fff8000000ull, { 33, 25, 1, 0, 0 }, 0x0, 184, }, + { 241, 3, 1, 0x0000008c40000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x0, 185, }, + { 241, 3, 1, 0x000000ac40000000ull, 0x000001eff0000000ull, { 33, 25, 61, 0, 0 }, 0x400, 186, }, + { 242, 3, 1, 0x0000008c80000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x0, 187, }, + { 242, 3, 1, 0x000000ac80000000ull, 0x000001eff0000000ull, { 33, 25, 61, 0, 0 }, 0x400, 188, }, + { 243, 3, 1, 0x0000008cc0000000ull, 0x000001fff8000000ull, { 33, 25, 0, 0, 0 }, 0x0, 189, }, + { 243, 3, 1, 0x000000acc0000000ull, 0x000001eff0000000ull, { 33, 25, 61, 0, 0 }, 0x400, 190, }, + { 244, 3, 1, 0x000000cec0000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 2321, }, + { 244, 3, 1, 0x000000eec0000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 2322, }, + { 245, 3, 1, 0x000000cc40000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 191, }, + { 245, 3, 1, 0x000000ec40000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 192, }, + { 246, 3, 1, 0x000000ccc0000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 193, }, + { 246, 3, 1, 0x000000ecc0000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 194, }, + { 247, 3, 1, 0x000000cc00000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 195, }, + { 247, 3, 1, 0x000000ec00000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 196, }, + { 248, 3, 1, 0x000000cc80000000ull, 0x000001fff8000000ull, { 33, 19, 0, 0, 0 }, 0x0, 197, }, + { 248, 3, 1, 0x000000ec80000000ull, 0x000001eff0000000ull, { 33, 19, 61, 0, 0 }, 0x400, 198, }, + { 249, 1, 1, 0x0000010028000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 199, }, + { 249, 1, 1, 0x0000010020000000ull, 0x000001eff8000000ull, { 24, 25, 26, 4, 0 }, 0x0, 200, }, + { 249, 1, 1, 0x0000010128000000ull, 0x000001eff8000000ull, { 24, 55, 26, 0, 0 }, 0x0, 201, }, + { 250, 3, 0, 0x0000000020000000ull, 0x000001ee78000000ull, { 67, 0, 0, 0, 0 }, 0x0, 202, }, + { 251, 2, 1, 0x00000000a0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 203, }, + { 252, 2, 1, 0x00000000a8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 204, }, + { 253, 2, 1, 0x00000000b0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 205, }, + { 254, 3, 0, 0x0000000198000000ull, 0x000001eff8000000ull, { 0, 0, 0, 0, 0 }, 0x0, 968, }, + { 255, 3, 1, 0x00000020f8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x8, 206, }, + { 256, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 22, 23, 26, 76, 0 }, 0x0, 2513, }, + { 256, 2, 2, 0x000000a000000000ull, 0x000001fe00003000ull, { 23, 22, 26, 76, 0 }, 0x40, 1745, }, + { 257, 3, 1, 0x00000020d0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 207, }, + { 258, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 22, 23, 26, 0, 0 }, 0x0, 2515, }, + { 258, 2, 2, 0x000000a000002000ull, 0x000001fe00003000ull, { 23, 22, 26, 0, 0 }, 0x40, 1747, }, + { 259, 3, 1, 0x00000020f0000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x8, 208, }, + { 261, 3, 1, 0x00000020d8000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 209, }, + { 265, 2, 1, 0x000000e840000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 949, }, + { 266, 2, 1, 0x000000ea40000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 950, }, + { 267, 2, 1, 0x000000f840000000ull, 0x000001fff0000000ull, { 24, 25, 26, 0, 0 }, 0x0, 951, }, + { 275, 3, 1, 0x0000008208000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x0, 210, }, + { 276, 3, 1, 0x0000008248000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x0, 211, }, + { 277, 3, 1, 0x0000008288000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x0, 212, }, + { 278, 3, 1, 0x00000082c8000000ull, 0x000001fff8000000ull, { 24, 33, 25, 0, 0 }, 0x0, 213, }, + { 280, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 18, 20, 21, 19, 0 }, 0x0, 997, }, + { 280, 5, 1, 0x000001d000000000ull, 0x000001fc00000000ull, { 18, 20, 21, 19, 0 }, 0x40, 1045, }, + { 281, 5, 1, 0x000001d000000000ull, 0x000001fc000fe000ull, { 18, 20, 21, 0, 0 }, 0x40, 998, }, + { 282, 1, 1, 0x0000010078000000ull, 0x000001eff8000000ull, { 24, 25, 26, 0, 0 }, 0x0, 214, }, + { 282, 1, 1, 0x0000010178000000ull, 0x000001eff8000000ull, { 24, 55, 26, 0, 0 }, 0x0, 215, }, + { 285, 2, 1, 0x0000000080000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 216, }, + { 286, 2, 1, 0x0000000088000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 217, }, + { 287, 2, 1, 0x0000000090000000ull, 0x000001eff8000000ull, { 24, 26, 0, 0, 0 }, 0x0, 218, }, }; static const char dis_table[] = { -0xa0, 0xc2, 0xa0, 0xa0, 0x2c, 0xc0, 0xa0, 0x2a, 0xc0, 0xa0, 0x1a, 0x70, -0x98, 0xb0, 0x01, 0x40, 0x90, 0x50, 0x90, 0x28, 0x24, 0x31, 0x48, 0x24, -0x31, 0x40, 0x90, 0x28, 0x24, 0x31, 0x38, 0x24, 0x31, 0x30, 0x90, 0x50, -0x90, 0x28, 0x24, 0x31, 0x20, 0x24, 0x31, 0x18, 0x90, 0x28, 0x24, 0x31, -0x10, 0x24, 0x31, 0x08, 0xa8, 0x0b, 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0x1d, +0xc0, 0x38, 0x81, 0xcb, 0x61, 0x17, 0xc0, 0x85, 0x34, 0x6e, 0x98, 0x50, +0x00, 0x80, 0xe5, 0x22, 0x19, 0xc0, 0x38, 0x63, 0xe5, 0x22, 0x15, 0xc0, +0x38, 0x61, 0xcb, 0x61, 0x17, 0x80, 0x85, 0x34, 0x6d, 0x90, 0x48, 0xcb, +0xa1, 0x17, 0x40, 0x85, 0x34, 0x6c, 0xcb, 0xa1, 0x17, 0x00, 0x85, 0x34, +0x6b, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x0e, +0xc0, 0x38, 0x47, 0xe5, 0x22, 0x08, 0xc0, 0x38, 0x2f, 0xcb, 0x61, 0x16, +0x80, 0x85, 0x34, 0x69, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x02, 0xc0, +0x38, 0x17, 0xe5, 0x21, 0xfc, 0xc0, 0x37, 0xff, 0xcb, 0x61, 0x16, 0x40, +0x85, 0x34, 0x68, 0x90, 0x48, 0xcb, 0xa1, 0x16, 0x00, 0x85, 0x34, 0x67, +0xcb, 0xa1, 0x15, 0xc0, 0x85, 0x34, 0x66, 0x92, 0x20, 0x91, 0x30, 0x90, +0xb8, 0xd5, 0x03, 0x00, 0xc0, 0xc0, 0x81, 0x8c, 0x01, 0xa0, 0x84, 0x30, +0x3e, 0xc0, 0xc0, 0x81, 0x8c, 0x01, 0x80, 0x84, 0x30, 0x3c, 0xd5, 0x02, +0x00, 0xc0, 0xc0, 0x81, 0x30, 0x28, 0xc0, 0xc0, 0x81, 0x30, 0x24, 0x90, +0x78, 0xd5, 0x02, 0x00, 0xc0, 0xc0, 0x81, 0x30, 0x1c, 0xc0, 0xc0, 0x81, +0x30, 0x18, 0xd5, 0x02, 0x00, 0xc0, 0xc0, 0x81, 0x30, 0x10, 0xc0, 0xc0, +0x81, 0x30, 0x0c, 0x91, 0x70, 0x90, 0xd8, 0xd5, 0x03, 0x80, 0xc8, 0xe1, +0xf8, 0xc0, 0x81, 0x8c, 0x01, 0xc0, 0x84, 0x30, 0x40, 0xc8, 0xe1, 0xf9, +0xc0, 0x81, 0x8c, 0x01, 0x90, 0x84, 0x30, 0x3d, 0xd5, 0x02, 0x80, 0xc8, +0xe1, 0xf8, 0x40, 0x81, 0x30, 0x2c, 0xc8, 0xe1, 0xf5, 0x40, 0x81, 0x30, +0x26, 0x90, 0x98, 0xd5, 0x02, 0x80, 0xc8, 0xe1, 0xef, 0x40, 0x81, 0x30, +0x20, 0xc8, 0xe1, 0xf0, 0x40, 0x81, 0x30, 0x1a, 0xd5, 0x02, 0x80, 0xc8, +0xe1, 0xee, 0xc0, 0x81, 0x30, 0x14, 0xc8, 0xe1, 0xeb, 0xc0, 0x81, 0x30, +0x0e, 0x9a, 0x30, 0x04, 0x40, 0x91, 0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, +0x80, 0xe5, 0x22, 0x1b, 0xc0, 0x38, 0x6b, 0xe5, 0x22, 0x1c, 0xc0, 0x38, +0x7d, 0xcb, 0x61, 0x15, 0x40, 0x85, 0x34, 0x64, 0x98, 0x50, 0x00, 0x80, +0xe5, 0x22, 0x13, 0xc0, 0x38, 0x4b, 0xe5, 0x22, 0x14, 0xc0, 0x38, 0x5d, +0xcb, 0x61, 0x15, 0x00, 0x85, 0x34, 0x63, 0x90, 0x48, 0xcb, 0xa1, 0x14, +0xc0, 0x85, 0x34, 0x62, 0xcb, 0xa1, 0x14, 0x80, 0x85, 0x34, 0x61, 0x91, +0x90, 0x90, 0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x0c, 0xc0, 0x38, +0x3f, 0xe5, 0x22, 0x06, 0xc0, 0x38, 0x27, 0xcb, 0x61, 0x12, 0xc0, 0x85, +0x34, 0x50, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x00, 0xc0, 0x38, 0x0f, +0xe5, 0x21, 0xfa, 0xc0, 0x37, 0xf7, 0xcb, 0x61, 0x12, 0x80, 0x85, 0x34, +0x4f, 0x90, 0x48, 0xcb, 0xa1, 0x12, 0x40, 0x85, 0x34, 0x4e, 0xcb, 0xa1, +0x12, 0x00, 0x85, 0x34, 0x4d, 0x91, 0x00, 0x90, 0x80, 0x90, 0x40, 0xe5, +0x20, 0x02, 0x40, 0x30, 0x0a, 0xe5, 0x20, 0x01, 0x80, 0x30, 0x07, 0x90, +0x40, 0xe5, 0x20, 0x00, 0xc0, 0x30, 0x04, 0xe5, 0x20, 0x00, 0x00, 0x30, +0x01, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x21, 0xf2, 0xc0, 0x37, 0xc5, 0xe5, +0x21, 0xf4, 0x00, 0x37, 0xdb, 0x90, 0x40, 0xe5, 0x21, 0xe9, 0x40, 0x37, +0x9f, 0xe5, 0x21, 0xea, 0x80, 0x37, 0xb5, 0x80, 0x99, 0x28, 0x02, 0xf0, +0x8c, 0x21, 0xf8, 0x90, 0x80, 0x90, 0x40, 0xe5, 0x22, 0x1e, 0xc0, 0x38, +0x79, 0xe5, 0x22, 0x1d, 0x40, 0x38, 0x7f, 0x90, 0x40, 0xe5, 0x22, 0x16, +0xc0, 0x38, 0x59, 0xe5, 0x22, 0x15, 0x40, 0x38, 0x5f, 0x91, 0x48, 0x90, +0xc8, 0x98, 0x50, 0x00, 0x80, 0xe5, 0x22, 0x0d, 0xc0, 0x38, 0x43, 0xe5, +0x22, 0x07, 0xc0, 0x38, 0x2b, 0xcb, 0x61, 0x10, 0x80, 0x85, 0x34, 0x46, +0x90, 0x40, 0xe5, 0x22, 0x01, 0xc0, 0x38, 0x13, 0xe5, 0x21, 0xfb, 0xc0, +0x37, 0xfb, 0x90, 0x48, 0xcb, 0xa1, 0x10, 0x00, 0x85, 0x34, 0x44, 0xcb, +0xa1, 0x10, 0x40, 0x85, 0x34, 0x45, 0x10, 0x10, 0x90, 0x80, 0x90, 0x40, +0xe5, 0x21, 0xf6, 0x40, 0x37, 0xd7, 0xe5, 0x21, 0xf4, 0xc0, 0x37, 0xdf, +0x90, 0x40, 0xe5, 0x21, 0xec, 0xc0, 0x37, 0xb1, 0xe5, 0x21, 0xeb, 0x40, +0x37, 0xb9, }; static const struct ia64_dis_names ia64_dis_names[] = { -{ 0x51, 40, 0, 9 }, -{ 0x31, 40, 1, 19 }, -{ 0x11, 41, 0, 18 }, -{ 0x29, 40, 0, 11 }, -{ 0x19, 40, 1, 23 }, -{ 0x9, 41, 0, 22 }, -{ 0x15, 40, 0, 13 }, -{ 0xd, 40, 1, 27 }, -{ 0x5, 41, 0, 26 }, -{ 0xb, 40, 0, 15 }, -{ 0x7, 40, 1, 31 }, -{ 0x3, 41, 0, 30 }, -{ 0x51, 38, 1, 57 }, -{ 0x50, 38, 0, 33 }, -{ 0xd1, 38, 1, 56 }, -{ 0xd0, 38, 0, 32 }, -{ 0x31, 38, 1, 67 }, -{ 0x30, 38, 1, 43 }, -{ 0x11, 39, 1, 66 }, -{ 0x10, 39, 0, 42 }, -{ 0x71, 38, 1, 65 }, -{ 0x70, 38, 1, 41 }, -{ 0x31, 39, 1, 64 }, -{ 0x30, 39, 0, 40 }, -{ 0x29, 38, 1, 59 }, -{ 0x28, 38, 0, 35 }, -{ 0x69, 38, 1, 58 }, -{ 0x68, 38, 0, 34 }, -{ 0x19, 38, 1, 71 }, -{ 0x18, 38, 1, 47 }, -{ 0x9, 39, 1, 70 }, -{ 0x8, 39, 0, 46 }, -{ 0x39, 38, 1, 69 }, -{ 0x38, 38, 1, 45 }, -{ 0x19, 39, 1, 68 }, -{ 0x18, 39, 0, 44 }, -{ 0x15, 38, 1, 61 }, -{ 0x14, 38, 0, 37 }, -{ 0x35, 38, 1, 60 }, -{ 0x34, 38, 0, 36 }, -{ 0xd, 38, 1, 75 }, -{ 0xc, 38, 1, 51 }, -{ 0x5, 39, 1, 74 }, -{ 0x4, 39, 0, 50 }, -{ 0x1d, 38, 1, 73 }, -{ 0x1c, 38, 1, 49 }, -{ 0xd, 39, 1, 72 }, -{ 0xc, 39, 0, 48 }, -{ 0xb, 38, 1, 63 }, -{ 0xa, 38, 0, 39 }, -{ 0x1b, 38, 1, 62 }, -{ 0x1a, 38, 0, 38 }, -{ 0x7, 38, 1, 79 }, -{ 0x6, 38, 1, 55 }, -{ 0x3, 39, 1, 78 }, -{ 0x2, 39, 0, 54 }, -{ 0xf, 38, 1, 77 }, -{ 0xe, 38, 1, 53 }, -{ 0x7, 39, 1, 76 }, -{ 0x6, 39, 0, 52 }, -{ 0x8, 37, 0, 81 }, -{ 0x18, 37, 0, 80 }, -{ 0x1, 37, 1, 85 }, -{ 0x2, 37, 0, 84 }, -{ 0x3, 37, 1, 83 }, -{ 0x4, 37, 0, 82 }, -{ 0x1, 284, 0, 86 }, -{ 0x20, 237, 0, 96 }, -{ 0x220, 237, 0, 92 }, -{ 0x1220, 237, 0, 89 }, -{ 0xa20, 237, 0, 90 }, -{ 0x620, 237, 0, 91 }, -{ 0x120, 237, 0, 93 }, -{ 0xa0, 237, 0, 94 }, -{ 0x60, 237, 0, 95 }, -{ 0x10, 237, 0, 100 }, -{ 0x90, 237, 0, 97 }, -{ 0x50, 237, 0, 98 }, -{ 0x30, 237, 0, 99 }, -{ 0x8, 237, 0, 101 }, -{ 0x4, 237, 0, 102 }, -{ 0x2, 237, 0, 103 }, -{ 0x1, 237, 0, 104 }, -{ 0x1, 357, 0, 106 }, -{ 0x3, 357, 0, 105 }, -{ 0x2, 363, 0, 107 }, -{ 0x1, 363, 0, 108 }, -{ 0x2, 359, 0, 109 }, -{ 0x1, 359, 0, 110 }, -{ 0x2, 361, 0, 111 }, -{ 0x1, 361, 0, 112 }, -{ 0x2, 365, 0, 113 }, -{ 0x1, 365, 0, 114 }, -{ 0x1, 216, 0, 141 }, -{ 0x5, 216, 0, 139 }, -{ 0x3, 216, 0, 140 }, -{ 0x140, 225, 0, 117 }, -{ 0x540, 225, 0, 115 }, -{ 0x340, 225, 0, 116 }, -{ 0xc0, 225, 0, 129 }, -{ 0x2c0, 225, 0, 127 }, -{ 0x1c0, 225, 0, 128 }, -{ 0x20, 225, 0, 144 }, -{ 0xa0, 225, 0, 142 }, -{ 0x60, 225, 0, 143 }, -{ 0x10, 225, 0, 156 }, -{ 0x50, 225, 0, 154 }, -{ 0x30, 225, 0, 155 }, -{ 0x8, 225, 0, 168 }, -{ 0x28, 225, 0, 166 }, -{ 0x18, 225, 0, 167 }, -{ 0x4, 225, 0, 178 }, -{ 0x2, 225, 0, 179 }, -{ 0x1, 225, 0, 180 }, -{ 0x140, 219, 0, 120 }, -{ 0x540, 219, 0, 118 }, -{ 0x340, 219, 0, 119 }, -{ 0xc0, 219, 0, 132 }, -{ 0x2c0, 219, 0, 130 }, -{ 0x1c0, 219, 0, 131 }, -{ 0x20, 219, 0, 147 }, -{ 0xa0, 219, 0, 145 }, -{ 0x60, 219, 0, 146 }, -{ 0x10, 219, 0, 159 }, -{ 0x50, 219, 0, 157 }, -{ 0x30, 219, 0, 158 }, -{ 0x8, 219, 0, 171 }, -{ 0x28, 219, 0, 169 }, -{ 0x18, 219, 0, 170 }, -{ 0x4, 219, 0, 181 }, -{ 0x2, 219, 0, 182 }, -{ 0x1, 219, 0, 183 }, -{ 0x140, 222, 0, 123 }, -{ 0x540, 222, 0, 121 }, -{ 0x340, 222, 0, 122 }, -{ 0xc0, 222, 0, 135 }, -{ 0x2c0, 222, 0, 133 }, -{ 0x1c0, 222, 0, 134 }, -{ 0x20, 222, 0, 150 }, -{ 0xa0, 222, 0, 148 }, -{ 0x60, 222, 0, 149 }, -{ 0x10, 222, 0, 162 }, -{ 0x50, 222, 0, 160 }, -{ 0x30, 222, 0, 161 }, -{ 0x8, 222, 0, 174 }, -{ 0x28, 222, 0, 172 }, -{ 0x18, 222, 0, 173 }, -{ 0x4, 222, 0, 184 }, -{ 0x2, 222, 0, 185 }, -{ 0x1, 222, 0, 186 }, -{ 0x140, 234, 0, 126 }, -{ 0x540, 234, 0, 124 }, -{ 0x340, 234, 0, 125 }, -{ 0xc0, 234, 0, 138 }, -{ 0x2c0, 234, 0, 136 }, -{ 0x1c0, 234, 0, 137 }, -{ 0x20, 234, 0, 153 }, -{ 0xa0, 234, 0, 151 }, -{ 0x60, 234, 0, 152 }, -{ 0x10, 234, 0, 165 }, -{ 0x50, 234, 0, 163 }, -{ 0x30, 234, 0, 164 }, -{ 0x8, 234, 0, 177 }, -{ 0x28, 234, 0, 175 }, -{ 0x18, 234, 0, 176 }, -{ 0x4, 234, 0, 187 }, -{ 0x2, 234, 0, 188 }, -{ 0x1, 234, 0, 189 }, -{ 0x8, 338, 0, 190 }, -{ 0x4, 338, 0, 191 }, -{ 0x2, 338, 0, 192 }, -{ 0x1, 338, 0, 193 }, -{ 0x20, 236, 0, 201 }, -{ 0x220, 236, 0, 197 }, -{ 0x1220, 236, 0, 194 }, -{ 0xa20, 236, 0, 195 }, -{ 0x620, 236, 0, 196 }, -{ 0x120, 236, 0, 198 }, -{ 0xa0, 236, 0, 199 }, -{ 0x60, 236, 0, 200 }, -{ 0x10, 236, 0, 205 }, -{ 0x90, 236, 0, 202 }, -{ 0x50, 236, 0, 203 }, -{ 0x30, 236, 0, 204 }, -{ 0x8, 236, 0, 206 }, -{ 0x4, 236, 0, 207 }, -{ 0x2, 236, 0, 208 }, -{ 0x1, 236, 0, 209 }, -{ 0x20, 235, 0, 217 }, -{ 0x220, 235, 0, 213 }, -{ 0x1220, 235, 0, 210 }, -{ 0xa20, 235, 0, 211 }, -{ 0x620, 235, 0, 212 }, -{ 0x120, 235, 0, 214 }, -{ 0xa0, 235, 0, 215 }, -{ 0x60, 235, 0, 216 }, -{ 0x10, 235, 0, 221 }, -{ 0x90, 235, 0, 218 }, -{ 0x50, 235, 0, 219 }, -{ 0x30, 235, 0, 220 }, -{ 0x8, 235, 0, 222 }, -{ 0x4, 235, 0, 223 }, -{ 0x2, 235, 0, 224 }, -{ 0x1, 235, 0, 225 }, -{ 0x140, 227, 0, 228 }, -{ 0x540, 227, 0, 226 }, -{ 0x340, 227, 0, 227 }, -{ 0xc0, 227, 0, 237 }, -{ 0x2c0, 227, 0, 235 }, -{ 0x1c0, 227, 0, 236 }, -{ 0x20, 227, 0, 246 }, -{ 0xa0, 227, 0, 244 }, -{ 0x60, 227, 0, 245 }, -{ 0x10, 227, 0, 255 }, -{ 0x50, 227, 0, 253 }, -{ 0x30, 227, 0, 254 }, -{ 0x8, 227, 0, 264 }, -{ 0x28, 227, 0, 262 }, -{ 0x18, 227, 0, 263 }, -{ 0x4, 227, 0, 271 }, -{ 0x2, 227, 0, 272 }, -{ 0x1, 227, 0, 273 }, -{ 0x140, 229, 0, 231 }, -{ 0x540, 229, 0, 229 }, -{ 0x340, 229, 0, 230 }, -{ 0xc0, 229, 0, 240 }, -{ 0x2c0, 229, 0, 238 }, -{ 0x1c0, 229, 0, 239 }, -{ 0x20, 229, 0, 249 }, -{ 0xa0, 229, 0, 247 }, -{ 0x60, 229, 0, 248 }, -{ 0x10, 229, 0, 258 }, -{ 0x50, 229, 0, 256 }, -{ 0x30, 229, 0, 257 }, -{ 0x8, 229, 0, 267 }, -{ 0x28, 229, 0, 265 }, -{ 0x18, 229, 0, 266 }, -{ 0x4, 229, 0, 274 }, -{ 0x2, 229, 0, 275 }, -{ 0x1, 229, 0, 276 }, -{ 0x140, 231, 0, 234 }, -{ 0x540, 231, 0, 232 }, -{ 0x340, 231, 0, 233 }, -{ 0xc0, 231, 0, 243 }, -{ 0x2c0, 231, 0, 241 }, -{ 0x1c0, 231, 0, 242 }, -{ 0x20, 231, 0, 252 }, -{ 0xa0, 231, 0, 250 }, -{ 0x60, 231, 0, 251 }, -{ 0x10, 231, 0, 261 }, -{ 0x50, 231, 0, 259 }, -{ 0x30, 231, 0, 260 }, -{ 0x8, 231, 0, 270 }, -{ 0x28, 231, 0, 268 }, -{ 0x18, 231, 0, 269 }, -{ 0x4, 231, 0, 277 }, -{ 0x2, 231, 0, 278 }, -{ 0x1, 231, 0, 279 }, -{ 0x140, 226, 0, 282 }, -{ 0x540, 226, 0, 280 }, -{ 0x340, 226, 0, 281 }, -{ 0xc0, 226, 0, 291 }, -{ 0x2c0, 226, 0, 289 }, -{ 0x1c0, 226, 0, 290 }, -{ 0x20, 226, 0, 300 }, -{ 0xa0, 226, 0, 298 }, -{ 0x60, 226, 0, 299 }, -{ 0x10, 226, 0, 309 }, -{ 0x50, 226, 0, 307 }, -{ 0x30, 226, 0, 308 }, -{ 0x8, 226, 0, 318 }, -{ 0x28, 226, 0, 316 }, -{ 0x18, 226, 0, 317 }, -{ 0x4, 226, 0, 325 }, -{ 0x2, 226, 0, 326 }, -{ 0x1, 226, 0, 327 }, -{ 0x140, 228, 0, 285 }, -{ 0x540, 228, 0, 283 }, -{ 0x340, 228, 0, 284 }, -{ 0xc0, 228, 0, 294 }, -{ 0x2c0, 228, 0, 292 }, -{ 0x1c0, 228, 0, 293 }, -{ 0x20, 228, 0, 303 }, -{ 0xa0, 228, 0, 301 }, -{ 0x60, 228, 0, 302 }, -{ 0x10, 228, 0, 312 }, -{ 0x50, 228, 0, 310 }, -{ 0x30, 228, 0, 311 }, -{ 0x8, 228, 0, 321 }, -{ 0x28, 228, 0, 319 }, -{ 0x18, 228, 0, 320 }, -{ 0x4, 228, 0, 328 }, -{ 0x2, 228, 0, 329 }, -{ 0x1, 228, 0, 330 }, -{ 0x140, 230, 0, 288 }, -{ 0x540, 230, 0, 286 }, -{ 0x340, 230, 0, 287 }, -{ 0xc0, 230, 0, 297 }, -{ 0x2c0, 230, 0, 295 }, -{ 0x1c0, 230, 0, 296 }, -{ 0x20, 230, 0, 306 }, -{ 0xa0, 230, 0, 304 }, -{ 0x60, 230, 0, 305 }, -{ 0x10, 230, 0, 315 }, -{ 0x50, 230, 0, 313 }, -{ 0x30, 230, 0, 314 }, -{ 0x8, 230, 0, 324 }, -{ 0x28, 230, 0, 322 }, -{ 0x18, 230, 0, 323 }, -{ 0x4, 230, 0, 331 }, -{ 0x2, 230, 0, 332 }, -{ 0x1, 230, 0, 333 }, -{ 0x1, 356, 0, 335 }, -{ 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44, 0, 1866 }, +{ 0x1, 344, 0, 1867 }, +{ 0x2, 51, 0, 1868 }, +{ 0x1, 51, 0, 1869 }, +{ 0x1, 97, 0, 1870 }, +{ 0x51, 16, 0, 1872 }, +{ 0xd1, 16, 0, 1871 }, +{ 0x31, 16, 1, 1882 }, +{ 0x11, 17, 0, 1881 }, +{ 0x71, 16, 1, 1880 }, +{ 0x31, 17, 0, 1879 }, +{ 0x29, 16, 0, 1874 }, +{ 0x69, 16, 0, 1873 }, +{ 0x19, 16, 1, 1886 }, +{ 0x9, 17, 0, 1885 }, +{ 0x39, 16, 1, 1884 }, +{ 0x19, 17, 0, 1883 }, +{ 0x15, 16, 0, 1876 }, +{ 0x35, 16, 0, 1875 }, +{ 0xd, 16, 1, 1890 }, +{ 0x5, 17, 0, 1889 }, +{ 0x1d, 16, 1, 1888 }, +{ 0xd, 17, 0, 1887 }, +{ 0xb, 16, 0, 1878 }, +{ 0x1b, 16, 0, 1877 }, +{ 0x7, 16, 1, 1894 }, +{ 0x3, 17, 0, 1893 }, +{ 0xf, 16, 1, 1892 }, +{ 0x7, 17, 0, 1891 }, +{ 0xa20, 14, 0, 1896 }, +{ 0x1a20, 14, 0, 1895 }, +{ 0x620, 14, 1, 1906 }, +{ 0x220, 15, 0, 1905 }, +{ 0xe20, 14, 1, 1904 }, +{ 0x620, 15, 0, 1903 }, +{ 0x520, 14, 0, 1898 }, +{ 0xd20, 14, 0, 1897 }, +{ 0x320, 14, 1, 1910 }, +{ 0x120, 15, 0, 1909 }, +{ 0x720, 14, 1, 1908 }, +{ 0x320, 15, 0, 1907 }, +{ 0x2a0, 14, 0, 1900 }, +{ 0x6a0, 14, 0, 1899 }, +{ 0x1a0, 14, 1, 1914 }, +{ 0xa0, 15, 0, 1913 }, +{ 0x3a0, 14, 1, 1912 }, +{ 0x1a0, 15, 0, 1911 }, +{ 0x160, 14, 0, 1902 }, +{ 0x360, 14, 0, 1901 }, +{ 0xe0, 14, 1, 1918 }, +{ 0x60, 15, 0, 1917 }, +{ 0x1e0, 14, 1, 1916 }, +{ 0xe0, 15, 0, 1915 }, +{ 0x51, 14, 1, 1944 }, +{ 0x50, 14, 0, 1920 }, +{ 0xd1, 14, 1, 1943 }, +{ 0xd0, 14, 0, 1919 }, +{ 0x31, 14, 1, 1954 }, +{ 0x30, 14, 1, 1930 }, +{ 0x11, 15, 1, 1953 }, +{ 0x10, 15, 0, 1929 }, +{ 0x71, 14, 1, 1952 }, +{ 0x70, 14, 1, 1928 }, +{ 0x31, 15, 1, 1951 }, +{ 0x30, 15, 0, 1927 }, +{ 0x29, 14, 1, 1946 }, +{ 0x28, 14, 0, 1922 }, +{ 0x69, 14, 1, 1945 }, +{ 0x68, 14, 0, 1921 }, +{ 0x19, 14, 1, 1958 }, +{ 0x18, 14, 1, 1934 }, +{ 0x9, 15, 1, 1957 }, +{ 0x8, 15, 0, 1933 }, +{ 0x39, 14, 1, 1956 }, +{ 0x38, 14, 1, 1932 }, +{ 0x19, 15, 1, 1955 }, +{ 0x18, 15, 0, 1931 }, +{ 0x15, 14, 1, 1948 }, +{ 0x14, 14, 0, 1924 }, +{ 0x35, 14, 1, 1947 }, +{ 0x34, 14, 0, 1923 }, +{ 0xd, 14, 1, 1962 }, +{ 0xc, 14, 1, 1938 }, +{ 0x5, 15, 1, 1961 }, +{ 0x4, 15, 0, 1937 }, +{ 0x1d, 14, 1, 1960 }, +{ 0x1c, 14, 1, 1936 }, +{ 0xd, 15, 1, 1959 }, +{ 0xc, 15, 0, 1935 }, +{ 0xb, 14, 1, 1950 }, +{ 0xa, 14, 0, 1926 }, +{ 0x1b, 14, 1, 1949 }, +{ 0x1a, 14, 0, 1925 }, +{ 0x7, 14, 1, 1966 }, +{ 0x6, 14, 1, 1942 }, +{ 0x3, 15, 1, 1965 }, +{ 0x2, 15, 0, 1941 }, +{ 0xf, 14, 1, 1964 }, +{ 0xe, 14, 1, 1940 }, +{ 0x7, 15, 1, 1963 }, +{ 0x6, 15, 0, 1939 }, +{ 0x8, 13, 0, 1968 }, +{ 0x18, 13, 0, 1967 }, +{ 0x1, 13, 1, 1972 }, +{ 0x2, 13, 0, 1971 }, +{ 0x3, 13, 1, 1970 }, +{ 0x4, 13, 0, 1969 }, +{ 0x1, 84, 1, 2048 }, +{ 0x1, 85, 1, 2047 }, +{ 0x1, 86, 1, 2046 }, +{ 0x1, 87, 1, 2045 }, +{ 0x39, 40, 1, 22 }, +{ 0x19, 41, 0, 21 }, +{ 0x3, 84, 1, 2044 }, +{ 0x3, 85, 1, 2043 }, +{ 0x3, 86, 1, 2042 }, +{ 0x3, 87, 1, 2041 }, +{ 0x69, 40, 0, 11 }, +{ 0x14, 79, 1, 2038 }, +{ 0xa, 83, 1, 2037 }, +{ 0xd1, 40, 0, 9 }, +{ 0x34, 79, 1, 1974 }, +{ 0xe, 91, 0, 1973 }, +{ 0xc, 79, 1, 2118 }, +{ 0x6, 83, 0, 2117 }, +{ 0x2, 79, 1, 1980 }, +{ 0x2, 82, 0, 1979 }, +{ 0x12, 79, 1, 1978 }, +{ 0x6, 82, 0, 1977 }, +{ 0xa, 79, 1, 2040 }, +{ 0x5, 83, 1, 2039 }, +{ 0x71, 40, 1, 18 }, +{ 0x31, 41, 0, 17 }, +{ 0x1a, 79, 1, 1976 }, +{ 0x7, 91, 0, 1975 }, +{ 0x6, 79, 1, 2120 }, +{ 0x3, 83, 0, 2119 }, +{ 0x1, 79, 1, 2128 }, +{ 0x1, 80, 1, 2127 }, +{ 0x1, 81, 1, 2126 }, +{ 0x1, 82, 0, 2125 }, +{ 0x3, 79, 1, 2124 }, +{ 0x3, 80, 1, 2123 }, +{ 0x3, 81, 1, 2122 }, +{ 0x3, 82, 0, 2121 }, +{ 0x8, 60, 1, 2060 }, +{ 0x2, 63, 1, 2057 }, +{ 0x1, 65, 1, 2059 }, +{ 0x1, 66, 1, 2058 }, +{ 0xf, 40, 1, 30 }, +{ 0x7, 41, 0, 29 }, +{ 0x18, 60, 1, 2056 }, +{ 0x6, 63, 1, 2053 }, +{ 0x3, 65, 1, 2055 }, +{ 0x3, 66, 1, 2054 }, +{ 0x1b, 40, 0, 15 }, +{ 0x14, 60, 1, 2050 }, +{ 0xa, 64, 1, 2049 }, +{ 0x35, 40, 0, 13 }, +{ 0x34, 60, 1, 1982 }, +{ 0xe, 70, 0, 1981 }, +{ 0xc, 60, 1, 2130 }, +{ 0x6, 64, 0, 2129 }, +{ 0x2, 60, 1, 1988 }, +{ 0x4, 63, 0, 1987 }, +{ 0x12, 60, 1, 1986 }, +{ 0xc, 63, 0, 1985 }, +{ 0xa, 60, 1, 2052 }, +{ 0x5, 64, 1, 2051 }, +{ 0x1d, 40, 1, 26 }, +{ 0xd, 41, 0, 25 }, +{ 0x1a, 60, 1, 1984 }, +{ 0x7, 70, 0, 1983 }, +{ 0x6, 60, 1, 2132 }, +{ 0x3, 64, 0, 2131 }, +{ 0x1, 60, 1, 2140 }, +{ 0x1, 61, 1, 2139 }, +{ 0x1, 62, 1, 2138 }, +{ 0x1, 63, 0, 2137 }, +{ 0x3, 60, 1, 2136 }, +{ 0x3, 61, 1, 2135 }, +{ 0x3, 62, 1, 2134 }, +{ 0x3, 63, 0, 2133 }, +{ 0x28, 76, 1, 2064 }, +{ 0x44, 77, 1, 2061 }, +{ 0x88, 77, 1, 2063 }, +{ 0x28, 78, 0, 2062 }, +{ 0x68, 76, 1, 1992 }, +{ 0x188, 77, 1, 1991 }, +{ 0x38, 89, 1, 1990 }, +{ 0x38, 90, 0, 1989 }, +{ 0x18, 76, 1, 2144 }, +{ 0x14, 77, 1, 2141 }, +{ 0x28, 77, 1, 2143 }, +{ 0x18, 78, 0, 2142 }, +{ 0x14, 76, 1, 2068 }, +{ 0x24, 77, 1, 2067 }, +{ 0x48, 77, 1, 2065 }, +{ 0x14, 78, 0, 2066 }, +{ 0x34, 76, 1, 1996 }, +{ 0x64, 77, 1, 1995 }, +{ 0x1c, 89, 1, 1994 }, +{ 0x1c, 90, 0, 1993 }, +{ 0xc, 76, 1, 2148 }, +{ 0xc, 77, 1, 2147 }, +{ 0x18, 77, 1, 2145 }, +{ 0xc, 78, 0, 2146 }, +{ 0xa, 76, 1, 2072 }, +{ 0x11, 77, 1, 2069 }, +{ 0x22, 77, 1, 2071 }, +{ 0xa, 78, 0, 2070 }, +{ 0x1a, 76, 1, 2000 }, +{ 0x62, 77, 1, 1999 }, +{ 0xe, 89, 1, 1998 }, +{ 0xe, 90, 0, 1997 }, +{ 0x6, 76, 1, 2152 }, +{ 0x5, 77, 1, 2149 }, +{ 0xa, 77, 1, 2151 }, +{ 0x6, 78, 0, 2150 }, +{ 0x5, 76, 1, 2076 }, +{ 0x9, 77, 1, 2075 }, +{ 0x12, 77, 1, 2073 }, +{ 0x5, 78, 0, 2074 }, +{ 0xd, 76, 1, 2004 }, +{ 0x19, 77, 1, 2003 }, +{ 0x7, 89, 1, 2002 }, +{ 0x7, 90, 0, 2001 }, +{ 0x3, 76, 1, 2156 }, +{ 0x3, 77, 1, 2155 }, +{ 0x6, 77, 1, 2153 }, +{ 0x3, 78, 0, 2154 }, +{ 0x28, 57, 1, 2080 }, +{ 0x44, 58, 1, 2077 }, +{ 0x88, 58, 1, 2079 }, +{ 0x28, 59, 0, 2078 }, +{ 0x68, 57, 1, 2008 }, +{ 0x188, 58, 1, 2007 }, +{ 0x38, 68, 1, 2006 }, +{ 0x38, 69, 0, 2005 }, +{ 0x18, 57, 1, 2160 }, +{ 0x14, 58, 1, 2157 }, +{ 0x28, 58, 1, 2159 }, +{ 0x18, 59, 0, 2158 }, +{ 0x14, 57, 1, 2084 }, +{ 0x24, 58, 1, 2083 }, +{ 0x48, 58, 1, 2081 }, +{ 0x14, 59, 0, 2082 }, +{ 0x34, 57, 1, 2012 }, +{ 0x64, 58, 1, 2011 }, +{ 0x1c, 68, 1, 2010 }, +{ 0x1c, 69, 0, 2009 }, +{ 0xc, 57, 1, 2164 }, +{ 0xc, 58, 1, 2163 }, +{ 0x18, 58, 1, 2161 }, +{ 0xc, 59, 0, 2162 }, +{ 0xa, 57, 1, 2088 }, +{ 0x11, 58, 1, 2085 }, +{ 0x22, 58, 1, 2087 }, +{ 0xa, 59, 0, 2086 }, +{ 0x1a, 57, 1, 2016 }, +{ 0x62, 58, 1, 2015 }, +{ 0xe, 68, 1, 2014 }, +{ 0xe, 69, 0, 2013 }, +{ 0x6, 57, 1, 2168 }, +{ 0x5, 58, 1, 2165 }, +{ 0xa, 58, 1, 2167 }, +{ 0x6, 59, 0, 2166 }, +{ 0x5, 57, 1, 2092 }, +{ 0x9, 58, 1, 2091 }, +{ 0x12, 58, 1, 2089 }, +{ 0x5, 59, 0, 2090 }, +{ 0xd, 57, 1, 2020 }, +{ 0x19, 58, 1, 2019 }, +{ 0x7, 68, 1, 2018 }, +{ 0x7, 69, 0, 2017 }, +{ 0x3, 57, 1, 2172 }, +{ 0x3, 58, 1, 2171 }, +{ 0x6, 58, 1, 2169 }, +{ 0x3, 59, 0, 2170 }, +{ 0x8, 71, 1, 2104 }, +{ 0x2, 72, 1, 2103 }, +{ 0x2, 73, 1, 2102 }, +{ 0x2, 74, 0, 2101 }, +{ 0x18, 71, 1, 2100 }, +{ 0x6, 72, 1, 2099 }, +{ 0x6, 73, 1, 2098 }, +{ 0x6, 74, 0, 2097 }, +{ 0x14, 71, 1, 2094 }, +{ 0xa, 75, 0, 2093 }, +{ 0x34, 71, 1, 2022 }, +{ 0xe, 88, 0, 2021 }, +{ 0xc, 71, 1, 2174 }, +{ 0x6, 75, 0, 2173 }, +{ 0x2, 71, 1, 2028 }, +{ 0x4, 74, 0, 2027 }, +{ 0x12, 71, 1, 2026 }, +{ 0xc, 74, 0, 2025 }, +{ 0xa, 71, 1, 2096 }, +{ 0x5, 75, 0, 2095 }, +{ 0x1a, 71, 1, 2024 }, +{ 0x7, 88, 0, 2023 }, +{ 0x6, 71, 1, 2176 }, +{ 0x3, 75, 0, 2175 }, +{ 0x1, 71, 1, 2184 }, +{ 0x1, 72, 1, 2183 }, +{ 0x1, 73, 1, 2182 }, +{ 0x1, 74, 0, 2181 }, +{ 0x3, 71, 1, 2180 }, +{ 0x3, 72, 1, 2179 }, +{ 0x3, 73, 1, 2178 }, +{ 0x3, 74, 0, 2177 }, +{ 0x8, 52, 1, 2116 }, +{ 0x2, 53, 1, 2115 }, +{ 0x2, 54, 1, 2114 }, +{ 0x2, 55, 0, 2113 }, +{ 0x18, 52, 1, 2112 }, +{ 0x6, 53, 1, 2111 }, +{ 0x6, 54, 1, 2110 }, +{ 0x6, 55, 0, 2109 }, +{ 0x14, 52, 1, 2106 }, +{ 0xa, 56, 0, 2105 }, +{ 0x34, 52, 1, 2030 }, +{ 0xe, 67, 0, 2029 }, +{ 0xc, 52, 1, 2186 }, +{ 0x6, 56, 0, 2185 }, +{ 0x2, 52, 1, 2036 }, +{ 0x4, 55, 0, 2035 }, +{ 0x12, 52, 1, 2034 }, +{ 0xc, 55, 0, 2033 }, +{ 0xa, 52, 1, 2108 }, +{ 0x5, 56, 0, 2107 }, +{ 0x1a, 52, 1, 2032 }, +{ 0x7, 67, 0, 2031 }, +{ 0x6, 52, 1, 2188 }, +{ 0x3, 56, 0, 2187 }, +{ 0x1, 52, 1, 2196 }, +{ 0x1, 53, 1, 2195 }, +{ 0x1, 54, 1, 2194 }, +{ 0x1, 55, 0, 2193 }, +{ 0x3, 52, 1, 2192 }, +{ 0x3, 53, 1, 2191 }, +{ 0x3, 54, 1, 2190 }, +{ 0x3, 55, 0, 2189 }, +{ 0x1, 4, 0, 2197 }, +{ 0x1, 254, 0, 2198 }, +{ 0x1, 336, 0, 2199 }, +{ 0x1, 331, 0, 2200 }, +{ 0x2, 315, 0, 2201 }, +{ 0x1, 315, 0, 2204 }, +{ 0x2, 314, 0, 2202 }, +{ 0x1, 314, 0, 2205 }, +{ 0x2, 313, 0, 2203 }, +{ 0x1, 313, 0, 2206 }, +{ 0x1, 312, 0, 2207 }, +{ 0x1, 311, 0, 2208 }, +{ 0x2, 310, 0, 2209 }, +{ 0x1, 310, 0, 2211 }, +{ 0x2, 309, 0, 2210 }, +{ 0x1, 309, 0, 2212 }, +{ 0x1, 339, 0, 2219 }, +{ 0x8, 338, 0, 2213 }, +{ 0x4, 338, 0, 2215 }, +{ 0x2, 338, 0, 2217 }, +{ 0x1, 338, 0, 2220 }, +{ 0x8, 337, 0, 2214 }, +{ 0x4, 337, 0, 2216 }, +{ 0x2, 337, 0, 2218 }, +{ 0x1, 337, 0, 2221 }, +{ 0x1, 308, 0, 2228 }, +{ 0x8, 307, 0, 2222 }, +{ 0x4, 307, 0, 2224 }, +{ 0x2, 307, 0, 2226 }, +{ 0x1, 307, 0, 2229 }, +{ 0x8, 306, 0, 2223 }, +{ 0x4, 306, 0, 2225 }, +{ 0x2, 306, 1, 2227 }, +{ 0x4, 107, 0, 1271 }, +{ 0x1, 306, 0, 2230 }, +{ 0x1, 6, 0, 2231 }, +{ 0x1, 7, 0, 2232 }, +{ 0x1, 253, 0, 2233 }, +{ 0x1, 252, 0, 2234 }, +{ 0x1, 403, 0, 2235 }, +{ 0x1, 303, 0, 2236 }, +{ 0x1, 12, 0, 2237 }, +{ 0x1, 10, 0, 2238 }, +{ 0x1, 378, 0, 2239 }, +{ 0x1, 351, 0, 2240 }, +{ 0x1, 350, 0, 2241 }, +{ 0x1, 402, 0, 2242 }, +{ 0x1, 302, 0, 2243 }, +{ 0x1, 11, 0, 2244 }, +{ 0x1, 9, 0, 2245 }, +{ 0x1, 5, 0, 2246 }, +{ 0x1, 377, 0, 2247 }, +{ 0x1, 376, 0, 2248 }, +{ 0x1, 1, 0, 2249 }, +{ 0x1, 0, 0, 2250 }, }; diff --git a/contrib/binutils/opcodes/ia64-dis.c b/contrib/binutils/opcodes/ia64-dis.c index f9add91..4c63815 100644 --- a/contrib/binutils/opcodes/ia64-dis.c +++ b/contrib/binutils/opcodes/ia64-dis.c @@ -167,10 +167,10 @@ print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info) } else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64) { - /* 60-bit immedate for long branches. */ + /* 60-bit immediate for long branches. */ value = (((insn >> 13) & 0xfffff) | (((insn >> 36) & 1) << 59) - | (slot[1] << 20)) << 4; + | (((slot[1] >> 2) & 0x7fffffffffLL) << 20)) << 4; } else { diff --git a/contrib/binutils/opcodes/ia64-gen.c b/contrib/binutils/opcodes/ia64-gen.c index 6443c7c..a4e2cec 100644 --- a/contrib/binutils/opcodes/ia64-gen.c +++ b/contrib/binutils/opcodes/ia64-gen.c @@ -1,5 +1,5 @@ /* ia64-gen.c -- Generate a shrunk set of opcode tables - Copyright 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1999, 2000, 2001, 2002 Free Software Foundation, Inc. Written by Bob Manson, Cygnus Solutions, <manson@cygnus.com> This file is part of GDB, GAS, and the GNU binutils. @@ -30,16 +30,17 @@ required. The resource table is constructed based on some text dependency tables, - which are also easier to maintain than the final representation. - -*/ + which are also easier to maintain than the final representation. */ #include <stdio.h> +#include <stdarg.h> +#include <errno.h> #include "ansidecl.h" #include "libiberty.h" #include "safe-ctype.h" #include "sysdep.h" +#include "getopt.h" #include "ia64-opc.h" #include "ia64-opc-a.c" #include "ia64-opc-i.c" @@ -49,49 +50,54 @@ #include "ia64-opc-x.c" #include "ia64-opc-d.c" +#include <libintl.h> +#define _(String) gettext (String) + +const char * program_name = NULL; int debug = 0; #define tmalloc(X) (X *) xmalloc (sizeof (X)) /* The main opcode table entry. Each entry is a unique combination of name and flags (no two entries in the table compare as being equal - via opcodes_eq). */ + via opcodes_eq). */ struct main_entry { /* The base name of this opcode. The names of its completers are - appended to it to generate the full instruction name. */ + appended to it to generate the full instruction name. */ struct string_entry *name; /* The base opcode entry. Which one to use is a fairly arbitrary choice; - it uses the first one passed to add_opcode_entry. */ + it uses the first one passed to add_opcode_entry. */ struct ia64_opcode *opcode; - /* The list of completers that can be applied to this opcode. */ + /* The list of completers that can be applied to this opcode. */ struct completer_entry *completers; - /* Next entry in the chain. */ + /* Next entry in the chain. */ struct main_entry *next; - /* Index in the main table. */ + /* Index in the main table. */ int main_index; } *maintable, **ordered_table; + int otlen = 0; int ottotlen = 0; int opcode_count = 0; -/* The set of possible completers for an opcode. */ +/* The set of possible completers for an opcode. */ struct completer_entry { - /* This entry's index in the ia64_completer_table[] array. */ + /* This entry's index in the ia64_completer_table[] array. */ int num; - /* The name of the completer. */ + /* The name of the completer. */ struct string_entry *name; - /* This entry's parent. */ + /* This entry's parent. */ struct completer_entry *parent; /* Set if this is a terminal completer (occurs at the end of an - opcode). */ + opcode). */ int is_terminal; - /* An alternative completer. */ + /* An alternative completer. */ struct completer_entry *alternative; /* Additional completers that can be appended to this one. */ @@ -100,53 +106,53 @@ struct completer_entry /* Before compute_completer_bits () is invoked, this contains the actual instruction opcode for this combination of opcode and completers. Afterwards, it contains those bits that are different from its - parent opcode. */ + parent opcode. */ ia64_insn bits; /* Bits set to 1 correspond to those bits in this completer's opcode that are different from its parent completer's opcode (or from the base opcode if the entry is the root of the opcode's completer - list). This field is filled in by compute_completer_bits (). */ + list). This field is filled in by compute_completer_bits (). */ ia64_insn mask; - /* Index into the opcode dependency list, or -1 if none. */ + /* Index into the opcode dependency list, or -1 if none. */ int dependencies; /* Remember the order encountered in the opcode tables. */ int order; }; -/* One entry in the disassembler name table. */ +/* One entry in the disassembler name table. */ struct disent { - /* The index into the ia64_name_dis array for this entry. */ + /* The index into the ia64_name_dis array for this entry. */ int ournum; - /* The index into the main_table[] array. */ + /* The index into the main_table[] array. */ int insn; - /* The disassmbly priority of this entry. */ + /* The disassmbly priority of this entry. */ int priority; - /* The completer_index value for this entry. */ + /* The completer_index value for this entry. */ int completer_index; - /* How many other entries share this decode. */ + /* How many other entries share this decode. */ int nextcnt; - /* The next entry sharing the same decode. */ + /* The next entry sharing the same decode. */ struct disent *nexte; - /* The next entry in the name list. */ + /* The next entry in the name list. */ struct disent *next_ent; } *disinsntable = NULL; /* A state machine that will eventually be used to generate the - disassembler table. */ + disassembler table. */ struct bittree { struct disent *disent; - struct bittree *bits[3]; /* 0, 1, and X (don't care) */ + struct bittree *bits[3]; /* 0, 1, and X (don't care). */ int bits_to_skip; int skip_flag; } *bittree; @@ -154,62 +160,63 @@ struct bittree /* The string table contains all opcodes and completers sorted in alphabetical order. */ -/* One entry in the string table. */ +/* One entry in the string table. */ struct string_entry { - /* The index in the ia64_strings[] array for this entry. */ + /* The index in the ia64_strings[] array for this entry. */ int num; - /* And the string. */ + /* And the string. */ char *s; } **string_table = NULL; + int strtablen = 0; int strtabtotlen = 0; -/* resource dependency entries */ +/* Resource dependency entries. */ struct rdep { - char *name; /* resource name */ + char *name; /* Resource name. */ unsigned - mode:2, /* RAW, WAW, or WAR */ - semantics:3; /* dependency semantics */ - char *extra; /* additional semantics info */ + mode:2, /* RAW, WAW, or WAR. */ + semantics:3; /* Dependency semantics. */ + char *extra; /* Additional semantics info. */ int nchks; - int total_chks; /* total #of terminal insns */ - int *chks; /* insn classes which read (RAW), write - (WAW), or write (WAR) this rsrc */ - int *chknotes; /* dependency notes for each class */ + int total_chks; /* Total #of terminal insns. */ + int *chks; /* Insn classes which read (RAW), write + (WAW), or write (WAR) this rsrc. */ + int *chknotes; /* Dependency notes for each class. */ int nregs; - int total_regs; /* total #of terminal insns */ - int *regs; /* insn class which write (RAW), write2 - (WAW), or read (WAR) this rsrc */ - int *regnotes; /* dependency notes for each class */ + int total_regs; /* Total #of terminal insns. */ + int *regs; /* Insn class which write (RAW), write2 + (WAW), or read (WAR) this rsrc. */ + int *regnotes; /* Dependency notes for each class. */ - int waw_special; /* special WAW dependency note */ + int waw_special; /* Special WAW dependency note. */ } **rdeps = NULL; static int rdepslen = 0; static int rdepstotlen = 0; -/* array of all instruction classes */ +/* Array of all instruction classes. */ struct iclass { - char *name; /* instruction class name */ - int is_class; /* is a class, not a terminal */ + char *name; /* Instruction class name. */ + int is_class; /* Is a class, not a terminal. */ int nsubs; - int *subs; /* other classes within this class */ + int *subs; /* Other classes within this class. */ int nxsubs; - int xsubs[4]; /* exclusions */ - char *comment; /* optional comment */ - int note; /* optional note */ - int terminal_resolved; /* did we match this with anything? */ - int orphan; /* detect class orphans */ + int xsubs[4]; /* Exclusions. */ + char *comment; /* Optional comment. */ + int note; /* Optional note. */ + int terminal_resolved; /* Did we match this with anything? */ + int orphan; /* Detect class orphans. */ } **ics = NULL; static int iclen = 0; static int ictotlen = 0; -/* an opcode dependency (chk/reg pair of dependency lists) */ +/* An opcode dependency (chk/reg pair of dependency lists). */ struct opdep { int chk; /* index into dlists */ @@ -219,7 +226,7 @@ struct opdep static int opdeplen = 0; static int opdeptotlen = 0; -/* a generic list of dependencies w/notes encoded. these may be shared. */ +/* A generic list of dependencies w/notes encoded. These may be shared. */ struct deplist { int len; @@ -229,7 +236,81 @@ struct deplist static int dlistlen = 0; static int dlisttotlen = 0; -/* add NAME to the resource table, where TYPE is RAW or WAW */ + +static void fail (const char *, ...); +static void warn (const char *, ...); +static struct rdep * insert_resource (const char *, enum ia64_dependency_mode); +static int deplist_equals (struct deplist *, struct deplist *); +static short insert_deplist (int, unsigned short *); +static short insert_dependencies (int, unsigned short *, int, unsigned short *); +static void mark_used (struct iclass *, int); +static int fetch_insn_class (const char *, int); +static int sub_compare (const void *, const void *); +static void load_insn_classes (void); +static void parse_resource_users (const char *, int **, int *, int **); +static int parse_semantics (char *); +static void add_dep (const char *, const char *, const char *, int, int, char *, int); +static void load_depfile (const char *, enum ia64_dependency_mode); +static void load_dependencies (void); +static int irf_operand (int, const char *); +static int in_iclass_mov_x (struct ia64_opcode *, struct iclass *, const char *, const char *); +static int in_iclass (struct ia64_opcode *, struct iclass *, const char *, const char *, int *); +static int lookup_regindex (const char *, int); +static int lookup_specifier (const char *); +static void print_dependency_table (void); +static struct string_entry * insert_string (char *); +static void gen_dis_table (struct bittree *); +static void print_dis_table (void); +static void generate_disassembler (void); +static void print_string_table (void); +static int completer_entries_eq (struct completer_entry *, struct completer_entry *); +static struct completer_entry * insert_gclist (struct completer_entry *); +static int get_prefix_len (const char *); +static void compute_completer_bits (struct main_entry *, struct completer_entry *); +static void collapse_redundant_completers (void); +static int insert_opcode_dependencies (struct ia64_opcode *, struct completer_entry *); +static void insert_completer_entry (struct ia64_opcode *, struct main_entry *, int); +static void print_completer_entry (struct completer_entry *); +static void print_completer_table (void); +static int opcodes_eq (struct ia64_opcode *, struct ia64_opcode *); +static void add_opcode_entry (struct ia64_opcode *); +static void print_main_table (void); +static void shrink (struct ia64_opcode *); +static void print_version (void); +static void usage (FILE *, int); +static void finish_distable (void); +static void insert_bit_table_ent (struct bittree *, int, ia64_insn, ia64_insn, int, int, int); +static void add_dis_entry (struct bittree *, ia64_insn, ia64_insn, int, struct completer_entry *, int); +static void compact_distree (struct bittree *); +static struct bittree * make_bittree_entry (void); +static struct disent * add_dis_table_ent (struct disent *, int, int, int); + + +static void +fail (const char *message, ...) +{ + va_list args; + + va_start (args, message); + fprintf (stderr, _("%s: Error: "), program_name); + vfprintf (stderr, message, args); + va_end (args); + xexit (1); +} + +static void +warn (const char *message, ...) +{ + va_list args; + + va_start (args, message); + + fprintf (stderr, _("%s: Warning: "), program_name); + vfprintf (stderr, message, args); + va_end (args); +} + +/* Add NAME to the resource table, where TYPE is RAW or WAW. */ static struct rdep * insert_resource (const char *name, enum ia64_dependency_mode type) { @@ -248,7 +329,7 @@ insert_resource (const char *name, enum ia64_dependency_mode type) return rdeps[rdepslen++]; } -/* are the lists of dependency indexes equivalent? */ +/* Are the lists of dependency indexes equivalent? */ static int deplist_equals (struct deplist *d1, struct deplist *d2) { @@ -257,55 +338,48 @@ deplist_equals (struct deplist *d1, struct deplist *d2) if (d1->len != d2->len) return 0; - for (i=0;i < d1->len;i++) - { - if (d1->deps[i] != d2->deps[i]) - return 0; - } + for (i = 0; i < d1->len; i++) + if (d1->deps[i] != d2->deps[i]) + return 0; return 1; } -/* add the list of dependencies to the list of dependency lists */ +/* Add the list of dependencies to the list of dependency lists. */ static short -insert_deplist(int count, unsigned short *deps) +insert_deplist (int count, unsigned short *deps) { - /* sort the list, then see if an equivalent list exists already. - this results in a much smaller set of dependency lists - */ + /* Sort the list, then see if an equivalent list exists already. + this results in a much smaller set of dependency lists. */ struct deplist *list; char set[0x10000]; int i; - memset ((void *)set, 0, sizeof(set)); - for (i=0;i < count;i++) + memset ((void *)set, 0, sizeof (set)); + for (i = 0; i < count; i++) set[deps[i]] = 1; + count = 0; - for (i=0;i < (int)sizeof(set);i++) + for (i = 0; i < (int) sizeof (set); i++) if (set[i]) ++count; - list = tmalloc(struct deplist); + list = tmalloc (struct deplist); list->len = count; - list->deps = (unsigned short *)malloc (sizeof(unsigned short) * count); - for (i=0, count=0;i < (int)sizeof(set);i++) - { - if (set[i]) - { - list->deps[count++] = i; - } - } + list->deps = (unsigned short *) malloc (sizeof (unsigned short) * count); - /* does this list exist already? */ - for (i=0;i < dlistlen;i++) - { - if (deplist_equals (list, dlists[i])) - { - free (list->deps); - free (list); - return i; - } - } + for (i = 0, count = 0; i < (int) sizeof (set); i++) + if (set[i]) + list->deps[count++] = i; + + /* Does this list exist already? */ + for (i = 0; i < dlistlen; i++) + if (deplist_equals (list, dlists[i])) + { + free (list->deps); + free (list); + return i; + } if (dlistlen == dlisttotlen) { @@ -318,7 +392,7 @@ insert_deplist(int count, unsigned short *deps) return dlistlen++; } -/* add the given pair of dependency lists to the opcode dependency list */ +/* Add the given pair of dependency lists to the opcode dependency list. */ static short insert_dependencies (int nchks, unsigned short *chks, int nregs, unsigned short *regs) @@ -333,13 +407,12 @@ insert_dependencies (int nchks, unsigned short *chks, if (nchks > 0) chkind = insert_deplist (nchks, chks); - for (i=0;i < opdeplen;i++) - { - if (opdeps[i]->chk == chkind - && opdeps[i]->reg == regind) - return i; - } - pair = tmalloc(struct opdep); + for (i = 0; i < opdeplen; i++) + if (opdeps[i]->chk == chkind + && opdeps[i]->reg == regind) + return i; + + pair = tmalloc (struct opdep); pair->chk = chkind; pair->reg = regind; @@ -363,20 +436,17 @@ mark_used (struct iclass *ic, int clear_terminals) if (clear_terminals) ic->terminal_resolved = 1; - for (i=0;i < ic->nsubs;i++) - { - mark_used (ics[ic->subs[i]], clear_terminals); - } - for (i=0;i < ic->nxsubs;i++) - { - mark_used (ics[ic->xsubs[i]], clear_terminals); - } + for (i = 0; i < ic->nsubs; i++) + mark_used (ics[ic->subs[i]], clear_terminals); + + for (i = 0; i < ic->nxsubs; i++) + mark_used (ics[ic->xsubs[i]], clear_terminals); } -/* look up an instruction class; if CREATE make a new one if none found; - returns the index into the insn class array */ +/* Look up an instruction class; if CREATE make a new one if none found; + returns the index into the insn class array. */ static int -fetch_insn_class(const char *full_name, int create) +fetch_insn_class (const char *full_name, int create) { char *name; char *notestr; @@ -414,14 +484,14 @@ fetch_insn_class(const char *full_name, int create) if (notestr) { char *nextnotestr; + note = atoi (notestr + 1); if ((nextnotestr = strchr (notestr + 1, '+')) != NULL) { if (strcmp (notestr, "+1+13") == 0) note = 13; else if (!xsect || nextnotestr < xsect) - fprintf (stderr, "Warning: multiple note %s not handled\n", - notestr); + warn (_("multiple note %s not handled\n"), notestr); } } @@ -436,8 +506,8 @@ fetch_insn_class(const char *full_name, int create) *comment = 0; } - for (i=0;i < iclen;i++) - if (strcmp(name, ics[i]->name) == 0 + for (i = 0; i < iclen; i++) + if (strcmp (name, ics[i]->name) == 0 && ((comment == NULL && ics[i]->comment == NULL) || (comment != NULL && ics[i]->comment != NULL && strncmp (ics[i]->comment, comment, @@ -448,40 +518,44 @@ fetch_insn_class(const char *full_name, int create) if (!create) return -1; - /* doesn't exist, so make a new one */ + /* Doesn't exist, so make a new one. */ if (iclen == ictotlen) { ictotlen += 20; ics = (struct iclass **) - xrealloc(ics, (ictotlen)*sizeof(struct iclass *)); + xrealloc (ics, (ictotlen) * sizeof (struct iclass *)); } + ind = iclen++; - ics[ind] = tmalloc(struct iclass); - memset((void *)ics[ind], 0, sizeof(struct iclass)); - ics[ind]->name = xstrdup(name); + ics[ind] = tmalloc (struct iclass); + memset ((void *)ics[ind], 0, sizeof (struct iclass)); + ics[ind]->name = xstrdup (name); ics[ind]->is_class = is_class; ics[ind]->orphan = 1; if (comment) { ics[ind]->comment = xstrdup (comment + 1); - ics[ind]->comment[strlen(ics[ind]->comment)-1] = 0; + ics[ind]->comment[strlen (ics[ind]->comment)-1] = 0; } + if (notestr) ics[ind]->note = note; - /* if it's a composite class, there's a comment or note, look for an - existing class or terminal with the same name. */ + /* If it's a composite class, there's a comment or note, look for an + existing class or terminal with the same name. */ if ((xsect || comment || notestr) && is_class) { /* First, populate with the class we're based on. */ char *subname = name; + if (xsect) *xsect = 0; else if (comment) *comment = 0; else if (notestr) *notestr = 0; + ics[ind]->nsubs = 1; ics[ind]->subs = tmalloc(int); ics[ind]->subs[0] = fetch_insn_class (subname, 1);; @@ -490,6 +564,7 @@ fetch_insn_class(const char *full_name, int create) while (xsect) { char *subname = xsect + 1; + xsect = strchr (subname, '\\'); if (xsect) *xsect = 0; @@ -501,8 +576,8 @@ fetch_insn_class(const char *full_name, int create) return ind; } -/* for sorting a class's sub-class list only; make sure classes appear before - terminals */ +/* For sorting a class's sub-class list only; make sure classes appear before + terminals. */ static int sub_compare (const void *e1, const void *e2) { @@ -521,41 +596,39 @@ sub_compare (const void *e1, const void *e2) } static void -load_insn_classes() +load_insn_classes (void) { - FILE *fp = fopen("ia64-ic.tbl", "r"); + FILE *fp = fopen ("ia64-ic.tbl", "r"); char buf[2048]; - if (fp == NULL){ - fprintf (stderr, "Can't find ia64-ic.tbl for reading\n"); - exit(1); - } + if (fp == NULL) + fail (_("can't find ia64-ic.tbl for reading\n")); - /* discard first line */ + /* Discard first line. */ fgets (buf, sizeof(buf), fp); - while (!feof(fp)) + while (!feof (fp)) { int iclass; char *name; char *tmp; - if (fgets (buf, sizeof(buf), fp) == NULL) + if (fgets (buf, sizeof (buf), fp) == NULL) break; - while (ISSPACE (buf[strlen(buf)-1])) - buf[strlen(buf)-1] = '\0'; + while (ISSPACE (buf[strlen (buf) - 1])) + buf[strlen (buf) - 1] = '\0'; name = tmp = buf; while (*tmp != ';') { ++tmp; - if (tmp == buf + sizeof(buf)) + if (tmp == buf + sizeof (buf)) abort (); } *tmp++ = '\0'; - iclass = fetch_insn_class(name, 1); + iclass = fetch_insn_class (name, 1); ics[iclass]->is_class = 1; if (strcmp (name, "none") == 0) @@ -565,7 +638,7 @@ load_insn_classes() continue; } - /* for this class, record all sub-classes */ + /* For this class, record all sub-classes. */ while (*tmp) { char *subname; @@ -574,44 +647,43 @@ load_insn_classes() while (*tmp && ISSPACE (*tmp)) { ++tmp; - if (tmp == buf + sizeof(buf)) - abort(); + if (tmp == buf + sizeof (buf)) + abort (); } subname = tmp; while (*tmp && *tmp != ',') { ++tmp; - if (tmp == buf + sizeof(buf)) - abort(); + if (tmp == buf + sizeof (buf)) + abort (); } if (*tmp == ',') *tmp++ = '\0'; ics[iclass]->subs = (int *) - xrealloc((void *)ics[iclass]->subs, - (ics[iclass]->nsubs+1)*sizeof(int)); + xrealloc ((void *)ics[iclass]->subs, + (ics[iclass]->nsubs + 1) * sizeof (int)); - sub = fetch_insn_class(subname, 1); + sub = fetch_insn_class (subname, 1); ics[iclass]->subs = (int *) - xrealloc(ics[iclass]->subs, (ics[iclass]->nsubs+1)*sizeof(int)); + xrealloc (ics[iclass]->subs, (ics[iclass]->nsubs + 1) * sizeof (int)); ics[iclass]->subs[ics[iclass]->nsubs++] = sub; } - /* make sure classes come before terminals */ + + /* Make sure classes come before terminals. */ qsort ((void *)ics[iclass]->subs, ics[iclass]->nsubs, sizeof(int), sub_compare); } - fclose(fp); + fclose (fp); if (debug) - { - printf ("%d classes\n", iclen); - } + printf ("%d classes\n", iclen); } -/* extract the insn classes from the given line */ +/* Extract the insn classes from the given line. */ static void -parse_resource_users(ref, usersp, nusersp, notesp) - char *ref; +parse_resource_users (ref, usersp, nusersp, notesp) + const char *ref; int **usersp; int *nusersp; int **notesp; @@ -641,53 +713,49 @@ parse_resource_users(ref, usersp, nusersp, notesp) c = *tmp; *tmp++ = '\0'; - xsect = strchr(name, '\\'); - if ((notestr = strstr(name, "+")) != NULL) + xsect = strchr (name, '\\'); + if ((notestr = strstr (name, "+")) != NULL) { char *nextnotestr; + note = atoi (notestr + 1); if ((nextnotestr = strchr (notestr + 1, '+')) != NULL) { - /* note 13 always implies note 1 */ + /* Note 13 always implies note 1. */ if (strcmp (notestr, "+1+13") == 0) note = 13; else if (!xsect || nextnotestr < xsect) - fprintf (stderr, "Warning: multiple note %s not handled\n", - notestr); + warn (_("multiple note %s not handled\n"), notestr); } if (!xsect) *notestr = '\0'; } else note = 0; - + /* All classes are created when the insn class table is parsed; Individual instructions might not appear until the dependency tables are read. Only create new classes if it's *not* an insn class, or if it's a composite class (which wouldn't necessarily be in the IC - table). - */ - if (strncmp(name, "IC:", 3) != 0 || xsect != NULL) + table). */ + if (strncmp (name, "IC:", 3) != 0 || xsect != NULL) create = 1; - iclass = fetch_insn_class(name, create); + iclass = fetch_insn_class (name, create); if (iclass != -1) { users = (int *) - xrealloc ((void *)users,(count+1)*sizeof(int)); + xrealloc ((void *) users,(count + 1) * sizeof (int)); notes = (int *) - xrealloc ((void *)notes,(count+1)*sizeof(int)); + xrealloc ((void *) notes,(count + 1) * sizeof (int)); notes[count] = note; users[count++] = iclass; mark_used (ics[iclass], 0); } - else - { - if (debug) - printf("Class %s not found\n", name); - } + else if (debug) + printf("Class %s not found\n", name); } - /* update the return values */ + /* Update the return values. */ *usersp = users; *nusersp = count; *notesp = notes; @@ -723,10 +791,10 @@ add_dep (const char *name, const char *chk, const char *reg, struct rdep *rs; rs = insert_resource (name, mode); - parse_resource_users (chk, &rs->chks, &rs->nchks, - &rs->chknotes); - parse_resource_users (reg, &rs->regs, &rs->nregs, - &rs->regnotes); + + parse_resource_users (chk, &rs->chks, &rs->nchks, &rs->chknotes); + parse_resource_users (reg, &rs->regs, &rs->nregs, &rs->regnotes); + rs->semantics = semantics; rs->extra = extra; rs->waw_special = flag; @@ -735,16 +803,14 @@ add_dep (const char *name, const char *chk, const char *reg, static void load_depfile (const char *filename, enum ia64_dependency_mode mode) { - FILE *fp = fopen(filename, "r"); + FILE *fp = fopen (filename, "r"); char buf[1024]; - if (fp == NULL){ - fprintf (stderr, "Can't find %s for reading\n", filename); - exit(1); - } + if (fp == NULL) + fail (_("can't find %s for reading\n"), filename); - fgets(buf, sizeof(buf), fp); - while (!feof(fp)) + fgets (buf, sizeof(buf), fp); + while (!feof (fp)) { char *name, *tmp; int semantics; @@ -754,8 +820,8 @@ load_depfile (const char *filename, enum ia64_dependency_mode mode) if (fgets (buf, sizeof(buf), fp) == NULL) break; - while (ISSPACE (buf[strlen(buf)-1])) - buf[strlen(buf)-1] = '\0'; + while (ISSPACE (buf[strlen (buf) - 1])) + buf[strlen (buf) - 1] = '\0'; name = tmp = buf; while (*tmp != ';') @@ -783,7 +849,7 @@ load_depfile (const char *filename, enum ia64_dependency_mode mode) /* For WAW entries, if the chks and regs differ, we need to enter the entries in both positions so that the tables will be parsed properly, - without a lot of extra work */ + without a lot of extra work. */ if (mode == IA64_DV_WAW && strcmp (regp, chkp) != 0) { add_dep (name, chkp, regp, semantics, mode, extra, 0); @@ -794,21 +860,21 @@ load_depfile (const char *filename, enum ia64_dependency_mode mode) add_dep (name, chkp, regp, semantics, mode, extra, 0); } } - fclose(fp); + fclose (fp); } static void -load_dependencies() +load_dependencies (void) { load_depfile ("ia64-raw.tbl", IA64_DV_RAW); load_depfile ("ia64-waw.tbl", IA64_DV_WAW); load_depfile ("ia64-war.tbl", IA64_DV_WAR); if (debug) - printf ("%d RAW/WAW/WAR dependencies\n", rdepslen); + printf ("%d RAW/WAW/WAR dependencies\n", rdepslen); } -/* is the given operand an indirect register file operand? */ +/* Is the given operand an indirect register file operand? */ static int irf_operand (int op, const char *field) { @@ -832,8 +898,8 @@ irf_operand (int op, const char *field) } } -/* handle mov_ar, mov_br, mov_cr, mov_indirect, mov_ip, mov_pr, mov_psr, and - mov_um insn classes */ +/* Handle mov_ar, mov_br, mov_cr, mov_indirect, mov_ip, mov_pr, mov_psr, and + mov_um insn classes. */ static int in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic, const char *format, const char *field) @@ -947,11 +1013,10 @@ in_iclass_mov_x (struct ia64_opcode *idesc, struct iclass *ic, return 0; } - -/* is the given opcode in the given insn class? */ +/* Is the given opcode in the given insn class? */ static int -in_iclass(struct ia64_opcode *idesc, struct iclass *ic, - const char *format, const char *field, int *notep) +in_iclass (struct ia64_opcode *idesc, struct iclass *ic, + const char *format, const char *field, int *notep) { int i; int resolved = 0; @@ -960,15 +1025,14 @@ in_iclass(struct ia64_opcode *idesc, struct iclass *ic, { if (!strncmp (ic->comment, "Format", 6)) { - /* assume that the first format seen is the most restrictive, and - only keep a later one if it looks like it's more restrictive. */ + /* Assume that the first format seen is the most restrictive, and + only keep a later one if it looks like it's more restrictive. */ if (format) { if (strlen (ic->comment) < strlen (format)) { - fprintf (stderr, "Warning: most recent format '%s'\n" - "appears more restrictive than '%s'\n", - ic->comment, format); + warn (_("most recent format '%s'\nappears more restrictive than '%s'\n"), + ic->comment, format); format = ic->comment; } } @@ -978,15 +1042,15 @@ in_iclass(struct ia64_opcode *idesc, struct iclass *ic, else if (!strncmp (ic->comment, "Field", 5)) { if (field) - fprintf (stderr, "Overlapping field %s->%s\n", - ic->comment, field); + warn (_("overlapping field %s->%s\n"), + ic->comment, field); field = ic->comment; } } - /* an insn class matches anything that is the same followed by completers, + /* An insn class matches anything that is the same followed by completers, except when the absence and presence of completers constitutes different - instructions */ + instructions. */ if (ic->nsubs == 0 && ic->nxsubs == 0) { int is_mov = strncmp (idesc->name, "mov", 3) == 0; @@ -997,26 +1061,26 @@ in_iclass(struct ia64_opcode *idesc, struct iclass *ic, && (idesc->name[len] == '\0' || idesc->name[len] == '.')); - /* all break and nop variations must match exactly */ + /* All break, nop, and hint variations must match exactly. */ if (resolved && (strcmp (ic->name, "break") == 0 - || strcmp (ic->name, "nop") == 0)) + || strcmp (ic->name, "nop") == 0 + || strcmp (ic->name, "hint") == 0)) resolved = strcmp (ic->name, idesc->name) == 0; - /* assume restrictions in the FORMAT/FIELD negate resolution, - unless specifically allowed by clauses in this block */ + /* Assume restrictions in the FORMAT/FIELD negate resolution, + unless specifically allowed by clauses in this block. */ if (resolved && field) { - /* check Field(sf)==sN against opcode sN */ + /* Check Field(sf)==sN against opcode sN. */ if (strstr(field, "(sf)==") != NULL) { char *sf; + if ((sf = strstr (idesc->name, ".s")) != 0) - { - resolved = strcmp (sf + 1, strstr (field, "==") + 2) == 0; - } + resolved = strcmp (sf + 1, strstr (field, "==") + 2) == 0; } - /* check Field(lftype)==XXX */ + /* Check Field(lftype)==XXX. */ else if (strstr (field, "(lftype)") != NULL) { if (strstr (idesc->name, "fault") != NULL) @@ -1024,7 +1088,7 @@ in_iclass(struct ia64_opcode *idesc, struct iclass *ic, else resolved = strstr (field, "fault") == NULL; } - /* handle Field(ctype)==XXX */ + /* Handle Field(ctype)==XXX. */ else if (strstr (field, "(ctype)") != NULL) { if (strstr (idesc->name, "or.andcm")) @@ -1045,6 +1109,7 @@ in_iclass(struct ia64_opcode *idesc, struct iclass *ic, resolved = strcmp (field, "Field(ctype)==") == 0; } } + if (resolved && format) { if (strncmp (idesc->name, "dep", 3) == 0 @@ -1075,8 +1140,8 @@ in_iclass(struct ia64_opcode *idesc, struct iclass *ic, resolved = 0; } - /* misc brl variations ('.cond' is optional); - plain brl matches brl.cond */ + /* Misc brl variations ('.cond' is optional); + plain brl matches brl.cond. */ if (!resolved && (strcmp (idesc->name, "brl") == 0 || strncmp (idesc->name, "brl.", 4) == 0) @@ -1085,7 +1150,7 @@ in_iclass(struct ia64_opcode *idesc, struct iclass *ic, resolved = 1; } - /* misc br variations ('.cond' is optional) */ + /* Misc br variations ('.cond' is optional). */ if (!resolved && (strcmp (idesc->name, "br") == 0 || strncmp (idesc->name, "br.", 3) == 0) @@ -1100,81 +1165,77 @@ in_iclass(struct ia64_opcode *idesc, struct iclass *ic, resolved = 1; } - /* probe variations */ + /* probe variations. */ if (!resolved && strncmp (idesc->name, "probe", 5) == 0) { resolved = strcmp (ic->name, "probe") == 0 && !((strstr (idesc->name, "fault") != NULL) ^ (format && strstr (format, "M40") != NULL)); } - /* mov variations */ + + /* mov variations. */ if (!resolved && is_mov) { if (plain_mov) { - /* mov alias for fmerge */ + /* mov alias for fmerge. */ if (strcmp (ic->name, "fmerge") == 0) { resolved = idesc->operands[0] == IA64_OPND_F1 && idesc->operands[1] == IA64_OPND_F3; } - /* mov alias for adds (r3 or imm14) */ + /* mov alias for adds (r3 or imm14). */ else if (strcmp (ic->name, "adds") == 0) { resolved = (idesc->operands[0] == IA64_OPND_R1 && (idesc->operands[1] == IA64_OPND_R3 || (idesc->operands[1] == IA64_OPND_IMM14))); } - /* mov alias for addl */ + /* mov alias for addl. */ else if (strcmp (ic->name, "addl") == 0) { resolved = idesc->operands[0] == IA64_OPND_R1 && idesc->operands[1] == IA64_OPND_IMM22; } } - /* some variants of mov and mov.[im] */ + + /* Some variants of mov and mov.[im]. */ if (!resolved && strncmp (ic->name, "mov_", 4) == 0) - { - resolved = in_iclass_mov_x (idesc, ic, format, field); - } + resolved = in_iclass_mov_x (idesc, ic, format, field); } - /* keep track of this so we can flag any insn classes which aren't - mapped onto at least one real insn */ + /* Keep track of this so we can flag any insn classes which aren't + mapped onto at least one real insn. */ if (resolved) - { - ic->terminal_resolved = 1; - } + ic->terminal_resolved = 1; } - else for (i=0;i < ic->nsubs;i++) + else for (i = 0; i < ic->nsubs; i++) { - if (in_iclass(idesc, ics[ic->subs[i]], format, field, notep)) + if (in_iclass (idesc, ics[ic->subs[i]], format, field, notep)) { int j; - for (j=0;j < ic->nxsubs;j++) - { - if (in_iclass(idesc, ics[ic->xsubs[j]], NULL, NULL, NULL)) - return 0; - } + + for (j = 0; j < ic->nxsubs; j++) + if (in_iclass (idesc, ics[ic->xsubs[j]], NULL, NULL, NULL)) + return 0; + if (debug > 1) - printf ("%s is in IC %s\n", - idesc->name, ic->name); + printf ("%s is in IC %s\n", idesc->name, ic->name); + resolved = 1; break; } } - /* If it's in this IC, add the IC note (if any) to the insn */ + /* If it's in this IC, add the IC note (if any) to the insn. */ if (resolved) { if (ic->note && notep) { if (*notep && *notep != ic->note) - { - fprintf (stderr, "Warning: overwriting note %d with note %d" - "(IC:%s)\n", - *notep, ic->note, ic->name); - } + warn (_("overwriting note %d with note %d (IC:%s)\n"), + *notep, ic->note, ic->name); + *notep = ic->note; } } @@ -1197,6 +1258,22 @@ lookup_regindex (const char *name, int specifier) return 18; else if (strstr (name, "[RNAT]")) return 19; + else if (strstr (name, "[FCR]")) + return 21; + else if (strstr (name, "[EFLAG]")) + return 24; + else if (strstr (name, "[CSD]")) + return 25; + else if (strstr (name, "[SSD]")) + return 26; + else if (strstr (name, "[CFLG]")) + return 27; + else if (strstr (name, "[FSR]")) + return 28; + else if (strstr (name, "[FIR]")) + return 29; + else if (strstr (name, "[FDR]")) + return 30; else if (strstr (name, "[CCV]")) return 32; else if (strstr (name, "[ITC]")) @@ -1355,8 +1432,8 @@ lookup_specifier (const char *name) if (strstr (name, "PR%, % in 16 ") != NULL) return IA64_RS_PRr; - fprintf (stderr, "Warning! Don't know how to specify %% dependency %s\n", - name); + warn (_("don't know how to specify %% dependency %s\n"), + name); } else if (strchr (name, '#')) { @@ -1377,8 +1454,8 @@ lookup_specifier (const char *name) if (strstr (name, "RR#") != NULL) return IA64_RS_RR; - fprintf (stderr, "Warning! Don't know how to specify # dependency %s\n", - name); + warn (_("Don't know how to specify # dependency %s\n"), + name); } else if (strncmp (name, "AR[FPSR]", 8) == 0) return IA64_RS_AR_FPSR; @@ -1402,7 +1479,7 @@ lookup_specifier (const char *name) return IA64_RS_ANY; } -void +static void print_dependency_table () { int i, j; @@ -1415,58 +1492,59 @@ print_dependency_table () { if (!ics[i]->nsubs) { - fprintf (stderr, "Warning: IC:%s", ics[i]->name); if (ics[i]->comment) - fprintf (stderr, "[%s]", ics[i]->comment); - fprintf (stderr, " has no terminals or sub-classes\n"); + warn (_("IC:%s [%s] has no terminals or sub-classes\n"), + ics[i]->name, ics[i]->comment); + else + warn (_("IC:%s has no terminals or sub-classes\n"), + ics[i]->name); } } else { if (!ics[i]->terminal_resolved && !ics[i]->orphan) { - fprintf(stderr, "Warning: no insns mapped directly to " - "terminal IC %s", ics[i]->name); if (ics[i]->comment) - fprintf(stderr, "[%s] ", ics[i]->comment); - fprintf(stderr, "\n"); + warn (_("no insns mapped directly to terminal IC %s [%s]"), + ics[i]->name, ics[i]->comment); + else + warn (_("no insns mapped directly to terminal IC %s\n"), + ics[i]->name); } } } - for (i=0;i < iclen;i++) + for (i = 0; i < iclen; i++) { if (ics[i]->orphan) { mark_used (ics[i], 1); - fprintf (stderr, "Warning: class %s is defined but not used\n", - ics[i]->name); + warn (_("class %s is defined but not used\n"), + ics[i]->name); } } - if (debug > 1) for (i=0;i < rdepslen;i++) - { - static const char *mode_str[] = { "RAW", "WAW", "WAR" }; - if (rdeps[i]->total_chks == 0) - { - fprintf (stderr, "Warning: rsrc %s (%s) has no chks%s\n", - rdeps[i]->name, mode_str[rdeps[i]->mode], - rdeps[i]->total_regs ? "" : " or regs"); - } - else if (rdeps[i]->total_regs == 0) - { - fprintf (stderr, "Warning: rsrc %s (%s) has no regs\n", - rdeps[i]->name, mode_str[rdeps[i]->mode]); - } - } + if (debug > 1) + for (i = 0; i < rdepslen; i++) + { + static const char *mode_str[] = { "RAW", "WAW", "WAR" }; + + if (rdeps[i]->total_chks == 0) + warn (_("Warning: rsrc %s (%s) has no chks%s\n"), + rdeps[i]->name, mode_str[rdeps[i]->mode], + rdeps[i]->total_regs ? "" : " or regs"); + else if (rdeps[i]->total_regs == 0) + warn (_("rsrc %s (%s) has no regs\n"), + rdeps[i]->name, mode_str[rdeps[i]->mode]); + } } - /* the dependencies themselves */ + /* The dependencies themselves. */ printf ("static const struct ia64_dependency\ndependencies[] = {\n"); - for (i=0;i < rdepslen;i++) + for (i = 0; i < rdepslen; i++) { /* '%', '#', AR[], CR[], or PSR. indicates we need to specify the actual - resource used */ + resource used. */ int specifier = lookup_specifier (rdeps[i]->name); int regindex = lookup_regindex (rdeps[i]->name, specifier); @@ -1481,7 +1559,7 @@ print_dependency_table () } printf ("};\n\n"); - /* and dependency lists */ + /* And dependency lists. */ for (i=0;i < dlistlen;i++) { int len = 2; @@ -1498,11 +1576,11 @@ print_dependency_table () printf ("\n};\n\n"); } - /* and opcode dependency list */ + /* And opcode dependency list. */ printf ("#define NELS(X) (sizeof(X)/sizeof(X[0]))\n"); printf ("static const struct ia64_opcode_dependency\n"); printf ("op_dependencies[] = {\n"); - for (i=0;i < opdeplen;i++) + for (i = 0; i < opdeplen; i++) { printf (" { "); if (opdeps[i]->chk == -1) @@ -1519,11 +1597,9 @@ print_dependency_table () } -/* Add STR to the string table. */ - +/* Add STR to the string table. */ static struct string_entry * -insert_string (str) - char *str; +insert_string (char *str) { int start = 0, end = strtablen; int i, x; @@ -1546,13 +1622,9 @@ insert_string (str) } if (strcmp (str, string_table[strtablen - 1]->s) > 0) - { - i = end; - } + i = end; else if (strcmp (str, string_table[0]->s) < 0) - { - i = 0; - } + i = 0; else { while (1) @@ -1561,52 +1633,43 @@ insert_string (str) i = (start + end) / 2; c = strcmp (str, string_table[i]->s); + if (c < 0) - { - end = i - 1; - } + end = i - 1; else if (c == 0) - { - return string_table[i]; - } + return string_table[i]; else - { - start = i + 1; - } + start = i + 1; + if (start > end) - { - break; - } + break; } } + for (; i > 0 && i < strtablen; i--) - { - if (strcmp (str, string_table[i - 1]->s) > 0) - { - break; - } - } + if (strcmp (str, string_table[i - 1]->s) > 0) + break; + for (; i < strtablen; i++) - { - if (strcmp (str, string_table[i]->s) < 0) - { - break; - } - } + if (strcmp (str, string_table[i]->s) < 0) + break; + for (x = strtablen - 1; x >= i; x--) { string_table[x + 1] = string_table[x]; string_table[x + 1]->num = x + 1; } + string_table[i] = tmalloc (struct string_entry); string_table[i]->s = xstrdup (str); string_table[i]->num = i; strtablen++; + return string_table[i]; } -struct bittree * -make_bittree_entry () +static struct bittree * +make_bittree_entry (void) { struct bittree *res = tmalloc (struct bittree); @@ -1618,8 +1681,9 @@ make_bittree_entry () res->bits_to_skip = 0; return res; } + -struct disent * +static struct disent * add_dis_table_ent (which, insn, order, completer_index) struct disent *which; int insn; @@ -1635,9 +1699,8 @@ add_dis_table_ent (which, insn, order, completer_index) ent->nextcnt++; while (ent->nexte != NULL) - { - ent = ent->nexte; - } + ent = ent->nexte; + ent = (ent->nexte = tmalloc (struct disent)); } else @@ -1661,7 +1724,7 @@ add_dis_table_ent (which, insn, order, completer_index) return which; } -void +static void finish_distable () { struct disent *ent = disinsntable; @@ -1675,7 +1738,7 @@ finish_distable () } } -void +static void insert_bit_table_ent (curr_ent, bit, opcode, mask, opcodenum, order, completer_index) struct bittree *curr_ent; @@ -1702,13 +1765,10 @@ insert_bit_table_ent (curr_ent, bit, opcode, mask, m = ((ia64_insn) 1) << bit; if (mask & m) - { - b = (opcode & m) ? 1 : 0; - } + b = (opcode & m) ? 1 : 0; else - { - b = 2; - } + b = 2; + next = curr_ent->bits[b]; if (next == NULL) { @@ -1719,7 +1779,7 @@ insert_bit_table_ent (curr_ent, bit, opcode, mask, completer_index); } -void +static void add_dis_entry (first, opcode, mask, opcodenum, ent, completer_index) struct bittree *first; ia64_insn opcode; @@ -1729,15 +1789,14 @@ add_dis_entry (first, opcode, mask, opcodenum, ent, completer_index) int completer_index; { if (completer_index & (1 << 20)) - { - abort (); - } + abort (); while (ent != NULL) { ia64_insn newopcode = (opcode & (~ ent->mask)) | ent->bits; add_dis_entry (first, newopcode, mask, opcodenum, ent->addl_entries, (completer_index << 1) | 1); + if (ent->is_terminal) { insert_bit_table_ent (bittree, 40, newopcode, mask, @@ -1749,8 +1808,8 @@ add_dis_entry (first, opcode, mask, opcodenum, ent, completer_index) } } -/* This optimization pass combines multiple "don't care" nodes. */ -void +/* This optimization pass combines multiple "don't care" nodes. */ +static void compact_distree (ent) struct bittree *ent; { @@ -1790,10 +1849,9 @@ compact_distree (ent) for (x = 0; x < 3; x++) { struct bittree *i = ent->bits[x]; + if (i != NULL) - { - compact_distree (i); - } + compact_distree (i); } } @@ -1803,7 +1861,7 @@ static int tot_insn_list_len = 0; /* Generate the disassembler state machine corresponding to the tree in ENT. */ -void +static void gen_dis_table (ent) struct bittree *ent; { @@ -1813,47 +1871,37 @@ gen_dis_table (ent) int totbits = bitsused; int needed_bytes; int zero_count = 0; - int zero_dest = 0; /* initialize this with 0 to keep gcc quiet... */ + int zero_dest = 0; /* Initialize this with 0 to keep gcc quiet... */ /* If this is a terminal entry, there's no point in skipping any - bits. */ + bits. */ if (ent->skip_flag && ent->bits[0] == NULL && ent->bits[1] == NULL && ent->bits[2] == NULL) { if (ent->disent == NULL) - { - abort (); - } + abort (); else - { - ent->skip_flag = 0; - } + ent->skip_flag = 0; } /* Calculate the amount of space needed for this entry, or at least - a conservatively large approximation. */ + a conservatively large approximation. */ if (ent->skip_flag) - { - totbits += 5; - } + totbits += 5; + for (x = 1; x < 3; x++) - { - if (ent->bits[x] != NULL) - { - totbits += 16; - } - } + if (ent->bits[x] != NULL) + totbits += 16; if (ent->disent != NULL) { if (ent->bits[2] != NULL) - { - abort (); - } + abort (); + totbits += 16; } - /* Now allocate the space. */ + /* Now allocate the space. */ needed_bytes = (totbits + 7) / 8; if ((needed_bytes + insn_list_len) > tot_insn_list_len) { @@ -1865,7 +1913,7 @@ gen_dis_table (ent) memset (insn_list + our_offset, 0, needed_bytes); /* Encode the skip entry by setting bit 6 set in the state op field, - and store the # of bits to skip immediately after. */ + and store the # of bits to skip immediately after. */ if (ent->skip_flag) { bitsused += 5; @@ -1878,8 +1926,7 @@ gen_dis_table (ent) && (ENT)->disent == NULL && (ENT)->skip_flag == 0) /* Store an "if (bit is zero)" instruction by setting bit 7 in the - state op field. */ - + state op field. */ if (ent->bits[0] != NULL) { struct bittree *nent = ent->bits[0]; @@ -1929,14 +1976,10 @@ gen_dis_table (ent) i = NULL; } else - { - idest = insn_list_len - our_offset; - } + idest = insn_list_len - our_offset; } else - { - idest = ent->disent->ournum; - } + idest = ent->disent->ournum; /* If the destination offset for the if (bit is 1) test is less than 256 bytes away, we can store it as 8-bits instead of 16; @@ -1946,8 +1989,7 @@ gen_dis_table (ent) Note that branchings within the table are relative, and there are no branches that branch past our instruction yet - so we do not need to adjust any other offsets. */ - + so we do not need to adjust any other offsets. */ if (x == 1) { if (idest <= 256) @@ -1965,9 +2007,7 @@ gen_dis_table (ent) idest--; } else - { - insn_list[our_offset] |= 0x20; - } + insn_list[our_offset] |= 0x20; } else { @@ -1996,74 +2036,58 @@ gen_dis_table (ent) idest &= ~32768; } else - { - insn_list[our_offset] |= 0x08; - } + insn_list[our_offset] |= 0x08; } + if (debug) { int id = idest; if (i == NULL) - { - id |= 32768; - } + id |= 32768; else if (! (id & 32768)) - { - id += our_offset; - } + id += our_offset; + if (x == 1) - { - printf ("%d: if (1) goto %d\n", our_offset, id); - } + printf ("%d: if (1) goto %d\n", our_offset, id); else - { - printf ("%d: try %d\n", our_offset, id); - } + printf ("%d: try %d\n", our_offset, id); } - /* Store the address of the entry being branched to. */ + /* Store the address of the entry being branched to. */ while (currbits >= 0) { char *byte = insn_list + our_offset + bitsused / 8; if (idest & (1 << currbits)) - { - *byte |= (1 << (7 - (bitsused % 8))); - } + *byte |= (1 << (7 - (bitsused % 8))); + bitsused++; currbits--; } - /* Now generate the states for the entry being branched to. */ + /* Now generate the states for the entry being branched to. */ if (i != NULL) - { - gen_dis_table (i); - } - + gen_dis_table (i); } } + if (debug) { if (ent->skip_flag) - { - printf ("%d: skipping %d\n", our_offset, ent->bits_to_skip); - } + printf ("%d: skipping %d\n", our_offset, ent->bits_to_skip); if (ent->bits[0] != NULL) - { - printf ("%d: if (0:%d) goto %d\n", our_offset, zero_count + 1, - zero_dest); - } + printf ("%d: if (0:%d) goto %d\n", our_offset, zero_count + 1, + zero_dest); } + if (bitsused != totbits) - { - abort (); - } + abort (); } -void -print_dis_table () +static void +print_dis_table (void) { int x; struct disent *cent = disinsntable; @@ -2072,9 +2096,8 @@ print_dis_table () for (x = 0; x < insn_list_len; x++) { if ((x > 0) && ((x % 12) == 0)) - { - printf ("\n"); - } + printf ("\n"); + printf ("0x%02x, ", insn_list[x]); } printf ("\n};\n\n"); @@ -2096,24 +2119,22 @@ print_dis_table () printf ("};\n\n"); } -void -generate_disassembler () +static void +generate_disassembler (void) { int i; bittree = make_bittree_entry (); - for (i=0; i < otlen;i++) + for (i = 0; i < otlen; i++) { struct main_entry *ptr = ordered_table[i]; if (ptr->opcode->type != IA64_TYPE_DYN) - { - add_dis_entry (bittree, - ptr->opcode->opcode, ptr->opcode->mask, - ptr->main_index, - ptr->completers, 1); - } + add_dis_entry (bittree, + ptr->opcode->opcode, ptr->opcode->mask, + ptr->main_index, + ptr->completers, 1); } compact_distree (bittree); @@ -2123,25 +2144,26 @@ generate_disassembler () print_dis_table (); } -void -print_string_table () +static void +print_string_table (void) { int x; char lbuf[80], buf[80]; int blen = 0; - printf ("static const char *ia64_strings[] = {\n"); + printf ("static const char * const ia64_strings[] = {\n"); lbuf[0] = '\0'; + for (x = 0; x < strtablen; x++) { int len; if (strlen (string_table[x]->s) > 75) - { - abort (); - } + abort (); + sprintf (buf, " \"%s\",", string_table[x]->s); len = strlen (buf); + if ((blen + len) > 75) { printf (" %s\n", lbuf); @@ -2151,10 +2173,10 @@ print_string_table () strcat (lbuf, buf); blen += len; } + if (blen > 0) - { - printf (" %s\n", lbuf); - } + printf (" %s\n", lbuf); + printf ("};\n\n"); } @@ -2162,9 +2184,9 @@ static struct completer_entry **glist; static int glistlen = 0; static int glisttotlen = 0; -/* If the completer trees ENT1 and ENT2 are equal, return 1. */ +/* If the completer trees ENT1 and ENT2 are equal, return 1. */ -int +static int completer_entries_eq (ent1, ent2) struct completer_entry *ent1, *ent2; { @@ -2176,25 +2198,23 @@ completer_entries_eq (ent1, ent2) || ent1->is_terminal != ent2->is_terminal || ent1->dependencies != ent2->dependencies || ent1->order != ent2->order) - { - return 0; - } + return 0; + if (! completer_entries_eq (ent1->addl_entries, ent2->addl_entries)) - { - return 0; - } + return 0; + ent1 = ent1->alternative; ent2 = ent2->alternative; } + return ent1 == ent2; } /* Insert ENT into the global list of completers and return it. If an equivalent entry (according to completer_entries_eq) already exists, - it is returned instead. */ -struct completer_entry * -insert_gclist (ent) - struct completer_entry *ent; + it is returned instead. */ +static struct completer_entry * +insert_gclist (struct completer_entry *ent) { if (ent != NULL) { @@ -2223,13 +2243,9 @@ insert_gclist (ent) } if (ent->name->num < glist[0]->name->num) - { - i = 0; - } + i = 0; else if (ent->name->num > glist[end - 1]->name->num) - { - i = end; - } + i = end; else { int c; @@ -2238,62 +2254,50 @@ insert_gclist (ent) { i = (start + end) / 2; c = ent->name->num - glist[i]->name->num; + if (c < 0) - { - end = i - 1; - } + end = i - 1; else if (c == 0) { while (i > 0 && ent->name->num == glist[i - 1]->name->num) - { - i--; - } + i--; + break; } else - { - start = i + 1; - } + start = i + 1; + if (start > end) - { - break; - } + break; } + if (c == 0) { while (i < glistlen) { if (ent->name->num != glist[i]->name->num) - { - break; - } + break; + if (completer_entries_eq (ent, glist[i])) - { - return glist[i]; - } + return glist[i]; + i++; } } } + for (; i > 0 && i < glistlen; i--) - { - if (ent->name->num >= glist[i - 1]->name->num) - { - break; - } - } + if (ent->name->num >= glist[i - 1]->name->num) + break; + for (; i < glistlen; i++) - { - if (ent->name->num < glist[i]->name->num) - { - break; - } - } + if (ent->name->num < glist[i]->name->num) + break; + for (x = glistlen - 1; x >= i; x--) - { - glist[x + 1] = glist[x]; - } + glist[x + 1] = glist[x]; + glist[i] = ent; glistlen++; } @@ -2307,19 +2311,13 @@ get_prefix_len (name) char *c; if (name[0] == '\0') - { - return 0; - } + return 0; c = strchr (name, '.'); if (c != NULL) - { - return c - name; - } + return c - name; else - { - return strlen (name); - } + return strlen (name); } static void @@ -2340,30 +2338,21 @@ compute_completer_bits (ment, ent) int x; while (p != NULL && ! p->is_terminal) - { - p = p->parent; - } + p = p->parent; if (p != NULL) - { - p_bits = p->bits; - } + p_bits = p->bits; else - { - p_bits = ment->opcode->opcode; - } + p_bits = ment->opcode->opcode; for (x = 0; x < 64; x++) { ia64_insn m = ((ia64_insn) 1) << x; + if ((p_bits & m) != (our_bits & m)) - { - mask |= m; - } + mask |= m; else - { - our_bits &= ~m; - } + our_bits &= ~m; } ent->bits = our_bits; ent->mask = mask; @@ -2379,9 +2368,9 @@ compute_completer_bits (ment, ent) } /* Find identical completer trees that are used in different - instructions and collapse their entries. */ -void -collapse_redundant_completers () + instructions and collapse their entries. */ +static void +collapse_redundant_completers (void) { struct main_entry *ptr; int x; @@ -2389,43 +2378,39 @@ collapse_redundant_completers () for (ptr = maintable; ptr != NULL; ptr = ptr->next) { if (ptr->completers == NULL) - { - abort (); - } + abort (); + compute_completer_bits (ptr, ptr->completers); ptr->completers = insert_gclist (ptr->completers); } /* The table has been finalized, now number the indexes. */ for (x = 0; x < glistlen; x++) - { - glist[x]->num = x; - } + glist[x]->num = x; } -/* attach two lists of dependencies to each opcode. +/* Attach two lists of dependencies to each opcode. 1) all resources which, when already marked in use, conflict with this opcode (chks) 2) all resources which must be marked in use when this opcode is used - (regs) -*/ -int + (regs). */ +static int insert_opcode_dependencies (opc, cmp) struct ia64_opcode *opc; struct completer_entry *cmp ATTRIBUTE_UNUSED; { - /* note all resources which point to this opcode. rfi has the most chks - (79) and cmpxchng has the most regs (54) so 100 here should be enough */ + /* Note all resources which point to this opcode. rfi has the most chks + (79) and cmpxchng has the most regs (54) so 100 here should be enough. */ int i; int nregs = 0; unsigned short regs[256]; int nchks = 0; unsigned short chks[256]; - /* flag insns for which no class matched; there should be none */ + /* Flag insns for which no class matched; there should be none. */ int no_class_found = 1; - for (i=0;i < rdepslen;i++) + for (i = 0; i < rdepslen; i++) { struct rdep *rs = rdeps[i]; int j; @@ -2441,21 +2426,19 @@ insert_opcode_dependencies (opc, cmp) if (in_iclass (opc, ics[rs->regs[j]], NULL, NULL, &ic_note)) { - /* We can ignore ic_note 11 for non PR resources */ + /* We can ignore ic_note 11 for non PR resources. */ if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0) ic_note = 0; if (ic_note != 0 && rs->regnotes[j] != 0 && ic_note != rs->regnotes[j] && !(ic_note == 11 && rs->regnotes[j] == 1)) - fprintf (stderr, "Warning: IC note %d in opcode %s (IC:%s)" - " conflicts with resource %s note %d\n", - ic_note, opc->name, ics[rs->regs[j]]->name, - rs->name, rs->regnotes[j]); + warn (_("IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n"), + ic_note, opc->name, ics[rs->regs[j]]->name, + rs->name, rs->regnotes[j]); /* Instruction class notes override resource notes. So far, only note 11 applies to an IC instead of a resource, - and note 11 implies note 1. - */ + and note 11 implies note 1. */ if (ic_note) regs[nregs++] = RDEP(ic_note, i); else @@ -2464,23 +2447,23 @@ insert_opcode_dependencies (opc, cmp) ++rs->total_regs; } } - for (j=0;j < rs->nchks;j++) + + for (j = 0; j < rs->nchks; j++) { int ic_note = 0; if (in_iclass (opc, ics[rs->chks[j]], NULL, NULL, &ic_note)) { - /* We can ignore ic_note 11 for non PR resources */ + /* We can ignore ic_note 11 for non PR resources. */ if (ic_note == 11 && strncmp (rs->name, "PR", 2) != 0) ic_note = 0; if (ic_note != 0 && rs->chknotes[j] != 0 && ic_note != rs->chknotes[j] && !(ic_note == 11 && rs->chknotes[j] == 1)) - fprintf (stderr, "Warning: IC note %d for opcode %s (IC:%s)" - " conflicts with resource %s note %d\n", - ic_note, opc->name, ics[rs->chks[j]]->name, - rs->name, rs->chknotes[j]); + warn (_("IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n"), + ic_note, opc->name, ics[rs->chks[j]]->name, + rs->name, rs->chknotes[j]); if (ic_note) chks[nchks++] = RDEP(ic_note, i); else @@ -2492,14 +2475,14 @@ insert_opcode_dependencies (opc, cmp) } if (no_class_found) - fprintf (stderr, "Warning: opcode %s has no class (ops %d %d %d)\n", - opc->name, - opc->operands[0], opc->operands[1], opc->operands[2]); + warn (_("opcode %s has no class (ops %d %d %d)\n"), + opc->name, + opc->operands[0], opc->operands[1], opc->operands[2]); return insert_dependencies (nchks, chks, nregs, regs); } -void +static void insert_completer_entry (opc, tabent, order) struct ia64_opcode *opc; struct main_entry *tabent; @@ -2511,15 +2494,13 @@ insert_completer_entry (opc, tabent, order) int at_end = 0; if (strlen (opc->name) > 128) - { - abort (); - } + abort (); + strcpy (pcopy, opc->name); prefix = pcopy + get_prefix_len (pcopy); + if (prefix[0] != '\0') - { - prefix++; - } + prefix++; while (! at_end) { @@ -2541,13 +2522,13 @@ insert_completer_entry (opc, tabent, order) break; } else - { - ptr = &((*ptr)->alternative); - } + ptr = &((*ptr)->alternative); } + if (need_new_ent) { struct completer_entry *nent = tmalloc (struct completer_entry); + nent->name = sent; nent->parent = parent; nent->addl_entries = NULL; @@ -2566,9 +2547,7 @@ insert_completer_entry (opc, tabent, order) } if ((*ptr)->is_terminal) - { - abort (); - } + abort (); (*ptr)->is_terminal = 1; (*ptr)->mask = (ia64_insn)-1; @@ -2577,7 +2556,7 @@ insert_completer_entry (opc, tabent, order) (*ptr)->order = order; } -void +static void print_completer_entry (ent) struct completer_entry *ent; { @@ -2592,10 +2571,9 @@ print_completer_entry (ent) mask = mask >> 1; bits = bits >> 1; } + if (bits & 0xffffffff00000000LL) - { - abort (); - } + abort (); } printf (" { 0x%x, 0x%x, %d, %d, %d, %d, %d, %d },\n", @@ -2609,20 +2587,18 @@ print_completer_entry (ent) ent->dependencies); } -void +static void print_completer_table () { int x; printf ("static const struct ia64_completer_table\ncompleter_table[] = {\n"); for (x = 0; x < glistlen; x++) - { - print_completer_entry (glist[x]); - } + print_completer_entry (glist[x]); printf ("};\n\n"); } -int +static int opcodes_eq (opc1, opc2) struct ia64_opcode *opc1; struct ia64_opcode *opc2; @@ -2633,26 +2609,22 @@ opcodes_eq (opc1, opc2) if ((opc1->mask != opc2->mask) || (opc1->type != opc2->type) || (opc1->num_outputs != opc2->num_outputs) || (opc1->flags != opc2->flags)) - { - return 0; - } + return 0; + for (x = 0; x < 5; x++) - { - if (opc1->operands[x] != opc2->operands[x]) - { - return 0; - } - } + if (opc1->operands[x] != opc2->operands[x]) + return 0; + plen1 = get_prefix_len (opc1->name); plen2 = get_prefix_len (opc2->name); + if (plen1 == plen2 && (memcmp (opc1->name, opc2->name, plen1) == 0)) - { - return 1; - } + return 1; + return 0; } -void +static void add_opcode_entry (opc) struct ia64_opcode *opc; { @@ -2662,9 +2634,8 @@ add_opcode_entry (opc) int found_it = 0; if (strlen (opc->name) > 128) - { - abort (); - } + abort (); + place = &maintable; strcpy (prefix, opc->name); prefix[get_prefix_len (prefix)] = '\0'; @@ -2672,7 +2643,7 @@ add_opcode_entry (opc) /* Walk the list of opcode table entries. If it's a new instruction, allocate and fill in a new entry. Note - the main table is alphabetical by opcode name. */ + the main table is alphabetical by opcode name. */ while (*place != NULL) { @@ -2683,9 +2654,8 @@ add_opcode_entry (opc) break; } if ((*place)->name->num > name->num) - { - break; - } + break; + place = &((*place)->next); } if (! found_it) @@ -2710,8 +2680,8 @@ add_opcode_entry (opc) insert_completer_entry (opc, *place, opcode_count++); } -void -print_main_table () +static void +print_main_table (void) { struct main_entry *ptr = maintable; int index = 0; @@ -2742,30 +2712,85 @@ print_main_table () printf ("};\n\n"); } -void +static void shrink (table) struct ia64_opcode *table; { int curr_opcode; for (curr_opcode = 0; table[curr_opcode].name != NULL; curr_opcode++) - { - add_opcode_entry (table + curr_opcode); - } + add_opcode_entry (table + curr_opcode); } + +/* Program options. */ +#define OPTION_SRCDIR 200 + +struct option long_options[] = +{ + {"srcdir", required_argument, NULL, OPTION_SRCDIR}, + {"debug", no_argument, NULL, 'd'}, + {"version", no_argument, NULL, 'V'}, + {"help", no_argument, NULL, 'h'}, + {0, no_argument, NULL, 0} +}; + +static void +print_version (void) +{ + printf ("%s: version 1.0\n", program_name); + xexit (0); +} + +static void +usage (FILE * stream, int status) +{ + fprintf (stream, "Usage: %s [-V | --version] [-d | --debug] [--srcdir=dirname] [--help]\n", + program_name); + xexit (status); +} + int -main (argc, argv) - int argc; - char **argv ATTRIBUTE_UNUSED; +main (int argc, char **argv) { - if (argc > 1) - { - debug = 1; - } + extern int chdir (char *); + char *srcdir = NULL; + int c; + + program_name = *argv; + xmalloc_set_program_name (program_name); + + while ((c = getopt_long (argc, argv, "vVdh", long_options, 0)) != EOF) + switch (c) + { + case OPTION_SRCDIR: + srcdir = optarg; + break; + case 'V': + case 'v': + print_version (); + break; + case 'd': + debug = 1; + break; + case 'h': + case '?': + usage (stderr, 0); + default: + case 0: + break; + } + + if (optind != argc) + usage (stdout, 1); + + if (srcdir != NULL) + if (chdir (srcdir) != 0) + fail (_("unable to change directory to \"%s\", errno = %s\n"), + srcdir, strerror (errno)); - load_insn_classes(); - load_dependencies(); + load_insn_classes (); + load_dependencies (); shrink (ia64_opcodes_a); shrink (ia64_opcodes_b); @@ -2777,7 +2802,7 @@ main (argc, argv) collapse_redundant_completers (); - printf ("/* This file is automatically generated by ia64-gen. Do not edit! */\n"); + printf ("/* This file is automatically generated by ia64-gen. Do not edit! */\n"); print_string_table (); print_dependency_table (); print_completer_table (); diff --git a/contrib/binutils/opcodes/ia64-ic.tbl b/contrib/binutils/opcodes/ia64-ic.tbl index 115a276..45e3bd5 100644 --- a/contrib/binutils/opcodes/ia64-ic.tbl +++ b/contrib/binutils/opcodes/ia64-ic.tbl @@ -3,7 +3,7 @@ all; IC:predicatable-instructions, IC:unpredicatable-instructions branches; IC:indirect-brs, IC:ip-rel-brs cfm-readers; IC:fr-readers, IC:fr-writers, IC:gr-readers, IC:gr-writers, IC:mod-sched-brs, IC:predicatable-instructions, IC:pr-writers, alloc, br.call, brl.call, br.ret, cover, loadrs, rfi, IC:chk-a, invala.e chk-a; chk.a.clr, chk.a.nc -cmpxchg; cmpxchg1, cmpxchg2, cmpxchg4, cmpxchg8 +cmpxchg; cmpxchg1, cmpxchg2, cmpxchg4, cmpxchg8, cmp8xchg16 czx; czx1, czx2 fcmp-s0; fcmp[Field(sf)==s0] fcmp-s1; fcmp[Field(sf)==s1] @@ -20,7 +20,7 @@ fpcmp-s0; fpcmp[Field(sf)==s0] fpcmp-s1; fpcmp[Field(sf)==s1] fpcmp-s2; fpcmp[Field(sf)==s2] fpcmp-s3; fpcmp[Field(sf)==s3] -fr-readers; IC:fp-arith, IC:fp-non-arith, IC:pr-writers-fp, chk.s[Format in {M21}], getf +fr-readers; IC:fp-arith, IC:fp-non-arith, IC:pr-writers-fp, chk.s[Format in {M21}], getf, IC:mem-writers-fp fr-writers; IC:fp-arith, IC:fp-non-arith\fclass, IC:mem-readers-fp, setf gr-readers; IC:gr-readers-writers, IC:mem-readers, IC:mem-writers, chk.s, cmp, cmp4, fc, itc.i, itc.d, itr.i, itr.d, IC:mov-to-AR-gr, IC:mov-to-BR, IC:mov-to-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-to-PR-allreg, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:probe-all, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, setf, tbit, tnat gr-readers-writers; IC:mov-from-IND, add, addl, addp4, adds, and, andcm, IC:czx, dep\dep[Format in {I13}], extr, IC:mem-readers-int, IC:ld-all-postinc, IC:lfetch-postinc, IC:mix, IC:mux, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-nofault, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, shl, shladd, shladdp4, shr, shrp, IC:st-postinc, sub, IC:sxt, tak, thash, tpa, ttag, IC:unpack, xor, IC:zxt @@ -29,7 +29,7 @@ indirect-brp; brp[Format in {B7}] indirect-brs; br.call[Format in {B5}], br.cond[Format in {B4}], br.ia, br.ret invala-all; invala[Format in {M24}], invala.e ip-rel-brs; IC:mod-sched-brs, br.call[Format in {B3}], brl.call, brl.cond, br.cond[Format in {B1}], br.cloop -ld; ld1, ld2, ld4, ld8, ld8.fill +ld; ld1, ld2, ld4, ld8, ld8.fill, ld16 ld-a; ld1.a, ld2.a, ld4.a, ld8.a ld-all-postinc; IC:ld[Format in {M2 M3}], IC:ldfp[Format in {M12}], IC:ldf[Format in {M7 M8}] ld-c; IC:ld-c-nc, IC:ld-c-clr @@ -71,8 +71,15 @@ mov-from-AR; IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP] mov-from-AR-BSPSTORE; IC:mov-from-AR-M[Field(ar3) == BSPSTORE] mov-from-AR-CCV; IC:mov-from-AR-M[Field(ar3) == CCV] +mov-from-AR-CFLG; IC:mov-from-AR-M[Field(ar3) == CFLG] +mov-from-AR-CSD; IC:mov-from-AR-M[Field(ar3) == CSD] mov-from-AR-EC; IC:mov-from-AR-I[Field(ar3) == EC] +mov-from-AR-EFLAG; IC:mov-from-AR-M[Field(ar3) == EFLAG] +mov-from-AR-FCR; IC:mov-from-AR-M[Field(ar3) == FCR] +mov-from-AR-FDR; IC:mov-from-AR-M[Field(ar3) == FDR] +mov-from-AR-FIR; IC:mov-from-AR-M[Field(ar3) == FIR] mov-from-AR-FPSR; IC:mov-from-AR-M[Field(ar3) == FPSR] +mov-from-AR-FSR; IC:mov-from-AR-M[Field(ar3) == FSR] mov-from-AR-I; mov_ar[Format in {I28}] mov-from-AR-ig; IC:mov-from-AR-IM[Field(ar3) in {48-63 112-127}] mov-from-AR-IM; mov_ar[Format in {I28 M31}] @@ -84,6 +91,7 @@ mov-from-AR-PFS; IC:mov-from-AR-I[Field(ar3) == PFS] mov-from-AR-RNAT; IC:mov-from-AR-M[Field(ar3) == RNAT] mov-from-AR-RSC; IC:mov-from-AR-M[Field(ar3) == RSC] mov-from-AR-rv; IC:none +mov-from-AR-SSD; IC:mov-from-AR-M[Field(ar3) == SSD] mov-from-AR-UNAT; IC:mov-from-AR-M[Field(ar3) == UNAT] mov-from-BR; mov_br[Format in {I22}] mov-from-CR; mov_cr[Format in {M33}] @@ -129,8 +137,15 @@ mov-to-AR; IC:mov-to-AR-M, IC:mov-to-AR-I mov-to-AR-BSP; IC:mov-to-AR-M[Field(ar3) == BSP] mov-to-AR-BSPSTORE; IC:mov-to-AR-M[Field(ar3) == BSPSTORE] mov-to-AR-CCV; IC:mov-to-AR-M[Field(ar3) == CCV] +mov-to-AR-CFLG; IC:mov-to-AR-M[Field(ar3) == CFLG] +mov-to-AR-CSD; IC:mov-to-AR-M[Field(ar3) == CSD] mov-to-AR-EC; IC:mov-to-AR-I[Field(ar3) == EC] +mov-to-AR-EFLAG; IC:mov-to-AR-M[Field(ar3) == EFLAG] +mov-to-AR-FCR; IC:mov-to-AR-M[Field(ar3) == FCR] +mov-to-AR-FDR; IC:mov-to-AR-M[Field(ar3) == FDR] +mov-to-AR-FIR; IC:mov-to-AR-M[Field(ar3) == FIR] mov-to-AR-FPSR; IC:mov-to-AR-M[Field(ar3) == FPSR] +mov-to-AR-FSR; IC:mov-to-AR-M[Field(ar3) == FSR] mov-to-AR-gr; IC:mov-to-AR-M[Format in {M29}], IC:mov-to-AR-I[Format in {I26}] mov-to-AR-I; mov_ar[Format in {I26 I27}] mov-to-AR-ig; IC:mov-to-AR-IM[Field(ar3) in {48-63 112-127}] @@ -142,6 +157,7 @@ mov-to-AR-M; mov_ar[Format in {M29 M30}] mov-to-AR-PFS; IC:mov-to-AR-I[Field(ar3) == PFS] mov-to-AR-RNAT; IC:mov-to-AR-M[Field(ar3) == RNAT] mov-to-AR-RSC; IC:mov-to-AR-M[Field(ar3) == RSC] +mov-to-AR-SSD; IC:mov-to-AR-M[Field(ar3) == SSD] mov-to-AR-UNAT; IC:mov-to-AR-M[Field(ar3) == UNAT] mov-to-BR; mov_br[Format in {I21}] mov-to-CR; mov_cr[Format in {M32}] @@ -200,8 +216,8 @@ pr-gen-writers-int; cmp, cmp4, tbit, tnat pr-norm-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==] pr-norm-writers-int; IC:pr-gen-writers-int[Field(ctype)==] pr-or-writers; IC:pr-gen-writers-int[Field(ctype) in {or orcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}] -pr-readers-br; br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.wtop, break.b, nop.b, IC:ReservedBQP -pr-readers-nobr-nomovpr; add, addl, addp4, adds, and, andcm, break.f, break.i, break.m, break.x, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak, tbit, thash, tnat, tpa, ttag, IC:unpack, IC:xchg, xma, xmpy, xor, IC:zxt +pr-readers-br; br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.wtop, break.b, hint.b, nop.b, IC:ReservedBQP +pr-readers-nobr-nomovpr; add, addl, addp4, adds, and, andcm, break.f, break.i, break.m, break.x, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, hint.f, hint.i, hint.m, hint.x, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak, tbit, thash, tnat, tpa, ttag, IC:unpack, IC:xchg, xma, xmpy, xor, IC:zxt pr-unc-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==unc]+11, fprcpa+11, fprsqrta+11, frcpa+11, frsqrta+11 pr-unc-writers-int; IC:pr-gen-writers-int[Field(ctype)==unc]+11 pr-writers; IC:pr-writers-int, IC:pr-writers-fp @@ -222,7 +238,7 @@ ReservedBQP; -+15 ReservedQP; -+16 rse-readers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-from-AR-BSP, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-BSPSTORE, IC:mov-from-AR-RNAT, IC:mov-to-AR-RNAT, rfi rse-writers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-to-AR-BSPSTORE, rfi -st; st1, st2, st4, st8, st8.spill +st; st1, st2, st4, st8, st8.spill, st16 st-postinc; IC:stf[Format in {M10}], IC:st[Format in {M5}] stf; stfs, stfd, stfe, stf8, stf.spill sxt; sxt1, sxt2, sxt4 diff --git a/contrib/binutils/opcodes/ia64-opc-a.c b/contrib/binutils/opcodes/ia64-opc-a.c index 27d7637..c9e3162 100644 --- a/contrib/binutils/opcodes/ia64-opc-a.c +++ b/contrib/binutils/opcodes/ia64-opc-a.c @@ -1,5 +1,5 @@ /* ia64-opc-a.c -- IA-64 `A' opcode table. - Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc. + Copyright 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc. Contributed by David Mosberger-Tang <davidm@hpl.hp.com> This file is part of GDB, GAS, and the GNU binutils. @@ -82,292 +82,296 @@ (bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \ (mOp | mX2a | mZa | mZb | mX4 | mX2b) +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + struct ia64_opcode ia64_opcodes_a[] = { - /* A-type instruction encodings (sorted according to major opcode) */ + /* A-type instruction encodings (sorted according to major opcode). */ - {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}}, - {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}}, - {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}}, - {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}}, - {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}}, - {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}}, - {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}}, - {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}}, - {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}}, - {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}}, - {"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}}, - {"sub", A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}}, - {"and", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}}, - {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}}, - {"or", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}}, - {"xor", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}}, - {"mov", A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}}, - {"mov", A, OpX2aVeR3a (8, 2, 0, 0), {R1, IMM14}, PSEUDO}, - {"adds", A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}}, - {"addp4", A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}}, - {"padd1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}}, - {"padd2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}}, - {"padd4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}}, - {"padd1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}}, - {"padd2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}}, - {"padd1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}}, - {"padd2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}}, - {"padd1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}}, - {"padd2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}}, - {"psub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}}, - {"psub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}}, - {"psub4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}}, - {"psub1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}}, - {"psub2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}}, - {"psub1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}}, - {"psub2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}}, - {"psub1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}}, - {"psub2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}}, - {"pavg1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}}, - {"pavg2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}}, - {"pavg1.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}}, - {"pavg2.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}}, - {"pavgsub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}}, - {"pavgsub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}}, - {"pcmp1.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}}, - {"pcmp2.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}}, - {"pcmp4.eq", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}}, - {"pcmp1.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}}, - {"pcmp2.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}}, - {"pcmp4.gt", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}}, - {"pshladd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}}, - {"pshradd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}}, + {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}, EMPTY}, + {"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}, EMPTY}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}, EMPTY}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}, EMPTY}, + {"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}, EMPTY}, + {"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}, EMPTY}, + {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}, EMPTY}, + {"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}, EMPTY}, + {"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}, EMPTY}, + {"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}, EMPTY}, + {"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}, EMPTY}, + {"sub", A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}, EMPTY}, + {"and", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}, EMPTY}, + {"andcm", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}, EMPTY}, + {"or", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}, EMPTY}, + {"xor", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}, EMPTY}, + {"mov", A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}, EMPTY}, + {"mov", A, OpX2aVeR3a (8, 2, 0, 0), {R1, IMM14}, PSEUDO, 0, NULL}, + {"adds", A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}, EMPTY}, + {"addp4", A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}, EMPTY}, + {"padd1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}, EMPTY}, + {"padd2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}, EMPTY}, + {"padd4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}, EMPTY}, + {"padd1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, + {"padd2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}, EMPTY}, + {"padd1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}, EMPTY}, + {"padd2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}, EMPTY}, + {"padd1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}, EMPTY}, + {"padd2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}, EMPTY}, + {"psub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}, EMPTY}, + {"psub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}, EMPTY}, + {"psub4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}, EMPTY}, + {"psub1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}, EMPTY}, + {"psub2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}, EMPTY}, + {"psub1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}, EMPTY}, + {"psub2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}, EMPTY}, + {"psub1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}, EMPTY}, + {"psub2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}, EMPTY}, + {"pavg1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}, EMPTY}, + {"pavg2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}, EMPTY}, + {"pavg1.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}, EMPTY}, + {"pavg2.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}, EMPTY}, + {"pavgsub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}, EMPTY}, + {"pavgsub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}, EMPTY}, + {"pcmp1.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}, EMPTY}, + {"pcmp2.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}, EMPTY}, + {"pcmp4.eq", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}, EMPTY}, + {"pcmp1.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}, EMPTY}, + {"pcmp2.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}, EMPTY}, + {"pcmp4.gt", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}, EMPTY}, + {"pshladd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}, EMPTY}, + {"pshradd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}, EMPTY}, - {"mov", A, OpR3b (9, 0), {R1, IMM22}, PSEUDO}, - {"addl", A, Op (9), {R1, IMM22, R3_2}}, + {"mov", A, OpR3b (9, 0), {R1, IMM22}, PSEUDO, 0, NULL}, + {"addl", A, Op (9), {R1, IMM22, R3_2}, EMPTY}, - {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}}, - {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}}, - {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}}, - {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}}, - {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}}, - {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}}, - {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}}, - {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}}, - {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}}, - {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, - {"cmp.ne.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}}, - {"cmp.eq.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, - {"cmp4.lt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}}, - {"cmp4.le", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}}, - {"cmp4.gt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}}, - {"cmp4.ge", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}}, - {"cmp4.lt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}}, - {"cmp4.le.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}}, - {"cmp4.gt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}}, - {"cmp4.ge.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}}, - {"cmp4.eq.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}}, - {"cmp4.ne.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, - {"cmp4.ne.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}}, - {"cmp4.eq.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, - {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}}, - {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}}, - {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}}, - {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}}, - {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}}, - {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}}, - {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}}, - {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}}, - {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.lt", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8, R3}}, - {"cmp.le", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}}, - {"cmp.gt", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}}, - {"cmp.ge", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8, R3}}, - {"cmp.lt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8, R3}}, - {"cmp.le.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}}, - {"cmp.gt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}}, - {"cmp.ge.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8, R3}}, - {"cmp.eq.and", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}}, - {"cmp.ne.andcm", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, - {"cmp.ne.and", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}}, - {"cmp.eq.andcm", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, - {"cmp4.lt", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8, R3}}, - {"cmp4.le", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}}, - {"cmp4.gt", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}}, - {"cmp4.ge", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8, R3}}, - {"cmp4.lt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8, R3}}, - {"cmp4.le.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}}, - {"cmp4.gt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}}, - {"cmp4.ge.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8, R3}}, - {"cmp4.eq.and", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}}, - {"cmp4.ne.andcm", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, - {"cmp4.ne.and", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}}, - {"cmp4.eq.andcm", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, - {"cmp.ltu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}}, - {"cmp.leu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}}, - {"cmp.gtu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}}, - {"cmp.geu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}}, - {"cmp.ltu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}}, - {"cmp.leu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}}, - {"cmp.gtu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}}, - {"cmp.geu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}}, - {"cmp.eq.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}}, - {"cmp.ne.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, - {"cmp.ne.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}}, - {"cmp.eq.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, - {"cmp4.ltu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}}, - {"cmp4.leu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}}, - {"cmp4.gtu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}}, - {"cmp4.geu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}}, - {"cmp4.ltu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}}, - {"cmp4.leu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}}, - {"cmp4.gtu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}}, - {"cmp4.geu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}}, - {"cmp4.eq.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}}, - {"cmp4.ne.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO}, - {"cmp4.ne.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}}, - {"cmp4.eq.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO}, - {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}}, - {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}}, - {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}}, - {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}}, - {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}}, - {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}}, - {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}}, - {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}}, - {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO}, - {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.ltu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8, R3}}, - {"cmp.leu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}}, - {"cmp.gtu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}}, - {"cmp.geu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8, R3}}, - {"cmp.ltu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8, R3}}, - {"cmp.leu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}}, - {"cmp.gtu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}}, - {"cmp.geu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8, R3}}, - {"cmp.eq.or", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}}, - {"cmp.ne.orcm", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, - {"cmp.ne.or", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}}, - {"cmp.eq.orcm", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, - {"cmp4.ltu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}}, - {"cmp4.leu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}}, - {"cmp4.gtu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}}, - {"cmp4.geu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}}, - {"cmp4.ltu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}}, - {"cmp4.leu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}}, - {"cmp4.gtu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}}, - {"cmp4.geu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}}, - {"cmp4.eq.or", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}}, - {"cmp4.ne.orcm", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO}, - {"cmp4.ne.or", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}}, - {"cmp4.eq.orcm", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO}, - {"cmp.eq", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}}, - {"cmp.ne", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}}, - {"cmp.eq.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}}, - {"cmp.ne.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}}, - {"cmp.eq.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}}, - {"cmp.ne.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO}, - {"cmp.ne.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}}, - {"cmp.eq.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO}, - {"cmp4.eq", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}}, - {"cmp4.ne", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}}, - {"cmp4.eq.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}}, - {"cmp4.ne.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}}, - {"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}}, - {"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO}, - {"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}}, - {"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO}, - {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}}, - {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO}, - {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO}, - {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}}, - {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO}, - {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO}, - {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}}, - {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO}, - {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO}, - {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}}, - {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO}, - {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO}, - {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}}, - {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO}, - {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO}, - {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}}, - {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO}, - {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO}, - {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}}, - {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO}, - {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO}, - {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}}, - {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO}, - {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO}, - {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO}, - {"cmp.eq", A2, OpX2TaC (0xe, 2, 0, 0), {P1, P2, IMM8, R3}}, - {"cmp.ne", A2, OpX2TaC (0xe, 2, 0, 0), {P2, P1, IMM8, R3}}, - {"cmp.eq.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P1, P2, IMM8, R3}}, - {"cmp.ne.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P2, P1, IMM8, R3}}, - {"cmp.eq.or.andcm", A2, OpX2TaC (0xe, 2, 1, 0), {P1, P2, IMM8, R3}}, - {"cmp.ne.and.orcm", A2, OpX2TaC (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO}, - {"cmp.ne.or.andcm", A2, OpX2TaC (0xe, 2, 1, 1), {P1, P2, IMM8, R3}}, - {"cmp.eq.and.orcm", A2, OpX2TaC (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO}, - {"cmp4.eq", A2, OpX2TaC (0xe, 3, 0, 0), {P1, P2, IMM8, R3}}, - {"cmp4.ne", A2, OpX2TaC (0xe, 3, 0, 0), {P2, P1, IMM8, R3}}, - {"cmp4.eq.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P1, P2, IMM8, R3}}, - {"cmp4.ne.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P2, P1, IMM8, R3}}, - {"cmp4.eq.or.andcm", A2, OpX2TaC (0xe, 3, 1, 0), {P1, P2, IMM8, R3}}, - {"cmp4.ne.and.orcm", A2, OpX2TaC (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO}, - {"cmp4.ne.or.andcm", A2, OpX2TaC (0xe, 3, 1, 1), {P1, P2, IMM8, R3}}, - {"cmp4.eq.and.orcm", A2, OpX2TaC (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO}, + {"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, + {"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, + {"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, + {"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, + {"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.eq.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.le", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, + {"cmp4.gt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, + {"cmp4.ge", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.lt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.le.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, + {"cmp4.gt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, + {"cmp4.ge.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.eq.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.eq.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.le", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}, EMPTY}, + {"cmp.gt", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}, EMPTY}, + {"cmp.ge", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.lt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.le.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}, EMPTY}, + {"cmp.gt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}, EMPTY}, + {"cmp.ge.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.eq.and", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne.andcm", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.and", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.eq.andcm", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.le", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}, EMPTY}, + {"cmp4.gt", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}, EMPTY}, + {"cmp4.ge", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp4.lt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.le.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}, EMPTY}, + {"cmp4.gt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}, EMPTY}, + {"cmp4.ge.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp4.eq.and", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne.andcm", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.and", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.eq.andcm", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.ltu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.leu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, + {"cmp.gtu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, + {"cmp.geu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp.ltu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.leu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, + {"cmp.gtu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, + {"cmp.geu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp.eq.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.eq.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.ltu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.leu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}, EMPTY}, + {"cmp4.gtu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}, EMPTY}, + {"cmp4.geu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.ltu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.leu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}, EMPTY}, + {"cmp4.gtu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}, EMPTY}, + {"cmp4.geu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.eq.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.eq.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ltu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.leu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}, EMPTY}, + {"cmp.gtu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}, EMPTY}, + {"cmp.geu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.ltu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.leu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}, EMPTY}, + {"cmp.gtu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}, EMPTY}, + {"cmp.geu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.eq.or", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne.orcm", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.or", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.eq.orcm", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.ltu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}, EMPTY}, + {"cmp4.leu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}, EMPTY}, + {"cmp4.gtu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}, EMPTY}, + {"cmp4.geu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}, EMPTY}, + {"cmp4.ltu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}, EMPTY}, + {"cmp4.leu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}, EMPTY}, + {"cmp4.gtu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}, EMPTY}, + {"cmp4.geu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}, EMPTY}, + {"cmp4.eq.or", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne.orcm", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.or", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.eq.orcm", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.eq", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp.eq.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp.eq.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp.ne.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp.eq.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.eq", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.eq.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}, EMPTY}, + {"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}, EMPTY}, + {"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}, EMPTY}, + {"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO, 0, NULL}, + {"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO, 0, NULL}, + {"cmp.eq", A2, OpX2TaC (0xe, 2, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne", A2, OpX2TaC (0xe, 2, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.eq.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp.eq.or.andcm", A2, OpX2TaC (0xe, 2, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.ne.and.orcm", A2, OpX2TaC (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp.ne.or.andcm", A2, OpX2TaC (0xe, 2, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp.eq.and.orcm", A2, OpX2TaC (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.eq", A2, OpX2TaC (0xe, 3, 0, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne", A2, OpX2TaC (0xe, 3, 0, 0), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp4.eq.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P2, P1, IMM8, R3}, EMPTY}, + {"cmp4.eq.or.andcm", A2, OpX2TaC (0xe, 3, 1, 0), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.ne.and.orcm", A2, OpX2TaC (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, + {"cmp4.ne.or.andcm", A2, OpX2TaC (0xe, 3, 1, 1), {P1, P2, IMM8, R3}, EMPTY}, + {"cmp4.eq.and.orcm", A2, OpX2TaC (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO, 0, NULL}, - {0} + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} }; #undef A @@ -410,3 +414,4 @@ struct ia64_opcode ia64_opcodes_a[] = #undef OpX2TaC #undef OpX2aZaZbX4 #undef OpX2aZaZbX4X2b +#undef EMPTY diff --git a/contrib/binutils/opcodes/ia64-opc-b.c b/contrib/binutils/opcodes/ia64-opc-b.c index 9a4a850..fc57ab6 100644 --- a/contrib/binutils/opcodes/ia64-opc-b.c +++ b/contrib/binutils/opcodes/ia64-opc-b.c @@ -1,5 +1,5 @@ /* ia64-opc-b.c -- IA-64 `B' opcode table. - Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. Contributed by David Mosberger-Tang <davidm@hpl.hp.com> This file is part of GDB, GAS, and the GNU binutils. @@ -69,12 +69,16 @@ (bOp (a) | bX6 (b) | bIh (c) | bWhb (d)), \ (mOp | mX6 | mIh | mWhb) +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + struct ia64_opcode ia64_opcodes_b[] = { /* B-type instruction encodings (sorted according to major opcode) */ #define BR(a,b) \ - B0, OpX6BtypePaWhaDPr (0, 0x20, 0, a, 0, b, 0), {B2}, PSEUDO + B0, OpX6BtypePaWhaDPr (0, 0x20, 0, a, 0, b, 0), {B2}, PSEUDO, 0, NULL {"br.few", BR (0, 0)}, {"br", BR (0, 0)}, {"br.few.clr", BR (0, 1)}, @@ -83,23 +87,25 @@ struct ia64_opcode ia64_opcodes_b[] = {"br.many.clr", BR (1, 1)}, #undef BR -#define BR(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2} +#define BR(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, EMPTY +#define BRP(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, PSEUDO, 0, NULL +#define BRT(a,b,c,d,e,f) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}, f, 0, NULL {"br.cond.sptk.few", BR (0x20, 0, 0, 0, 0)}, - {"br.cond.sptk", BR (0x20, 0, 0, 0, 0), PSEUDO}, + {"br.cond.sptk", BRP (0x20, 0, 0, 0, 0)}, {"br.cond.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, - {"br.cond.sptk.clr", BR (0x20, 0, 0, 0, 1), PSEUDO}, + {"br.cond.sptk.clr", BRP (0x20, 0, 0, 0, 1)}, {"br.cond.spnt.few", BR (0x20, 0, 0, 1, 0)}, - {"br.cond.spnt", BR (0x20, 0, 0, 1, 0), PSEUDO}, + {"br.cond.spnt", BRP (0x20, 0, 0, 1, 0)}, {"br.cond.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, - {"br.cond.spnt.clr", BR (0x20, 0, 0, 1, 1), PSEUDO}, + {"br.cond.spnt.clr", BRP (0x20, 0, 0, 1, 1)}, {"br.cond.dptk.few", BR (0x20, 0, 0, 2, 0)}, - {"br.cond.dptk", BR (0x20, 0, 0, 2, 0), PSEUDO}, + {"br.cond.dptk", BRP (0x20, 0, 0, 2, 0)}, {"br.cond.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, - {"br.cond.dptk.clr", BR (0x20, 0, 0, 2, 1), PSEUDO}, + {"br.cond.dptk.clr", BRP (0x20, 0, 0, 2, 1)}, {"br.cond.dpnt.few", BR (0x20, 0, 0, 3, 0)}, - {"br.cond.dpnt", BR (0x20, 0, 0, 3, 0), PSEUDO}, + {"br.cond.dpnt", BRP (0x20, 0, 0, 3, 0)}, {"br.cond.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, - {"br.cond.dpnt.clr", BR (0x20, 0, 0, 3, 1), PSEUDO}, + {"br.cond.dpnt.clr", BRP (0x20, 0, 0, 3, 1)}, {"br.cond.sptk.many", BR (0x20, 0, 1, 0, 0)}, {"br.cond.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, {"br.cond.spnt.many", BR (0x20, 0, 1, 1, 0)}, @@ -109,21 +115,21 @@ struct ia64_opcode ia64_opcodes_b[] = {"br.cond.dpnt.many", BR (0x20, 0, 1, 3, 0)}, {"br.cond.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, {"br.sptk.few", BR (0x20, 0, 0, 0, 0)}, - {"br.sptk", BR (0x20, 0, 0, 0, 0), PSEUDO}, + {"br.sptk", BRP (0x20, 0, 0, 0, 0)}, {"br.sptk.few.clr", BR (0x20, 0, 0, 0, 1)}, - {"br.sptk.clr", BR (0x20, 0, 0, 0, 1), PSEUDO}, + {"br.sptk.clr", BRP (0x20, 0, 0, 0, 1)}, {"br.spnt.few", BR (0x20, 0, 0, 1, 0)}, - {"br.spnt", BR (0x20, 0, 0, 1, 0), PSEUDO}, + {"br.spnt", BRP (0x20, 0, 0, 1, 0)}, {"br.spnt.few.clr", BR (0x20, 0, 0, 1, 1)}, - {"br.spnt.clr", BR (0x20, 0, 0, 1, 1), PSEUDO}, + {"br.spnt.clr", BRP (0x20, 0, 0, 1, 1)}, {"br.dptk.few", BR (0x20, 0, 0, 2, 0)}, - {"br.dptk", BR (0x20, 0, 0, 2, 0), PSEUDO}, + {"br.dptk", BRP (0x20, 0, 0, 2, 0)}, {"br.dptk.few.clr", BR (0x20, 0, 0, 2, 1)}, - {"br.dptk.clr", BR (0x20, 0, 0, 2, 1), PSEUDO}, + {"br.dptk.clr", BRP (0x20, 0, 0, 2, 1)}, {"br.dpnt.few", BR (0x20, 0, 0, 3, 0)}, - {"br.dpnt", BR (0x20, 0, 0, 3, 0), PSEUDO}, + {"br.dpnt", BRP (0x20, 0, 0, 3, 0)}, {"br.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)}, - {"br.dpnt.clr", BR (0x20, 0, 0, 3, 1), PSEUDO}, + {"br.dpnt.clr", BRP (0x20, 0, 0, 3, 1)}, {"br.sptk.many", BR (0x20, 0, 1, 0, 0)}, {"br.sptk.many.clr", BR (0x20, 0, 1, 0, 1)}, {"br.spnt.many", BR (0x20, 0, 1, 1, 0)}, @@ -133,21 +139,21 @@ struct ia64_opcode ia64_opcodes_b[] = {"br.dpnt.many", BR (0x20, 0, 1, 3, 0)}, {"br.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)}, {"br.ia.sptk.few", BR (0x20, 1, 0, 0, 0)}, - {"br.ia.sptk", BR (0x20, 1, 0, 0, 0), PSEUDO}, + {"br.ia.sptk", BRP (0x20, 1, 0, 0, 0)}, {"br.ia.sptk.few.clr", BR (0x20, 1, 0, 0, 1)}, - {"br.ia.sptk.clr", BR (0x20, 1, 0, 0, 1), PSEUDO}, + {"br.ia.sptk.clr", BRP (0x20, 1, 0, 0, 1)}, {"br.ia.spnt.few", BR (0x20, 1, 0, 1, 0)}, - {"br.ia.spnt", BR (0x20, 1, 0, 1, 0), PSEUDO}, + {"br.ia.spnt", BRP (0x20, 1, 0, 1, 0)}, {"br.ia.spnt.few.clr", BR (0x20, 1, 0, 1, 1)}, - {"br.ia.spnt.clr", BR (0x20, 1, 0, 1, 1), PSEUDO}, + {"br.ia.spnt.clr", BRP (0x20, 1, 0, 1, 1)}, {"br.ia.dptk.few", BR (0x20, 1, 0, 2, 0)}, - {"br.ia.dptk", BR (0x20, 1, 0, 2, 0), PSEUDO}, + {"br.ia.dptk", BRP (0x20, 1, 0, 2, 0)}, {"br.ia.dptk.few.clr", BR (0x20, 1, 0, 2, 1)}, - {"br.ia.dptk.clr", BR (0x20, 1, 0, 2, 1), PSEUDO}, + {"br.ia.dptk.clr", BRP (0x20, 1, 0, 2, 1)}, {"br.ia.dpnt.few", BR (0x20, 1, 0, 3, 0)}, - {"br.ia.dpnt", BR (0x20, 1, 0, 3, 0), PSEUDO}, + {"br.ia.dpnt", BRP (0x20, 1, 0, 3, 0)}, {"br.ia.dpnt.few.clr", BR (0x20, 1, 0, 3, 1)}, - {"br.ia.dpnt.clr", BR (0x20, 1, 0, 3, 1), PSEUDO}, + {"br.ia.dpnt.clr", BRP (0x20, 1, 0, 3, 1)}, {"br.ia.sptk.many", BR (0x20, 1, 1, 0, 0)}, {"br.ia.sptk.many.clr", BR (0x20, 1, 1, 0, 1)}, {"br.ia.spnt.many", BR (0x20, 1, 1, 1, 0)}, @@ -156,69 +162,71 @@ struct ia64_opcode ia64_opcodes_b[] = {"br.ia.dptk.many.clr", BR (0x20, 1, 1, 2, 1)}, {"br.ia.dpnt.many", BR (0x20, 1, 1, 3, 0)}, {"br.ia.dpnt.many.clr", BR (0x20, 1, 1, 3, 1)}, - {"br.ret.sptk.few", BR (0x21, 4, 0, 0, 0), MOD_RRBS}, - {"br.ret.sptk", BR (0x21, 4, 0, 0, 0), PSEUDO | MOD_RRBS}, - {"br.ret.sptk.few.clr", BR (0x21, 4, 0, 0, 1), MOD_RRBS}, - {"br.ret.sptk.clr", BR (0x21, 4, 0, 0, 1), PSEUDO | MOD_RRBS}, - {"br.ret.spnt.few", BR (0x21, 4, 0, 1, 0), MOD_RRBS}, - {"br.ret.spnt", BR (0x21, 4, 0, 1, 0), PSEUDO | MOD_RRBS}, - {"br.ret.spnt.few.clr", BR (0x21, 4, 0, 1, 1), MOD_RRBS}, - {"br.ret.spnt.clr", BR (0x21, 4, 0, 1, 1), PSEUDO | MOD_RRBS}, - {"br.ret.dptk.few", BR (0x21, 4, 0, 2, 0), MOD_RRBS}, - {"br.ret.dptk", BR (0x21, 4, 0, 2, 0), PSEUDO | MOD_RRBS}, - {"br.ret.dptk.few.clr", BR (0x21, 4, 0, 2, 1), MOD_RRBS}, - {"br.ret.dptk.clr", BR (0x21, 4, 0, 2, 1), PSEUDO | MOD_RRBS}, - {"br.ret.dpnt.few", BR (0x21, 4, 0, 3, 0), MOD_RRBS}, - {"br.ret.dpnt", BR (0x21, 4, 0, 3, 0), PSEUDO | MOD_RRBS}, - {"br.ret.dpnt.few.clr", BR (0x21, 4, 0, 3, 1), MOD_RRBS}, - {"br.ret.dpnt.clr", BR (0x21, 4, 0, 3, 1), PSEUDO | MOD_RRBS}, - {"br.ret.sptk.many", BR (0x21, 4, 1, 0, 0), MOD_RRBS}, - {"br.ret.sptk.many.clr", BR (0x21, 4, 1, 0, 1), MOD_RRBS}, - {"br.ret.spnt.many", BR (0x21, 4, 1, 1, 0), MOD_RRBS}, - {"br.ret.spnt.many.clr", BR (0x21, 4, 1, 1, 1), MOD_RRBS}, - {"br.ret.dptk.many", BR (0x21, 4, 1, 2, 0), MOD_RRBS}, - {"br.ret.dptk.many.clr", BR (0x21, 4, 1, 2, 1), MOD_RRBS}, - {"br.ret.dpnt.many", BR (0x21, 4, 1, 3, 0), MOD_RRBS}, - {"br.ret.dpnt.many.clr", BR (0x21, 4, 1, 3, 1), MOD_RRBS}, + {"br.ret.sptk.few", BRT (0x21, 4, 0, 0, 0, MOD_RRBS)}, + {"br.ret.sptk", BRT (0x21, 4, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.ret.sptk.few.clr", BRT (0x21, 4, 0, 0, 1, MOD_RRBS)}, + {"br.ret.sptk.clr", BRT (0x21, 4, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.ret.spnt.few", BRT (0x21, 4, 0, 1, 0, MOD_RRBS)}, + {"br.ret.spnt", BRT (0x21, 4, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.ret.spnt.few.clr", BRT (0x21, 4, 0, 1, 1, MOD_RRBS)}, + {"br.ret.spnt.clr", BRT (0x21, 4, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.ret.dptk.few", BRT (0x21, 4, 0, 2, 0, MOD_RRBS)}, + {"br.ret.dptk", BRT (0x21, 4, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.ret.dptk.few.clr", BRT (0x21, 4, 0, 2, 1, MOD_RRBS)}, + {"br.ret.dptk.clr", BRT (0x21, 4, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.ret.dpnt.few", BRT (0x21, 4, 0, 3, 0, MOD_RRBS)}, + {"br.ret.dpnt", BRT (0x21, 4, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.ret.dpnt.few.clr", BRT (0x21, 4, 0, 3, 1, MOD_RRBS)}, + {"br.ret.dpnt.clr", BRT (0x21, 4, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.ret.sptk.many", BRT (0x21, 4, 1, 0, 0, MOD_RRBS)}, + {"br.ret.sptk.many.clr", BRT (0x21, 4, 1, 0, 1, MOD_RRBS)}, + {"br.ret.spnt.many", BRT (0x21, 4, 1, 1, 0, MOD_RRBS)}, + {"br.ret.spnt.many.clr", BRT (0x21, 4, 1, 1, 1, MOD_RRBS)}, + {"br.ret.dptk.many", BRT (0x21, 4, 1, 2, 0, MOD_RRBS)}, + {"br.ret.dptk.many.clr", BRT (0x21, 4, 1, 2, 1, MOD_RRBS)}, + {"br.ret.dpnt.many", BRT (0x21, 4, 1, 3, 0, MOD_RRBS)}, + {"br.ret.dpnt.many.clr", BRT (0x21, 4, 1, 3, 1, MOD_RRBS)}, #undef BR +#undef BRP +#undef BRT - {"cover", B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS}, - {"clrrrb", B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS}, - {"clrrrb.pr", B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS}, - {"rfi", B0, OpX6 (0, 0x08), {0, }, NO_PRED | LAST | PRIV | MOD_RRBS}, - {"bsw.0", B0, OpX6 (0, 0x0c), {0, }, NO_PRED | LAST | PRIV}, - {"bsw.1", B0, OpX6 (0, 0x0d), {0, }, NO_PRED | LAST | PRIV}, - {"epc", B0, OpX6 (0, 0x10), {0, }, NO_PRED}, + {"cover", B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL}, + {"clrrrb", B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL}, + {"clrrrb.pr", B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS, 0, NULL}, + {"rfi", B0, OpX6 (0, 0x08), {0, }, NO_PRED | LAST | PRIV | MOD_RRBS, 0, NULL}, + {"bsw.0", B0, OpX6 (0, 0x0c), {0, }, NO_PRED | LAST | PRIV, 0, NULL}, + {"bsw.1", B0, OpX6 (0, 0x0d), {0, }, NO_PRED | LAST | PRIV, 0, NULL}, + {"epc", B0, OpX6 (0, 0x10), {0, }, NO_PRED, 0, NULL}, - {"break.b", B0, OpX6 (0, 0x00), {IMMU21}}, + {"break.b", B0, OpX6 (0, 0x00), {IMMU21}, EMPTY}, - {"br.call.sptk.few", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}}, - {"br.call.sptk", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}, PSEUDO}, - {"br.call.sptk.few.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}}, - {"br.call.sptk.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}, PSEUDO}, - {"br.call.spnt.few", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}}, - {"br.call.spnt", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}, PSEUDO}, - {"br.call.spnt.few.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}}, - {"br.call.spnt.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}, PSEUDO}, - {"br.call.dptk.few", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}}, - {"br.call.dptk", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}, PSEUDO}, - {"br.call.dptk.few.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}}, - {"br.call.dptk.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}, PSEUDO}, - {"br.call.dpnt.few", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}}, - {"br.call.dpnt", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}, PSEUDO}, - {"br.call.dpnt.few.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}}, - {"br.call.dpnt.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}, PSEUDO}, - {"br.call.sptk.many", B, OpPaWhcD (1, 1, 1, 0), {B1, B2}}, - {"br.call.sptk.many.clr", B, OpPaWhcD (1, 1, 1, 1), {B1, B2}}, - {"br.call.spnt.many", B, OpPaWhcD (1, 1, 3, 0), {B1, B2}}, - {"br.call.spnt.many.clr", B, OpPaWhcD (1, 1, 3, 1), {B1, B2}}, - {"br.call.dptk.many", B, OpPaWhcD (1, 1, 5, 0), {B1, B2}}, - {"br.call.dptk.many.clr", B, OpPaWhcD (1, 1, 5, 1), {B1, B2}}, - {"br.call.dpnt.many", B, OpPaWhcD (1, 1, 7, 0), {B1, B2}}, - {"br.call.dpnt.many.clr", B, OpPaWhcD (1, 1, 7, 1), {B1, B2}}, + {"br.call.sptk.few", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}, EMPTY}, + {"br.call.sptk", B, OpPaWhcD (1, 0, 1, 0), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.sptk.few.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}, EMPTY}, + {"br.call.sptk.clr", B, OpPaWhcD (1, 0, 1, 1), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.spnt.few", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}, EMPTY}, + {"br.call.spnt", B, OpPaWhcD (1, 0, 3, 0), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.spnt.few.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}, EMPTY}, + {"br.call.spnt.clr", B, OpPaWhcD (1, 0, 3, 1), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.dptk.few", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}, EMPTY}, + {"br.call.dptk", B, OpPaWhcD (1, 0, 5, 0), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.dptk.few.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}, EMPTY}, + {"br.call.dptk.clr", B, OpPaWhcD (1, 0, 5, 1), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.dpnt.few", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}, EMPTY}, + {"br.call.dpnt", B, OpPaWhcD (1, 0, 7, 0), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.dpnt.few.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}, EMPTY}, + {"br.call.dpnt.clr", B, OpPaWhcD (1, 0, 7, 1), {B1, B2}, PSEUDO, 0, NULL}, + {"br.call.sptk.many", B, OpPaWhcD (1, 1, 1, 0), {B1, B2}, EMPTY}, + {"br.call.sptk.many.clr", B, OpPaWhcD (1, 1, 1, 1), {B1, B2}, EMPTY}, + {"br.call.spnt.many", B, OpPaWhcD (1, 1, 3, 0), {B1, B2}, EMPTY}, + {"br.call.spnt.many.clr", B, OpPaWhcD (1, 1, 3, 1), {B1, B2}, EMPTY}, + {"br.call.dptk.many", B, OpPaWhcD (1, 1, 5, 0), {B1, B2}, EMPTY}, + {"br.call.dptk.many.clr", B, OpPaWhcD (1, 1, 5, 1), {B1, B2}, EMPTY}, + {"br.call.dpnt.many", B, OpPaWhcD (1, 1, 7, 0), {B1, B2}, EMPTY}, + {"br.call.dpnt.many.clr", B, OpPaWhcD (1, 1, 7, 1), {B1, B2}, EMPTY}, #define BRP(a,b,c) \ - B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED + B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED, 0, NULL {"brp.sptk", BRP (0x10, 0, 0)}, {"brp.dptk", BRP (0x10, 0, 2)}, {"brp.sptk.imp", BRP (0x10, 1, 0)}, @@ -229,10 +237,11 @@ struct ia64_opcode ia64_opcodes_b[] = {"brp.ret.dptk.imp", BRP (0x11, 1, 2)}, #undef BRP - {"nop.b", B0, OpX6 (2, 0x00), {IMMU21}}, + {"nop.b", B0, OpX6 (2, 0x00), {IMMU21}, EMPTY}, + {"hint.b", B0, OpX6 (2, 0x01), {IMMU21}, EMPTY}, #define BR(a,b) \ - B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO + B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO, 0, NULL {"br.few", BR (0, 0)}, {"br", BR (0, 0)}, {"br.few.clr", BR (0, 1)}, @@ -242,23 +251,25 @@ struct ia64_opcode ia64_opcodes_b[] = #undef BR #define BR(a,b,c) \ - B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c} + B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c}, EMPTY +#define BRP(a,b,c) \ + B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c}, PSEUDO, 0, NULL {"br.cond.sptk.few", BR (0, 0, 0)}, - {"br.cond.sptk", BR (0, 0, 0), PSEUDO}, + {"br.cond.sptk", BRP (0, 0, 0)}, {"br.cond.sptk.few.clr", BR (0, 0, 1)}, - {"br.cond.sptk.clr", BR (0, 0, 1), PSEUDO}, + {"br.cond.sptk.clr", BRP (0, 0, 1)}, {"br.cond.spnt.few", BR (0, 1, 0)}, - {"br.cond.spnt", BR (0, 1, 0), PSEUDO}, + {"br.cond.spnt", BRP (0, 1, 0)}, {"br.cond.spnt.few.clr", BR (0, 1, 1)}, - {"br.cond.spnt.clr", BR (0, 1, 1), PSEUDO}, + {"br.cond.spnt.clr", BRP (0, 1, 1)}, {"br.cond.dptk.few", BR (0, 2, 0)}, - {"br.cond.dptk", BR (0, 2, 0), PSEUDO}, + {"br.cond.dptk", BRP (0, 2, 0)}, {"br.cond.dptk.few.clr", BR (0, 2, 1)}, - {"br.cond.dptk.clr", BR (0, 2, 1), PSEUDO}, + {"br.cond.dptk.clr", BRP (0, 2, 1)}, {"br.cond.dpnt.few", BR (0, 3, 0)}, - {"br.cond.dpnt", BR (0, 3, 0), PSEUDO}, + {"br.cond.dpnt", BRP (0, 3, 0)}, {"br.cond.dpnt.few.clr", BR (0, 3, 1)}, - {"br.cond.dpnt.clr", BR (0, 3, 1), PSEUDO}, + {"br.cond.dpnt.clr", BRP (0, 3, 1)}, {"br.cond.sptk.many", BR (1, 0, 0)}, {"br.cond.sptk.many.clr", BR (1, 0, 1)}, {"br.cond.spnt.many", BR (1, 1, 0)}, @@ -268,21 +279,21 @@ struct ia64_opcode ia64_opcodes_b[] = {"br.cond.dpnt.many", BR (1, 3, 0)}, {"br.cond.dpnt.many.clr", BR (1, 3, 1)}, {"br.sptk.few", BR (0, 0, 0)}, - {"br.sptk", BR (0, 0, 0), PSEUDO}, + {"br.sptk", BRP (0, 0, 0)}, {"br.sptk.few.clr", BR (0, 0, 1)}, - {"br.sptk.clr", BR (0, 0, 1), PSEUDO}, + {"br.sptk.clr", BRP (0, 0, 1)}, {"br.spnt.few", BR (0, 1, 0)}, - {"br.spnt", BR (0, 1, 0), PSEUDO}, + {"br.spnt", BRP (0, 1, 0)}, {"br.spnt.few.clr", BR (0, 1, 1)}, - {"br.spnt.clr", BR (0, 1, 1), PSEUDO}, + {"br.spnt.clr", BRP (0, 1, 1)}, {"br.dptk.few", BR (0, 2, 0)}, - {"br.dptk", BR (0, 2, 0), PSEUDO}, + {"br.dptk", BRP (0, 2, 0)}, {"br.dptk.few.clr", BR (0, 2, 1)}, - {"br.dptk.clr", BR (0, 2, 1), PSEUDO}, + {"br.dptk.clr", BRP (0, 2, 1)}, {"br.dpnt.few", BR (0, 3, 0)}, - {"br.dpnt", BR (0, 3, 0), PSEUDO}, + {"br.dpnt", BRP (0, 3, 0)}, {"br.dpnt.few.clr", BR (0, 3, 1)}, - {"br.dpnt.clr", BR (0, 3, 1), PSEUDO}, + {"br.dpnt.clr", BRP (0, 3, 1)}, {"br.sptk.many", BR (1, 0, 0)}, {"br.sptk.many.clr", BR (1, 0, 1)}, {"br.spnt.many", BR (1, 1, 0)}, @@ -292,77 +303,80 @@ struct ia64_opcode ia64_opcodes_b[] = {"br.dpnt.many", BR (1, 3, 0)}, {"br.dpnt.many.clr", BR (1, 3, 1)}, #undef BR +#undef BRP -#define BR(a,b,c,d) \ - B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 - {"br.wexit.sptk.few", BR (2, 0, 0, 0) | MOD_RRBS}, - {"br.wexit.sptk", BR (2, 0, 0, 0) | PSEUDO | MOD_RRBS}, - {"br.wexit.sptk.few.clr", BR (2, 0, 0, 1) | MOD_RRBS}, - {"br.wexit.sptk.clr", BR (2, 0, 0, 1) | PSEUDO | MOD_RRBS}, - {"br.wexit.spnt.few", BR (2, 0, 1, 0) | MOD_RRBS}, - {"br.wexit.spnt", BR (2, 0, 1, 0) | PSEUDO | MOD_RRBS}, - {"br.wexit.spnt.few.clr", BR (2, 0, 1, 1) | MOD_RRBS}, - {"br.wexit.spnt.clr", BR (2, 0, 1, 1) | PSEUDO | MOD_RRBS}, - {"br.wexit.dptk.few", BR (2, 0, 2, 0) | MOD_RRBS}, - {"br.wexit.dptk", BR (2, 0, 2, 0) | PSEUDO | MOD_RRBS}, - {"br.wexit.dptk.few.clr", BR (2, 0, 2, 1) | MOD_RRBS}, - {"br.wexit.dptk.clr", BR (2, 0, 2, 1) | PSEUDO | MOD_RRBS}, - {"br.wexit.dpnt.few", BR (2, 0, 3, 0) | MOD_RRBS}, - {"br.wexit.dpnt", BR (2, 0, 3, 0) | PSEUDO | MOD_RRBS}, - {"br.wexit.dpnt.few.clr", BR (2, 0, 3, 1) | MOD_RRBS}, - {"br.wexit.dpnt.clr", BR (2, 0, 3, 1) | PSEUDO | MOD_RRBS}, - {"br.wexit.sptk.many", BR (2, 1, 0, 0) | MOD_RRBS}, - {"br.wexit.sptk.many.clr", BR (2, 1, 0, 1) | MOD_RRBS}, - {"br.wexit.spnt.many", BR (2, 1, 1, 0) | MOD_RRBS}, - {"br.wexit.spnt.many.clr", BR (2, 1, 1, 1) | MOD_RRBS}, - {"br.wexit.dptk.many", BR (2, 1, 2, 0) | MOD_RRBS}, - {"br.wexit.dptk.many.clr", BR (2, 1, 2, 1) | MOD_RRBS}, - {"br.wexit.dpnt.many", BR (2, 1, 3, 0) | MOD_RRBS}, - {"br.wexit.dpnt.many.clr", BR (2, 1, 3, 1) | MOD_RRBS}, - {"br.wtop.sptk.few", BR (3, 0, 0, 0) | MOD_RRBS}, - {"br.wtop.sptk", BR (3, 0, 0, 0) | PSEUDO | MOD_RRBS}, - {"br.wtop.sptk.few.clr", BR (3, 0, 0, 1) | MOD_RRBS}, - {"br.wtop.sptk.clr", BR (3, 0, 0, 1) | PSEUDO | MOD_RRBS}, - {"br.wtop.spnt.few", BR (3, 0, 1, 0) | MOD_RRBS}, - {"br.wtop.spnt", BR (3, 0, 1, 0) | PSEUDO | MOD_RRBS}, - {"br.wtop.spnt.few.clr", BR (3, 0, 1, 1) | MOD_RRBS}, - {"br.wtop.spnt.clr", BR (3, 0, 1, 1) | PSEUDO | MOD_RRBS}, - {"br.wtop.dptk.few", BR (3, 0, 2, 0) | MOD_RRBS}, - {"br.wtop.dptk", BR (3, 0, 2, 0) | PSEUDO | MOD_RRBS}, - {"br.wtop.dptk.few.clr", BR (3, 0, 2, 1) | MOD_RRBS}, - {"br.wtop.dptk.clr", BR (3, 0, 2, 1) | PSEUDO | MOD_RRBS}, - {"br.wtop.dpnt.few", BR (3, 0, 3, 0) | MOD_RRBS}, - {"br.wtop.dpnt", BR (3, 0, 3, 0) | PSEUDO | MOD_RRBS}, - {"br.wtop.dpnt.few.clr", BR (3, 0, 3, 1) | MOD_RRBS}, - {"br.wtop.dpnt.clr", BR (3, 0, 3, 1) | PSEUDO | MOD_RRBS}, - {"br.wtop.sptk.many", BR (3, 1, 0, 0) | MOD_RRBS}, - {"br.wtop.sptk.many.clr", BR (3, 1, 0, 1) | MOD_RRBS}, - {"br.wtop.spnt.many", BR (3, 1, 1, 0) | MOD_RRBS}, - {"br.wtop.spnt.many.clr", BR (3, 1, 1, 1) | MOD_RRBS}, - {"br.wtop.dptk.many", BR (3, 1, 2, 0) | MOD_RRBS}, - {"br.wtop.dptk.many.clr", BR (3, 1, 2, 1) | MOD_RRBS}, - {"br.wtop.dpnt.many", BR (3, 1, 3, 0) | MOD_RRBS}, - {"br.wtop.dpnt.many.clr", BR (3, 1, 3, 1) | MOD_RRBS}, +#define BR(a,b,c,d, e) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | e, 0, NULL + {"br.wexit.sptk.few", BR (2, 0, 0, 0, MOD_RRBS)}, + {"br.wexit.sptk", BR (2, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.wexit.sptk.few.clr", BR (2, 0, 0, 1, MOD_RRBS)}, + {"br.wexit.sptk.clr", BR (2, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.wexit.spnt.few", BR (2, 0, 1, 0, MOD_RRBS)}, + {"br.wexit.spnt", BR (2, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.wexit.spnt.few.clr", BR (2, 0, 1, 1, MOD_RRBS)}, + {"br.wexit.spnt.clr", BR (2, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.wexit.dptk.few", BR (2, 0, 2, 0, MOD_RRBS)}, + {"br.wexit.dptk", BR (2, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.wexit.dptk.few.clr", BR (2, 0, 2, 1, MOD_RRBS)}, + {"br.wexit.dptk.clr", BR (2, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.wexit.dpnt.few", BR (2, 0, 3, 0, MOD_RRBS)}, + {"br.wexit.dpnt", BR (2, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.wexit.dpnt.few.clr", BR (2, 0, 3, 1, MOD_RRBS)}, + {"br.wexit.dpnt.clr", BR (2, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.wexit.sptk.many", BR (2, 1, 0, 0, MOD_RRBS)}, + {"br.wexit.sptk.many.clr", BR (2, 1, 0, 1, MOD_RRBS)}, + {"br.wexit.spnt.many", BR (2, 1, 1, 0, MOD_RRBS)}, + {"br.wexit.spnt.many.clr", BR (2, 1, 1, 1, MOD_RRBS)}, + {"br.wexit.dptk.many", BR (2, 1, 2, 0, MOD_RRBS)}, + {"br.wexit.dptk.many.clr", BR (2, 1, 2, 1, MOD_RRBS)}, + {"br.wexit.dpnt.many", BR (2, 1, 3, 0, MOD_RRBS)}, + {"br.wexit.dpnt.many.clr", BR (2, 1, 3, 1, MOD_RRBS)}, + {"br.wtop.sptk.few", BR (3, 0, 0, 0, MOD_RRBS)}, + {"br.wtop.sptk", BR (3, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.wtop.sptk.few.clr", BR (3, 0, 0, 1, MOD_RRBS)}, + {"br.wtop.sptk.clr", BR (3, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.wtop.spnt.few", BR (3, 0, 1, 0, MOD_RRBS)}, + {"br.wtop.spnt", BR (3, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.wtop.spnt.few.clr", BR (3, 0, 1, 1, MOD_RRBS)}, + {"br.wtop.spnt.clr", BR (3, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.wtop.dptk.few", BR (3, 0, 2, 0, MOD_RRBS)}, + {"br.wtop.dptk", BR (3, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.wtop.dptk.few.clr", BR (3, 0, 2, 1, MOD_RRBS)}, + {"br.wtop.dptk.clr", BR (3, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.wtop.dpnt.few", BR (3, 0, 3, 0, MOD_RRBS)}, + {"br.wtop.dpnt", BR (3, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.wtop.dpnt.few.clr", BR (3, 0, 3, 1, MOD_RRBS)}, + {"br.wtop.dpnt.clr", BR (3, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.wtop.sptk.many", BR (3, 1, 0, 0, MOD_RRBS)}, + {"br.wtop.sptk.many.clr", BR (3, 1, 0, 1, MOD_RRBS)}, + {"br.wtop.spnt.many", BR (3, 1, 1, 0, MOD_RRBS)}, + {"br.wtop.spnt.many.clr", BR (3, 1, 1, 1, MOD_RRBS)}, + {"br.wtop.dptk.many", BR (3, 1, 2, 0, MOD_RRBS)}, + {"br.wtop.dptk.many.clr", BR (3, 1, 2, 1, MOD_RRBS)}, + {"br.wtop.dpnt.many", BR (3, 1, 3, 0, MOD_RRBS)}, + {"br.wtop.dpnt.many.clr", BR (3, 1, 3, 1, MOD_RRBS)}, #undef BR #define BR(a,b,c,d) \ - B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED, 0, NULL +#define BRT(a,b,c,d,e) \ + B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED | e, 0, NULL {"br.cloop.sptk.few", BR (5, 0, 0, 0)}, - {"br.cloop.sptk", BR (5, 0, 0, 0) | PSEUDO}, + {"br.cloop.sptk", BRT (5, 0, 0, 0, PSEUDO)}, {"br.cloop.sptk.few.clr", BR (5, 0, 0, 1)}, - {"br.cloop.sptk.clr", BR (5, 0, 0, 1) | PSEUDO}, + {"br.cloop.sptk.clr", BRT (5, 0, 0, 1, PSEUDO)}, {"br.cloop.spnt.few", BR (5, 0, 1, 0)}, - {"br.cloop.spnt", BR (5, 0, 1, 0) | PSEUDO}, + {"br.cloop.spnt", BRT (5, 0, 1, 0, PSEUDO)}, {"br.cloop.spnt.few.clr", BR (5, 0, 1, 1)}, - {"br.cloop.spnt.clr", BR (5, 0, 1, 1) | PSEUDO}, + {"br.cloop.spnt.clr", BRT (5, 0, 1, 1, PSEUDO)}, {"br.cloop.dptk.few", BR (5, 0, 2, 0)}, - {"br.cloop.dptk", BR (5, 0, 2, 0) | PSEUDO}, + {"br.cloop.dptk", BRT (5, 0, 2, 0, PSEUDO)}, {"br.cloop.dptk.few.clr", BR (5, 0, 2, 1)}, - {"br.cloop.dptk.clr", BR (5, 0, 2, 1) | PSEUDO}, + {"br.cloop.dptk.clr", BRT (5, 0, 2, 1, PSEUDO)}, {"br.cloop.dpnt.few", BR (5, 0, 3, 0)}, - {"br.cloop.dpnt", BR (5, 0, 3, 0) | PSEUDO}, + {"br.cloop.dpnt", BRT (5, 0, 3, 0, PSEUDO)}, {"br.cloop.dpnt.few.clr", BR (5, 0, 3, 1)}, - {"br.cloop.dpnt.clr", BR (5, 0, 3, 1) | PSEUDO}, + {"br.cloop.dpnt.clr", BRT (5, 0, 3, 1, PSEUDO)}, {"br.cloop.sptk.many", BR (5, 1, 0, 0)}, {"br.cloop.sptk.many.clr", BR (5, 1, 0, 1)}, {"br.cloop.spnt.many", BR (5, 1, 1, 0)}, @@ -371,87 +385,85 @@ struct ia64_opcode ia64_opcodes_b[] = {"br.cloop.dptk.many.clr", BR (5, 1, 2, 1)}, {"br.cloop.dpnt.many", BR (5, 1, 3, 0)}, {"br.cloop.dpnt.many.clr", BR (5, 1, 3, 1)}, - {"br.cexit.sptk.few", BR (6, 0, 0, 0) | MOD_RRBS}, - {"br.cexit.sptk", BR (6, 0, 0, 0) | PSEUDO | MOD_RRBS}, - {"br.cexit.sptk.few.clr", BR (6, 0, 0, 1) | MOD_RRBS}, - {"br.cexit.sptk.clr", BR (6, 0, 0, 1) | PSEUDO | MOD_RRBS}, - {"br.cexit.spnt.few", BR (6, 0, 1, 0) | MOD_RRBS}, - {"br.cexit.spnt", BR (6, 0, 1, 0) | PSEUDO | MOD_RRBS}, - {"br.cexit.spnt.few.clr", BR (6, 0, 1, 1) | MOD_RRBS}, - {"br.cexit.spnt.clr", BR (6, 0, 1, 1) | PSEUDO | MOD_RRBS}, - {"br.cexit.dptk.few", BR (6, 0, 2, 0) | MOD_RRBS}, - {"br.cexit.dptk", BR (6, 0, 2, 0) | PSEUDO | MOD_RRBS}, - {"br.cexit.dptk.few.clr", BR (6, 0, 2, 1) | MOD_RRBS}, - {"br.cexit.dptk.clr", BR (6, 0, 2, 1) | PSEUDO | MOD_RRBS}, - {"br.cexit.dpnt.few", BR (6, 0, 3, 0) | MOD_RRBS}, - {"br.cexit.dpnt", BR (6, 0, 3, 0) | PSEUDO | MOD_RRBS}, - {"br.cexit.dpnt.few.clr", BR (6, 0, 3, 1) | MOD_RRBS}, - {"br.cexit.dpnt.clr", BR (6, 0, 3, 1) | PSEUDO | MOD_RRBS}, - {"br.cexit.sptk.many", BR (6, 1, 0, 0) | MOD_RRBS}, - {"br.cexit.sptk.many.clr", BR (6, 1, 0, 1) | MOD_RRBS}, - {"br.cexit.spnt.many", BR (6, 1, 1, 0) | MOD_RRBS}, - {"br.cexit.spnt.many.clr", BR (6, 1, 1, 1) | MOD_RRBS}, - {"br.cexit.dptk.many", BR (6, 1, 2, 0) | MOD_RRBS}, - {"br.cexit.dptk.many.clr", BR (6, 1, 2, 1) | MOD_RRBS}, - {"br.cexit.dpnt.many", BR (6, 1, 3, 0) | MOD_RRBS}, - {"br.cexit.dpnt.many.clr", BR (6, 1, 3, 1) | MOD_RRBS}, - {"br.ctop.sptk.few", BR (7, 0, 0, 0) | MOD_RRBS}, - {"br.ctop.sptk", BR (7, 0, 0, 0) | PSEUDO | MOD_RRBS}, - {"br.ctop.sptk.few.clr", BR (7, 0, 0, 1) | MOD_RRBS}, - {"br.ctop.sptk.clr", BR (7, 0, 0, 1) | PSEUDO | MOD_RRBS}, - {"br.ctop.spnt.few", BR (7, 0, 1, 0) | MOD_RRBS}, - {"br.ctop.spnt", BR (7, 0, 1, 0) | PSEUDO | MOD_RRBS}, - {"br.ctop.spnt.few.clr", BR (7, 0, 1, 1) | MOD_RRBS}, - {"br.ctop.spnt.clr", BR (7, 0, 1, 1) | PSEUDO | MOD_RRBS}, - {"br.ctop.dptk.few", BR (7, 0, 2, 0) | MOD_RRBS}, - {"br.ctop.dptk", BR (7, 0, 2, 0) | PSEUDO | MOD_RRBS}, - {"br.ctop.dptk.few.clr", BR (7, 0, 2, 1) | MOD_RRBS}, - {"br.ctop.dptk.clr", BR (7, 0, 2, 1) | PSEUDO | MOD_RRBS}, - {"br.ctop.dpnt.few", BR (7, 0, 3, 0) | MOD_RRBS}, - {"br.ctop.dpnt", BR (7, 0, 3, 0) | PSEUDO | MOD_RRBS}, - {"br.ctop.dpnt.few.clr", BR (7, 0, 3, 1) | MOD_RRBS}, - {"br.ctop.dpnt.clr", BR (7, 0, 3, 1) | PSEUDO | MOD_RRBS}, - {"br.ctop.sptk.many", BR (7, 1, 0, 0) | MOD_RRBS}, - {"br.ctop.sptk.many.clr", BR (7, 1, 0, 1) | MOD_RRBS}, - {"br.ctop.spnt.many", BR (7, 1, 1, 0) | MOD_RRBS}, - {"br.ctop.spnt.many.clr", BR (7, 1, 1, 1) | MOD_RRBS}, - {"br.ctop.dptk.many", BR (7, 1, 2, 0) | MOD_RRBS}, - {"br.ctop.dptk.many.clr", BR (7, 1, 2, 1) | MOD_RRBS}, - {"br.ctop.dpnt.many", BR (7, 1, 3, 0) | MOD_RRBS}, - {"br.ctop.dpnt.many.clr", BR (7, 1, 3, 1) | MOD_RRBS}, - -#undef BR -#define BR(a,b,c,d) \ - B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 - {"br.call.sptk.few", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}}, - {"br.call.sptk", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, PSEUDO}, - {"br.call.sptk.few.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}}, - {"br.call.sptk.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, PSEUDO}, - {"br.call.spnt.few", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}}, - {"br.call.spnt", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, PSEUDO}, - {"br.call.spnt.few.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}}, - {"br.call.spnt.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, PSEUDO}, - {"br.call.dptk.few", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}}, - {"br.call.dptk", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, PSEUDO}, - {"br.call.dptk.few.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}}, - {"br.call.dptk.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, PSEUDO}, - {"br.call.dpnt.few", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}}, - {"br.call.dpnt", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, PSEUDO}, - {"br.call.dpnt.few.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}}, - {"br.call.dpnt.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, PSEUDO}, - {"br.call.sptk.many", B, OpPaWhaD (5, 1, 0, 0), {B1, TGT25c}}, - {"br.call.sptk.many.clr", B, OpPaWhaD (5, 1, 0, 1), {B1, TGT25c}}, - {"br.call.spnt.many", B, OpPaWhaD (5, 1, 1, 0), {B1, TGT25c}}, - {"br.call.spnt.many.clr", B, OpPaWhaD (5, 1, 1, 1), {B1, TGT25c}}, - {"br.call.dptk.many", B, OpPaWhaD (5, 1, 2, 0), {B1, TGT25c}}, - {"br.call.dptk.many.clr", B, OpPaWhaD (5, 1, 2, 1), {B1, TGT25c}}, - {"br.call.dpnt.many", B, OpPaWhaD (5, 1, 3, 0), {B1, TGT25c}}, - {"br.call.dpnt.many.clr", B, OpPaWhaD (5, 1, 3, 1), {B1, TGT25c}}, + {"br.cexit.sptk.few", BRT (6, 0, 0, 0, MOD_RRBS)}, + {"br.cexit.sptk", BRT (6, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.cexit.sptk.few.clr", BRT (6, 0, 0, 1, MOD_RRBS)}, + {"br.cexit.sptk.clr", BRT (6, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.cexit.spnt.few", BRT (6, 0, 1, 0, MOD_RRBS)}, + {"br.cexit.spnt", BRT (6, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.cexit.spnt.few.clr", BRT (6, 0, 1, 1, MOD_RRBS)}, + {"br.cexit.spnt.clr", BRT (6, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.cexit.dptk.few", BRT (6, 0, 2, 0, MOD_RRBS)}, + {"br.cexit.dptk", BRT (6, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.cexit.dptk.few.clr", BRT (6, 0, 2, 1, MOD_RRBS)}, + {"br.cexit.dptk.clr", BRT (6, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.cexit.dpnt.few", BRT (6, 0, 3, 0, MOD_RRBS)}, + {"br.cexit.dpnt", BRT (6, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.cexit.dpnt.few.clr", BRT (6, 0, 3, 1, MOD_RRBS)}, + {"br.cexit.dpnt.clr", BRT (6, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.cexit.sptk.many", BRT (6, 1, 0, 0, MOD_RRBS)}, + {"br.cexit.sptk.many.clr", BRT (6, 1, 0, 1, MOD_RRBS)}, + {"br.cexit.spnt.many", BRT (6, 1, 1, 0, MOD_RRBS)}, + {"br.cexit.spnt.many.clr", BRT (6, 1, 1, 1, MOD_RRBS)}, + {"br.cexit.dptk.many", BRT (6, 1, 2, 0, MOD_RRBS)}, + {"br.cexit.dptk.many.clr", BRT (6, 1, 2, 1, MOD_RRBS)}, + {"br.cexit.dpnt.many", BRT (6, 1, 3, 0, MOD_RRBS)}, + {"br.cexit.dpnt.many.clr", BRT (6, 1, 3, 1, MOD_RRBS)}, + {"br.ctop.sptk.few", BRT (7, 0, 0, 0, MOD_RRBS)}, + {"br.ctop.sptk", BRT (7, 0, 0, 0, PSEUDO | MOD_RRBS)}, + {"br.ctop.sptk.few.clr", BRT (7, 0, 0, 1, MOD_RRBS)}, + {"br.ctop.sptk.clr", BRT (7, 0, 0, 1, PSEUDO | MOD_RRBS)}, + {"br.ctop.spnt.few", BRT (7, 0, 1, 0, MOD_RRBS)}, + {"br.ctop.spnt", BRT (7, 0, 1, 0, PSEUDO | MOD_RRBS)}, + {"br.ctop.spnt.few.clr", BRT (7, 0, 1, 1, MOD_RRBS)}, + {"br.ctop.spnt.clr", BRT (7, 0, 1, 1, PSEUDO | MOD_RRBS)}, + {"br.ctop.dptk.few", BRT (7, 0, 2, 0, MOD_RRBS)}, + {"br.ctop.dptk", BRT (7, 0, 2, 0, PSEUDO | MOD_RRBS)}, + {"br.ctop.dptk.few.clr", BRT (7, 0, 2, 1, MOD_RRBS)}, + {"br.ctop.dptk.clr", BRT (7, 0, 2, 1, PSEUDO | MOD_RRBS)}, + {"br.ctop.dpnt.few", BRT (7, 0, 3, 0, MOD_RRBS)}, + {"br.ctop.dpnt", BRT (7, 0, 3, 0, PSEUDO | MOD_RRBS)}, + {"br.ctop.dpnt.few.clr", BRT (7, 0, 3, 1, MOD_RRBS)}, + {"br.ctop.dpnt.clr", BRT (7, 0, 3, 1, PSEUDO | MOD_RRBS)}, + {"br.ctop.sptk.many", BRT (7, 1, 0, 0, MOD_RRBS)}, + {"br.ctop.sptk.many.clr", BRT (7, 1, 0, 1, MOD_RRBS)}, + {"br.ctop.spnt.many", BRT (7, 1, 1, 0, MOD_RRBS)}, + {"br.ctop.spnt.many.clr", BRT (7, 1, 1, 1, MOD_RRBS)}, + {"br.ctop.dptk.many", BRT (7, 1, 2, 0, MOD_RRBS)}, + {"br.ctop.dptk.many.clr", BRT (7, 1, 2, 1, MOD_RRBS)}, + {"br.ctop.dpnt.many", BRT (7, 1, 3, 0, MOD_RRBS)}, + {"br.ctop.dpnt.many.clr", BRT (7, 1, 3, 1, MOD_RRBS)}, #undef BR +#undef BRT + + {"br.call.sptk.few", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, EMPTY}, + {"br.call.sptk", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.sptk.few.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, EMPTY}, + {"br.call.sptk.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.spnt.few", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, EMPTY}, + {"br.call.spnt", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.spnt.few.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, EMPTY}, + {"br.call.spnt.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.dptk.few", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, EMPTY}, + {"br.call.dptk", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.dptk.few.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, EMPTY}, + {"br.call.dptk.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.dpnt.few", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, EMPTY}, + {"br.call.dpnt", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.dpnt.few.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, EMPTY}, + {"br.call.dpnt.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, PSEUDO, 0, NULL}, + {"br.call.sptk.many", B, OpPaWhaD (5, 1, 0, 0), {B1, TGT25c}, EMPTY}, + {"br.call.sptk.many.clr", B, OpPaWhaD (5, 1, 0, 1), {B1, TGT25c}, EMPTY}, + {"br.call.spnt.many", B, OpPaWhaD (5, 1, 1, 0), {B1, TGT25c}, EMPTY}, + {"br.call.spnt.many.clr", B, OpPaWhaD (5, 1, 1, 1), {B1, TGT25c}, EMPTY}, + {"br.call.dptk.many", B, OpPaWhaD (5, 1, 2, 0), {B1, TGT25c}, EMPTY}, + {"br.call.dptk.many.clr", B, OpPaWhaD (5, 1, 2, 1), {B1, TGT25c}, EMPTY}, + {"br.call.dpnt.many", B, OpPaWhaD (5, 1, 3, 0), {B1, TGT25c}, EMPTY}, + {"br.call.dpnt.many.clr", B, OpPaWhaD (5, 1, 3, 1), {B1, TGT25c}, EMPTY}, - /* branch predict */ + /* Branch predict. */ #define BRP(a,b) \ - B0, OpIhWhb (7, a, b), {TGT25c, TAG13}, NO_PRED + B0, OpIhWhb (7, a, b), {TGT25c, TAG13}, NO_PRED, 0, NULL {"brp.sptk", BRP (0, 0)}, {"brp.loop", BRP (0, 1)}, {"brp.dptk", BRP (0, 2)}, @@ -462,7 +474,7 @@ struct ia64_opcode ia64_opcodes_b[] = {"brp.exit.imp", BRP (1, 3)}, #undef BRP - {0} + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} }; #undef B0 @@ -494,3 +506,4 @@ struct ia64_opcode ia64_opcodes_b[] = #undef OpX6BtypePaWhaDPr #undef OpIhWhb #undef OpX6IhWhb +#undef EMPTY diff --git a/contrib/binutils/opcodes/ia64-opc-d.c b/contrib/binutils/opcodes/ia64-opc-d.c index 27390f5..d916085 100644 --- a/contrib/binutils/opcodes/ia64-opc-d.c +++ b/contrib/binutils/opcodes/ia64-opc-d.c @@ -1,14 +1,34 @@ +/* ia64-opc-d.c -- IA-64 `D' opcode table. + Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. + Contributed by David Mosberger-Tang <davidm@hpl.hp.com> + + This file is part of GDB, GAS, and the GNU binutils. + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + struct ia64_opcode ia64_opcodes_d[] = { - {"add", IA64_TYPE_DYN, 1, 0, 0, - {IA64_OPND_R1, IA64_OPND_IMM22, IA64_OPND_R3_2}}, - {"add", IA64_TYPE_DYN, 1, 0, 0, - {IA64_OPND_R1, IA64_OPND_IMM14, IA64_OPND_R3}}, - {"break", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}}, - {"chk.s", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_R2, IA64_OPND_TGT25b}}, - {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_AR3}}, - {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_IMM8}}, - {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_R2}}, - {"nop", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}}, - {0} + {"add", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_IMM22, IA64_OPND_R3_2}, 0, 0, NULL}, + {"add", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_IMM14, IA64_OPND_R3}, 0, 0, NULL}, + {"break", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, + {"chk.s", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_R2, IA64_OPND_TGT25b}, 0, 0, NULL}, + {"hint", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_AR3}, 0, 0, NULL}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_IMM8}, 0, 0, NULL}, + {"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_R2}, 0, 0, NULL}, + {"nop", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}, 0, 0, NULL}, + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} }; diff --git a/contrib/binutils/opcodes/ia64-opc-f.c b/contrib/binutils/opcodes/ia64-opc-f.c index 2f898c6..89dbcde 100644 --- a/contrib/binutils/opcodes/ia64-opc-f.c +++ b/contrib/binutils/opcodes/ia64-opc-f.c @@ -1,5 +1,5 @@ /* ia64-opc-f.c -- IA-64 `F' opcode table. - Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. Contributed by David Mosberger-Tang <davidm@hpl.hp.com> This file is part of GDB, GAS, and the GNU binutils. @@ -36,6 +36,7 @@ #define bXb(x) (((ia64_insn) ((x) & 0x1)) << 33) #define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34) #define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) #define mF2 bF2 (-1) #define mF4 bF4 (-1) @@ -48,6 +49,7 @@ #define mXb bXb (-1) #define mX2 bX2 (-1) #define mX6 bX6 (-1) +#define mY bY (-1) #define OpXa(a,b) (bOp (a) | bXa (b)), (mOp | mXa) #define OpXaSf(a,b,c) (bOp (a) | bXa (b) | bSf (c)), (mOp | mXa | mSf) @@ -69,542 +71,549 @@ (bOp (a) | bXb (b) | bQ (c) | bSf (d)), (mOp | mXb | mQ | mSf) #define OpXbX6(a,b,c) \ (bOp (a) | bXb (b) | bX6 (c)), (mOp | mXb | mX6) +#define OpXbX6Y(a,b,c,d) \ + (bOp (a) | bXb (b) | bX6 (c) | bY (d)), (mOp | mXb | mX6 | mY) #define OpXbX6F2(a,b,c,d) \ (bOp (a) | bXb (b) | bX6 (c) | bF2 (d)), (mOp | mXb | mX6 | mF2) #define OpXbX6Sf(a,b,c,d) \ (bOp (a) | bXb (b) | bX6 (c) | bSf (d)), (mOp | mXb | mX6 | mSf) +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + struct ia64_opcode ia64_opcodes_f[] = { - /* F-type instruction encodings (sorted according to major opcode) */ - - {"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}}, - {"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO}, - {"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}}, - {"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}}, - {"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}}, - - {"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}}, - {"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO}, - {"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}}, - {"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}}, - {"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F3}}, - - {"fmin.s0", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}}, - {"fmin", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, PSEUDO}, - {"fmin.s1", f, OpXbX6Sf (0, 0, 0x14, 1), {F1, F2, F3}}, - {"fmin.s2", f, OpXbX6Sf (0, 0, 0x14, 2), {F1, F2, F3}}, - {"fmin.s3", f, OpXbX6Sf (0, 0, 0x14, 3), {F1, F2, F3}}, - {"fmax.s0", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}}, - {"fmax", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, PSEUDO}, - {"fmax.s1", f, OpXbX6Sf (0, 0, 0x15, 1), {F1, F2, F3}}, - {"fmax.s2", f, OpXbX6Sf (0, 0, 0x15, 2), {F1, F2, F3}}, - {"fmax.s3", f, OpXbX6Sf (0, 0, 0x15, 3), {F1, F2, F3}}, - {"famin.s0", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}}, - {"famin", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, PSEUDO}, - {"famin.s1", f, OpXbX6Sf (0, 0, 0x16, 1), {F1, F2, F3}}, - {"famin.s2", f, OpXbX6Sf (0, 0, 0x16, 2), {F1, F2, F3}}, - {"famin.s3", f, OpXbX6Sf (0, 0, 0x16, 3), {F1, F2, F3}}, - {"famax.s0", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}}, - {"famax", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, PSEUDO}, - {"famax.s1", f, OpXbX6Sf (0, 0, 0x17, 1), {F1, F2, F3}}, - {"famax.s2", f, OpXbX6Sf (0, 0, 0x17, 2), {F1, F2, F3}}, - {"famax.s3", f, OpXbX6Sf (0, 0, 0x17, 3), {F1, F2, F3}}, - - {"mov", f, OpXbX6 (0, 0, 0x10), {F1, F3}, PSEUDO | F2_EQ_F3}, - {"fabs", f, OpXbX6F2 (0, 0, 0x10, 0), {F1, F3}, PSEUDO}, - {"fneg", f, OpXbX6 (0, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3}, - {"fnegabs", f, OpXbX6F2 (0, 0, 0x11, 0), {F1, F3}, PSEUDO}, - {"fmerge.s", f, OpXbX6 (0, 0, 0x10), {F1, F2, F3}}, - {"fmerge.ns", f, OpXbX6 (0, 0, 0x11), {F1, F2, F3}}, - - {"fmerge.se", f, OpXbX6 (0, 0, 0x12), {F1, F2, F3}}, - {"fmix.lr", f, OpXbX6 (0, 0, 0x39), {F1, F2, F3}}, - {"fmix.r", f, OpXbX6 (0, 0, 0x3a), {F1, F2, F3}}, - {"fmix.l", f, OpXbX6 (0, 0, 0x3b), {F1, F2, F3}}, - {"fsxt.r", f, OpXbX6 (0, 0, 0x3c), {F1, F2, F3}}, - {"fsxt.l", f, OpXbX6 (0, 0, 0x3d), {F1, F2, F3}}, - {"fpack", f, OpXbX6 (0, 0, 0x28), {F1, F2, F3}}, - {"fswap", f, OpXbX6 (0, 0, 0x34), {F1, F2, F3}}, - {"fswap.nl", f, OpXbX6 (0, 0, 0x35), {F1, F2, F3}}, - {"fswap.nr", f, OpXbX6 (0, 0, 0x36), {F1, F2, F3}}, - {"fand", f, OpXbX6 (0, 0, 0x2c), {F1, F2, F3}}, - {"fandcm", f, OpXbX6 (0, 0, 0x2d), {F1, F2, F3}}, - {"for", f, OpXbX6 (0, 0, 0x2e), {F1, F2, F3}}, - {"fxor", f, OpXbX6 (0, 0, 0x2f), {F1, F2, F3}}, - - {"fcvt.fx.s0", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}}, - {"fcvt.fx", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, PSEUDO}, - {"fcvt.fx.s1", f, OpXbX6Sf (0, 0, 0x18, 1), {F1, F2}}, - {"fcvt.fx.s2", f, OpXbX6Sf (0, 0, 0x18, 2), {F1, F2}}, - {"fcvt.fx.s3", f, OpXbX6Sf (0, 0, 0x18, 3), {F1, F2}}, - {"fcvt.fxu.s0", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}}, - {"fcvt.fxu", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, PSEUDO}, - {"fcvt.fxu.s1", f, OpXbX6Sf (0, 0, 0x19, 1), {F1, F2}}, - {"fcvt.fxu.s2", f, OpXbX6Sf (0, 0, 0x19, 2), {F1, F2}}, - {"fcvt.fxu.s3", f, OpXbX6Sf (0, 0, 0x19, 3), {F1, F2}}, - {"fcvt.fx.trunc.s0", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}}, - {"fcvt.fx.trunc", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, PSEUDO}, - {"fcvt.fx.trunc.s1", f, OpXbX6Sf (0, 0, 0x1a, 1), {F1, F2}}, - {"fcvt.fx.trunc.s2", f, OpXbX6Sf (0, 0, 0x1a, 2), {F1, F2}}, - {"fcvt.fx.trunc.s3", f, OpXbX6Sf (0, 0, 0x1a, 3), {F1, F2}}, - {"fcvt.fxu.trunc.s0", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}}, - {"fcvt.fxu.trunc", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, PSEUDO}, - {"fcvt.fxu.trunc.s1", f, OpXbX6Sf (0, 0, 0x1b, 1), {F1, F2}}, - {"fcvt.fxu.trunc.s2", f, OpXbX6Sf (0, 0, 0x1b, 2), {F1, F2}}, - {"fcvt.fxu.trunc.s3", f, OpXbX6Sf (0, 0, 0x1b, 3), {F1, F2}}, - - {"fcvt.xf", f, OpXbX6 (0, 0, 0x1c), {F1, F2}}, - - {"fsetc.s0", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}}, - {"fsetc", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, PSEUDO}, - {"fsetc.s1", f0, OpXbX6Sf (0, 0, 0x04, 1), {IMMU7a, IMMU7b}}, - {"fsetc.s2", f0, OpXbX6Sf (0, 0, 0x04, 2), {IMMU7a, IMMU7b}}, - {"fsetc.s3", f0, OpXbX6Sf (0, 0, 0x04, 3), {IMMU7a, IMMU7b}}, - {"fclrf.s0", f0, OpXbX6Sf (0, 0, 0x05, 0)}, - {"fclrf", f0, OpXbX6Sf (0, 0, 0x05, 0), {0}, PSEUDO}, - {"fclrf.s1", f0, OpXbX6Sf (0, 0, 0x05, 1)}, - {"fclrf.s2", f0, OpXbX6Sf (0, 0, 0x05, 2)}, - {"fclrf.s3", f0, OpXbX6Sf (0, 0, 0x05, 3)}, - {"fchkf.s0", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}}, - {"fchkf", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, PSEUDO}, - {"fchkf.s1", f0, OpXbX6Sf (0, 0, 0x08, 1), {TGT25}}, - {"fchkf.s2", f0, OpXbX6Sf (0, 0, 0x08, 2), {TGT25}}, - {"fchkf.s3", f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}}, - - {"break.f", f0, OpXbX6 (0, 0, 0x00), {IMMU21}}, - {"nop.f", f0, OpXbX6 (0, 0, 0x01), {IMMU21}}, - - {"fprcpa.s0", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}}, - {"fprcpa", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO}, - {"fprcpa.s1", f2, OpXbQSf (1, 1, 0, 1), {F1, P2, F2, F3}}, - {"fprcpa.s2", f2, OpXbQSf (1, 1, 0, 2), {F1, P2, F2, F3}}, - {"fprcpa.s3", f2, OpXbQSf (1, 1, 0, 3), {F1, P2, F2, F3}}, - - {"fprsqrta.s0", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}}, - {"fprsqrta", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, PSEUDO}, - {"fprsqrta.s1", f2, OpXbQSf (1, 1, 1, 1), {F1, P2, F3}}, - {"fprsqrta.s2", f2, OpXbQSf (1, 1, 1, 2), {F1, P2, F3}}, - {"fprsqrta.s3", f2, OpXbQSf (1, 1, 1, 3), {F1, P2, F3}}, - - {"fpmin.s0", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}}, - {"fpmin", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, PSEUDO}, - {"fpmin.s1", f, OpXbX6Sf (1, 0, 0x14, 1), {F1, F2, F3}}, - {"fpmin.s2", f, OpXbX6Sf (1, 0, 0x14, 2), {F1, F2, F3}}, - {"fpmin.s3", f, OpXbX6Sf (1, 0, 0x14, 3), {F1, F2, F3}}, - {"fpmax.s0", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}}, - {"fpmax", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, PSEUDO}, - {"fpmax.s1", f, OpXbX6Sf (1, 0, 0x15, 1), {F1, F2, F3}}, - {"fpmax.s2", f, OpXbX6Sf (1, 0, 0x15, 2), {F1, F2, F3}}, - {"fpmax.s3", f, OpXbX6Sf (1, 0, 0x15, 3), {F1, F2, F3}}, - {"fpamin.s0", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}}, - {"fpamin", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, PSEUDO}, - {"fpamin.s1", f, OpXbX6Sf (1, 0, 0x16, 1), {F1, F2, F3}}, - {"fpamin.s2", f, OpXbX6Sf (1, 0, 0x16, 2), {F1, F2, F3}}, - {"fpamin.s3", f, OpXbX6Sf (1, 0, 0x16, 3), {F1, F2, F3}}, - {"fpamax.s0", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}}, - {"fpamax", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, PSEUDO}, - {"fpamax.s1", f, OpXbX6Sf (1, 0, 0x17, 1), {F1, F2, F3}}, - {"fpamax.s2", f, OpXbX6Sf (1, 0, 0x17, 2), {F1, F2, F3}}, - {"fpamax.s3", f, OpXbX6Sf (1, 0, 0x17, 3), {F1, F2, F3}}, - - {"fpcmp.eq.s0", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}}, - {"fpcmp.eq", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, PSEUDO}, - {"fpcmp.eq.s1", f, OpXbX6Sf (1, 0, 0x30, 1), {F1, F2, F3}}, - {"fpcmp.eq.s2", f, OpXbX6Sf (1, 0, 0x30, 2), {F1, F2, F3}}, - {"fpcmp.eq.s3", f, OpXbX6Sf (1, 0, 0x30, 3), {F1, F2, F3}}, - {"fpcmp.lt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}}, - {"fpcmp.lt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, PSEUDO}, - {"fpcmp.lt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F2, F3}}, - {"fpcmp.lt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F2, F3}}, - {"fpcmp.lt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F2, F3}}, - {"fpcmp.le.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}}, - {"fpcmp.le", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, PSEUDO}, - {"fpcmp.le.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F2, F3}}, - {"fpcmp.le.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F2, F3}}, - {"fpcmp.le.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F2, F3}}, - {"fpcmp.gt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO}, - {"fpcmp.gt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO}, - {"fpcmp.gt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F3, F2}, PSEUDO}, - {"fpcmp.gt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F3, F2}, PSEUDO}, - {"fpcmp.gt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F3, F2}, PSEUDO}, - {"fpcmp.ge.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO}, - {"fpcmp.ge", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO}, - {"fpcmp.ge.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F3, F2}, PSEUDO}, - {"fpcmp.ge.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F3, F2}, PSEUDO}, - {"fpcmp.ge.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F3, F2}, PSEUDO}, - {"fpcmp.unord.s0", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}}, - {"fpcmp.unord", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, PSEUDO}, - {"fpcmp.unord.s1", f, OpXbX6Sf (1, 0, 0x33, 1), {F1, F2, F3}}, - {"fpcmp.unord.s2", f, OpXbX6Sf (1, 0, 0x33, 2), {F1, F2, F3}}, - {"fpcmp.unord.s3", f, OpXbX6Sf (1, 0, 0x33, 3), {F1, F2, F3}}, - {"fpcmp.neq.s0", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}}, - {"fpcmp.neq", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, PSEUDO}, - {"fpcmp.neq.s1", f, OpXbX6Sf (1, 0, 0x34, 1), {F1, F2, F3}}, - {"fpcmp.neq.s2", f, OpXbX6Sf (1, 0, 0x34, 2), {F1, F2, F3}}, - {"fpcmp.neq.s3", f, OpXbX6Sf (1, 0, 0x34, 3), {F1, F2, F3}}, - {"fpcmp.nlt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}}, - {"fpcmp.nlt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, PSEUDO}, - {"fpcmp.nlt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F2, F3}}, - {"fpcmp.nlt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F2, F3}}, - {"fpcmp.nlt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F2, F3}}, - {"fpcmp.nle.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}}, - {"fpcmp.nle", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, PSEUDO}, - {"fpcmp.nle.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F2, F3}}, - {"fpcmp.nle.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F2, F3}}, - {"fpcmp.nle.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F2, F3}}, - {"fpcmp.ngt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO}, - {"fpcmp.ngt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO}, - {"fpcmp.ngt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F3, F2}, PSEUDO}, - {"fpcmp.ngt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F3, F2}, PSEUDO}, - {"fpcmp.ngt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F3, F2}, PSEUDO}, - {"fpcmp.nge.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO}, - {"fpcmp.nge", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO}, - {"fpcmp.nge.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F3, F2}, PSEUDO}, - {"fpcmp.nge.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F3, F2}, PSEUDO}, - {"fpcmp.nge.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F3, F2}, PSEUDO}, - {"fpcmp.ord.s0", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}}, - {"fpcmp.ord", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, PSEUDO}, - {"fpcmp.ord.s1", f, OpXbX6Sf (1, 0, 0x37, 1), {F1, F2, F3}}, - {"fpcmp.ord.s2", f, OpXbX6Sf (1, 0, 0x37, 2), {F1, F2, F3}}, - {"fpcmp.ord.s3", f, OpXbX6Sf (1, 0, 0x37, 3), {F1, F2, F3}}, - - {"fpabs", f, OpXbX6F2 (1, 0, 0x10, 0), {F1, F3}, PSEUDO}, - {"fpneg", f, OpXbX6 (1, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3}, - {"fpnegabs", f, OpXbX6F2 (1, 0, 0x11, 0), {F1, F3}, PSEUDO}, - {"fpmerge.s", f, OpXbX6 (1, 0, 0x10), {F1, F2, F3}}, - {"fpmerge.ns", f, OpXbX6 (1, 0, 0x11), {F1, F2, F3}}, - {"fpmerge.se", f, OpXbX6 (1, 0, 0x12), {F1, F2, F3}}, - - {"fpcvt.fx.s0", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}}, - {"fpcvt.fx", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, PSEUDO}, - {"fpcvt.fx.s1", f, OpXbX6Sf (1, 0, 0x18, 1), {F1, F2}}, - {"fpcvt.fx.s2", f, OpXbX6Sf (1, 0, 0x18, 2), {F1, F2}}, - {"fpcvt.fx.s3", f, OpXbX6Sf (1, 0, 0x18, 3), {F1, F2}}, - {"fpcvt.fxu.s0", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}}, - {"fpcvt.fxu", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, PSEUDO}, - {"fpcvt.fxu.s1", f, OpXbX6Sf (1, 0, 0x19, 1), {F1, F2}}, - {"fpcvt.fxu.s2", f, OpXbX6Sf (1, 0, 0x19, 2), {F1, F2}}, - {"fpcvt.fxu.s3", f, OpXbX6Sf (1, 0, 0x19, 3), {F1, F2}}, - {"fpcvt.fx.trunc.s0", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}}, - {"fpcvt.fx.trunc", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, PSEUDO}, - {"fpcvt.fx.trunc.s1", f, OpXbX6Sf (1, 0, 0x1a, 1), {F1, F2}}, - {"fpcvt.fx.trunc.s2", f, OpXbX6Sf (1, 0, 0x1a, 2), {F1, F2}}, - {"fpcvt.fx.trunc.s3", f, OpXbX6Sf (1, 0, 0x1a, 3), {F1, F2}}, - {"fpcvt.fxu.trunc.s0", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}}, - {"fpcvt.fxu.trunc", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, PSEUDO}, - {"fpcvt.fxu.trunc.s1", f, OpXbX6Sf (1, 0, 0x1b, 1), {F1, F2}}, - {"fpcvt.fxu.trunc.s2", f, OpXbX6Sf (1, 0, 0x1b, 2), {F1, F2}}, - {"fpcvt.fxu.trunc.s3", f, OpXbX6Sf (1, 0, 0x1b, 3), {F1, F2}}, - - {"fcmp.eq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}}, - {"fcmp.eq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO}, - {"fcmp.eq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P1, P2, F2, F3}}, - {"fcmp.eq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P1, P2, F2, F3}}, - {"fcmp.eq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P1, P2, F2, F3}}, - {"fcmp.lt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}}, - {"fcmp.lt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO}, - {"fcmp.lt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F2, F3}}, - {"fcmp.lt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F2, F3}}, - {"fcmp.lt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F2, F3}}, - {"fcmp.le.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}}, - {"fcmp.le", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO}, - {"fcmp.le.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F2, F3}}, - {"fcmp.le.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F2, F3}}, - {"fcmp.le.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F2, F3}}, - {"fcmp.unord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}}, - {"fcmp.unord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO}, - {"fcmp.unord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P1, P2, F2, F3}}, - {"fcmp.unord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P1, P2, F2, F3}}, - {"fcmp.unord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P1, P2, F2, F3}}, - {"fcmp.eq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}}, - {"fcmp.eq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO}, - {"fcmp.eq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P1, P2, F2, F3}}, - {"fcmp.eq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P1, P2, F2, F3}}, - {"fcmp.eq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P1, P2, F2, F3}}, - {"fcmp.lt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}}, - {"fcmp.lt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO}, - {"fcmp.lt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F2, F3}}, - {"fcmp.lt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F2, F3}}, - {"fcmp.lt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F2, F3}}, - {"fcmp.le.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}}, - {"fcmp.le.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO}, - {"fcmp.le.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F2, F3}}, - {"fcmp.le.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F2, F3}}, - {"fcmp.le.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F2, F3}}, - {"fcmp.unord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}}, - {"fcmp.unord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO}, - {"fcmp.unord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P1, P2, F2, F3}}, - {"fcmp.unord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P1, P2, F2, F3}}, - {"fcmp.unord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P1, P2, F2, F3}}, + /* F-type instruction encodings (sorted according to major opcode). */ + + {"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, EMPTY}, + {"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}, EMPTY}, + {"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}, EMPTY}, + {"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}, EMPTY}, + + {"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, EMPTY}, + {"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL}, + {"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}, EMPTY}, + {"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}, EMPTY}, + {"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F3}, EMPTY}, + + {"fmin.s0", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, EMPTY}, + {"fmin", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fmin.s1", f, OpXbX6Sf (0, 0, 0x14, 1), {F1, F2, F3}, EMPTY}, + {"fmin.s2", f, OpXbX6Sf (0, 0, 0x14, 2), {F1, F2, F3}, EMPTY}, + {"fmin.s3", f, OpXbX6Sf (0, 0, 0x14, 3), {F1, F2, F3}, EMPTY}, + {"fmax.s0", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, EMPTY}, + {"fmax", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fmax.s1", f, OpXbX6Sf (0, 0, 0x15, 1), {F1, F2, F3}, EMPTY}, + {"fmax.s2", f, OpXbX6Sf (0, 0, 0x15, 2), {F1, F2, F3}, EMPTY}, + {"fmax.s3", f, OpXbX6Sf (0, 0, 0x15, 3), {F1, F2, F3}, EMPTY}, + {"famin.s0", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, EMPTY}, + {"famin", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"famin.s1", f, OpXbX6Sf (0, 0, 0x16, 1), {F1, F2, F3}, EMPTY}, + {"famin.s2", f, OpXbX6Sf (0, 0, 0x16, 2), {F1, F2, F3}, EMPTY}, + {"famin.s3", f, OpXbX6Sf (0, 0, 0x16, 3), {F1, F2, F3}, EMPTY}, + {"famax.s0", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, EMPTY}, + {"famax", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"famax.s1", f, OpXbX6Sf (0, 0, 0x17, 1), {F1, F2, F3}, EMPTY}, + {"famax.s2", f, OpXbX6Sf (0, 0, 0x17, 2), {F1, F2, F3}, EMPTY}, + {"famax.s3", f, OpXbX6Sf (0, 0, 0x17, 3), {F1, F2, F3}, EMPTY}, + + {"mov", f, OpXbX6 (0, 0, 0x10), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL}, + {"fabs", f, OpXbX6F2 (0, 0, 0x10, 0), {F1, F3}, PSEUDO, 0, NULL}, + {"fneg", f, OpXbX6 (0, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL}, + {"fnegabs", f, OpXbX6F2 (0, 0, 0x11, 0), {F1, F3}, PSEUDO, 0, NULL}, + {"fmerge.s", f, OpXbX6 (0, 0, 0x10), {F1, F2, F3}, EMPTY}, + {"fmerge.ns", f, OpXbX6 (0, 0, 0x11), {F1, F2, F3}, EMPTY}, + + {"fmerge.se", f, OpXbX6 (0, 0, 0x12), {F1, F2, F3}, EMPTY}, + {"fmix.lr", f, OpXbX6 (0, 0, 0x39), {F1, F2, F3}, EMPTY}, + {"fmix.r", f, OpXbX6 (0, 0, 0x3a), {F1, F2, F3}, EMPTY}, + {"fmix.l", f, OpXbX6 (0, 0, 0x3b), {F1, F2, F3}, EMPTY}, + {"fsxt.r", f, OpXbX6 (0, 0, 0x3c), {F1, F2, F3}, EMPTY}, + {"fsxt.l", f, OpXbX6 (0, 0, 0x3d), {F1, F2, F3}, EMPTY}, + {"fpack", f, OpXbX6 (0, 0, 0x28), {F1, F2, F3}, EMPTY}, + {"fswap", f, OpXbX6 (0, 0, 0x34), {F1, F2, F3}, EMPTY}, + {"fswap.nl", f, OpXbX6 (0, 0, 0x35), {F1, F2, F3}, EMPTY}, + {"fswap.nr", f, OpXbX6 (0, 0, 0x36), {F1, F2, F3}, EMPTY}, + {"fand", f, OpXbX6 (0, 0, 0x2c), {F1, F2, F3}, EMPTY}, + {"fandcm", f, OpXbX6 (0, 0, 0x2d), {F1, F2, F3}, EMPTY}, + {"for", f, OpXbX6 (0, 0, 0x2e), {F1, F2, F3}, EMPTY}, + {"fxor", f, OpXbX6 (0, 0, 0x2f), {F1, F2, F3}, EMPTY}, + + {"fcvt.fx.s0", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, EMPTY}, + {"fcvt.fx", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fcvt.fx.s1", f, OpXbX6Sf (0, 0, 0x18, 1), {F1, F2}, EMPTY}, + {"fcvt.fx.s2", f, OpXbX6Sf (0, 0, 0x18, 2), {F1, F2}, EMPTY}, + {"fcvt.fx.s3", f, OpXbX6Sf (0, 0, 0x18, 3), {F1, F2}, EMPTY}, + {"fcvt.fxu.s0", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, EMPTY}, + {"fcvt.fxu", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fcvt.fxu.s1", f, OpXbX6Sf (0, 0, 0x19, 1), {F1, F2}, EMPTY}, + {"fcvt.fxu.s2", f, OpXbX6Sf (0, 0, 0x19, 2), {F1, F2}, EMPTY}, + {"fcvt.fxu.s3", f, OpXbX6Sf (0, 0, 0x19, 3), {F1, F2}, EMPTY}, + {"fcvt.fx.trunc.s0", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, EMPTY}, + {"fcvt.fx.trunc", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fcvt.fx.trunc.s1", f, OpXbX6Sf (0, 0, 0x1a, 1), {F1, F2}, EMPTY}, + {"fcvt.fx.trunc.s2", f, OpXbX6Sf (0, 0, 0x1a, 2), {F1, F2}, EMPTY}, + {"fcvt.fx.trunc.s3", f, OpXbX6Sf (0, 0, 0x1a, 3), {F1, F2}, EMPTY}, + {"fcvt.fxu.trunc.s0", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, EMPTY}, + {"fcvt.fxu.trunc", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fcvt.fxu.trunc.s1", f, OpXbX6Sf (0, 0, 0x1b, 1), {F1, F2}, EMPTY}, + {"fcvt.fxu.trunc.s2", f, OpXbX6Sf (0, 0, 0x1b, 2), {F1, F2}, EMPTY}, + {"fcvt.fxu.trunc.s3", f, OpXbX6Sf (0, 0, 0x1b, 3), {F1, F2}, EMPTY}, + + {"fcvt.xf", f, OpXbX6 (0, 0, 0x1c), {F1, F2}, EMPTY}, + + {"fsetc.s0", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, EMPTY}, + {"fsetc", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, PSEUDO, 0, NULL}, + {"fsetc.s1", f0, OpXbX6Sf (0, 0, 0x04, 1), {IMMU7a, IMMU7b}, EMPTY}, + {"fsetc.s2", f0, OpXbX6Sf (0, 0, 0x04, 2), {IMMU7a, IMMU7b}, EMPTY}, + {"fsetc.s3", f0, OpXbX6Sf (0, 0, 0x04, 3), {IMMU7a, IMMU7b}, EMPTY}, + {"fclrf.s0", f0, OpXbX6Sf (0, 0, 0x05, 0), {}, EMPTY}, + {"fclrf", f0, OpXbX6Sf (0, 0, 0x05, 0), {0}, PSEUDO, 0, NULL}, + {"fclrf.s1", f0, OpXbX6Sf (0, 0, 0x05, 1), {}, EMPTY}, + {"fclrf.s2", f0, OpXbX6Sf (0, 0, 0x05, 2), {}, EMPTY}, + {"fclrf.s3", f0, OpXbX6Sf (0, 0, 0x05, 3), {}, EMPTY}, + {"fchkf.s0", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, EMPTY}, + {"fchkf", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, PSEUDO, 0, NULL}, + {"fchkf.s1", f0, OpXbX6Sf (0, 0, 0x08, 1), {TGT25}, EMPTY}, + {"fchkf.s2", f0, OpXbX6Sf (0, 0, 0x08, 2), {TGT25}, EMPTY}, + {"fchkf.s3", f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}, EMPTY}, + + {"break.f", f0, OpXbX6 (0, 0, 0x00), {IMMU21}, EMPTY}, + {"nop.f", f0, OpXbX6Y (0, 0, 0x01, 0), {IMMU21}, EMPTY}, + {"hint.f", f0, OpXbX6Y (0, 0, 0x01, 1), {IMMU21}, EMPTY}, + + {"fprcpa.s0", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, EMPTY}, + {"fprcpa", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fprcpa.s1", f2, OpXbQSf (1, 1, 0, 1), {F1, P2, F2, F3}, EMPTY}, + {"fprcpa.s2", f2, OpXbQSf (1, 1, 0, 2), {F1, P2, F2, F3}, EMPTY}, + {"fprcpa.s3", f2, OpXbQSf (1, 1, 0, 3), {F1, P2, F2, F3}, EMPTY}, + + {"fprsqrta.s0", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, EMPTY}, + {"fprsqrta", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, PSEUDO, 0, NULL}, + {"fprsqrta.s1", f2, OpXbQSf (1, 1, 1, 1), {F1, P2, F3}, EMPTY}, + {"fprsqrta.s2", f2, OpXbQSf (1, 1, 1, 2), {F1, P2, F3}, EMPTY}, + {"fprsqrta.s3", f2, OpXbQSf (1, 1, 1, 3), {F1, P2, F3}, EMPTY}, + + {"fpmin.s0", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, EMPTY}, + {"fpmin", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpmin.s1", f, OpXbX6Sf (1, 0, 0x14, 1), {F1, F2, F3}, EMPTY}, + {"fpmin.s2", f, OpXbX6Sf (1, 0, 0x14, 2), {F1, F2, F3}, EMPTY}, + {"fpmin.s3", f, OpXbX6Sf (1, 0, 0x14, 3), {F1, F2, F3}, EMPTY}, + {"fpmax.s0", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, EMPTY}, + {"fpmax", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpmax.s1", f, OpXbX6Sf (1, 0, 0x15, 1), {F1, F2, F3}, EMPTY}, + {"fpmax.s2", f, OpXbX6Sf (1, 0, 0x15, 2), {F1, F2, F3}, EMPTY}, + {"fpmax.s3", f, OpXbX6Sf (1, 0, 0x15, 3), {F1, F2, F3}, EMPTY}, + {"fpamin.s0", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, EMPTY}, + {"fpamin", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpamin.s1", f, OpXbX6Sf (1, 0, 0x16, 1), {F1, F2, F3}, EMPTY}, + {"fpamin.s2", f, OpXbX6Sf (1, 0, 0x16, 2), {F1, F2, F3}, EMPTY}, + {"fpamin.s3", f, OpXbX6Sf (1, 0, 0x16, 3), {F1, F2, F3}, EMPTY}, + {"fpamax.s0", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, EMPTY}, + {"fpamax", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpamax.s1", f, OpXbX6Sf (1, 0, 0x17, 1), {F1, F2, F3}, EMPTY}, + {"fpamax.s2", f, OpXbX6Sf (1, 0, 0x17, 2), {F1, F2, F3}, EMPTY}, + {"fpamax.s3", f, OpXbX6Sf (1, 0, 0x17, 3), {F1, F2, F3}, EMPTY}, + + {"fpcmp.eq.s0", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.eq", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.eq.s1", f, OpXbX6Sf (1, 0, 0x30, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.eq.s2", f, OpXbX6Sf (1, 0, 0x30, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.eq.s3", f, OpXbX6Sf (1, 0, 0x30, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.lt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.lt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.lt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.lt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.lt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.le.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.le", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.le.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.le.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.le.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.gt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.gt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.gt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.gt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.gt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ge.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.unord.s0", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.unord", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.unord.s1", f, OpXbX6Sf (1, 0, 0x33, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.unord.s2", f, OpXbX6Sf (1, 0, 0x33, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.unord.s3", f, OpXbX6Sf (1, 0, 0x33, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.neq.s0", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.neq", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.neq.s1", f, OpXbX6Sf (1, 0, 0x34, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.neq.s2", f, OpXbX6Sf (1, 0, 0x34, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.neq.s3", f, OpXbX6Sf (1, 0, 0x34, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.nlt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.nlt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.nlt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.nlt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.nlt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.nle.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.nle", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.nle.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.nle.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.nle.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F2, F3}, EMPTY}, + {"fpcmp.ngt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ngt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ngt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ngt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ngt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.nge.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fpcmp.ord.s0", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, EMPTY}, + {"fpcmp.ord", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, PSEUDO, 0, NULL}, + {"fpcmp.ord.s1", f, OpXbX6Sf (1, 0, 0x37, 1), {F1, F2, F3}, EMPTY}, + {"fpcmp.ord.s2", f, OpXbX6Sf (1, 0, 0x37, 2), {F1, F2, F3}, EMPTY}, + {"fpcmp.ord.s3", f, OpXbX6Sf (1, 0, 0x37, 3), {F1, F2, F3}, EMPTY}, + + {"fpabs", f, OpXbX6F2 (1, 0, 0x10, 0), {F1, F3}, PSEUDO, 0, NULL}, + {"fpneg", f, OpXbX6 (1, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3, 0, NULL}, + {"fpnegabs", f, OpXbX6F2 (1, 0, 0x11, 0), {F1, F3}, PSEUDO, 0, NULL}, + {"fpmerge.s", f, OpXbX6 (1, 0, 0x10), {F1, F2, F3}, EMPTY}, + {"fpmerge.ns", f, OpXbX6 (1, 0, 0x11), {F1, F2, F3}, EMPTY}, + {"fpmerge.se", f, OpXbX6 (1, 0, 0x12), {F1, F2, F3}, EMPTY}, + + {"fpcvt.fx.s0", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, EMPTY}, + {"fpcvt.fx", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fpcvt.fx.s1", f, OpXbX6Sf (1, 0, 0x18, 1), {F1, F2}, EMPTY}, + {"fpcvt.fx.s2", f, OpXbX6Sf (1, 0, 0x18, 2), {F1, F2}, EMPTY}, + {"fpcvt.fx.s3", f, OpXbX6Sf (1, 0, 0x18, 3), {F1, F2}, EMPTY}, + {"fpcvt.fxu.s0", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, EMPTY}, + {"fpcvt.fxu", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fpcvt.fxu.s1", f, OpXbX6Sf (1, 0, 0x19, 1), {F1, F2}, EMPTY}, + {"fpcvt.fxu.s2", f, OpXbX6Sf (1, 0, 0x19, 2), {F1, F2}, EMPTY}, + {"fpcvt.fxu.s3", f, OpXbX6Sf (1, 0, 0x19, 3), {F1, F2}, EMPTY}, + {"fpcvt.fx.trunc.s0", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, EMPTY}, + {"fpcvt.fx.trunc", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fpcvt.fx.trunc.s1", f, OpXbX6Sf (1, 0, 0x1a, 1), {F1, F2}, EMPTY}, + {"fpcvt.fx.trunc.s2", f, OpXbX6Sf (1, 0, 0x1a, 2), {F1, F2}, EMPTY}, + {"fpcvt.fx.trunc.s3", f, OpXbX6Sf (1, 0, 0x1a, 3), {F1, F2}, EMPTY}, + {"fpcvt.fxu.trunc.s0", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, EMPTY}, + {"fpcvt.fxu.trunc", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, PSEUDO, 0, NULL}, + {"fpcvt.fxu.trunc.s1", f, OpXbX6Sf (1, 0, 0x1b, 1), {F1, F2}, EMPTY}, + {"fpcvt.fxu.trunc.s2", f, OpXbX6Sf (1, 0, 0x1b, 2), {F1, F2}, EMPTY}, + {"fpcvt.fxu.trunc.s3", f, OpXbX6Sf (1, 0, 0x1b, 3), {F1, F2}, EMPTY}, + + {"fcmp.eq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.eq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.lt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.le.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.unord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.eq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.eq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.lt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.lt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.le.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.le.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.unord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P1, P2, F2, F3}, EMPTY}, + {"fcmp.unord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P1, P2, F2, F3}, EMPTY}, /* pseudo-ops of the above */ - {"fcmp.gt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}}, - {"fcmp.gt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, PSEUDO}, - {"fcmp.gt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F3, F2}}, - {"fcmp.gt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F3, F2}}, - {"fcmp.gt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F3, F2}}, - {"fcmp.ge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}}, - {"fcmp.ge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, PSEUDO}, - {"fcmp.ge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F3, F2}}, - {"fcmp.ge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F3, F2}}, - {"fcmp.ge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F3, F2}}, - {"fcmp.neq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}}, - {"fcmp.neq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO}, - {"fcmp.neq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P2, P1, F2, F3}}, - {"fcmp.neq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P2, P1, F2, F3}}, - {"fcmp.neq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P2, P1, F2, F3}}, - {"fcmp.nlt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}}, - {"fcmp.nlt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO}, - {"fcmp.nlt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F2, F3}}, - {"fcmp.nlt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F2, F3}}, - {"fcmp.nlt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F2, F3}}, - {"fcmp.nle.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}}, - {"fcmp.nle", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO}, - {"fcmp.nle.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F2, F3}}, - {"fcmp.nle.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F2, F3}}, - {"fcmp.nle.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F2, F3}}, - {"fcmp.ngt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}}, - {"fcmp.ngt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, PSEUDO}, - {"fcmp.ngt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F3, F2}}, - {"fcmp.ngt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F3, F2}}, - {"fcmp.ngt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F3, F2}}, - {"fcmp.nge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}}, - {"fcmp.nge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, PSEUDO}, - {"fcmp.nge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F3, F2}}, - {"fcmp.nge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F3, F2}}, - {"fcmp.nge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F3, F2}}, - {"fcmp.ord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}}, - {"fcmp.ord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO}, - {"fcmp.ord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P2, P1, F2, F3}}, - {"fcmp.ord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P2, P1, F2, F3}}, - {"fcmp.ord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P2, P1, F2, F3}}, - {"fcmp.gt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}}, - {"fcmp.gt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, PSEUDO}, - {"fcmp.gt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F3, F2}}, - {"fcmp.gt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F3, F2}}, - {"fcmp.gt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F3, F2}}, - {"fcmp.ge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}}, - {"fcmp.ge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, PSEUDO}, - {"fcmp.ge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F3, F2}}, - {"fcmp.ge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F3, F2}}, - {"fcmp.ge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F3, F2}}, - {"fcmp.neq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}}, - {"fcmp.neq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO}, - {"fcmp.neq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P2, P1, F2, F3}}, - {"fcmp.neq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P2, P1, F2, F3}}, - {"fcmp.neq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P2, P1, F2, F3}}, - {"fcmp.nlt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}}, - {"fcmp.nlt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO}, - {"fcmp.nlt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F2, F3}}, - {"fcmp.nlt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F2, F3}}, - {"fcmp.nlt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F2, F3}}, - {"fcmp.nle.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}}, - {"fcmp.nle.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO}, - {"fcmp.nle.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F2, F3}}, - {"fcmp.nle.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F2, F3}}, - {"fcmp.nle.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F2, F3}}, - {"fcmp.ngt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}}, - {"fcmp.ngt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, PSEUDO}, - {"fcmp.ngt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F3, F2}}, - {"fcmp.ngt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F3, F2}}, - {"fcmp.ngt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F3, F2}}, - {"fcmp.nge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}}, - {"fcmp.nge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, PSEUDO}, - {"fcmp.nge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F3, F2}}, - {"fcmp.nge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F3, F2}}, - {"fcmp.nge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F3, F2}}, - {"fcmp.ord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}}, - {"fcmp.ord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO}, - {"fcmp.ord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P2, P1, F2, F3}}, - {"fcmp.ord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P2, P1, F2, F3}}, - {"fcmp.ord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P2, P1, F2, F3}}, - - {"fclass.m", f2, OpTa (5, 0), {P1, P2, F2, IMMU9}}, - {"fclass.nm", f2, OpTa (5, 0), {P2, P1, F2, IMMU9}, PSEUDO}, - {"fclass.m.unc", f2, OpTa (5, 1), {P1, P2, F2, IMMU9}}, - {"fclass.nm.unc", f2, OpTa (5, 1), {P2, P1, F2, IMMU9}, PSEUDO}, + {"fcmp.gt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.gt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.ge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.neq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.neq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.nlt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.nle.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ngt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.ngt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.nge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.ord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.gt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.gt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.gt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.ge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.ge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F3, F2}, EMPTY}, + {"fcmp.neq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.neq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.neq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.nlt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nlt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.nle.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.nle.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ngt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.ngt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ngt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, PSEUDO, 0, NULL}, + {"fcmp.nge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.nge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F3, F2}, EMPTY}, + {"fcmp.ord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO, 0, NULL}, + {"fcmp.ord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P2, P1, F2, F3}, EMPTY}, + {"fcmp.ord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P2, P1, F2, F3}, EMPTY}, + + {"fclass.m", f2, OpTa (5, 0), {P1, P2, F2, IMMU9}, EMPTY}, + {"fclass.nm", f2, OpTa (5, 0), {P2, P1, F2, IMMU9}, PSEUDO, 0, NULL}, + {"fclass.m.unc", f2, OpTa (5, 1), {P1, P2, F2, IMMU9}, EMPTY}, + {"fclass.nm.unc", f2, OpTa (5, 1), {P2, P1, F2, IMMU9}, PSEUDO, 0, NULL}, /* note: fnorm and fcvt.xuf have identical encodings! */ - {"fnorm.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, - {"fnorm", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, - {"fnorm.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO}, - {"fnorm.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO}, - {"fnorm.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO}, - {"fnorm.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, - {"fnorm.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, - {"fnorm.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO}, - {"fnorm.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO}, - {"fnorm.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO}, - {"fadd.s0", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO}, - {"fadd", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO}, - {"fadd.s1", f, OpXaSfF4 (0x8, 0, 1, 1), {F1, F3, F2}, PSEUDO}, - {"fadd.s2", f, OpXaSfF4 (0x8, 0, 2, 1), {F1, F3, F2}, PSEUDO}, - {"fadd.s3", f, OpXaSfF4 (0x8, 0, 3, 1), {F1, F3, F2}, PSEUDO}, - {"fadd.s.s0", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO}, - {"fadd.s", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO}, - {"fadd.s.s1", f, OpXaSfF4 (0x8, 1, 1, 1), {F1, F3, F2}, PSEUDO}, - {"fadd.s.s2", f, OpXaSfF4 (0x8, 1, 2, 1), {F1, F3, F2}, PSEUDO}, - {"fadd.s.s3", f, OpXaSfF4 (0x8, 1, 3, 1), {F1, F3, F2}, PSEUDO}, - {"fmpy.s0", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fmpy", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fmpy.s1", f, OpXaSfF2 (0x8, 0, 1, 0), {F1, F3, F4}, PSEUDO}, - {"fmpy.s2", f, OpXaSfF2 (0x8, 0, 2, 0), {F1, F3, F4}, PSEUDO}, - {"fmpy.s3", f, OpXaSfF2 (0x8, 0, 3, 0), {F1, F3, F4}, PSEUDO}, - {"fmpy.s.s0", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fmpy.s", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fmpy.s.s1", f, OpXaSfF2 (0x8, 1, 1, 0), {F1, F3, F4}, PSEUDO}, - {"fmpy.s.s2", f, OpXaSfF2 (0x8, 1, 2, 0), {F1, F3, F4}, PSEUDO}, - {"fmpy.s.s3", f, OpXaSfF2 (0x8, 1, 3, 0), {F1, F3, F4}, PSEUDO}, - {"fma.s0", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}}, - {"fma", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, PSEUDO}, - {"fma.s1", f, OpXaSf (0x8, 0, 1), {F1, F3, F4, F2}}, - {"fma.s2", f, OpXaSf (0x8, 0, 2), {F1, F3, F4, F2}}, - {"fma.s3", f, OpXaSf (0x8, 0, 3), {F1, F3, F4, F2}}, - {"fma.s.s0", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}}, - {"fma.s", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, PSEUDO}, - {"fma.s.s1", f, OpXaSf (0x8, 1, 1), {F1, F3, F4, F2}}, - {"fma.s.s2", f, OpXaSf (0x8, 1, 2), {F1, F3, F4, F2}}, - {"fma.s.s3", f, OpXaSf (0x8, 1, 3), {F1, F3, F4, F2}}, - - {"fnorm.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, - {"fnorm.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, - {"fnorm.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO}, - {"fnorm.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO}, - {"fnorm.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO}, - {"fcvt.xuf.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO}, - {"fadd.d.s0", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO}, - {"fadd.d", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO}, - {"fadd.d.s1", f, OpXaSfF4 (0x9, 0, 1, 1), {F1, F3, F2}, PSEUDO}, - {"fadd.d.s2", f, OpXaSfF4 (0x9, 0, 2, 1), {F1, F3, F2}, PSEUDO}, - {"fadd.d.s3", f, OpXaSfF4 (0x9, 0, 3, 1), {F1, F3, F2}, PSEUDO}, - {"fmpy.d.s0", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fmpy.d", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fmpy.d.s1", f, OpXaSfF2 (0x9, 0, 1, 0), {F1, F3, F4}, PSEUDO}, - {"fmpy.d.s2", f, OpXaSfF2 (0x9, 0, 2, 0), {F1, F3, F4}, PSEUDO}, - {"fmpy.d.s3", f, OpXaSfF2 (0x9, 0, 3, 0), {F1, F3, F4}, PSEUDO}, - {"fma.d.s0", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}}, - {"fma.d", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, PSEUDO}, - {"fma.d.s1", f, OpXaSf (0x9, 0, 1), {F1, F3, F4, F2}}, - {"fma.d.s2", f, OpXaSf (0x9, 0, 2), {F1, F3, F4, F2}}, - {"fma.d.s3", f, OpXaSf (0x9, 0, 3), {F1, F3, F4, F2}}, - - {"fpmpy.s0", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fpmpy", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fpmpy.s1", f, OpXaSfF2 (0x9, 1, 1, 0), {F1, F3, F4}, PSEUDO}, - {"fpmpy.s2", f, OpXaSfF2 (0x9, 1, 2, 0), {F1, F3, F4}, PSEUDO}, - {"fpmpy.s3", f, OpXaSfF2 (0x9, 1, 3, 0), {F1, F3, F4}, PSEUDO}, - {"fpma.s0", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}}, - {"fpma", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, PSEUDO}, - {"fpma.s1", f, OpXaSf (0x9, 1, 1), {F1, F3, F4, F2}}, - {"fpma.s2", f, OpXaSf (0x9, 1, 2), {F1, F3, F4, F2}}, - {"fpma.s3", f, OpXaSf (0x9, 1, 3), {F1, F3, F4, F2}}, - - {"fsub.s0", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO}, - {"fsub", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO}, - {"fsub.s1", f, OpXaSfF4 (0xa, 0, 1, 1), {F1, F3, F2}, PSEUDO}, - {"fsub.s2", f, OpXaSfF4 (0xa, 0, 2, 1), {F1, F3, F2}, PSEUDO}, - {"fsub.s3", f, OpXaSfF4 (0xa, 0, 3, 1), {F1, F3, F2}, PSEUDO}, - {"fsub.s.s0", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO}, - {"fsub.s", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO}, - {"fsub.s.s1", f, OpXaSfF4 (0xa, 1, 1, 1), {F1, F3, F2}, PSEUDO}, - {"fsub.s.s2", f, OpXaSfF4 (0xa, 1, 2, 1), {F1, F3, F2}, PSEUDO}, - {"fsub.s.s3", f, OpXaSfF4 (0xa, 1, 3, 1), {F1, F3, F2}, PSEUDO}, - {"fms.s0", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}}, - {"fms", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, PSEUDO}, - {"fms.s1", f, OpXaSf (0xa, 0, 1), {F1, F3, F4, F2}}, - {"fms.s2", f, OpXaSf (0xa, 0, 2), {F1, F3, F4, F2}}, - {"fms.s3", f, OpXaSf (0xa, 0, 3), {F1, F3, F4, F2}}, - {"fms.s.s0", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}}, - {"fms.s", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, PSEUDO}, - {"fms.s.s1", f, OpXaSf (0xa, 1, 1), {F1, F3, F4, F2}}, - {"fms.s.s2", f, OpXaSf (0xa, 1, 2), {F1, F3, F4, F2}}, - {"fms.s.s3", f, OpXaSf (0xa, 1, 3), {F1, F3, F4, F2}}, - {"fsub.d.s0", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO}, - {"fsub.d", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO}, - {"fsub.d.s1", f, OpXaSfF4 (0xb, 0, 1, 1), {F1, F3, F2}, PSEUDO}, - {"fsub.d.s2", f, OpXaSfF4 (0xb, 0, 2, 1), {F1, F3, F2}, PSEUDO}, - {"fsub.d.s3", f, OpXaSfF4 (0xb, 0, 3, 1), {F1, F3, F2}, PSEUDO}, - {"fms.d.s0", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}}, - {"fms.d", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, PSEUDO}, - {"fms.d.s1", f, OpXaSf (0xb, 0, 1), {F1, F3, F4, F2}}, - {"fms.d.s2", f, OpXaSf (0xb, 0, 2), {F1, F3, F4, F2}}, - {"fms.d.s3", f, OpXaSf (0xb, 0, 3), {F1, F3, F4, F2}}, - - {"fpms.s0", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}}, - {"fpms", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, PSEUDO}, - {"fpms.s1", f, OpXaSf (0xb, 1, 1), {F1, F3, F4, F2}}, - {"fpms.s2", f, OpXaSf (0xb, 1, 2), {F1, F3, F4, F2}}, - {"fpms.s3", f, OpXaSf (0xb, 1, 3), {F1, F3, F4, F2}}, - - {"fnmpy.s0", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fnmpy", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fnmpy.s1", f, OpXaSfF2 (0xc, 0, 1, 0), {F1, F3, F4}, PSEUDO}, - {"fnmpy.s2", f, OpXaSfF2 (0xc, 0, 2, 0), {F1, F3, F4}, PSEUDO}, - {"fnmpy.s3", f, OpXaSfF2 (0xc, 0, 3, 0), {F1, F3, F4}, PSEUDO}, - {"fnmpy.s.s0", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fnmpy.s", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fnmpy.s.s1", f, OpXaSfF2 (0xc, 1, 1, 0), {F1, F3, F4}, PSEUDO}, - {"fnmpy.s.s2", f, OpXaSfF2 (0xc, 1, 2, 0), {F1, F3, F4}, PSEUDO}, - {"fnmpy.s.s3", f, OpXaSfF2 (0xc, 1, 3, 0), {F1, F3, F4}, PSEUDO}, - {"fnma.s0", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}}, - {"fnma", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, PSEUDO}, - {"fnma.s1", f, OpXaSf (0xc, 0, 1), {F1, F3, F4, F2}}, - {"fnma.s2", f, OpXaSf (0xc, 0, 2), {F1, F3, F4, F2}}, - {"fnma.s3", f, OpXaSf (0xc, 0, 3), {F1, F3, F4, F2}}, - {"fnma.s.s0", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}}, - {"fnma.s", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, PSEUDO}, - {"fnma.s.s1", f, OpXaSf (0xc, 1, 1), {F1, F3, F4, F2}}, - {"fnma.s.s2", f, OpXaSf (0xc, 1, 2), {F1, F3, F4, F2}}, - {"fnma.s.s3", f, OpXaSf (0xc, 1, 3), {F1, F3, F4, F2}}, - {"fnmpy.d.s0", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fnmpy.d", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fnmpy.d.s1", f, OpXaSfF2 (0xd, 0, 1, 0), {F1, F3, F4}, PSEUDO}, - {"fnmpy.d.s2", f, OpXaSfF2 (0xd, 0, 2, 0), {F1, F3, F4}, PSEUDO}, - {"fnmpy.d.s3", f, OpXaSfF2 (0xd, 0, 3, 0), {F1, F3, F4}, PSEUDO}, - {"fnma.d.s0", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}}, - {"fnma.d", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, PSEUDO}, - {"fnma.d.s1", f, OpXaSf (0xd, 0, 1), {F1, F3, F4, F2}}, - {"fnma.d.s2", f, OpXaSf (0xd, 0, 2), {F1, F3, F4, F2}}, - {"fnma.d.s3", f, OpXaSf (0xd, 0, 3), {F1, F3, F4, F2}}, - - {"fpnmpy.s0", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fpnmpy", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO}, - {"fpnmpy.s1", f, OpXaSfF2 (0xd, 1, 1, 0), {F1, F3, F4}, PSEUDO}, - {"fpnmpy.s2", f, OpXaSfF2 (0xd, 1, 2, 0), {F1, F3, F4}, PSEUDO}, - {"fpnmpy.s3", f, OpXaSfF2 (0xd, 1, 3, 0), {F1, F3, F4}, PSEUDO}, - {"fpnma.s0", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}}, - {"fpnma", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, PSEUDO}, - {"fpnma.s1", f, OpXaSf (0xd, 1, 1), {F1, F3, F4, F2}}, - {"fpnma.s2", f, OpXaSf (0xd, 1, 2), {F1, F3, F4, F2}}, - {"fpnma.s3", f, OpXaSf (0xd, 1, 3), {F1, F3, F4, F2}}, - - {"xmpy.l", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO}, - {"xmpy.lu", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO}, - {"xmpy.h", f, OpXaX2F2 (0xe, 1, 3, 0), {F1, F3, F4}, PSEUDO}, - {"xmpy.hu", f, OpXaX2F2 (0xe, 1, 2, 0), {F1, F3, F4}, PSEUDO}, - {"xma.l", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}}, - {"xma.lu", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, PSEUDO}, - {"xma.h", f, OpXaX2 (0xe, 1, 3), {F1, F3, F4, F2}}, - {"xma.hu", f, OpXaX2 (0xe, 1, 2), {F1, F3, F4, F2}}, - - {"fselect", f, OpXa (0xe, 0), {F1, F3, F4, F2}}, - - {0} + {"fnorm.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fadd.s0", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s1", f, OpXaSfF4 (0x8, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s2", f, OpXaSfF4 (0x8, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s3", f, OpXaSfF4 (0x8, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s.s0", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s.s1", f, OpXaSfF4 (0x8, 1, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s.s2", f, OpXaSfF4 (0x8, 1, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.s.s3", f, OpXaSfF4 (0x8, 1, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fmpy.s0", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s1", f, OpXaSfF2 (0x8, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s2", f, OpXaSfF2 (0x8, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s3", f, OpXaSfF2 (0x8, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s.s0", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s.s1", f, OpXaSfF2 (0x8, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s.s2", f, OpXaSfF2 (0x8, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.s.s3", f, OpXaSfF2 (0x8, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fma.s0", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fma", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fma.s1", f, OpXaSf (0x8, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fma.s2", f, OpXaSf (0x8, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fma.s3", f, OpXaSf (0x8, 0, 3), {F1, F3, F4, F2}, EMPTY}, + {"fma.s.s0", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fma.s", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fma.s.s1", f, OpXaSf (0x8, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fma.s.s2", f, OpXaSf (0x8, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fma.s.s3", f, OpXaSf (0x8, 1, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fnorm.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fnorm.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fcvt.xuf.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO, 0, NULL}, + {"fadd.d.s0", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.d", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.d.s1", f, OpXaSfF4 (0x9, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.d.s2", f, OpXaSfF4 (0x9, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fadd.d.s3", f, OpXaSfF4 (0x9, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fmpy.d.s0", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.d", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.d.s1", f, OpXaSfF2 (0x9, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.d.s2", f, OpXaSfF2 (0x9, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fmpy.d.s3", f, OpXaSfF2 (0x9, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fma.d.s0", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fma.d", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fma.d.s1", f, OpXaSf (0x9, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fma.d.s2", f, OpXaSf (0x9, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fma.d.s3", f, OpXaSf (0x9, 0, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fpmpy.s0", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpmpy", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpmpy.s1", f, OpXaSfF2 (0x9, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpmpy.s2", f, OpXaSfF2 (0x9, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpmpy.s3", f, OpXaSfF2 (0x9, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpma.s0", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fpma", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fpma.s1", f, OpXaSf (0x9, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fpma.s2", f, OpXaSf (0x9, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fpma.s3", f, OpXaSf (0x9, 1, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fsub.s0", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s1", f, OpXaSfF4 (0xa, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s2", f, OpXaSfF4 (0xa, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s3", f, OpXaSfF4 (0xa, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s.s0", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s.s1", f, OpXaSfF4 (0xa, 1, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s.s2", f, OpXaSfF4 (0xa, 1, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.s.s3", f, OpXaSfF4 (0xa, 1, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fms.s0", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fms", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fms.s1", f, OpXaSf (0xa, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fms.s2", f, OpXaSf (0xa, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fms.s3", f, OpXaSf (0xa, 0, 3), {F1, F3, F4, F2}, EMPTY}, + {"fms.s.s0", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fms.s", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fms.s.s1", f, OpXaSf (0xa, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fms.s.s2", f, OpXaSf (0xa, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fms.s.s3", f, OpXaSf (0xa, 1, 3), {F1, F3, F4, F2}, EMPTY}, + {"fsub.d.s0", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.d", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.d.s1", f, OpXaSfF4 (0xb, 0, 1, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.d.s2", f, OpXaSfF4 (0xb, 0, 2, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fsub.d.s3", f, OpXaSfF4 (0xb, 0, 3, 1), {F1, F3, F2}, PSEUDO, 0, NULL}, + {"fms.d.s0", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fms.d", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fms.d.s1", f, OpXaSf (0xb, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fms.d.s2", f, OpXaSf (0xb, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fms.d.s3", f, OpXaSf (0xb, 0, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fpms.s0", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fpms", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fpms.s1", f, OpXaSf (0xb, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fpms.s2", f, OpXaSf (0xb, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fpms.s3", f, OpXaSf (0xb, 1, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fnmpy.s0", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s1", f, OpXaSfF2 (0xc, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s2", f, OpXaSfF2 (0xc, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s3", f, OpXaSfF2 (0xc, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s.s0", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s.s1", f, OpXaSfF2 (0xc, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s.s2", f, OpXaSfF2 (0xc, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.s.s3", f, OpXaSfF2 (0xc, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnma.s0", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fnma", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fnma.s1", f, OpXaSf (0xc, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s2", f, OpXaSf (0xc, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s3", f, OpXaSf (0xc, 0, 3), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s.s0", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fnma.s.s1", f, OpXaSf (0xc, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s.s2", f, OpXaSf (0xc, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fnma.s.s3", f, OpXaSf (0xc, 1, 3), {F1, F3, F4, F2}, EMPTY}, + {"fnmpy.d.s0", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.d", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.d.s1", f, OpXaSfF2 (0xd, 0, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.d.s2", f, OpXaSfF2 (0xd, 0, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnmpy.d.s3", f, OpXaSfF2 (0xd, 0, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fnma.d.s0", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, EMPTY}, + {"fnma.d", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fnma.d.s1", f, OpXaSf (0xd, 0, 1), {F1, F3, F4, F2}, EMPTY}, + {"fnma.d.s2", f, OpXaSf (0xd, 0, 2), {F1, F3, F4, F2}, EMPTY}, + {"fnma.d.s3", f, OpXaSf (0xd, 0, 3), {F1, F3, F4, F2}, EMPTY}, + + {"fpnmpy.s0", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnmpy", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnmpy.s1", f, OpXaSfF2 (0xd, 1, 1, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnmpy.s2", f, OpXaSfF2 (0xd, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnmpy.s3", f, OpXaSfF2 (0xd, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"fpnma.s0", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"fpnma", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"fpnma.s1", f, OpXaSf (0xd, 1, 1), {F1, F3, F4, F2}, EMPTY}, + {"fpnma.s2", f, OpXaSf (0xd, 1, 2), {F1, F3, F4, F2}, EMPTY}, + {"fpnma.s3", f, OpXaSf (0xd, 1, 3), {F1, F3, F4, F2}, EMPTY}, + + {"xmpy.l", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"xmpy.lu", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"xmpy.h", f, OpXaX2F2 (0xe, 1, 3, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"xmpy.hu", f, OpXaX2F2 (0xe, 1, 2, 0), {F1, F3, F4}, PSEUDO, 0, NULL}, + {"xma.l", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, EMPTY}, + {"xma.lu", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, PSEUDO, 0, NULL}, + {"xma.h", f, OpXaX2 (0xe, 1, 3), {F1, F3, F4, F2}, EMPTY}, + {"xma.hu", f, OpXaX2 (0xe, 1, 2), {F1, F3, F4, F2}, EMPTY}, + + {"fselect", f, OpXa (0xe, 0), {F1, F3, F4, F2}, EMPTY}, + + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} }; #undef f0 @@ -644,3 +653,4 @@ struct ia64_opcode ia64_opcodes_f[] = #undef OpXbX6 #undef OpXbX6F2 #undef OpXbX6Sf +#undef EMPTY diff --git a/contrib/binutils/opcodes/ia64-opc-i.c b/contrib/binutils/opcodes/ia64-opc-i.c index 899e651..86440f7 100644 --- a/contrib/binutils/opcodes/ia64-opc-i.c +++ b/contrib/binutils/opcodes/ia64-opc-i.c @@ -1,5 +1,5 @@ /* ia64-opc-i.c -- IA-64 `I' opcode table. - Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. Contributed by David Mosberger-Tang <davidm@hpl.hp.com> This file is part of GDB, GAS, and the GNU binutils. @@ -86,6 +86,8 @@ #define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) #define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ (mOp | mX3 | mX6) +#define OpX3X6Yb(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bYb(d)), \ + (mOp | mX3 | mX6 | mYb) #define OpX3XbIhWh(a,b,c,d,e) \ (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \ (mOp | mX3 | mXb | mIh | mWh) @@ -93,17 +95,22 @@ (bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \ (mOp | mX3 | mXb | mIh | mWh | mTag13) +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + struct ia64_opcode ia64_opcodes_i[] = { - /* I-type instruction encodings (sorted according to major opcode) */ + /* I-type instruction encodings (sorted according to major opcode). */ - {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX}, - {"nop.i", I0, OpX3X6 (0, 0, 0x01), {IMMU21}, X_IN_MLX}, - {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}}, + {"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX, 0, NULL}, + {"nop.i", I0, OpX3X6Yb (0, 0, 0x01, 0), {IMMU21}, X_IN_MLX, 0, NULL}, + {"hint.i", I0, OpX3X6Yb (0, 0, 0x01, 1), {IMMU21}, X_IN_MLX, 0, NULL}, + {"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}, EMPTY}, - {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO}, + {"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO, 0, NULL}, #define MOV(a,b,c,d) \ - I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b} + I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}, EMPTY {"mov.sptk", MOV (7, 0, 0, 0)}, {"mov.sptk.imp", MOV (7, 0, 1, 0)}, {"mov", MOV (7, 0, 0, 1)}, @@ -117,46 +124,46 @@ struct ia64_opcode ia64_opcodes_i[] = {"mov.ret.dptk", MOV (7, 1, 0, 2)}, {"mov.ret.dptk.imp", MOV (7, 1, 1, 2)}, #undef MOV - {"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}}, - {"mov", I, OpX3 (0, 3), {PR, R2, IMM17}}, - {"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}}, - {"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}}, - {"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}}, - {"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}}, - {"mov.i", I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}}, - {"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}}, - {"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}}, - {"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}}, - {"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}}, - {"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}}, - {"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}}, - {"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}}, - {"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}}, - {"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}}, - {"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}}, - {"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}}, + {"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}, EMPTY}, + {"mov", I, OpX3 (0, 3), {PR, R2, IMM17}, EMPTY}, + {"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}, EMPTY}, + {"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}, EMPTY}, + {"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}, EMPTY}, + {"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}, EMPTY}, + {"mov.i", I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}, EMPTY}, + {"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}, EMPTY}, + {"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}, EMPTY}, + {"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}, EMPTY}, + {"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}, EMPTY}, + {"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}, EMPTY}, + {"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}, EMPTY}, + {"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}, EMPTY}, + {"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}, EMPTY}, + {"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}, EMPTY}, + {"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}, EMPTY}, + {"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}, EMPTY}, - {"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}}, + {"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}, EMPTY}, - {"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}}, + {"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}, EMPTY}, {"shr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6}, - PSEUDO | LEN_EQ_64MCNT}, - {"extr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}}, + PSEUDO | LEN_EQ_64MCNT, 0, NULL}, + {"extr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}, EMPTY}, {"shr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6}, - PSEUDO | LEN_EQ_64MCNT}, - {"extr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}}, + PSEUDO | LEN_EQ_64MCNT, 0, NULL}, + {"extr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}, EMPTY}, {"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a}, - PSEUDO | LEN_EQ_64MCNT}, - {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}}, - {"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}}, - {"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}}, + PSEUDO | LEN_EQ_64MCNT, 0, NULL}, + {"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}, EMPTY}, + {"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}, EMPTY}, + {"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}, EMPTY}, #define TBIT(a,b,c,d) \ - I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6} + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}, EMPTY #define TBITCM(a,b,c,d) \ - I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO, 0, NULL {"tbit.z", TBIT (0, 0, 0, 0)}, {"tbit.nz", TBITCM (0, 0, 0, 0)}, {"tbit.z.unc", TBIT (0, 0, 0, 1)}, @@ -175,9 +182,9 @@ struct ia64_opcode ia64_opcodes_i[] = {"tbit.z.and.orcm", TBITCM (1, 1, 0, 1)}, #undef TBIT #define TNAT(a,b,c,d) \ - I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3} + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}, EMPTY #define TNATCM(a,b,c,d) \ - I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO + I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO, 0, NULL {"tnat.z", TNAT (0, 0, 1, 0)}, {"tnat.nz", TNATCM (0, 0, 1, 0)}, {"tnat.z.unc", TNAT (0, 0, 1, 1)}, @@ -196,50 +203,50 @@ struct ia64_opcode ia64_opcodes_i[] = {"tnat.z.and.orcm", TNATCM (1, 1, 1, 1)}, #undef TNAT - {"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}}, - {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}}, - {"pmpy2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}}, - {"pmpy2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}}, - {"mix1.r", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}}, - {"mix2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}}, - {"mix4.r", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}}, - {"mix1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}}, - {"mix2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}}, - {"mix4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}}, - {"pack2.uss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}}, - {"pack2.sss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}}, - {"pack4.sss", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}}, - {"unpack1.h", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}}, - {"unpack2.h", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}}, - {"unpack4.h", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}}, - {"unpack1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}}, - {"unpack2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}}, - {"unpack4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}}, - {"pmin1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}}, - {"pmax1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}}, - {"pmin2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}}, - {"pmax2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}}, - {"psad1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}}, - {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}}, - {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}}, - {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}}, - {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}}, - {"shr", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}}, - {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}}, - {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}}, - {"shr.u", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}}, - {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}}, - {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}}, - {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}}, - {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}}, - {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}}, - {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}}, - {"shl", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}}, - {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}}, - {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}}, - {"popcnt", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}}, + {"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}, EMPTY}, + {"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}, EMPTY}, + {"pmpy2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}, EMPTY}, + {"pmpy2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}, EMPTY}, + {"mix1.r", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY}, + {"mix2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}, EMPTY}, + {"mix4.r", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}, EMPTY}, + {"mix1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY}, + {"mix2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}, EMPTY}, + {"mix4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}, EMPTY}, + {"pack2.uss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}, EMPTY}, + {"pack2.sss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}, EMPTY}, + {"pack4.sss", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}, EMPTY}, + {"unpack1.h", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY}, + {"unpack2.h", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}, EMPTY}, + {"unpack4.h", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}, EMPTY}, + {"unpack1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY}, + {"unpack2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}, EMPTY}, + {"unpack4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}, EMPTY}, + {"pmin1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}, EMPTY}, + {"pmax1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}, EMPTY}, + {"pmin2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}, EMPTY}, + {"pmax2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}, EMPTY}, + {"psad1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}, EMPTY}, + {"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}, EMPTY}, + {"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}, EMPTY}, + {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY}, + {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}, EMPTY}, + {"shr", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}, EMPTY}, + {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY}, + {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}, EMPTY}, + {"shr.u", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}, EMPTY}, + {"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY}, + {"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}, EMPTY}, + {"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY}, + {"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}, EMPTY}, + {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, + {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, + {"shl", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}, EMPTY}, + {"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY}, + {"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}, EMPTY}, + {"popcnt", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}, EMPTY}, - {0} + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} }; #undef I0 @@ -294,3 +301,4 @@ struct ia64_opcode ia64_opcodes_i[] = #undef OpX3X6 #undef OpX3XbIhWh #undef OpX3XbIhWhTag13 +#undef EMPTY diff --git a/contrib/binutils/opcodes/ia64-opc-m.c b/contrib/binutils/opcodes/ia64-opc-m.c index bc09816..8e9454b 100644 --- a/contrib/binutils/opcodes/ia64-opc-m.c +++ b/contrib/binutils/opcodes/ia64-opc-m.c @@ -1,5 +1,5 @@ /* ia64-opc-m.c -- IA-64 `M' opcode table. - Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. Contributed by David Mosberger-Tang <davidm@hpl.hp.com> This file is part of GDB, GAS, and the GNU binutils. @@ -33,6 +33,8 @@ #define bX4(x) (((ia64_insn) ((x) & 0xf)) << 27) #define bX6a(x) (((ia64_insn) ((x) & 0x3f)) << 30) #define bX6b(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bX7(x) (((ia64_insn) ((x) & 0x1)) << 36) /* note: alias for bM() */ +#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) #define bHint(x) (((ia64_insn) ((x) & 0x3)) << 28) #define mM bM (-1) @@ -42,15 +44,21 @@ #define mX4 bX4 (-1) #define mX6a bX6a (-1) #define mX6b bX6b (-1) +#define mX7 bX7 (-1) +#define mY bY (-1) #define mHint bHint (-1) #define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3) #define OpX3X6b(a,b,c) (bOp (a) | bX3 (b) | bX6b (c)), \ (mOp | mX3 | mX6b) +#define OpX3X6bX7(a,b,c,d) (bOp (a) | bX3 (b) | bX6b (c) | bX7 (d)), \ + (mOp | mX3 | mX6b | mX7) #define OpX3X4(a,b,c) (bOp (a) | bX3 (b) | bX4 (c)), \ (mOp | mX3 | mX4) #define OpX3X4X2(a,b,c,d) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d)), \ (mOp | mX3 | mX4 | mX2) +#define OpX3X4X2Y(a,b,c,d,e) (bOp (a) | bX3 (b) | bX4 (c) | bX2 (d) | bY (e)), \ + (mOp | mX3 | mX4 | mX2 | mY) #define OpX6aHint(a,b,c) (bOp (a) | bX6a (b) | bHint (c)), \ (mOp | mX6a | mHint) #define OpXX6aHint(a,b,c,d) (bOp (a) | bX (b) | bX6a (c) | bHint (d)), \ @@ -61,208 +69,224 @@ (bOp (a) | bM (b) | bX (c) | bX6a (d) | bHint (e)), \ (mOp | mM | mX | mX6a | mHint) +/* Used to initialise unused fields in ia64_opcode struct, + in order to stop gcc from complaining. */ +#define EMPTY 0,0,NULL + struct ia64_opcode ia64_opcodes_m[] = { - /* M-type instruction encodings (sorted according to major opcode) */ + /* M-type instruction encodings (sorted according to major opcode). */ - {"chk.a.nc", M0, OpX3 (0, 4), {R1, TGT25c}}, - {"chk.a.clr", M0, OpX3 (0, 5), {R1, TGT25c}}, - {"chk.a.nc", M0, OpX3 (0, 6), {F1, TGT25c}}, - {"chk.a.clr", M0, OpX3 (0, 7), {F1, TGT25c}}, + {"chk.a.nc", M0, OpX3 (0, 4), {R1, TGT25c}, EMPTY}, + {"chk.a.clr", M0, OpX3 (0, 5), {R1, TGT25c}, EMPTY}, + {"chk.a.nc", M0, OpX3 (0, 6), {F1, TGT25c}, EMPTY}, + {"chk.a.clr", M0, OpX3 (0, 7), {F1, TGT25c}, EMPTY}, - {"invala", M0, OpX3X4X2 (0, 0, 0, 1)}, - {"fwb", M0, OpX3X4X2 (0, 0, 0, 2)}, - {"mf", M0, OpX3X4X2 (0, 0, 2, 2)}, - {"mf.a", M0, OpX3X4X2 (0, 0, 3, 2)}, - {"srlz.d", M0, OpX3X4X2 (0, 0, 0, 3)}, - {"srlz.i", M0, OpX3X4X2 (0, 0, 1, 3)}, - {"sync.i", M0, OpX3X4X2 (0, 0, 3, 3)}, - {"flushrs", M0, OpX3X4X2 (0, 0, 0xc, 0), {0, }, FIRST | NO_PRED}, - {"loadrs", M0, OpX3X4X2 (0, 0, 0xa, 0), {0, }, FIRST | NO_PRED}, - {"invala.e", M0, OpX3X4X2 (0, 0, 2, 1), {R1}}, - {"invala.e", M0, OpX3X4X2 (0, 0, 3, 1), {F1}}, - {"mov.m", M, OpX3X4X2 (0, 0, 8, 2), {AR3, IMM8}}, + {"invala", M0, OpX3X4X2 (0, 0, 0, 1), {}, EMPTY}, + {"fwb", M0, OpX3X4X2 (0, 0, 0, 2), {}, EMPTY}, + {"mf", M0, OpX3X4X2 (0, 0, 2, 2), {}, EMPTY}, + {"mf.a", M0, OpX3X4X2 (0, 0, 3, 2), {}, EMPTY}, + {"srlz.d", M0, OpX3X4X2 (0, 0, 0, 3), {}, EMPTY}, + {"srlz.i", M0, OpX3X4X2 (0, 0, 1, 3), {}, EMPTY}, + {"sync.i", M0, OpX3X4X2 (0, 0, 3, 3), {}, EMPTY}, + {"flushrs", M0, OpX3X4X2 (0, 0, 0xc, 0), {}, FIRST | NO_PRED, 0, NULL}, + {"loadrs", M0, OpX3X4X2 (0, 0, 0xa, 0), {}, FIRST | NO_PRED, 0, NULL}, + {"invala.e", M0, OpX3X4X2 (0, 0, 2, 1), {R1}, EMPTY}, + {"invala.e", M0, OpX3X4X2 (0, 0, 3, 1), {F1}, EMPTY}, + {"mov.m", M, OpX3X4X2 (0, 0, 8, 2), {AR3, IMM8}, EMPTY}, - {"break.m", M0, OpX3X4X2 (0, 0, 0, 0), {IMMU21}}, - {"nop.m", M0, OpX3X4X2 (0, 0, 1, 0), {IMMU21}}, + {"break.m", M0, OpX3X4X2 (0, 0, 0, 0), {IMMU21}, EMPTY}, + {"nop.m", M0, OpX3X4X2Y (0, 0, 1, 0, 0), {IMMU21}, EMPTY}, + {"hint.m", M0, OpX3X4X2Y (0, 0, 1, 0, 1), {IMMU21}, EMPTY}, - {"sum", M0, OpX3X4 (0, 0, 4), {IMMU24}}, - {"rum", M0, OpX3X4 (0, 0, 5), {IMMU24}}, - {"ssm", M0, OpX3X4 (0, 0, 6), {IMMU24}, PRIV}, - {"rsm", M0, OpX3X4 (0, 0, 7), {IMMU24}, PRIV}, + {"sum", M0, OpX3X4 (0, 0, 4), {IMMU24}, EMPTY}, + {"rum", M0, OpX3X4 (0, 0, 5), {IMMU24}, EMPTY}, + {"ssm", M0, OpX3X4 (0, 0, 6), {IMMU24}, PRIV, 0, NULL}, + {"rsm", M0, OpX3X4 (0, 0, 7), {IMMU24}, PRIV, 0, NULL}, - {"mov.m", M, OpX3X6b (1, 0, 0x2a), {AR3, R2}}, - {"mov.m", M, OpX3X6b (1, 0, 0x22), {R1, AR3}}, - {"mov", M, OpX3X6b (1, 0, 0x2c), {CR3, R2}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x24), {R1, CR3}, PRIV}, + {"mov.m", M, OpX3X6b (1, 0, 0x2a), {AR3, R2}, EMPTY}, + {"mov.m", M, OpX3X6b (1, 0, 0x22), {R1, AR3}, EMPTY}, + {"mov", M, OpX3X6b (1, 0, 0x2c), {CR3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x24), {R1, CR3}, PRIV, 0, NULL}, - {"alloc", M, OpX3 (1, 6), {R1, AR_PFS, SOF, SOL, SOR}, FIRST|NO_PRED|MOD_RRBS}, + {"alloc", M, OpX3 (1, 6), {R1, AR_PFS, SOF, SOL, SOR}, FIRST|NO_PRED|MOD_RRBS, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x2d), {PSR_L, R2}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x29), {PSR_UM, R2}}, - {"mov", M, OpX3X6b (1, 0, 0x25), {R1, PSR}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x21), {R1, PSR_UM}}, - {"probe.r", M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}}, - {"probe.w", M, OpX3X6b (1, 0, 0x39), {R1, R3, R2}}, - {"probe.r", M, OpX3X6b (1, 0, 0x18), {R1, R3, IMMU2}}, - {"probe.w", M, OpX3X6b (1, 0, 0x19), {R1, R3, IMMU2}}, - {"probe.rw.fault", M0, OpX3X6b (1, 0, 0x31), {R3, IMMU2}}, - {"probe.r.fault", M0, OpX3X6b (1, 0, 0x32), {R3, IMMU2}}, - {"probe.w.fault", M0, OpX3X6b (1, 0, 0x33), {R3, IMMU2}}, - {"itc.d", M0, OpX3X6b (1, 0, 0x2e), {R2}, LAST | PRIV}, - {"itc.i", M0, OpX3X6b (1, 0, 0x2f), {R2}, LAST | PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x2d), {PSR_L, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x29), {PSR_UM, R2}, EMPTY}, + {"mov", M, OpX3X6b (1, 0, 0x25), {R1, PSR}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x21), {R1, PSR_UM}, EMPTY}, + {"probe.r", M, OpX3X6b (1, 0, 0x38), {R1, R3, R2}, EMPTY}, + {"probe.w", M, OpX3X6b (1, 0, 0x39), {R1, R3, R2}, EMPTY}, + {"probe.r", M, OpX3X6b (1, 0, 0x18), {R1, R3, IMMU2}, EMPTY}, + {"probe.w", M, OpX3X6b (1, 0, 0x19), {R1, R3, IMMU2}, EMPTY}, + {"probe.rw.fault", M0, OpX3X6b (1, 0, 0x31), {R3, IMMU2}, EMPTY}, + {"probe.r.fault", M0, OpX3X6b (1, 0, 0x32), {R3, IMMU2}, EMPTY}, + {"probe.w.fault", M0, OpX3X6b (1, 0, 0x33), {R3, IMMU2}, EMPTY}, + {"itc.d", M0, OpX3X6b (1, 0, 0x2e), {R2}, LAST | PRIV, 0, NULL}, + {"itc.i", M0, OpX3X6b (1, 0, 0x2f), {R2}, LAST | PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x00), {RR_R3, R2}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x01), {DBR_R3, R2}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x02), {IBR_R3, R2}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x03), {PKR_R3, R2}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x04), {PMC_R3, R2}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x05), {PMD_R3, R2}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x06), {MSR_R3, R2}, PRIV}, - {"itr.d", M, OpX3X6b (1, 0, 0x0e), {DTR_R3, R2}, PRIV}, - {"itr.i", M, OpX3X6b (1, 0, 0x0f), {ITR_R3, R2}, PRIV}, + {"mov", M, OpX3X6b (1, 0, 0x00), {RR_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x01), {DBR_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x02), {IBR_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x03), {PKR_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x04), {PMC_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x05), {PMD_R3, R2}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x06), {MSR_R3, R2}, PRIV, 0, NULL}, + {"itr.d", M, OpX3X6b (1, 0, 0x0e), {DTR_R3, R2}, PRIV, 0, NULL}, + {"itr.i", M, OpX3X6b (1, 0, 0x0f), {ITR_R3, R2}, PRIV, 0, NULL}, - {"mov", M, OpX3X6b (1, 0, 0x10), {R1, RR_R3}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x11), {R1, DBR_R3}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x12), {R1, IBR_R3}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x13), {R1, PKR_R3}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x14), {R1, PMC_R3}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x15), {R1, PMD_R3}}, - {"mov", M, OpX3X6b (1, 0, 0x16), {R1, MSR_R3}, PRIV}, - {"mov", M, OpX3X6b (1, 0, 0x17), {R1, CPUID_R3}}, + {"mov", M, OpX3X6b (1, 0, 0x10), {R1, RR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x11), {R1, DBR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x12), {R1, IBR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x13), {R1, PKR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x14), {R1, PMC_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x15), {R1, PMD_R3}, EMPTY}, + {"mov", M, OpX3X6b (1, 0, 0x16), {R1, MSR_R3}, PRIV, 0, NULL}, + {"mov", M, OpX3X6b (1, 0, 0x17), {R1, CPUID_R3}, EMPTY}, - {"ptc.l", M0, OpX3X6b (1, 0, 0x09), {R3, R2}, PRIV}, - {"ptc.g", M0, OpX3X6b (1, 0, 0x0a), {R3, R2}, LAST | PRIV}, - {"ptc.ga", M0, OpX3X6b (1, 0, 0x0b), {R3, R2}, LAST | PRIV}, - {"ptr.d", M0, OpX3X6b (1, 0, 0x0c), {R3, R2}, PRIV}, - {"ptr.i", M0, OpX3X6b (1, 0, 0x0d), {R3, R2}, PRIV}, + {"ptc.l", M0, OpX3X6b (1, 0, 0x09), {R3, R2}, PRIV, 0, NULL}, + {"ptc.g", M0, OpX3X6b (1, 0, 0x0a), {R3, R2}, LAST | PRIV, 0, NULL}, + {"ptc.ga", M0, OpX3X6b (1, 0, 0x0b), {R3, R2}, LAST | PRIV, 0, NULL}, + {"ptr.d", M0, OpX3X6b (1, 0, 0x0c), {R3, R2}, PRIV, 0, NULL}, + {"ptr.i", M0, OpX3X6b (1, 0, 0x0d), {R3, R2}, PRIV, 0, NULL}, - {"thash", M, OpX3X6b (1, 0, 0x1a), {R1, R3}}, - {"ttag", M, OpX3X6b (1, 0, 0x1b), {R1, R3}}, - {"tpa", M, OpX3X6b (1, 0, 0x1e), {R1, R3}, PRIV}, - {"tak", M, OpX3X6b (1, 0, 0x1f), {R1, R3}, PRIV}, + {"thash", M, OpX3X6b (1, 0, 0x1a), {R1, R3}, EMPTY}, + {"ttag", M, OpX3X6b (1, 0, 0x1b), {R1, R3}, EMPTY}, + {"tpa", M, OpX3X6b (1, 0, 0x1e), {R1, R3}, PRIV, 0, NULL}, + {"tak", M, OpX3X6b (1, 0, 0x1f), {R1, R3}, PRIV, 0, NULL}, - {"chk.s.m", M0, OpX3 (1, 1), {R2, TGT25b}}, - {"chk.s", M0, OpX3 (1, 3), {F2, TGT25b}}, + {"chk.s.m", M0, OpX3 (1, 1), {R2, TGT25b}, EMPTY}, + {"chk.s", M0, OpX3 (1, 3), {F2, TGT25b}, EMPTY}, - {"fc", M0, OpX3X6b (1, 0, 0x30), {R3}}, - {"ptc.e", M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV}, + {"fc", M0, OpX3X6bX7 (1, 0, 0x30, 0), {R3}, EMPTY}, + {"fc.i", M0, OpX3X6bX7 (1, 0, 0x30, 1), {R3}, EMPTY}, + {"ptc.e", M0, OpX3X6b (1, 0, 0x34), {R3}, PRIV, 0, NULL}, /* integer load */ - {"ld1", M, OpMXX6aHint (4, 0, 0, 0x00, 0), {R1, MR3}}, - {"ld1.nt1", M, OpMXX6aHint (4, 0, 0, 0x00, 1), {R1, MR3}}, - {"ld1.nta", M, OpMXX6aHint (4, 0, 0, 0x00, 3), {R1, MR3}}, - {"ld2", M, OpMXX6aHint (4, 0, 0, 0x01, 0), {R1, MR3}}, - {"ld2.nt1", M, OpMXX6aHint (4, 0, 0, 0x01, 1), {R1, MR3}}, - {"ld2.nta", M, OpMXX6aHint (4, 0, 0, 0x01, 3), {R1, MR3}}, - {"ld4", M, OpMXX6aHint (4, 0, 0, 0x02, 0), {R1, MR3}}, - {"ld4.nt1", M, OpMXX6aHint (4, 0, 0, 0x02, 1), {R1, MR3}}, - {"ld4.nta", M, OpMXX6aHint (4, 0, 0, 0x02, 3), {R1, MR3}}, - {"ld8", M, OpMXX6aHint (4, 0, 0, 0x03, 0), {R1, MR3}}, - {"ld8.nt1", M, OpMXX6aHint (4, 0, 0, 0x03, 1), {R1, MR3}}, - {"ld8.nta", M, OpMXX6aHint (4, 0, 0, 0x03, 3), {R1, MR3}}, - {"ld1.s", M, OpMXX6aHint (4, 0, 0, 0x04, 0), {R1, MR3}}, - {"ld1.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x04, 1), {R1, MR3}}, - {"ld1.s.nta", M, OpMXX6aHint (4, 0, 0, 0x04, 3), {R1, MR3}}, - {"ld2.s", M, OpMXX6aHint (4, 0, 0, 0x05, 0), {R1, MR3}}, - {"ld2.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x05, 1), {R1, MR3}}, - {"ld2.s.nta", M, OpMXX6aHint (4, 0, 0, 0x05, 3), {R1, MR3}}, - {"ld4.s", M, OpMXX6aHint (4, 0, 0, 0x06, 0), {R1, MR3}}, - {"ld4.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x06, 1), {R1, MR3}}, - {"ld4.s.nta", M, OpMXX6aHint (4, 0, 0, 0x06, 3), {R1, MR3}}, - {"ld8.s", M, OpMXX6aHint (4, 0, 0, 0x07, 0), {R1, MR3}}, - {"ld8.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x07, 1), {R1, MR3}}, - {"ld8.s.nta", M, OpMXX6aHint (4, 0, 0, 0x07, 3), {R1, MR3}}, - {"ld1.a", M, OpMXX6aHint (4, 0, 0, 0x08, 0), {R1, MR3}}, - {"ld1.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x08, 1), {R1, MR3}}, - {"ld1.a.nta", M, OpMXX6aHint (4, 0, 0, 0x08, 3), {R1, MR3}}, - {"ld2.a", M, OpMXX6aHint (4, 0, 0, 0x09, 0), {R1, MR3}}, - {"ld2.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x09, 1), {R1, MR3}}, - {"ld2.a.nta", M, OpMXX6aHint (4, 0, 0, 0x09, 3), {R1, MR3}}, - {"ld4.a", M, OpMXX6aHint (4, 0, 0, 0x0a, 0), {R1, MR3}}, - {"ld4.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0a, 1), {R1, MR3}}, - {"ld4.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0a, 3), {R1, MR3}}, - {"ld8.a", M, OpMXX6aHint (4, 0, 0, 0x0b, 0), {R1, MR3}}, - {"ld8.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0b, 1), {R1, MR3}}, - {"ld8.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0b, 3), {R1, MR3}}, - {"ld1.sa", M, OpMXX6aHint (4, 0, 0, 0x0c, 0), {R1, MR3}}, - {"ld1.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0c, 1), {R1, MR3}}, - {"ld1.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0c, 3), {R1, MR3}}, - {"ld2.sa", M, OpMXX6aHint (4, 0, 0, 0x0d, 0), {R1, MR3}}, - {"ld2.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0d, 1), {R1, MR3}}, - {"ld2.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0d, 3), {R1, MR3}}, - {"ld4.sa", M, OpMXX6aHint (4, 0, 0, 0x0e, 0), {R1, MR3}}, - {"ld4.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0e, 1), {R1, MR3}}, - {"ld4.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0e, 3), {R1, MR3}}, - {"ld8.sa", M, OpMXX6aHint (4, 0, 0, 0x0f, 0), {R1, MR3}}, - {"ld8.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0f, 1), {R1, MR3}}, - {"ld8.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0f, 3), {R1, MR3}}, - {"ld1.bias", M, OpMXX6aHint (4, 0, 0, 0x10, 0), {R1, MR3}}, - {"ld1.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x10, 1), {R1, MR3}}, - {"ld1.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x10, 3), {R1, MR3}}, - {"ld2.bias", M, OpMXX6aHint (4, 0, 0, 0x11, 0), {R1, MR3}}, - {"ld2.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x11, 1), {R1, MR3}}, - {"ld2.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x11, 3), {R1, MR3}}, - {"ld4.bias", M, OpMXX6aHint (4, 0, 0, 0x12, 0), {R1, MR3}}, - {"ld4.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x12, 1), {R1, MR3}}, - {"ld4.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x12, 3), {R1, MR3}}, - {"ld8.bias", M, OpMXX6aHint (4, 0, 0, 0x13, 0), {R1, MR3}}, - {"ld8.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x13, 1), {R1, MR3}}, - {"ld8.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x13, 3), {R1, MR3}}, - {"ld1.acq", M, OpMXX6aHint (4, 0, 0, 0x14, 0), {R1, MR3}}, - {"ld1.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x14, 1), {R1, MR3}}, - {"ld1.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x14, 3), {R1, MR3}}, - {"ld2.acq", M, OpMXX6aHint (4, 0, 0, 0x15, 0), {R1, MR3}}, - {"ld2.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x15, 1), {R1, MR3}}, - {"ld2.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x15, 3), {R1, MR3}}, - {"ld4.acq", M, OpMXX6aHint (4, 0, 0, 0x16, 0), {R1, MR3}}, - {"ld4.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x16, 1), {R1, MR3}}, - {"ld4.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x16, 3), {R1, MR3}}, - {"ld8.acq", M, OpMXX6aHint (4, 0, 0, 0x17, 0), {R1, MR3}}, - {"ld8.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x17, 1), {R1, MR3}}, - {"ld8.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x17, 3), {R1, MR3}}, - {"ld8.fill", M, OpMXX6aHint (4, 0, 0, 0x1b, 0), {R1, MR3}}, - {"ld8.fill.nt1", M, OpMXX6aHint (4, 0, 0, 0x1b, 1), {R1, MR3}}, - {"ld8.fill.nta", M, OpMXX6aHint (4, 0, 0, 0x1b, 3), {R1, MR3}}, - {"ld1.c.clr", M, OpMXX6aHint (4, 0, 0, 0x20, 0), {R1, MR3}}, - {"ld1.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x20, 1), {R1, MR3}}, - {"ld1.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x20, 3), {R1, MR3}}, - {"ld2.c.clr", M, OpMXX6aHint (4, 0, 0, 0x21, 0), {R1, MR3}}, - {"ld2.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x21, 1), {R1, MR3}}, - {"ld2.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x21, 3), {R1, MR3}}, - {"ld4.c.clr", M, OpMXX6aHint (4, 0, 0, 0x22, 0), {R1, MR3}}, - {"ld4.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x22, 1), {R1, MR3}}, - {"ld4.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x22, 3), {R1, MR3}}, - {"ld8.c.clr", M, OpMXX6aHint (4, 0, 0, 0x23, 0), {R1, MR3}}, - {"ld8.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x23, 1), {R1, MR3}}, - {"ld8.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x23, 3), {R1, MR3}}, - {"ld1.c.nc", M, OpMXX6aHint (4, 0, 0, 0x24, 0), {R1, MR3}}, - {"ld1.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x24, 1), {R1, MR3}}, - {"ld1.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x24, 3), {R1, MR3}}, - {"ld2.c.nc", M, OpMXX6aHint (4, 0, 0, 0x25, 0), {R1, MR3}}, - {"ld2.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x25, 1), {R1, MR3}}, - {"ld2.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x25, 3), {R1, MR3}}, - {"ld4.c.nc", M, OpMXX6aHint (4, 0, 0, 0x26, 0), {R1, MR3}}, - {"ld4.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x26, 1), {R1, MR3}}, - {"ld4.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x26, 3), {R1, MR3}}, - {"ld8.c.nc", M, OpMXX6aHint (4, 0, 0, 0x27, 0), {R1, MR3}}, - {"ld8.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x27, 1), {R1, MR3}}, - {"ld8.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x27, 3), {R1, MR3}}, - {"ld1.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x28, 0), {R1, MR3}}, - {"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x28, 1), {R1, MR3}}, - {"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x28, 3), {R1, MR3}}, - {"ld2.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x29, 0), {R1, MR3}}, - {"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x29, 1), {R1, MR3}}, - {"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x29, 3), {R1, MR3}}, - {"ld4.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2a, 0), {R1, MR3}}, - {"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2a, 1), {R1, MR3}}, - {"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2a, 3), {R1, MR3}}, - {"ld8.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2b, 0), {R1, MR3}}, - {"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2b, 1), {R1, MR3}}, - {"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2b, 3), {R1, MR3}}, + {"ld1", M, OpMXX6aHint (4, 0, 0, 0x00, 0), {R1, MR3}, EMPTY}, + {"ld1.nt1", M, OpMXX6aHint (4, 0, 0, 0x00, 1), {R1, MR3}, EMPTY}, + {"ld1.nta", M, OpMXX6aHint (4, 0, 0, 0x00, 3), {R1, MR3}, EMPTY}, + {"ld2", M, OpMXX6aHint (4, 0, 0, 0x01, 0), {R1, MR3}, EMPTY}, + {"ld2.nt1", M, OpMXX6aHint (4, 0, 0, 0x01, 1), {R1, MR3}, EMPTY}, + {"ld2.nta", M, OpMXX6aHint (4, 0, 0, 0x01, 3), {R1, MR3}, EMPTY}, + {"ld4", M, OpMXX6aHint (4, 0, 0, 0x02, 0), {R1, MR3}, EMPTY}, + {"ld4.nt1", M, OpMXX6aHint (4, 0, 0, 0x02, 1), {R1, MR3}, EMPTY}, + {"ld4.nta", M, OpMXX6aHint (4, 0, 0, 0x02, 3), {R1, MR3}, EMPTY}, + {"ld8", M, OpMXX6aHint (4, 0, 0, 0x03, 0), {R1, MR3}, EMPTY}, + {"ld8.nt1", M, OpMXX6aHint (4, 0, 0, 0x03, 1), {R1, MR3}, EMPTY}, + {"ld8.nta", M, OpMXX6aHint (4, 0, 0, 0x03, 3), {R1, MR3}, EMPTY}, + {"ld16", M2, OpMXX6aHint (4, 0, 1, 0x28, 0), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16.nt1", M2, OpMXX6aHint (4, 0, 1, 0x28, 1), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16.nta", M2, OpMXX6aHint (4, 0, 1, 0x28, 3), {R1, AR_CSD, MR3}, EMPTY}, + {"ld1.s", M, OpMXX6aHint (4, 0, 0, 0x04, 0), {R1, MR3}, EMPTY}, + {"ld1.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x04, 1), {R1, MR3}, EMPTY}, + {"ld1.s.nta", M, OpMXX6aHint (4, 0, 0, 0x04, 3), {R1, MR3}, EMPTY}, + {"ld2.s", M, OpMXX6aHint (4, 0, 0, 0x05, 0), {R1, MR3}, EMPTY}, + {"ld2.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x05, 1), {R1, MR3}, EMPTY}, + {"ld2.s.nta", M, OpMXX6aHint (4, 0, 0, 0x05, 3), {R1, MR3}, EMPTY}, + {"ld4.s", M, OpMXX6aHint (4, 0, 0, 0x06, 0), {R1, MR3}, EMPTY}, + {"ld4.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x06, 1), {R1, MR3}, EMPTY}, + {"ld4.s.nta", M, OpMXX6aHint (4, 0, 0, 0x06, 3), {R1, MR3}, EMPTY}, + {"ld8.s", M, OpMXX6aHint (4, 0, 0, 0x07, 0), {R1, MR3}, EMPTY}, + {"ld8.s.nt1", M, OpMXX6aHint (4, 0, 0, 0x07, 1), {R1, MR3}, EMPTY}, + {"ld8.s.nta", M, OpMXX6aHint (4, 0, 0, 0x07, 3), {R1, MR3}, EMPTY}, + {"ld1.a", M, OpMXX6aHint (4, 0, 0, 0x08, 0), {R1, MR3}, EMPTY}, + {"ld1.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x08, 1), {R1, MR3}, EMPTY}, + {"ld1.a.nta", M, OpMXX6aHint (4, 0, 0, 0x08, 3), {R1, MR3}, EMPTY}, + {"ld2.a", M, OpMXX6aHint (4, 0, 0, 0x09, 0), {R1, MR3}, EMPTY}, + {"ld2.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x09, 1), {R1, MR3}, EMPTY}, + {"ld2.a.nta", M, OpMXX6aHint (4, 0, 0, 0x09, 3), {R1, MR3}, EMPTY}, + {"ld4.a", M, OpMXX6aHint (4, 0, 0, 0x0a, 0), {R1, MR3}, EMPTY}, + {"ld4.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0a, 1), {R1, MR3}, EMPTY}, + {"ld4.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0a, 3), {R1, MR3}, EMPTY}, + {"ld8.a", M, OpMXX6aHint (4, 0, 0, 0x0b, 0), {R1, MR3}, EMPTY}, + {"ld8.a.nt1", M, OpMXX6aHint (4, 0, 0, 0x0b, 1), {R1, MR3}, EMPTY}, + {"ld8.a.nta", M, OpMXX6aHint (4, 0, 0, 0x0b, 3), {R1, MR3}, EMPTY}, + {"ld1.sa", M, OpMXX6aHint (4, 0, 0, 0x0c, 0), {R1, MR3}, EMPTY}, + {"ld1.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0c, 1), {R1, MR3}, EMPTY}, + {"ld1.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0c, 3), {R1, MR3}, EMPTY}, + {"ld2.sa", M, OpMXX6aHint (4, 0, 0, 0x0d, 0), {R1, MR3}, EMPTY}, + {"ld2.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0d, 1), {R1, MR3}, EMPTY}, + {"ld2.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0d, 3), {R1, MR3}, EMPTY}, + {"ld4.sa", M, OpMXX6aHint (4, 0, 0, 0x0e, 0), {R1, MR3}, EMPTY}, + {"ld4.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0e, 1), {R1, MR3}, EMPTY}, + {"ld4.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0e, 3), {R1, MR3}, EMPTY}, + {"ld8.sa", M, OpMXX6aHint (4, 0, 0, 0x0f, 0), {R1, MR3}, EMPTY}, + {"ld8.sa.nt1", M, OpMXX6aHint (4, 0, 0, 0x0f, 1), {R1, MR3}, EMPTY}, + {"ld8.sa.nta", M, OpMXX6aHint (4, 0, 0, 0x0f, 3), {R1, MR3}, EMPTY}, + {"ld1.bias", M, OpMXX6aHint (4, 0, 0, 0x10, 0), {R1, MR3}, EMPTY}, + {"ld1.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x10, 1), {R1, MR3}, EMPTY}, + {"ld1.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x10, 3), {R1, MR3}, EMPTY}, + {"ld2.bias", M, OpMXX6aHint (4, 0, 0, 0x11, 0), {R1, MR3}, EMPTY}, + {"ld2.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x11, 1), {R1, MR3}, EMPTY}, + {"ld2.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x11, 3), {R1, MR3}, EMPTY}, + {"ld4.bias", M, OpMXX6aHint (4, 0, 0, 0x12, 0), {R1, MR3}, EMPTY}, + {"ld4.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x12, 1), {R1, MR3}, EMPTY}, + {"ld4.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x12, 3), {R1, MR3}, EMPTY}, + {"ld8.bias", M, OpMXX6aHint (4, 0, 0, 0x13, 0), {R1, MR3}, EMPTY}, + {"ld8.bias.nt1", M, OpMXX6aHint (4, 0, 0, 0x13, 1), {R1, MR3}, EMPTY}, + {"ld8.bias.nta", M, OpMXX6aHint (4, 0, 0, 0x13, 3), {R1, MR3}, EMPTY}, + {"ld1.acq", M, OpMXX6aHint (4, 0, 0, 0x14, 0), {R1, MR3}, EMPTY}, + {"ld1.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x14, 1), {R1, MR3}, EMPTY}, + {"ld1.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x14, 3), {R1, MR3}, EMPTY}, + {"ld2.acq", M, OpMXX6aHint (4, 0, 0, 0x15, 0), {R1, MR3}, EMPTY}, + {"ld2.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x15, 1), {R1, MR3}, EMPTY}, + {"ld2.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x15, 3), {R1, MR3}, EMPTY}, + {"ld4.acq", M, OpMXX6aHint (4, 0, 0, 0x16, 0), {R1, MR3}, EMPTY}, + {"ld4.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x16, 1), {R1, MR3}, EMPTY}, + {"ld4.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x16, 3), {R1, MR3}, EMPTY}, + {"ld8.acq", M, OpMXX6aHint (4, 0, 0, 0x17, 0), {R1, MR3}, EMPTY}, + {"ld8.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x17, 1), {R1, MR3}, EMPTY}, + {"ld8.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x17, 3), {R1, MR3}, EMPTY}, + {"ld16.acq", M2, OpMXX6aHint (4, 0, 1, 0x2c, 0), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16.acq.nt1", M2, OpMXX6aHint (4, 0, 1, 0x2c, 1), {R1, AR_CSD, MR3}, EMPTY}, + {"ld16.acq.nta", M2, OpMXX6aHint (4, 0, 1, 0x2c, 3), {R1, AR_CSD, MR3}, EMPTY}, + {"ld8.fill", M, OpMXX6aHint (4, 0, 0, 0x1b, 0), {R1, MR3}, EMPTY}, + {"ld8.fill.nt1", M, OpMXX6aHint (4, 0, 0, 0x1b, 1), {R1, MR3}, EMPTY}, + {"ld8.fill.nta", M, OpMXX6aHint (4, 0, 0, 0x1b, 3), {R1, MR3}, EMPTY}, + {"ld1.c.clr", M, OpMXX6aHint (4, 0, 0, 0x20, 0), {R1, MR3}, EMPTY}, + {"ld1.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x20, 1), {R1, MR3}, EMPTY}, + {"ld1.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x20, 3), {R1, MR3}, EMPTY}, + {"ld2.c.clr", M, OpMXX6aHint (4, 0, 0, 0x21, 0), {R1, MR3}, EMPTY}, + {"ld2.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x21, 1), {R1, MR3}, EMPTY}, + {"ld2.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x21, 3), {R1, MR3}, EMPTY}, + {"ld4.c.clr", M, OpMXX6aHint (4, 0, 0, 0x22, 0), {R1, MR3}, EMPTY}, + {"ld4.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x22, 1), {R1, MR3}, EMPTY}, + {"ld4.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x22, 3), {R1, MR3}, EMPTY}, + {"ld8.c.clr", M, OpMXX6aHint (4, 0, 0, 0x23, 0), {R1, MR3}, EMPTY}, + {"ld8.c.clr.nt1", M, OpMXX6aHint (4, 0, 0, 0x23, 1), {R1, MR3}, EMPTY}, + {"ld8.c.clr.nta", M, OpMXX6aHint (4, 0, 0, 0x23, 3), {R1, MR3}, EMPTY}, + {"ld1.c.nc", M, OpMXX6aHint (4, 0, 0, 0x24, 0), {R1, MR3}, EMPTY}, + {"ld1.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x24, 1), {R1, MR3}, EMPTY}, + {"ld1.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x24, 3), {R1, MR3}, EMPTY}, + {"ld2.c.nc", M, OpMXX6aHint (4, 0, 0, 0x25, 0), {R1, MR3}, EMPTY}, + {"ld2.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x25, 1), {R1, MR3}, EMPTY}, + {"ld2.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x25, 3), {R1, MR3}, EMPTY}, + {"ld4.c.nc", M, OpMXX6aHint (4, 0, 0, 0x26, 0), {R1, MR3}, EMPTY}, + {"ld4.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x26, 1), {R1, MR3}, EMPTY}, + {"ld4.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x26, 3), {R1, MR3}, EMPTY}, + {"ld8.c.nc", M, OpMXX6aHint (4, 0, 0, 0x27, 0), {R1, MR3}, EMPTY}, + {"ld8.c.nc.nt1", M, OpMXX6aHint (4, 0, 0, 0x27, 1), {R1, MR3}, EMPTY}, + {"ld8.c.nc.nta", M, OpMXX6aHint (4, 0, 0, 0x27, 3), {R1, MR3}, EMPTY}, + {"ld1.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x28, 0), {R1, MR3}, EMPTY}, + {"ld1.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x28, 1), {R1, MR3}, EMPTY}, + {"ld1.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x28, 3), {R1, MR3}, EMPTY}, + {"ld2.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x29, 0), {R1, MR3}, EMPTY}, + {"ld2.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x29, 1), {R1, MR3}, EMPTY}, + {"ld2.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x29, 3), {R1, MR3}, EMPTY}, + {"ld4.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2a, 0), {R1, MR3}, EMPTY}, + {"ld4.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2a, 1), {R1, MR3}, EMPTY}, + {"ld4.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2a, 3), {R1, MR3}, EMPTY}, + {"ld8.c.clr.acq", M, OpMXX6aHint (4, 0, 0, 0x2b, 0), {R1, MR3}, EMPTY}, + {"ld8.c.clr.acq.nt1", M, OpMXX6aHint (4, 0, 0, 0x2b, 1), {R1, MR3}, EMPTY}, + {"ld8.c.clr.acq.nta", M, OpMXX6aHint (4, 0, 0, 0x2b, 3), {R1, MR3}, EMPTY}, + + /* Pseudo-op that generates ldxmov relocation. */ + {"ld8.mov", M, OpMXX6aHint (4, 0, 0, 0x03, 0), + {R1, MR3, IA64_OPND_LDXMOV}, EMPTY}, - /* integer load w/increment by register */ -#define LDINCREG(c,h) M, OpMXX6aHint (4, 1, 0, c, h), {R1, MR3, R2}, POSTINC, + /* Integer load w/increment by register. */ +#define LDINCREG(c,h) M, OpMXX6aHint (4, 1, 0, c, h), {R1, MR3, R2}, POSTINC, 0, NULL {"ld1", LDINCREG (0x00, 0)}, {"ld1.nt1", LDINCREG (0x00, 1)}, {"ld1.nta", LDINCREG (0x00, 3)}, @@ -376,26 +400,31 @@ struct ia64_opcode ia64_opcodes_m[] = {"ld8.c.clr.acq.nta", LDINCREG (0x2b, 3)}, #undef LDINCREG - {"st1", M, OpMXX6aHint (4, 0, 0, 0x30, 0), {MR3, R2}}, - {"st1.nta", M, OpMXX6aHint (4, 0, 0, 0x30, 3), {MR3, R2}}, - {"st2", M, OpMXX6aHint (4, 0, 0, 0x31, 0), {MR3, R2}}, - {"st2.nta", M, OpMXX6aHint (4, 0, 0, 0x31, 3), {MR3, R2}}, - {"st4", M, OpMXX6aHint (4, 0, 0, 0x32, 0), {MR3, R2}}, - {"st4.nta", M, OpMXX6aHint (4, 0, 0, 0x32, 3), {MR3, R2}}, - {"st8", M, OpMXX6aHint (4, 0, 0, 0x33, 0), {MR3, R2}}, - {"st8.nta", M, OpMXX6aHint (4, 0, 0, 0x33, 3), {MR3, R2}}, - {"st1.rel", M, OpMXX6aHint (4, 0, 0, 0x34, 0), {MR3, R2}}, - {"st1.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x34, 3), {MR3, R2}}, - {"st2.rel", M, OpMXX6aHint (4, 0, 0, 0x35, 0), {MR3, R2}}, - {"st2.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x35, 3), {MR3, R2}}, - {"st4.rel", M, OpMXX6aHint (4, 0, 0, 0x36, 0), {MR3, R2}}, - {"st4.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x36, 3), {MR3, R2}}, - {"st8.rel", M, OpMXX6aHint (4, 0, 0, 0x37, 0), {MR3, R2}}, - {"st8.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x37, 3), {MR3, R2}}, - {"st8.spill", M, OpMXX6aHint (4, 0, 0, 0x3b, 0), {MR3, R2}}, - {"st8.spill.nta", M, OpMXX6aHint (4, 0, 0, 0x3b, 3), {MR3, R2}}, + {"st1", M, OpMXX6aHint (4, 0, 0, 0x30, 0), {MR3, R2}, EMPTY}, + {"st1.nta", M, OpMXX6aHint (4, 0, 0, 0x30, 3), {MR3, R2}, EMPTY}, + {"st2", M, OpMXX6aHint (4, 0, 0, 0x31, 0), {MR3, R2}, EMPTY}, + {"st2.nta", M, OpMXX6aHint (4, 0, 0, 0x31, 3), {MR3, R2}, EMPTY}, + {"st4", M, OpMXX6aHint (4, 0, 0, 0x32, 0), {MR3, R2}, EMPTY}, + {"st4.nta", M, OpMXX6aHint (4, 0, 0, 0x32, 3), {MR3, R2}, EMPTY}, + {"st8", M, OpMXX6aHint (4, 0, 0, 0x33, 0), {MR3, R2}, EMPTY}, + {"st8.nta", M, OpMXX6aHint (4, 0, 0, 0x33, 3), {MR3, R2}, EMPTY}, + {"st16", M, OpMXX6aHint (4, 0, 1, 0x30, 0), {MR3, R2, AR_CSD}, EMPTY}, + {"st16.nta", M, OpMXX6aHint (4, 0, 1, 0x30, 3), {MR3, R2, AR_CSD}, EMPTY}, + {"st1.rel", M, OpMXX6aHint (4, 0, 0, 0x34, 0), {MR3, R2}, EMPTY}, + {"st1.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x34, 3), {MR3, R2}, EMPTY}, + {"st2.rel", M, OpMXX6aHint (4, 0, 0, 0x35, 0), {MR3, R2}, EMPTY}, + {"st2.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x35, 3), {MR3, R2}, EMPTY}, + {"st4.rel", M, OpMXX6aHint (4, 0, 0, 0x36, 0), {MR3, R2}, EMPTY}, + {"st4.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x36, 3), {MR3, R2}, EMPTY}, + {"st8.rel", M, OpMXX6aHint (4, 0, 0, 0x37, 0), {MR3, R2}, EMPTY}, + {"st8.rel.nta", M, OpMXX6aHint (4, 0, 0, 0x37, 3), {MR3, R2}, EMPTY}, + {"st16.rel", M, OpMXX6aHint (4, 0, 1, 0x34, 0), {MR3, R2, AR_CSD}, EMPTY}, + {"st16.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x34, 3), {MR3, R2, AR_CSD}, EMPTY}, + {"st8.spill", M, OpMXX6aHint (4, 0, 0, 0x3b, 0), {MR3, R2}, EMPTY}, + {"st8.spill.nta", M, OpMXX6aHint (4, 0, 0, 0x3b, 3), {MR3, R2}, EMPTY}, -#define CMPXCHG(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV} +#define CMPXCHG(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CCV}, EMPTY +#define CMPXCHG16(c,h) M, OpMXX6aHint (4, 0, 1, c, h), {R1, MR3, R2, AR_CSD, AR_CCV}, EMPTY {"cmpxchg1.acq", CMPXCHG (0x00, 0)}, {"cmpxchg1.acq.nt1", CMPXCHG (0x00, 1)}, {"cmpxchg1.acq.nta", CMPXCHG (0x00, 3)}, @@ -408,6 +437,9 @@ struct ia64_opcode ia64_opcodes_m[] = {"cmpxchg8.acq", CMPXCHG (0x03, 0)}, {"cmpxchg8.acq.nt1", CMPXCHG (0x03, 1)}, {"cmpxchg8.acq.nta", CMPXCHG (0x03, 3)}, + {"cmp8xchg16.acq", CMPXCHG16 (0x20, 0)}, + {"cmp8xchg16.acq.nt1", CMPXCHG16 (0x20, 1)}, + {"cmp8xchg16.acq.nta", CMPXCHG16 (0x20, 3)}, {"cmpxchg1.rel", CMPXCHG (0x04, 0)}, {"cmpxchg1.rel.nt1", CMPXCHG (0x04, 1)}, {"cmpxchg1.rel.nta", CMPXCHG (0x04, 3)}, @@ -420,40 +452,44 @@ struct ia64_opcode ia64_opcodes_m[] = {"cmpxchg8.rel", CMPXCHG (0x07, 0)}, {"cmpxchg8.rel.nt1", CMPXCHG (0x07, 1)}, {"cmpxchg8.rel.nta", CMPXCHG (0x07, 3)}, + {"cmp8xchg16.rel", CMPXCHG16 (0x24, 0)}, + {"cmp8xchg16.rel.nt1", CMPXCHG16 (0x24, 1)}, + {"cmp8xchg16.rel.nta", CMPXCHG16 (0x24, 3)}, #undef CMPXCHG - {"xchg1", M, OpMXX6aHint (4, 0, 1, 0x08, 0), {R1, MR3, R2}}, - {"xchg1.nt1", M, OpMXX6aHint (4, 0, 1, 0x08, 1), {R1, MR3, R2}}, - {"xchg1.nta", M, OpMXX6aHint (4, 0, 1, 0x08, 3), {R1, MR3, R2}}, - {"xchg2", M, OpMXX6aHint (4, 0, 1, 0x09, 0), {R1, MR3, R2}}, - {"xchg2.nt1", M, OpMXX6aHint (4, 0, 1, 0x09, 1), {R1, MR3, R2}}, - {"xchg2.nta", M, OpMXX6aHint (4, 0, 1, 0x09, 3), {R1, MR3, R2}}, - {"xchg4", M, OpMXX6aHint (4, 0, 1, 0x0a, 0), {R1, MR3, R2}}, - {"xchg4.nt1", M, OpMXX6aHint (4, 0, 1, 0x0a, 1), {R1, MR3, R2}}, - {"xchg4.nta", M, OpMXX6aHint (4, 0, 1, 0x0a, 3), {R1, MR3, R2}}, - {"xchg8", M, OpMXX6aHint (4, 0, 1, 0x0b, 0), {R1, MR3, R2}}, - {"xchg8.nt1", M, OpMXX6aHint (4, 0, 1, 0x0b, 1), {R1, MR3, R2}}, - {"xchg8.nta", M, OpMXX6aHint (4, 0, 1, 0x0b, 3), {R1, MR3, R2}}, +#undef CMPXCHG16 + {"xchg1", M, OpMXX6aHint (4, 0, 1, 0x08, 0), {R1, MR3, R2}, EMPTY}, + {"xchg1.nt1", M, OpMXX6aHint (4, 0, 1, 0x08, 1), {R1, MR3, R2}, EMPTY}, + {"xchg1.nta", M, OpMXX6aHint (4, 0, 1, 0x08, 3), {R1, MR3, R2}, EMPTY}, + {"xchg2", M, OpMXX6aHint (4, 0, 1, 0x09, 0), {R1, MR3, R2}, EMPTY}, + {"xchg2.nt1", M, OpMXX6aHint (4, 0, 1, 0x09, 1), {R1, MR3, R2}, EMPTY}, + {"xchg2.nta", M, OpMXX6aHint (4, 0, 1, 0x09, 3), {R1, MR3, R2}, EMPTY}, + {"xchg4", M, OpMXX6aHint (4, 0, 1, 0x0a, 0), {R1, MR3, R2}, EMPTY}, + {"xchg4.nt1", M, OpMXX6aHint (4, 0, 1, 0x0a, 1), {R1, MR3, R2}, EMPTY}, + {"xchg4.nta", M, OpMXX6aHint (4, 0, 1, 0x0a, 3), {R1, MR3, R2}, EMPTY}, + {"xchg8", M, OpMXX6aHint (4, 0, 1, 0x0b, 0), {R1, MR3, R2}, EMPTY}, + {"xchg8.nt1", M, OpMXX6aHint (4, 0, 1, 0x0b, 1), {R1, MR3, R2}, EMPTY}, + {"xchg8.nta", M, OpMXX6aHint (4, 0, 1, 0x0b, 3), {R1, MR3, R2}, EMPTY}, - {"fetchadd4.acq", M, OpMXX6aHint (4, 0, 1, 0x12, 0), {R1, MR3, INC3}}, - {"fetchadd4.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x12, 1), {R1, MR3, INC3}}, - {"fetchadd4.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x12, 3), {R1, MR3, INC3}}, - {"fetchadd8.acq", M, OpMXX6aHint (4, 0, 1, 0x13, 0), {R1, MR3, INC3}}, - {"fetchadd8.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x13, 1), {R1, MR3, INC3}}, - {"fetchadd8.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x13, 3), {R1, MR3, INC3}}, - {"fetchadd4.rel", M, OpMXX6aHint (4, 0, 1, 0x16, 0), {R1, MR3, INC3}}, - {"fetchadd4.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x16, 1), {R1, MR3, INC3}}, - {"fetchadd4.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x16, 3), {R1, MR3, INC3}}, - {"fetchadd8.rel", M, OpMXX6aHint (4, 0, 1, 0x17, 0), {R1, MR3, INC3}}, - {"fetchadd8.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x17, 1), {R1, MR3, INC3}}, - {"fetchadd8.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x17, 3), {R1, MR3, INC3}}, + {"fetchadd4.acq", M, OpMXX6aHint (4, 0, 1, 0x12, 0), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x12, 1), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x12, 3), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.acq", M, OpMXX6aHint (4, 0, 1, 0x13, 0), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.acq.nt1", M, OpMXX6aHint (4, 0, 1, 0x13, 1), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.acq.nta", M, OpMXX6aHint (4, 0, 1, 0x13, 3), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.rel", M, OpMXX6aHint (4, 0, 1, 0x16, 0), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x16, 1), {R1, MR3, INC3}, EMPTY}, + {"fetchadd4.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x16, 3), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.rel", M, OpMXX6aHint (4, 0, 1, 0x17, 0), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.rel.nt1", M, OpMXX6aHint (4, 0, 1, 0x17, 1), {R1, MR3, INC3}, EMPTY}, + {"fetchadd8.rel.nta", M, OpMXX6aHint (4, 0, 1, 0x17, 3), {R1, MR3, INC3}, EMPTY}, - {"getf.sig", M, OpMXX6a (4, 0, 1, 0x1c), {R1, F2}}, - {"getf.exp", M, OpMXX6a (4, 0, 1, 0x1d), {R1, F2}}, - {"getf.s", M, OpMXX6a (4, 0, 1, 0x1e), {R1, F2}}, - {"getf.d", M, OpMXX6a (4, 0, 1, 0x1f), {R1, F2}}, + {"getf.sig", M, OpMXX6a (4, 0, 1, 0x1c), {R1, F2}, EMPTY}, + {"getf.exp", M, OpMXX6a (4, 0, 1, 0x1d), {R1, F2}, EMPTY}, + {"getf.s", M, OpMXX6a (4, 0, 1, 0x1e), {R1, F2}, EMPTY}, + {"getf.d", M, OpMXX6a (4, 0, 1, 0x1f), {R1, F2}, EMPTY}, - /* integer load w/increment by immediate */ -#define LDINCIMMED(c,h) M, OpX6aHint (5, c, h), {R1, MR3, IMM9b}, POSTINC + /* Integer load w/increment by immediate. */ +#define LDINCIMMED(c,h) M, OpX6aHint (5, c, h), {R1, MR3, IMM9b}, POSTINC, 0, NULL {"ld1", LDINCIMMED (0x00, 0)}, {"ld1.nt1", LDINCIMMED (0x00, 1)}, {"ld1.nta", LDINCIMMED (0x00, 3)}, @@ -567,8 +603,8 @@ struct ia64_opcode ia64_opcodes_m[] = {"ld8.c.clr.acq.nta", LDINCIMMED (0x2b, 3)}, #undef LDINCIMMED - /* store w/increment by immediate */ -#define STINCIMMED(c,h) M, OpX6aHint (5, c, h), {MR3, R2, IMM9a}, POSTINC + /* Store w/increment by immediate. */ +#define STINCIMMED(c,h) M, OpX6aHint (5, c, h), {MR3, R2, IMM9a}, POSTINC, 0, NULL {"st1", STINCIMMED (0x30, 0)}, {"st1.nta", STINCIMMED (0x30, 3)}, {"st2", STINCIMMED (0x31, 0)}, @@ -589,85 +625,85 @@ struct ia64_opcode ia64_opcodes_m[] = {"st8.spill.nta", STINCIMMED (0x3b, 3)}, #undef STINCIMMED - /* floating-point load */ - {"ldfs", M, OpMXX6aHint (6, 0, 0, 0x02, 0), {F1, MR3}}, - {"ldfs.nt1", M, OpMXX6aHint (6, 0, 0, 0x02, 1), {F1, MR3}}, - {"ldfs.nta", M, OpMXX6aHint (6, 0, 0, 0x02, 3), {F1, MR3}}, - {"ldfd", M, OpMXX6aHint (6, 0, 0, 0x03, 0), {F1, MR3}}, - {"ldfd.nt1", M, OpMXX6aHint (6, 0, 0, 0x03, 1), {F1, MR3}}, - {"ldfd.nta", M, OpMXX6aHint (6, 0, 0, 0x03, 3), {F1, MR3}}, - {"ldf8", M, OpMXX6aHint (6, 0, 0, 0x01, 0), {F1, MR3}}, - {"ldf8.nt1", M, OpMXX6aHint (6, 0, 0, 0x01, 1), {F1, MR3}}, - {"ldf8.nta", M, OpMXX6aHint (6, 0, 0, 0x01, 3), {F1, MR3}}, - {"ldfe", M, OpMXX6aHint (6, 0, 0, 0x00, 0), {F1, MR3}}, - {"ldfe.nt1", M, OpMXX6aHint (6, 0, 0, 0x00, 1), {F1, MR3}}, - {"ldfe.nta", M, OpMXX6aHint (6, 0, 0, 0x00, 3), {F1, MR3}}, - {"ldfs.s", M, OpMXX6aHint (6, 0, 0, 0x06, 0), {F1, MR3}}, - {"ldfs.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x06, 1), {F1, MR3}}, - {"ldfs.s.nta", M, OpMXX6aHint (6, 0, 0, 0x06, 3), {F1, MR3}}, - {"ldfd.s", M, OpMXX6aHint (6, 0, 0, 0x07, 0), {F1, MR3}}, - {"ldfd.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x07, 1), {F1, MR3}}, - {"ldfd.s.nta", M, OpMXX6aHint (6, 0, 0, 0x07, 3), {F1, MR3}}, - {"ldf8.s", M, OpMXX6aHint (6, 0, 0, 0x05, 0), {F1, MR3}}, - {"ldf8.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x05, 1), {F1, MR3}}, - {"ldf8.s.nta", M, OpMXX6aHint (6, 0, 0, 0x05, 3), {F1, MR3}}, - {"ldfe.s", M, OpMXX6aHint (6, 0, 0, 0x04, 0), {F1, MR3}}, - {"ldfe.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x04, 1), {F1, MR3}}, - {"ldfe.s.nta", M, OpMXX6aHint (6, 0, 0, 0x04, 3), {F1, MR3}}, - {"ldfs.a", M, OpMXX6aHint (6, 0, 0, 0x0a, 0), {F1, MR3}}, - {"ldfs.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0a, 1), {F1, MR3}}, - {"ldfs.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0a, 3), {F1, MR3}}, - {"ldfd.a", M, OpMXX6aHint (6, 0, 0, 0x0b, 0), {F1, MR3}}, - {"ldfd.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0b, 1), {F1, MR3}}, - {"ldfd.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0b, 3), {F1, MR3}}, - {"ldf8.a", M, OpMXX6aHint (6, 0, 0, 0x09, 0), {F1, MR3}}, - {"ldf8.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x09, 1), {F1, MR3}}, - {"ldf8.a.nta", M, OpMXX6aHint (6, 0, 0, 0x09, 3), {F1, MR3}}, - {"ldfe.a", M, OpMXX6aHint (6, 0, 0, 0x08, 0), {F1, MR3}}, - {"ldfe.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x08, 1), {F1, MR3}}, - {"ldfe.a.nta", M, OpMXX6aHint (6, 0, 0, 0x08, 3), {F1, MR3}}, - {"ldfs.sa", M, OpMXX6aHint (6, 0, 0, 0x0e, 0), {F1, MR3}}, - {"ldfs.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0e, 1), {F1, MR3}}, - {"ldfs.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0e, 3), {F1, MR3}}, - {"ldfd.sa", M, OpMXX6aHint (6, 0, 0, 0x0f, 0), {F1, MR3}}, - {"ldfd.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0f, 1), {F1, MR3}}, - {"ldfd.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0f, 3), {F1, MR3}}, - {"ldf8.sa", M, OpMXX6aHint (6, 0, 0, 0x0d, 0), {F1, MR3}}, - {"ldf8.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0d, 1), {F1, MR3}}, - {"ldf8.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0d, 3), {F1, MR3}}, - {"ldfe.sa", M, OpMXX6aHint (6, 0, 0, 0x0c, 0), {F1, MR3}}, - {"ldfe.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0c, 1), {F1, MR3}}, - {"ldfe.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0c, 3), {F1, MR3}}, - {"ldf.fill", M, OpMXX6aHint (6, 0, 0, 0x1b, 0), {F1, MR3}}, - {"ldf.fill.nt1", M, OpMXX6aHint (6, 0, 0, 0x1b, 1), {F1, MR3}}, - {"ldf.fill.nta", M, OpMXX6aHint (6, 0, 0, 0x1b, 3), {F1, MR3}}, - {"ldfs.c.clr", M, OpMXX6aHint (6, 0, 0, 0x22, 0), {F1, MR3}}, - {"ldfs.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x22, 1), {F1, MR3}}, - {"ldfs.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x22, 3), {F1, MR3}}, - {"ldfd.c.clr", M, OpMXX6aHint (6, 0, 0, 0x23, 0), {F1, MR3}}, - {"ldfd.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x23, 1), {F1, MR3}}, - {"ldfd.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x23, 3), {F1, MR3}}, - {"ldf8.c.clr", M, OpMXX6aHint (6, 0, 0, 0x21, 0), {F1, MR3}}, - {"ldf8.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x21, 1), {F1, MR3}}, - {"ldf8.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x21, 3), {F1, MR3}}, - {"ldfe.c.clr", M, OpMXX6aHint (6, 0, 0, 0x20, 0), {F1, MR3}}, - {"ldfe.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x20, 1), {F1, MR3}}, - {"ldfe.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x20, 3), {F1, MR3}}, - {"ldfs.c.nc", M, OpMXX6aHint (6, 0, 0, 0x26, 0), {F1, MR3}}, - {"ldfs.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x26, 1), {F1, MR3}}, - {"ldfs.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x26, 3), {F1, MR3}}, - {"ldfd.c.nc", M, OpMXX6aHint (6, 0, 0, 0x27, 0), {F1, MR3}}, - {"ldfd.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x27, 1), {F1, MR3}}, - {"ldfd.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x27, 3), {F1, MR3}}, - {"ldf8.c.nc", M, OpMXX6aHint (6, 0, 0, 0x25, 0), {F1, MR3}}, - {"ldf8.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x25, 1), {F1, MR3}}, - {"ldf8.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x25, 3), {F1, MR3}}, - {"ldfe.c.nc", M, OpMXX6aHint (6, 0, 0, 0x24, 0), {F1, MR3}}, - {"ldfe.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x24, 1), {F1, MR3}}, - {"ldfe.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x24, 3), {F1, MR3}}, + /* Floating-point load. */ + {"ldfs", M, OpMXX6aHint (6, 0, 0, 0x02, 0), {F1, MR3}, EMPTY}, + {"ldfs.nt1", M, OpMXX6aHint (6, 0, 0, 0x02, 1), {F1, MR3}, EMPTY}, + {"ldfs.nta", M, OpMXX6aHint (6, 0, 0, 0x02, 3), {F1, MR3}, EMPTY}, + {"ldfd", M, OpMXX6aHint (6, 0, 0, 0x03, 0), {F1, MR3}, EMPTY}, + {"ldfd.nt1", M, OpMXX6aHint (6, 0, 0, 0x03, 1), {F1, MR3}, EMPTY}, + {"ldfd.nta", M, OpMXX6aHint (6, 0, 0, 0x03, 3), {F1, MR3}, EMPTY}, + {"ldf8", M, OpMXX6aHint (6, 0, 0, 0x01, 0), {F1, MR3}, EMPTY}, + {"ldf8.nt1", M, OpMXX6aHint (6, 0, 0, 0x01, 1), {F1, MR3}, EMPTY}, + {"ldf8.nta", M, OpMXX6aHint (6, 0, 0, 0x01, 3), {F1, MR3}, EMPTY}, + {"ldfe", M, OpMXX6aHint (6, 0, 0, 0x00, 0), {F1, MR3}, EMPTY}, + {"ldfe.nt1", M, OpMXX6aHint (6, 0, 0, 0x00, 1), {F1, MR3}, EMPTY}, + {"ldfe.nta", M, OpMXX6aHint (6, 0, 0, 0x00, 3), {F1, MR3}, EMPTY}, + {"ldfs.s", M, OpMXX6aHint (6, 0, 0, 0x06, 0), {F1, MR3}, EMPTY}, + {"ldfs.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x06, 1), {F1, MR3}, EMPTY}, + {"ldfs.s.nta", M, OpMXX6aHint (6, 0, 0, 0x06, 3), {F1, MR3}, EMPTY}, + {"ldfd.s", M, OpMXX6aHint (6, 0, 0, 0x07, 0), {F1, MR3}, EMPTY}, + {"ldfd.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x07, 1), {F1, MR3}, EMPTY}, + {"ldfd.s.nta", M, OpMXX6aHint (6, 0, 0, 0x07, 3), {F1, MR3}, EMPTY}, + {"ldf8.s", M, OpMXX6aHint (6, 0, 0, 0x05, 0), {F1, MR3}, EMPTY}, + {"ldf8.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x05, 1), {F1, MR3}, EMPTY}, + {"ldf8.s.nta", M, OpMXX6aHint (6, 0, 0, 0x05, 3), {F1, MR3}, EMPTY}, + {"ldfe.s", M, OpMXX6aHint (6, 0, 0, 0x04, 0), {F1, MR3}, EMPTY}, + {"ldfe.s.nt1", M, OpMXX6aHint (6, 0, 0, 0x04, 1), {F1, MR3}, EMPTY}, + {"ldfe.s.nta", M, OpMXX6aHint (6, 0, 0, 0x04, 3), {F1, MR3}, EMPTY}, + {"ldfs.a", M, OpMXX6aHint (6, 0, 0, 0x0a, 0), {F1, MR3}, EMPTY}, + {"ldfs.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0a, 1), {F1, MR3}, EMPTY}, + {"ldfs.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0a, 3), {F1, MR3}, EMPTY}, + {"ldfd.a", M, OpMXX6aHint (6, 0, 0, 0x0b, 0), {F1, MR3}, EMPTY}, + {"ldfd.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x0b, 1), {F1, MR3}, EMPTY}, + {"ldfd.a.nta", M, OpMXX6aHint (6, 0, 0, 0x0b, 3), {F1, MR3}, EMPTY}, + {"ldf8.a", M, OpMXX6aHint (6, 0, 0, 0x09, 0), {F1, MR3}, EMPTY}, + {"ldf8.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x09, 1), {F1, MR3}, EMPTY}, + {"ldf8.a.nta", M, OpMXX6aHint (6, 0, 0, 0x09, 3), {F1, MR3}, EMPTY}, + {"ldfe.a", M, OpMXX6aHint (6, 0, 0, 0x08, 0), {F1, MR3}, EMPTY}, + {"ldfe.a.nt1", M, OpMXX6aHint (6, 0, 0, 0x08, 1), {F1, MR3}, EMPTY}, + {"ldfe.a.nta", M, OpMXX6aHint (6, 0, 0, 0x08, 3), {F1, MR3}, EMPTY}, + {"ldfs.sa", M, OpMXX6aHint (6, 0, 0, 0x0e, 0), {F1, MR3}, EMPTY}, + {"ldfs.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0e, 1), {F1, MR3}, EMPTY}, + {"ldfs.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0e, 3), {F1, MR3}, EMPTY}, + {"ldfd.sa", M, OpMXX6aHint (6, 0, 0, 0x0f, 0), {F1, MR3}, EMPTY}, + {"ldfd.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0f, 1), {F1, MR3}, EMPTY}, + {"ldfd.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0f, 3), {F1, MR3}, EMPTY}, + {"ldf8.sa", M, OpMXX6aHint (6, 0, 0, 0x0d, 0), {F1, MR3}, EMPTY}, + {"ldf8.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0d, 1), {F1, MR3}, EMPTY}, + {"ldf8.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0d, 3), {F1, MR3}, EMPTY}, + {"ldfe.sa", M, OpMXX6aHint (6, 0, 0, 0x0c, 0), {F1, MR3}, EMPTY}, + {"ldfe.sa.nt1", M, OpMXX6aHint (6, 0, 0, 0x0c, 1), {F1, MR3}, EMPTY}, + {"ldfe.sa.nta", M, OpMXX6aHint (6, 0, 0, 0x0c, 3), {F1, MR3}, EMPTY}, + {"ldf.fill", M, OpMXX6aHint (6, 0, 0, 0x1b, 0), {F1, MR3}, EMPTY}, + {"ldf.fill.nt1", M, OpMXX6aHint (6, 0, 0, 0x1b, 1), {F1, MR3}, EMPTY}, + {"ldf.fill.nta", M, OpMXX6aHint (6, 0, 0, 0x1b, 3), {F1, MR3}, EMPTY}, + {"ldfs.c.clr", M, OpMXX6aHint (6, 0, 0, 0x22, 0), {F1, MR3}, EMPTY}, + {"ldfs.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x22, 1), {F1, MR3}, EMPTY}, + {"ldfs.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x22, 3), {F1, MR3}, EMPTY}, + {"ldfd.c.clr", M, OpMXX6aHint (6, 0, 0, 0x23, 0), {F1, MR3}, EMPTY}, + {"ldfd.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x23, 1), {F1, MR3}, EMPTY}, + {"ldfd.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x23, 3), {F1, MR3}, EMPTY}, + {"ldf8.c.clr", M, OpMXX6aHint (6, 0, 0, 0x21, 0), {F1, MR3}, EMPTY}, + {"ldf8.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x21, 1), {F1, MR3}, EMPTY}, + {"ldf8.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x21, 3), {F1, MR3}, EMPTY}, + {"ldfe.c.clr", M, OpMXX6aHint (6, 0, 0, 0x20, 0), {F1, MR3}, EMPTY}, + {"ldfe.c.clr.nt1", M, OpMXX6aHint (6, 0, 0, 0x20, 1), {F1, MR3}, EMPTY}, + {"ldfe.c.clr.nta", M, OpMXX6aHint (6, 0, 0, 0x20, 3), {F1, MR3}, EMPTY}, + {"ldfs.c.nc", M, OpMXX6aHint (6, 0, 0, 0x26, 0), {F1, MR3}, EMPTY}, + {"ldfs.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x26, 1), {F1, MR3}, EMPTY}, + {"ldfs.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x26, 3), {F1, MR3}, EMPTY}, + {"ldfd.c.nc", M, OpMXX6aHint (6, 0, 0, 0x27, 0), {F1, MR3}, EMPTY}, + {"ldfd.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x27, 1), {F1, MR3}, EMPTY}, + {"ldfd.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x27, 3), {F1, MR3}, EMPTY}, + {"ldf8.c.nc", M, OpMXX6aHint (6, 0, 0, 0x25, 0), {F1, MR3}, EMPTY}, + {"ldf8.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x25, 1), {F1, MR3}, EMPTY}, + {"ldf8.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x25, 3), {F1, MR3}, EMPTY}, + {"ldfe.c.nc", M, OpMXX6aHint (6, 0, 0, 0x24, 0), {F1, MR3}, EMPTY}, + {"ldfe.c.nc.nt1", M, OpMXX6aHint (6, 0, 0, 0x24, 1), {F1, MR3}, EMPTY}, + {"ldfe.c.nc.nta", M, OpMXX6aHint (6, 0, 0, 0x24, 3), {F1, MR3}, EMPTY}, - /* floating-point load w/increment by register */ -#define FLDINCREG(c,h) M, OpMXX6aHint (6, 1, 0, c, h), {F1, MR3, R2}, POSTINC + /* Floating-point load w/increment by register. */ +#define FLDINCREG(c,h) M, OpMXX6aHint (6, 1, 0, c, h), {F1, MR3, R2}, POSTINC, 0, NULL {"ldfs", FLDINCREG (0x02, 0)}, {"ldfs.nt1", FLDINCREG (0x02, 1)}, {"ldfs.nta", FLDINCREG (0x02, 3)}, @@ -745,76 +781,76 @@ struct ia64_opcode ia64_opcodes_m[] = {"ldfe.c.nc.nta", FLDINCREG (0x24, 3)}, #undef FLDINCREG - /* floating-point store */ - {"stfs", M, OpMXX6aHint (6, 0, 0, 0x32, 0), {MR3, F2}}, - {"stfs.nta", M, OpMXX6aHint (6, 0, 0, 0x32, 3), {MR3, F2}}, - {"stfd", M, OpMXX6aHint (6, 0, 0, 0x33, 0), {MR3, F2}}, - {"stfd.nta", M, OpMXX6aHint (6, 0, 0, 0x33, 3), {MR3, F2}}, - {"stf8", M, OpMXX6aHint (6, 0, 0, 0x31, 0), {MR3, F2}}, - {"stf8.nta", M, OpMXX6aHint (6, 0, 0, 0x31, 3), {MR3, F2}}, - {"stfe", M, OpMXX6aHint (6, 0, 0, 0x30, 0), {MR3, F2}}, - {"stfe.nta", M, OpMXX6aHint (6, 0, 0, 0x30, 3), {MR3, F2}}, - {"stf.spill", M, OpMXX6aHint (6, 0, 0, 0x3b, 0), {MR3, F2}}, - {"stf.spill.nta", M, OpMXX6aHint (6, 0, 0, 0x3b, 3), {MR3, F2}}, + /* Floating-point store. */ + {"stfs", M, OpMXX6aHint (6, 0, 0, 0x32, 0), {MR3, F2}, EMPTY}, + {"stfs.nta", M, OpMXX6aHint (6, 0, 0, 0x32, 3), {MR3, F2}, EMPTY}, + {"stfd", M, OpMXX6aHint (6, 0, 0, 0x33, 0), {MR3, F2}, EMPTY}, + {"stfd.nta", M, OpMXX6aHint (6, 0, 0, 0x33, 3), {MR3, F2}, EMPTY}, + {"stf8", M, OpMXX6aHint (6, 0, 0, 0x31, 0), {MR3, F2}, EMPTY}, + {"stf8.nta", M, OpMXX6aHint (6, 0, 0, 0x31, 3), {MR3, F2}, EMPTY}, + {"stfe", M, OpMXX6aHint (6, 0, 0, 0x30, 0), {MR3, F2}, EMPTY}, + {"stfe.nta", M, OpMXX6aHint (6, 0, 0, 0x30, 3), {MR3, F2}, EMPTY}, + {"stf.spill", M, OpMXX6aHint (6, 0, 0, 0x3b, 0), {MR3, F2}, EMPTY}, + {"stf.spill.nta", M, OpMXX6aHint (6, 0, 0, 0x3b, 3), {MR3, F2}, EMPTY}, - /* floating-point load pair */ - {"ldfps", M2, OpMXX6aHint (6, 0, 1, 0x02, 0), {F1, F2, MR3}}, - {"ldfps.nt1", M2, OpMXX6aHint (6, 0, 1, 0x02, 1), {F1, F2, MR3}}, - {"ldfps.nta", M2, OpMXX6aHint (6, 0, 1, 0x02, 3), {F1, F2, MR3}}, - {"ldfpd", M2, OpMXX6aHint (6, 0, 1, 0x03, 0), {F1, F2, MR3}}, - {"ldfpd.nt1", M2, OpMXX6aHint (6, 0, 1, 0x03, 1), {F1, F2, MR3}}, - {"ldfpd.nta", M2, OpMXX6aHint (6, 0, 1, 0x03, 3), {F1, F2, MR3}}, - {"ldfp8", M2, OpMXX6aHint (6, 0, 1, 0x01, 0), {F1, F2, MR3}}, - {"ldfp8.nt1", M2, OpMXX6aHint (6, 0, 1, 0x01, 1), {F1, F2, MR3}}, - {"ldfp8.nta", M2, OpMXX6aHint (6, 0, 1, 0x01, 3), {F1, F2, MR3}}, - {"ldfps.s", M2, OpMXX6aHint (6, 0, 1, 0x06, 0), {F1, F2, MR3}}, - {"ldfps.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x06, 1), {F1, F2, MR3}}, - {"ldfps.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x06, 3), {F1, F2, MR3}}, - {"ldfpd.s", M2, OpMXX6aHint (6, 0, 1, 0x07, 0), {F1, F2, MR3}}, - {"ldfpd.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x07, 1), {F1, F2, MR3}}, - {"ldfpd.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x07, 3), {F1, F2, MR3}}, - {"ldfp8.s", M2, OpMXX6aHint (6, 0, 1, 0x05, 0), {F1, F2, MR3}}, - {"ldfp8.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x05, 1), {F1, F2, MR3}}, - {"ldfp8.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x05, 3), {F1, F2, MR3}}, - {"ldfps.a", M2, OpMXX6aHint (6, 0, 1, 0x0a, 0), {F1, F2, MR3}}, - {"ldfps.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0a, 1), {F1, F2, MR3}}, - {"ldfps.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0a, 3), {F1, F2, MR3}}, - {"ldfpd.a", M2, OpMXX6aHint (6, 0, 1, 0x0b, 0), {F1, F2, MR3}}, - {"ldfpd.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0b, 1), {F1, F2, MR3}}, - {"ldfpd.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0b, 3), {F1, F2, MR3}}, - {"ldfp8.a", M2, OpMXX6aHint (6, 0, 1, 0x09, 0), {F1, F2, MR3}}, - {"ldfp8.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x09, 1), {F1, F2, MR3}}, - {"ldfp8.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x09, 3), {F1, F2, MR3}}, - {"ldfps.sa", M2, OpMXX6aHint (6, 0, 1, 0x0e, 0), {F1, F2, MR3}}, - {"ldfps.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0e, 1), {F1, F2, MR3}}, - {"ldfps.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0e, 3), {F1, F2, MR3}}, - {"ldfpd.sa", M2, OpMXX6aHint (6, 0, 1, 0x0f, 0), {F1, F2, MR3}}, - {"ldfpd.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0f, 1), {F1, F2, MR3}}, - {"ldfpd.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0f, 3), {F1, F2, MR3}}, - {"ldfp8.sa", M2, OpMXX6aHint (6, 0, 1, 0x0d, 0), {F1, F2, MR3}}, - {"ldfp8.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0d, 1), {F1, F2, MR3}}, - {"ldfp8.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0d, 3), {F1, F2, MR3}}, - {"ldfps.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x22, 0), {F1, F2, MR3}}, - {"ldfps.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x22, 1), {F1, F2, MR3}}, - {"ldfps.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x22, 3), {F1, F2, MR3}}, - {"ldfpd.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x23, 0), {F1, F2, MR3}}, - {"ldfpd.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x23, 1), {F1, F2, MR3}}, - {"ldfpd.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x23, 3), {F1, F2, MR3}}, - {"ldfp8.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x21, 0), {F1, F2, MR3}}, - {"ldfp8.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x21, 1), {F1, F2, MR3}}, - {"ldfp8.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x21, 3), {F1, F2, MR3}}, - {"ldfps.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x26, 0), {F1, F2, MR3}}, - {"ldfps.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x26, 1), {F1, F2, MR3}}, - {"ldfps.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x26, 3), {F1, F2, MR3}}, - {"ldfpd.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x27, 0), {F1, F2, MR3}}, - {"ldfpd.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x27, 1), {F1, F2, MR3}}, - {"ldfpd.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x27, 3), {F1, F2, MR3}}, - {"ldfp8.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x25, 0), {F1, F2, MR3}}, - {"ldfp8.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x25, 1), {F1, F2, MR3}}, - {"ldfp8.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x25, 3), {F1, F2, MR3}}, + /* Floating-point load pair. */ + {"ldfps", M2, OpMXX6aHint (6, 0, 1, 0x02, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.nt1", M2, OpMXX6aHint (6, 0, 1, 0x02, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.nta", M2, OpMXX6aHint (6, 0, 1, 0x02, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd", M2, OpMXX6aHint (6, 0, 1, 0x03, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.nt1", M2, OpMXX6aHint (6, 0, 1, 0x03, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.nta", M2, OpMXX6aHint (6, 0, 1, 0x03, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8", M2, OpMXX6aHint (6, 0, 1, 0x01, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.nt1", M2, OpMXX6aHint (6, 0, 1, 0x01, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.nta", M2, OpMXX6aHint (6, 0, 1, 0x01, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.s", M2, OpMXX6aHint (6, 0, 1, 0x06, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x06, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x06, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.s", M2, OpMXX6aHint (6, 0, 1, 0x07, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x07, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x07, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.s", M2, OpMXX6aHint (6, 0, 1, 0x05, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.s.nt1", M2, OpMXX6aHint (6, 0, 1, 0x05, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.s.nta", M2, OpMXX6aHint (6, 0, 1, 0x05, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.a", M2, OpMXX6aHint (6, 0, 1, 0x0a, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0a, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0a, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.a", M2, OpMXX6aHint (6, 0, 1, 0x0b, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0b, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x0b, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.a", M2, OpMXX6aHint (6, 0, 1, 0x09, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.a.nt1", M2, OpMXX6aHint (6, 0, 1, 0x09, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.a.nta", M2, OpMXX6aHint (6, 0, 1, 0x09, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.sa", M2, OpMXX6aHint (6, 0, 1, 0x0e, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0e, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0e, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.sa", M2, OpMXX6aHint (6, 0, 1, 0x0f, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0f, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0f, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.sa", M2, OpMXX6aHint (6, 0, 1, 0x0d, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.sa.nt1", M2, OpMXX6aHint (6, 0, 1, 0x0d, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.sa.nta", M2, OpMXX6aHint (6, 0, 1, 0x0d, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x22, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x22, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x22, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x23, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x23, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x23, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.clr", M2, OpMXX6aHint (6, 0, 1, 0x21, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.clr.nt1", M2, OpMXX6aHint (6, 0, 1, 0x21, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.clr.nta", M2, OpMXX6aHint (6, 0, 1, 0x21, 3), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x26, 0), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x26, 1), {F1, F2, MR3}, EMPTY}, + {"ldfps.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x26, 3), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x27, 0), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x27, 1), {F1, F2, MR3}, EMPTY}, + {"ldfpd.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x27, 3), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.nc", M2, OpMXX6aHint (6, 0, 1, 0x25, 0), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.nc.nt1", M2, OpMXX6aHint (6, 0, 1, 0x25, 1), {F1, F2, MR3}, EMPTY}, + {"ldfp8.c.nc.nta", M2, OpMXX6aHint (6, 0, 1, 0x25, 3), {F1, F2, MR3}, EMPTY}, - /* floating-point load pair w/increment by immediate */ -#define LD(a,b,c) M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}, POSTINC + /* Floating-point load pair w/increment by immediate. */ +#define LD(a,b,c) M2, OpMXX6aHint (6, 1, 1, a, b), {F1, F2, MR3, c}, POSTINC, 0, NULL {"ldfps", LD (0x02, 0, C8)}, {"ldfps.nt1", LD (0x02, 1, C8)}, {"ldfps.nta", LD (0x02, 3, C8)}, @@ -871,26 +907,26 @@ struct ia64_opcode ia64_opcodes_m[] = {"ldfp8.c.nc.nta", LD (0x25, 3, C16)}, #undef LD - /* line prefetch */ - {"lfetch", M0, OpMXX6aHint (6, 0, 0, 0x2c, 0), {MR3}}, - {"lfetch.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2c, 1), {MR3}}, - {"lfetch.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2c, 2), {MR3}}, - {"lfetch.nta", M0, OpMXX6aHint (6, 0, 0, 0x2c, 3), {MR3}}, - {"lfetch.excl", M0, OpMXX6aHint (6, 0, 0, 0x2d, 0), {MR3}}, - {"lfetch.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2d, 1), {MR3}}, - {"lfetch.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2d, 2), {MR3}}, - {"lfetch.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2d, 3), {MR3}}, - {"lfetch.fault", M0, OpMXX6aHint (6, 0, 0, 0x2e, 0), {MR3}}, - {"lfetch.fault.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2e, 1), {MR3}}, - {"lfetch.fault.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2e, 2), {MR3}}, - {"lfetch.fault.nta", M0, OpMXX6aHint (6, 0, 0, 0x2e, 3), {MR3}}, - {"lfetch.fault.excl", M0, OpMXX6aHint (6, 0, 0, 0x2f, 0), {MR3}}, - {"lfetch.fault.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2f, 1), {MR3}}, - {"lfetch.fault.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2f, 2), {MR3}}, - {"lfetch.fault.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2f, 3), {MR3}}, + /* Line prefetch. */ + {"lfetch", M0, OpMXX6aHint (6, 0, 0, 0x2c, 0), {MR3}, EMPTY}, + {"lfetch.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2c, 1), {MR3}, EMPTY}, + {"lfetch.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2c, 2), {MR3}, EMPTY}, + {"lfetch.nta", M0, OpMXX6aHint (6, 0, 0, 0x2c, 3), {MR3}, EMPTY}, + {"lfetch.excl", M0, OpMXX6aHint (6, 0, 0, 0x2d, 0), {MR3}, EMPTY}, + {"lfetch.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2d, 1), {MR3}, EMPTY}, + {"lfetch.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2d, 2), {MR3}, EMPTY}, + {"lfetch.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2d, 3), {MR3}, EMPTY}, + {"lfetch.fault", M0, OpMXX6aHint (6, 0, 0, 0x2e, 0), {MR3}, EMPTY}, + {"lfetch.fault.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2e, 1), {MR3}, EMPTY}, + {"lfetch.fault.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2e, 2), {MR3}, EMPTY}, + {"lfetch.fault.nta", M0, OpMXX6aHint (6, 0, 0, 0x2e, 3), {MR3}, EMPTY}, + {"lfetch.fault.excl", M0, OpMXX6aHint (6, 0, 0, 0x2f, 0), {MR3}, EMPTY}, + {"lfetch.fault.excl.nt1", M0, OpMXX6aHint (6, 0, 0, 0x2f, 1), {MR3}, EMPTY}, + {"lfetch.fault.excl.nt2", M0, OpMXX6aHint (6, 0, 0, 0x2f, 2), {MR3}, EMPTY}, + {"lfetch.fault.excl.nta", M0, OpMXX6aHint (6, 0, 0, 0x2f, 3), {MR3}, EMPTY}, - /* line prefetch w/increment by register */ -#define LFETCHINCREG(c,h) M0, OpMXX6aHint (6, 1, 0, c, h), {MR3, R2}, POSTINC + /* Line prefetch w/increment by register. */ +#define LFETCHINCREG(c,h) M0, OpMXX6aHint (6, 1, 0, c, h), {MR3, R2}, POSTINC, 0, NULL {"lfetch", LFETCHINCREG (0x2c, 0)}, {"lfetch.nt1", LFETCHINCREG (0x2c, 1)}, {"lfetch.nt2", LFETCHINCREG (0x2c, 2)}, @@ -909,14 +945,14 @@ struct ia64_opcode ia64_opcodes_m[] = {"lfetch.fault.excl.nta", LFETCHINCREG (0x2f, 3)}, #undef LFETCHINCREG - /* semaphore operations */ - {"setf.sig", M, OpMXX6a (6, 0, 1, 0x1c), {F1, R2}}, - {"setf.exp", M, OpMXX6a (6, 0, 1, 0x1d), {F1, R2}}, - {"setf.s", M, OpMXX6a (6, 0, 1, 0x1e), {F1, R2}}, - {"setf.d", M, OpMXX6a (6, 0, 1, 0x1f), {F1, R2}}, + /* Semaphore operations. */ + {"setf.sig", M, OpMXX6a (6, 0, 1, 0x1c), {F1, R2}, EMPTY}, + {"setf.exp", M, OpMXX6a (6, 0, 1, 0x1d), {F1, R2}, EMPTY}, + {"setf.s", M, OpMXX6a (6, 0, 1, 0x1e), {F1, R2}, EMPTY}, + {"setf.d", M, OpMXX6a (6, 0, 1, 0x1f), {F1, R2}, EMPTY}, - /* floating-point load w/increment by immediate */ -#define FLDINCIMMED(c,h) M, OpX6aHint (7, c, h), {F1, MR3, IMM9b}, POSTINC + /* Floating-point load w/increment by immediate. */ +#define FLDINCIMMED(c,h) M, OpX6aHint (7, c, h), {F1, MR3, IMM9b}, POSTINC, 0, NULL {"ldfs", FLDINCIMMED (0x02, 0)}, {"ldfs.nt1", FLDINCIMMED (0x02, 1)}, {"ldfs.nta", FLDINCIMMED (0x02, 3)}, @@ -994,8 +1030,8 @@ struct ia64_opcode ia64_opcodes_m[] = {"ldfe.c.nc.nta", FLDINCIMMED (0x24, 3)}, #undef FLDINCIMMED - /* floating-point store w/increment by immediate */ -#define FSTINCIMMED(c,h) M, OpX6aHint (7, c, h), {MR3, F2, IMM9a}, POSTINC + /* Floating-point store w/increment by immediate. */ +#define FSTINCIMMED(c,h) M, OpX6aHint (7, c, h), {MR3, F2, IMM9a}, POSTINC, 0, NULL {"stfs", FSTINCIMMED (0x32, 0)}, {"stfs.nta", FSTINCIMMED (0x32, 3)}, {"stfd", FSTINCIMMED (0x33, 0)}, @@ -1008,8 +1044,8 @@ struct ia64_opcode ia64_opcodes_m[] = {"stf.spill.nta", FSTINCIMMED (0x3b, 3)}, #undef FSTINCIMMED - /* line prefetch w/increment by immediate */ -#define LFETCHINCIMMED(c,h) M0, OpX6aHint (7, c, h), {MR3, IMM9b}, POSTINC + /* Line prefetch w/increment by immediate. */ +#define LFETCHINCIMMED(c,h) M0, OpX6aHint (7, c, h), {MR3, IMM9b}, POSTINC, 0, NULL {"lfetch", LFETCHINCIMMED (0x2c, 0)}, {"lfetch.nt1", LFETCHINCIMMED (0x2c, 1)}, {"lfetch.nt2", LFETCHINCIMMED (0x2c, 2)}, @@ -1028,7 +1064,7 @@ struct ia64_opcode ia64_opcodes_m[] = {"lfetch.fault.excl.nta", LFETCHINCIMMED (0x2f, 3)}, #undef LFETCHINCIMMED - {0} + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} }; #undef M0 @@ -1058,3 +1094,4 @@ struct ia64_opcode ia64_opcodes_m[] = #undef OpXX6aHint #undef OpMXX6a #undef OpMXX6aHint +#undef EMPTY diff --git a/contrib/binutils/opcodes/ia64-opc-x.c b/contrib/binutils/opcodes/ia64-opc-x.c index 5f382fd..e1d4345 100644 --- a/contrib/binutils/opcodes/ia64-opc-x.c +++ b/contrib/binutils/opcodes/ia64-opc-x.c @@ -1,5 +1,5 @@ /* ia64-opc-x.c -- IA-64 `X' opcode table. - Copyright 1998, 1999, 2000 Free Software Foundation, Inc. + Copyright 1998, 1999, 2000, 2002 Free Software Foundation, Inc. Contributed by Timothy Wall <twall@cygnus.com> This file is part of GDB, GAS, and the GNU binutils. @@ -21,11 +21,11 @@ #include "ia64-opc.h" -/* identify the specific X-unit type */ +/* Identify the specific X-unit type. */ #define X0 IA64_TYPE_X, 0 #define X IA64_TYPE_X, 1 -/* instruction bit fields: */ +/* Instruction bit fields: */ #define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6) #define bD(x) (((ia64_insn) ((x) & 0x1)) << 35) #define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12) @@ -34,6 +34,7 @@ #define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33) #define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33) #define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27) +#define bY(x) (((ia64_insn) ((x) & 0x1)) << 26) #define mBtype bBtype (-1) #define mD bD (-1) @@ -43,9 +44,12 @@ #define mWha bWha (-1) #define mX3 bX3 (-1) #define mX6 bX6 (-1) +#define mY bY (-1) #define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \ (mOp | mX3 | mX6) +#define OpX3X6Y(a,b,c,d) (bOp (a) | bX3 (b) | bX6(c) | bY(d)), \ + (mOp | mX3 | mX6 | mY) #define OpVc(a,b) (bOp (a) | bVc (b)), (mOp | mVc) #define OpPaWhaD(a,b,c,d) \ (bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD) @@ -58,36 +62,39 @@ struct ia64_opcode ia64_opcodes_x[] = { - {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}}, - {"nop.x", X0, OpX3X6 (0, 0, 0x01), {IMMU62}}, - {"movl", X, OpVc (6, 0), {R1, IMMU64}}, + {"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}, 0, 0, NULL}, + {"nop.x", X0, OpX3X6Y (0, 0, 0x01, 0), {IMMU62}, 0, 0, NULL}, + {"hint.x", X0, OpX3X6Y (0, 0, 0x01, 1), {IMMU62}, 0, 0, NULL}, + {"movl", X, OpVc (6, 0), {R1, IMMU64}, 0, 0, NULL}, #define BRL(a,b) \ - X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, 0 - {"brl.few", BRL (0, 0) | PSEUDO}, - {"brl", BRL (0, 0) | PSEUDO}, - {"brl.few.clr", BRL (0, 1) | PSEUDO}, - {"brl.clr", BRL (0, 1) | PSEUDO}, - {"brl.many", BRL (1, 0) | PSEUDO}, - {"brl.many.clr", BRL (1, 1) | PSEUDO}, + X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, PSEUDO, 0, NULL + {"brl.few", BRL (0, 0)}, + {"brl", BRL (0, 0)}, + {"brl.few.clr", BRL (0, 1)}, + {"brl.clr", BRL (0, 1)}, + {"brl.many", BRL (1, 0)}, + {"brl.many.clr", BRL (1, 1)}, #undef BRL #define BRL(a,b,c) \ - X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0 + X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0, 0, NULL +#define BRLP(a,b,c) \ + X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, PSEUDO, 0, NULL {"brl.cond.sptk.few", BRL (0, 0, 0)}, - {"brl.cond.sptk", BRL (0, 0, 0) | PSEUDO}, + {"brl.cond.sptk", BRLP (0, 0, 0)}, {"brl.cond.sptk.few.clr", BRL (0, 0, 1)}, - {"brl.cond.sptk.clr", BRL (0, 0, 1) | PSEUDO}, + {"brl.cond.sptk.clr", BRLP (0, 0, 1)}, {"brl.cond.spnt.few", BRL (0, 1, 0)}, - {"brl.cond.spnt", BRL (0, 1, 0) | PSEUDO}, + {"brl.cond.spnt", BRLP (0, 1, 0)}, {"brl.cond.spnt.few.clr", BRL (0, 1, 1)}, - {"brl.cond.spnt.clr", BRL (0, 1, 1) | PSEUDO}, + {"brl.cond.spnt.clr", BRLP (0, 1, 1)}, {"brl.cond.dptk.few", BRL (0, 2, 0)}, - {"brl.cond.dptk", BRL (0, 2, 0) | PSEUDO}, + {"brl.cond.dptk", BRLP (0, 2, 0)}, {"brl.cond.dptk.few.clr", BRL (0, 2, 1)}, - {"brl.cond.dptk.clr", BRL (0, 2, 1) | PSEUDO}, + {"brl.cond.dptk.clr", BRLP (0, 2, 1)}, {"brl.cond.dpnt.few", BRL (0, 3, 0)}, - {"brl.cond.dpnt", BRL (0, 3, 0) | PSEUDO}, + {"brl.cond.dpnt", BRLP (0, 3, 0)}, {"brl.cond.dpnt.few.clr", BRL (0, 3, 1)}, - {"brl.cond.dpnt.clr", BRL (0, 3, 1) | PSEUDO}, + {"brl.cond.dpnt.clr", BRLP (0, 3, 1)}, {"brl.cond.sptk.many", BRL (1, 0, 0)}, {"brl.cond.sptk.many.clr", BRL (1, 0, 1)}, {"brl.cond.spnt.many", BRL (1, 1, 0)}, @@ -97,21 +104,21 @@ struct ia64_opcode ia64_opcodes_x[] = {"brl.cond.dpnt.many", BRL (1, 3, 0)}, {"brl.cond.dpnt.many.clr", BRL (1, 3, 1)}, {"brl.sptk.few", BRL (0, 0, 0)}, - {"brl.sptk", BRL (0, 0, 0) | PSEUDO}, + {"brl.sptk", BRLP (0, 0, 0)}, {"brl.sptk.few.clr", BRL (0, 0, 1)}, - {"brl.sptk.clr", BRL (0, 0, 1) | PSEUDO}, + {"brl.sptk.clr", BRLP (0, 0, 1)}, {"brl.spnt.few", BRL (0, 1, 0)}, - {"brl.spnt", BRL (0, 1, 0) | PSEUDO}, + {"brl.spnt", BRLP (0, 1, 0)}, {"brl.spnt.few.clr", BRL (0, 1, 1)}, - {"brl.spnt.clr", BRL (0, 1, 1) | PSEUDO}, + {"brl.spnt.clr", BRLP (0, 1, 1)}, {"brl.dptk.few", BRL (0, 2, 0)}, - {"brl.dptk", BRL (0, 2, 0) | PSEUDO}, + {"brl.dptk", BRLP (0, 2, 0)}, {"brl.dptk.few.clr", BRL (0, 2, 1)}, - {"brl.dptk.clr", BRL (0, 2, 1) | PSEUDO}, + {"brl.dptk.clr", BRLP (0, 2, 1)}, {"brl.dpnt.few", BRL (0, 3, 0)}, - {"brl.dpnt", BRL (0, 3, 0) | PSEUDO}, + {"brl.dpnt", BRLP (0, 3, 0)}, {"brl.dpnt.few.clr", BRL (0, 3, 1)}, - {"brl.dpnt.clr", BRL (0, 3, 1) | PSEUDO}, + {"brl.dpnt.clr", BRLP (0, 3, 1)}, {"brl.sptk.many", BRL (1, 0, 0)}, {"brl.sptk.many.clr", BRL (1, 0, 1)}, {"brl.spnt.many", BRL (1, 1, 0)}, @@ -121,23 +128,25 @@ struct ia64_opcode ia64_opcodes_x[] = {"brl.dpnt.many", BRL (1, 3, 0)}, {"brl.dpnt.many.clr", BRL (1, 3, 1)}, #undef BRL -#define BRL(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, 0 +#undef BRLP +#define BRL(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, 0, 0, NULL +#define BRLP(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, PSEUDO, 0, NULL {"brl.call.sptk.few", BRL (0, 0, 0)}, - {"brl.call.sptk", BRL (0, 0, 0) | PSEUDO}, + {"brl.call.sptk", BRLP (0, 0, 0)}, {"brl.call.sptk.few.clr", BRL (0, 0, 1)}, - {"brl.call.sptk.clr", BRL (0, 0, 1) | PSEUDO}, + {"brl.call.sptk.clr", BRLP (0, 0, 1)}, {"brl.call.spnt.few", BRL (0, 1, 0)}, - {"brl.call.spnt", BRL (0, 1, 0) | PSEUDO}, + {"brl.call.spnt", BRLP (0, 1, 0)}, {"brl.call.spnt.few.clr", BRL (0, 1, 1)}, - {"brl.call.spnt.clr", BRL (0, 1, 1) | PSEUDO}, + {"brl.call.spnt.clr", BRLP (0, 1, 1)}, {"brl.call.dptk.few", BRL (0, 2, 0)}, - {"brl.call.dptk", BRL (0, 2, 0) | PSEUDO}, + {"brl.call.dptk", BRLP (0, 2, 0)}, {"brl.call.dptk.few.clr", BRL (0, 2, 1)}, - {"brl.call.dptk.clr", BRL (0, 2, 1) | PSEUDO}, + {"brl.call.dptk.clr", BRLP (0, 2, 1)}, {"brl.call.dpnt.few", BRL (0, 3, 0)}, - {"brl.call.dpnt", BRL (0, 3, 0) | PSEUDO}, + {"brl.call.dpnt", BRLP (0, 3, 0)}, {"brl.call.dpnt.few.clr", BRL (0, 3, 1)}, - {"brl.call.dpnt.clr", BRL (0, 3, 1) | PSEUDO}, + {"brl.call.dpnt.clr", BRLP (0, 3, 1)}, {"brl.call.sptk.many", BRL (1, 0, 0)}, {"brl.call.sptk.many.clr", BRL (1, 0, 1)}, {"brl.call.spnt.many", BRL (1, 1, 0)}, @@ -147,7 +156,8 @@ struct ia64_opcode ia64_opcodes_x[] = {"brl.call.dpnt.many", BRL (1, 3, 0)}, {"brl.call.dpnt.many.clr", BRL (1, 3, 1)}, #undef BRL - {0} +#undef BRLP + {NULL, 0, 0, 0, 0, {0}, 0, 0, NULL} }; #undef X0 diff --git a/contrib/binutils/opcodes/ia64-opc.c b/contrib/binutils/opcodes/ia64-opc.c index 9726381..fc90213 100644 --- a/contrib/binutils/opcodes/ia64-opc.c +++ b/contrib/binutils/opcodes/ia64-opc.c @@ -1,5 +1,5 @@ /* ia64-opc.c -- Functions to access the compacted opcode table - Copyright 1999, 2000 Free Software Foundation, Inc. + Copyright 1999, 2000, 2003 Free Software Foundation, Inc. Written by Bob Manson of Cygnus Solutions, <manson@cygnus.com> This file is part of GDB, GAS, and the GNU binutils. @@ -25,19 +25,19 @@ #include "ia64-asmtab.h" #include "ia64-asmtab.c" -static void get_opc_prefix PARAMS ((const char **, char *)); -static short int find_string_ent PARAMS ((const char *)); -static short int find_main_ent PARAMS ((short int)); -static short int find_completer PARAMS ((short int, short int, const char *)); -static ia64_insn apply_completer PARAMS ((ia64_insn, int)); -static int extract_op_bits PARAMS ((int, int, int)); -static int extract_op PARAMS ((int, int *, unsigned int *)); -static int opcode_verify PARAMS ((ia64_insn, int, enum ia64_insn_type)); -static int locate_opcode_ent PARAMS ((ia64_insn, enum ia64_insn_type)); +static void get_opc_prefix (const char **, char *); +static short int find_string_ent (const char *); +static short int find_main_ent (short int); +static short int find_completer (short int, short int, const char *); +static ia64_insn apply_completer (ia64_insn, int); +static int extract_op_bits (int, int, int); +static int extract_op (int, int *, unsigned int *); +static int opcode_verify (ia64_insn, int, enum ia64_insn_type); +static int locate_opcode_ent (ia64_insn, enum ia64_insn_type); static struct ia64_opcode *make_ia64_opcode - PARAMS ((ia64_insn, const char *, int, int)); + (ia64_insn, const char *, int, int); static struct ia64_opcode *ia64_find_matching_opcode - PARAMS ((const char *, short int)); + (const char *, short int); const struct ia64_templ_desc ia64_templ_desc[16] = { @@ -65,9 +65,7 @@ const struct ia64_templ_desc ia64_templ_desc[16] = of the opcode, or at the NUL character. */ static void -get_opc_prefix (ptr, dest) - const char **ptr; - char *dest; +get_opc_prefix (const char **ptr, char *dest) { char *c = strchr (*ptr, '.'); if (c != NULL) @@ -89,8 +87,7 @@ get_opc_prefix (ptr, dest) STR; return -1 if one does not exist. */ static short -find_string_ent (str) - const char *str; +find_string_ent (const char *str) { short start = 0; short end = sizeof (ia64_strings) / sizeof (const char *); @@ -124,8 +121,7 @@ find_string_ent (str) return -1 if one does not exist. */ static short -find_main_ent (nameindex) - short nameindex; +find_main_ent (short nameindex) { short start = 0; short end = sizeof (main_table) / sizeof (struct ia64_main_table); @@ -164,10 +160,7 @@ find_main_ent (nameindex) return -1 if one does not exist. */ static short -find_completer (main_ent, prev_completer, name) - short main_ent; - short prev_completer; - const char *name; +find_completer (short main_ent, short prev_completer, const char *name) { short name_index = find_string_ent (name); @@ -200,9 +193,7 @@ find_completer (main_ent, prev_completer, name) return the result. */ static ia64_insn -apply_completer (opcode, completer_index) - ia64_insn opcode; - int completer_index; +apply_completer (ia64_insn opcode, int completer_index) { ia64_insn mask = completer_table[completer_index].mask; ia64_insn bits = completer_table[completer_index].bits; @@ -220,10 +211,7 @@ apply_completer (opcode, completer_index) first byte in OP_POINTER.) */ static int -extract_op_bits (op_pointer, bitoffset, bits) - int op_pointer; - int bitoffset; - int bits; +extract_op_bits (int op_pointer, int bitoffset, int bits) { int res = 0; @@ -259,10 +247,7 @@ extract_op_bits (op_pointer, bitoffset, bits) state entry in bits is returned. */ static int -extract_op (op_pointer, opval, op) - int op_pointer; - int *opval; - unsigned int *op; +extract_op (int op_pointer, int *opval, unsigned int *op) { int oplen = 5; @@ -317,10 +302,7 @@ extract_op (op_pointer, opval, op) PLACE matches OPCODE and is of type TYPE. */ static int -opcode_verify (opcode, place, type) - ia64_insn opcode; - int place; - enum ia64_insn_type type; +opcode_verify (ia64_insn opcode, int place, enum ia64_insn_type type) { if (main_table[place].opcode_type != type) { @@ -364,9 +346,7 @@ opcode_verify (opcode, place, type) priority. */ static int -locate_opcode_ent (opcode, type) - ia64_insn opcode; - enum ia64_insn_type type; +locate_opcode_ent (ia64_insn opcode, enum ia64_insn_type type) { int currtest[41]; int bitpos[41]; @@ -545,11 +525,7 @@ locate_opcode_ent (opcode, type) /* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */ static struct ia64_opcode * -make_ia64_opcode (opcode, name, place, depind) - ia64_insn opcode; - const char *name; - int place; - int depind; +make_ia64_opcode (ia64_insn opcode, const char *name, int place, int depind) { struct ia64_opcode *res = (struct ia64_opcode *) xmalloc (sizeof (struct ia64_opcode)); @@ -572,9 +548,7 @@ make_ia64_opcode (opcode, name, place, depind) /* Determine the ia64_opcode entry for the opcode specified by INSN and TYPE. If a valid entry is not found, return NULL. */ struct ia64_opcode * -ia64_dis_opcode (insn, type) - ia64_insn insn; - enum ia64_insn_type type; +ia64_dis_opcode (ia64_insn insn, enum ia64_insn_type type) { int disent = locate_opcode_ent (insn, type); @@ -633,9 +607,7 @@ ia64_dis_opcode (insn, type) matches NAME. Return NULL if one is not found. */ static struct ia64_opcode * -ia64_find_matching_opcode (name, place) - const char *name; - short place; +ia64_find_matching_opcode (const char *name, short place) { char op[129]; const char *suffix; @@ -696,8 +668,7 @@ ia64_find_matching_opcode (name, place) release any resources used by the returned entry. */ struct ia64_opcode * -ia64_find_next_opcode (prev_ent) - struct ia64_opcode *prev_ent; +ia64_find_next_opcode (struct ia64_opcode *prev_ent) { return ia64_find_matching_opcode (prev_ent->name, prev_ent->ent_index + 1); @@ -710,8 +681,7 @@ ia64_find_next_opcode (prev_ent) release any resources used by the returned entry. */ struct ia64_opcode * -ia64_find_opcode (name) - const char *name; +ia64_find_opcode (const char *name) { char op[129]; const char *suffix; @@ -741,16 +711,14 @@ ia64_find_opcode (name) /* Free any resources used by ENT. */ void -ia64_free_opcode (ent) - struct ia64_opcode *ent; +ia64_free_opcode (struct ia64_opcode *ent) { free ((void *)ent->name); free (ent); } const struct ia64_dependency * -ia64_find_dependency (index) - int index; +ia64_find_dependency (int index) { index = DEP(index); diff --git a/contrib/binutils/opcodes/ia64-opc.h b/contrib/binutils/opcodes/ia64-opc.h index b721cb8..f9476d8 100644 --- a/contrib/binutils/opcodes/ia64-opc.h +++ b/contrib/binutils/opcodes/ia64-opc.h @@ -44,6 +44,7 @@ #define AR_CCV IA64_OPND_AR_CCV #define AR_PFS IA64_OPND_AR_PFS +#define AR_CSD IA64_OPND_AR_CSD #define C1 IA64_OPND_C1 #define C8 IA64_OPND_C8 #define C16 IA64_OPND_C16 diff --git a/contrib/binutils/opcodes/ia64-raw.tbl b/contrib/binutils/opcodes/ia64-raw.tbl index ec35888..476721c 100644 --- a/contrib/binutils/opcodes/ia64-raw.tbl +++ b/contrib/binutils/opcodes/ia64-raw.tbl @@ -2,8 +2,14 @@ Resource Name; Writers; Readers; Semantics of Dependency ALAT; chk.a.clr, IC:mem-readers-alat, IC:mem-writers, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, IC:chk-a, invala.e; none AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ia, br.ret, cover, flushrs, loadrs, IC:mov-from-AR-BSP, rfi; impliedF AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, IC:mov-from-AR-BSPSTORE; impliedF +AR[CFLG]; IC:mov-to-AR-CFLG; br.ia, IC:mov-from-AR-CFLG; impliedF AR[CCV]; IC:mov-to-AR-CCV; br.ia, IC:cmpxchg, IC:mov-from-AR-CCV; impliedF +AR[CSD]; ld16, IC:mov-to-AR-CSD; br.ia, cmp8xchg16, IC:mov-from-AR-CSD, st16; impliedF AR[EC]; IC:mod-sched-brs, br.ret, IC:mov-to-AR-EC; br.call, brl.call, br.ia, IC:mod-sched-brs, IC:mov-from-AR-EC; impliedF +AR[EFLAG]; IC:mov-to-AR-EFLAG; br.ia, IC:mov-from-AR-EFLAG; impliedF +AR[FCR]; IC:mov-to-AR-FCR; br.ia, IC:mov-from-AR-FCR; impliedF +AR[FDR]; IC:mov-to-AR-FDR; br.ia, IC:mov-from-AR-FDR; impliedF +AR[FIR]; IC:mov-to-AR-FIR; br.ia, IC:mov-from-AR-FIR; impliedF AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; br.ia, IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0, fsetc, IC:mov-from-AR-FPSR; impliedF AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; br.ia, IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-from-AR-FPSR; impliedF AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; br.ia, IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-from-AR-FPSR; impliedF @@ -14,6 +20,7 @@ AR[FPSR].sf2.flags; IC:fp-arith-s2, fclrf.s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-to AR[FPSR].sf3.flags; IC:fp-arith-s3, fclrf.s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; br.ia, fchkf.s3, IC:mov-from-AR-FPSR; impliedF AR[FPSR].traps; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF AR[FPSR].rv; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF +AR[FSR]; IC:mov-to-AR-FSR; br.ia, IC:mov-from-AR-FSR; impliedF AR[ITC]; IC:mov-to-AR-ITC; br.ia, IC:mov-from-AR-ITC; impliedF AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; br.ia, IC:mov-from-AR-K+1; impliedF AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; br.ia, IC:mod-sched-brs-counted, IC:mov-from-AR-LC; impliedF @@ -22,6 +29,7 @@ AR[PFS]; IC:mov-to-AR-PFS; alloc, br.ia, epc, IC:mov-from-AR-PFS; impliedF AR[PFS]; IC:mov-to-AR-PFS; br.ret; none AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RNAT; impliedF AR[RSC]; IC:mov-to-AR-RSC; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RSC, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-RNAT, IC:mov-from-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF +AR[SSD]; IC:mov-to-AR-SSD; br.ia, IC:mov-from-AR-SSD; impliedF AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; br.ia, ld8.fill, IC:mov-from-AR-UNAT; impliedF AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; br.ia, IC:mov-from-AR-rv+1; none AR%, % in 48-63, 112-127; IC:mov-to-AR-ig+1; br.ia, IC:mov-from-AR-ig+1; impliedF diff --git a/contrib/binutils/opcodes/ia64-waw.tbl b/contrib/binutils/opcodes/ia64-waw.tbl index c8a3365..98daebf 100644 --- a/contrib/binutils/opcodes/ia64-waw.tbl +++ b/contrib/binutils/opcodes/ia64-waw.tbl @@ -3,7 +3,13 @@ ALAT; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; IC:mem-read AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; impliedF AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; impliedF AR[CCV]; IC:mov-to-AR-CCV; IC:mov-to-AR-CCV; impliedF +AR[CFLG]; IC:mov-to-AR-CFLG; IC:mov-to-AR-CFLG; impliedF +AR[CSD]; ld16, IC:mov-to-AR-CSD; ld16, IC:mov-to-AR-CSD; impliedF AR[EC]; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; impliedF +AR[EFLAG]; mov-to-AR-EFLAG; mov-to-AR-EFLAG; impliedF +AR[FCR]; mov-to-AR-FCR; mov-to-AR-FCR; impliedF +AR[FDR]; mov-to-AR-FDR; mov-to-AR-FDR; impliedF +AR[FIR]; mov-to-AR-FIR; mov-to-AR-FIR; impliedF AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; IC:mov-to-AR-FPSR, fsetc.s0; impliedF AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; IC:mov-to-AR-FPSR, fsetc.s1; impliedF AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; IC:mov-to-AR-FPSR, fsetc.s2; impliedF @@ -18,6 +24,7 @@ AR[FPSR].sf3.flags; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; IC:fp-arith-s3, IC: AR[FPSR].sf3.flags; fclrf.s3, IC:fcmp-s3, IC:fp-arith-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; fclrf.s3, IC:mov-to-AR-FPSR; impliedF AR[FPSR].rv; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF AR[FPSR].traps; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF +AR[FSR]; IC:mov-to-AR-FSR; IC:mov-to-AR-FSR; impliedF AR[ITC]; IC:mov-to-AR-ITC; IC:mov-to-AR-ITC; impliedF AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; IC:mov-to-AR-K+1; impliedF AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; impliedF diff --git a/contrib/binutils/opcodes/po/Make-in b/contrib/binutils/opcodes/po/Make-in index 0552db1..6176dbf 100644 --- a/contrib/binutils/opcodes/po/Make-in +++ b/contrib/binutils/opcodes/po/Make-in @@ -24,6 +24,8 @@ gnulocaledir = $(prefix)/share/locale gettextsrcdir = $(prefix)/share/gettext/po subdir = po +DESTDIR = + INSTALL = @INSTALL@ INSTALL_DATA = @INSTALL_DATA@ MKINSTALLDIRS = @MKINSTALLDIRS@ @@ -111,9 +113,9 @@ install-data: install-data-@USE_NLS@ install-data-no: all install-data-yes: all if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $(datadir); \ + $(MKINSTALLDIRS) $(DESTDIR)$(datadir); \ else \ - $(top_srcdir)/mkinstalldirs $(datadir); \ + $(top_srcdir)/mkinstalldirs $(DESTDIR)$(datadir); \ fi @catalogs='$(CATALOGS)'; \ for cat in $$catalogs; do \ @@ -123,7 +125,7 @@ install-data-yes: all *) destdir=$(localedir);; \ esac; \ lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - dir=$$destdir/$$lang/LC_MESSAGES; \ + dir=$(DESTDIR)$$destdir/$$lang/LC_MESSAGES; \ if test -r $(MKINSTALLDIRS); then \ $(MKINSTALLDIRS) $$dir; \ else \ @@ -153,12 +155,12 @@ install-data-yes: all done if test "$(PACKAGE)" = "gettext"; then \ if test -r $(MKINSTALLDIRS); then \ - $(MKINSTALLDIRS) $(gettextsrcdir); \ + $(MKINSTALLDIRS) $(DESTDIR)$(gettextsrcdir); \ else \ - $(top_srcdir)/mkinstalldirs $(gettextsrcdir); \ + $(top_srcdir)/mkinstalldirs $(DESTDIR)$(gettextsrcdir); \ fi; \ $(INSTALL_DATA) $(srcdir)/Makefile.in.in \ - $(gettextsrcdir)/Makefile.in.in; \ + $(DESTDIR)$(gettextsrcdir)/Makefile.in.in; \ else \ : ; \ fi @@ -171,12 +173,12 @@ uninstall: for cat in $$catalogs; do \ cat=`basename $$cat`; \ lang=`echo $$cat | sed 's/\$(CATOBJEXT)$$//'`; \ - rm -f $(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ - rm -f $(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ - rm -f $(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ - rm -f $(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ + rm -f $(DESTDIR)$(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ + rm -f $(DESTDIR)$(localedir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ + rm -f $(DESTDIR)$(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT); \ + rm -f $(DESTDIR)$(gnulocaledir)/$$lang/LC_MESSAGES/$(PACKAGE)$(INSTOBJEXT).m; \ done - rm -f $(gettextsrcdir)/po-Makefile.in.in + rm -f $(DESTDIR)$(gettextsrcdir)/po-Makefile.in.in check: all diff --git a/contrib/binutils/opcodes/po/POTFILES.in b/contrib/binutils/opcodes/po/POTFILES.in index 9851ce8..333c612 100644 --- a/contrib/binutils/opcodes/po/POTFILES.in +++ b/contrib/binutils/opcodes/po/POTFILES.in @@ -16,8 +16,9 @@ d10v-dis.c d10v-opc.c d30v-dis.c d30v-opc.c -dis-buf.c disassemble.c +dis-buf.c +dis-init.c dlx-dis.c fr30-asm.c fr30-desc.c @@ -48,12 +49,26 @@ ia64-dis.c ia64-gen.c ia64-opc-a.c ia64-opc-b.c +ia64-opc.c ia64-opc-d.c ia64-opc-f.c +ia64-opc.h ia64-opc-i.c ia64-opc-m.c -ia64-opc.c -ia64-opc.h +ip2k-asm.c +ip2k-desc.c +ip2k-desc.h +ip2k-dis.c +ip2k-ibld.c +ip2k-opc.c +ip2k-opc.h +iq2000-asm.c +iq2000-desc.c +iq2000-desc.h +iq2000-dis.c +iq2000-ibld.c +iq2000-opc.c +iq2000-opc.h m10200-dis.c m10200-opc.c m10300-dis.c @@ -73,9 +88,9 @@ m68k-opc.c m88k-dis.c mcore-dis.c mcore-opc.h +mips16-opc.c mips-dis.c mips-opc.c -mips16-opc.c mmix-dis.c mmix-opc.c ns32k-dis.c @@ -97,15 +112,16 @@ ppc-opc.c s390-dis.c s390-mkopc.c s390-opc.c -sh-dis.c -sh-opc.h sh64-dis.c sh64-opc.c sh64-opc.h +sh-dis.c +sh-opc.h sparc-dis.c sparc-opc.c sysdep.h tic30-dis.c +tic4x-dis.c tic54x-dis.c tic54x-opc.c tic80-dis.c @@ -122,6 +138,7 @@ xstormy16-dis.c xstormy16-ibld.c xstormy16-opc.c xstormy16-opc.h +xtensa-dis.c z8k-dis.c -z8k-opc.h z8kgen.c +z8k-opc.h diff --git a/contrib/binutils/opcodes/po/opcodes.pot b/contrib/binutils/opcodes/po/opcodes.pot index 575d860..15fdff0 100644 --- a/contrib/binutils/opcodes/po/opcodes.pot +++ b/contrib/binutils/opcodes/po/opcodes.pot @@ -1,13 +1,12 @@ # SOME DESCRIPTIVE TITLE. -# Copyright (C) YEAR THE PACKAGE'S COPYRIGHT HOLDER -# This file is distributed under the same license as the PACKAGE package. +# Copyright (C) YEAR Free Software Foundation, Inc. # FIRST AUTHOR <EMAIL@ADDRESS>, YEAR. # #, fuzzy msgid "" msgstr "" "Project-Id-Version: PACKAGE VERSION\n" -"POT-Creation-Date: 2002-10-30 10:07-0500\n" +"POT-Creation-Date: 2003-07-17 14:54+0100\n" "PO-Revision-Date: YEAR-MO-DA HO:MI+ZONE\n" "Last-Translator: FULL NAME <EMAIL@ADDRESS>\n" "Language-Team: LANGUAGE <LL@li.org>\n" @@ -27,47 +26,47 @@ msgstr "" msgid "Illegal limm reference in last instruction!\n" msgstr "" -#: arm-dis.c:507 +#: arm-dis.c:554 msgid "<illegal precision>" msgstr "" -#: arm-dis.c:1010 +#: arm-dis.c:1162 #, c-format msgid "Unrecognised register name set: %s\n" msgstr "" -#: arm-dis.c:1017 +#: arm-dis.c:1169 #, c-format msgid "Unrecognised disassembler option: %s\n" msgstr "" -#: arm-dis.c:1191 +#: arm-dis.c:1343 msgid "" "\n" "The following ARM specific disassembler options are supported for use with\n" "the -M switch:\n" msgstr "" -#: avr-dis.c:118 avr-dis.c:128 +#: avr-dis.c:117 avr-dis.c:127 msgid "undefined" msgstr "" -#: avr-dis.c:180 +#: avr-dis.c:179 msgid "Internal disassembler error" msgstr "" -#: avr-dis.c:228 +#: avr-dis.c:227 #, c-format msgid "unknown constraint `%c'" msgstr "" -#: cgen-asm.c:346 fr30-ibld.c:195 frv-ibld.c:195 m32r-ibld.c:195 -#: openrisc-ibld.c:195 xstormy16-ibld.c:195 +#: cgen-asm.c:348 fr30-ibld.c:195 frv-ibld.c:195 ip2k-ibld.c:195 +#: iq2000-ibld.c:195 m32r-ibld.c:195 openrisc-ibld.c:195 xstormy16-ibld.c:195 #, c-format msgid "operand out of range (%ld not between %ld and %ld)" msgstr "" -#: cgen-asm.c:367 +#: cgen-asm.c:369 #, c-format msgid "operand out of range (%lu not between %lu and %lu)" msgstr "" @@ -88,128 +87,134 @@ msgstr "" msgid "Address 0x%x is out of bounds.\n" msgstr "" -#: fr30-asm.c:323 frv-asm.c:595 m32r-asm.c:325 openrisc-asm.c:244 -#: xstormy16-asm.c:231 +#: fr30-asm.c:323 frv-asm.c:626 ip2k-asm.c:574 iq2000-asm.c:460 m32r-asm.c:325 +#: openrisc-asm.c:244 xstormy16-asm.c:284 #, c-format msgid "Unrecognized field %d while parsing.\n" msgstr "" -#: fr30-asm.c:373 frv-asm.c:645 m32r-asm.c:375 openrisc-asm.c:294 -#: xstormy16-asm.c:281 +#: fr30-asm.c:373 frv-asm.c:676 ip2k-asm.c:624 iq2000-asm.c:510 m32r-asm.c:375 +#: openrisc-asm.c:294 xstormy16-asm.c:334 msgid "missing mnemonic in syntax string" msgstr "" #. We couldn't parse it. -#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:781 -#: frv-asm.c:785 frv-asm.c:872 frv-asm.c:974 m32r-asm.c:511 m32r-asm.c:515 +#: fr30-asm.c:509 fr30-asm.c:513 fr30-asm.c:600 fr30-asm.c:702 frv-asm.c:812 +#: frv-asm.c:816 frv-asm.c:903 frv-asm.c:1005 ip2k-asm.c:760 ip2k-asm.c:764 +#: ip2k-asm.c:851 ip2k-asm.c:953 iq2000-asm.c:646 iq2000-asm.c:650 +#: iq2000-asm.c:737 iq2000-asm.c:839 m32r-asm.c:511 m32r-asm.c:515 #: m32r-asm.c:602 m32r-asm.c:704 openrisc-asm.c:430 openrisc-asm.c:434 -#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:417 -#: xstormy16-asm.c:421 xstormy16-asm.c:508 xstormy16-asm.c:610 +#: openrisc-asm.c:521 openrisc-asm.c:623 xstormy16-asm.c:470 +#: xstormy16-asm.c:474 xstormy16-asm.c:561 xstormy16-asm.c:663 msgid "unrecognized instruction" msgstr "" -#: fr30-asm.c:556 frv-asm.c:828 m32r-asm.c:558 openrisc-asm.c:477 -#: xstormy16-asm.c:464 +#: fr30-asm.c:556 frv-asm.c:859 ip2k-asm.c:807 iq2000-asm.c:693 m32r-asm.c:558 +#: openrisc-asm.c:477 xstormy16-asm.c:517 #, c-format msgid "syntax error (expected char `%c', found `%c')" msgstr "" -#: fr30-asm.c:566 frv-asm.c:838 m32r-asm.c:568 openrisc-asm.c:487 -#: xstormy16-asm.c:474 +#: fr30-asm.c:566 frv-asm.c:869 ip2k-asm.c:817 iq2000-asm.c:703 m32r-asm.c:568 +#: openrisc-asm.c:487 xstormy16-asm.c:527 #, c-format msgid "syntax error (expected char `%c', found end of instruction)" msgstr "" -#: fr30-asm.c:594 frv-asm.c:866 m32r-asm.c:596 openrisc-asm.c:515 -#: xstormy16-asm.c:502 +#: fr30-asm.c:594 frv-asm.c:897 ip2k-asm.c:845 iq2000-asm.c:731 m32r-asm.c:596 +#: openrisc-asm.c:515 xstormy16-asm.c:555 msgid "junk at end of line" msgstr "" -#: fr30-asm.c:701 frv-asm.c:973 m32r-asm.c:703 openrisc-asm.c:622 -#: xstormy16-asm.c:609 +#: fr30-asm.c:701 frv-asm.c:1004 ip2k-asm.c:952 iq2000-asm.c:838 +#: m32r-asm.c:703 openrisc-asm.c:622 xstormy16-asm.c:662 msgid "unrecognized form of instruction" msgstr "" -#: fr30-asm.c:713 frv-asm.c:985 m32r-asm.c:715 openrisc-asm.c:634 -#: xstormy16-asm.c:621 +#: fr30-asm.c:713 frv-asm.c:1016 ip2k-asm.c:964 iq2000-asm.c:850 +#: m32r-asm.c:715 openrisc-asm.c:634 xstormy16-asm.c:674 #, c-format msgid "bad instruction `%.50s...'" msgstr "" -#: fr30-asm.c:716 frv-asm.c:988 m32r-asm.c:718 openrisc-asm.c:637 -#: xstormy16-asm.c:624 +#: fr30-asm.c:716 frv-asm.c:1019 ip2k-asm.c:967 iq2000-asm.c:853 +#: m32r-asm.c:718 openrisc-asm.c:637 xstormy16-asm.c:677 #, c-format msgid "bad instruction `%.50s'" msgstr "" #. Default text to print if an instruction isn't recognized. -#: fr30-dis.c:39 frv-dis.c:39 m32r-dis.c:39 mmix-dis.c:282 openrisc-dis.c:39 -#: xstormy16-dis.c:39 +#: fr30-dis.c:41 frv-dis.c:41 ip2k-dis.c:41 iq2000-dis.c:41 m32r-dis.c:41 +#: mmix-dis.c:284 openrisc-dis.c:41 xstormy16-dis.c:41 msgid "*unknown*" msgstr "" -#: fr30-dis.c:318 frv-dis.c:360 m32r-dis.c:249 openrisc-dis.c:136 -#: xstormy16-dis.c:169 +#: fr30-dis.c:320 frv-dis.c:371 ip2k-dis.c:329 iq2000-dis.c:192 m32r-dis.c:251 +#: openrisc-dis.c:138 xstormy16-dis.c:171 #, c-format msgid "Unrecognized field %d while printing insn.\n" msgstr "" -#: fr30-ibld.c:166 frv-ibld.c:166 m32r-ibld.c:166 openrisc-ibld.c:166 -#: xstormy16-ibld.c:166 +#: fr30-ibld.c:166 frv-ibld.c:166 ip2k-ibld.c:166 iq2000-ibld.c:166 +#: m32r-ibld.c:166 openrisc-ibld.c:166 xstormy16-ibld.c:166 #, c-format msgid "operand out of range (%ld not between %ld and %lu)" msgstr "" -#: fr30-ibld.c:179 frv-ibld.c:179 m32r-ibld.c:179 openrisc-ibld.c:179 -#: xstormy16-ibld.c:179 +#: fr30-ibld.c:179 frv-ibld.c:179 ip2k-ibld.c:179 iq2000-ibld.c:179 +#: m32r-ibld.c:179 openrisc-ibld.c:179 xstormy16-ibld.c:179 #, c-format msgid "operand out of range (%lu not between 0 and %lu)" msgstr "" -#: fr30-ibld.c:730 frv-ibld.c:820 m32r-ibld.c:659 openrisc-ibld.c:633 -#: xstormy16-ibld.c:678 +#: fr30-ibld.c:730 frv-ibld.c:829 ip2k-ibld.c:607 iq2000-ibld.c:713 +#: m32r-ibld.c:659 openrisc-ibld.c:633 xstormy16-ibld.c:678 #, c-format msgid "Unrecognized field %d while building insn.\n" msgstr "" -#: fr30-ibld.c:937 frv-ibld.c:1103 m32r-ibld.c:792 openrisc-ibld.c:735 -#: xstormy16-ibld.c:826 +#: fr30-ibld.c:937 frv-ibld.c:1121 ip2k-ibld.c:684 iq2000-ibld.c:890 +#: m32r-ibld.c:792 openrisc-ibld.c:735 xstormy16-ibld.c:826 #, c-format msgid "Unrecognized field %d while decoding insn.\n" msgstr "" -#: fr30-ibld.c:1086 frv-ibld.c:1348 m32r-ibld.c:902 openrisc-ibld.c:815 -#: xstormy16-ibld.c:939 +#: fr30-ibld.c:1086 frv-ibld.c:1375 ip2k-ibld.c:761 iq2000-ibld.c:1024 +#: m32r-ibld.c:902 openrisc-ibld.c:815 xstormy16-ibld.c:939 #, c-format msgid "Unrecognized field %d while getting int operand.\n" msgstr "" -#: fr30-ibld.c:1215 frv-ibld.c:1573 m32r-ibld.c:992 openrisc-ibld.c:875 -#: xstormy16-ibld.c:1032 +#: fr30-ibld.c:1215 frv-ibld.c:1609 ip2k-ibld.c:818 iq2000-ibld.c:1138 +#: m32r-ibld.c:992 openrisc-ibld.c:875 xstormy16-ibld.c:1032 #, c-format msgid "Unrecognized field %d while getting vma operand.\n" msgstr "" -#: fr30-ibld.c:1349 frv-ibld.c:1807 m32r-ibld.c:1090 openrisc-ibld.c:944 -#: xstormy16-ibld.c:1134 +#: fr30-ibld.c:1349 frv-ibld.c:1852 ip2k-ibld.c:880 iq2000-ibld.c:1261 +#: m32r-ibld.c:1090 openrisc-ibld.c:944 xstormy16-ibld.c:1134 #, c-format msgid "Unrecognized field %d while setting int operand.\n" msgstr "" -#: fr30-ibld.c:1471 frv-ibld.c:2029 m32r-ibld.c:1176 openrisc-ibld.c:1001 -#: xstormy16-ibld.c:1224 +#: fr30-ibld.c:1471 frv-ibld.c:2083 ip2k-ibld.c:930 iq2000-ibld.c:1372 +#: m32r-ibld.c:1176 openrisc-ibld.c:1001 xstormy16-ibld.c:1224 #, c-format msgid "Unrecognized field %d while setting vma operand.\n" msgstr "" -#: h8300-dis.c:385 +#: frv-asm.c:365 +msgid "register number must be even" +msgstr "" + +#: h8300-dis.c:377 #, c-format -msgid "Hmmmm %x" +msgid "Hmmmm 0x%x" msgstr "" -#: h8300-dis.c:396 +#: h8300-dis.c:760 #, c-format -msgid "Don't understand %x \n" +msgid "Don't understand 0x%x \n" msgstr "" #: h8500-dis.c:143 @@ -223,10 +228,185 @@ msgstr "" msgid "%02x\t\t*unknown*" msgstr "" -#: i386-dis.c:1649 +#: i386-dis.c:1699 msgid "<internal disassembler error>" msgstr "" +#: ia64-gen.c:295 +#, c-format +msgid "%s: Error: " +msgstr "" + +#: ia64-gen.c:308 +#, c-format +msgid "%s: Warning: " +msgstr "" + +#: ia64-gen.c:494 ia64-gen.c:728 +#, c-format +msgid "multiple note %s not handled\n" +msgstr "" + +#: ia64-gen.c:605 +msgid "can't find ia64-ic.tbl for reading\n" +msgstr "" + +#: ia64-gen.c:810 +#, c-format +msgid "can't find %s for reading\n" +msgstr "" + +#: ia64-gen.c:1034 +#, c-format +msgid "" +"most recent format '%s'\n" +"appears more restrictive than '%s'\n" +msgstr "" + +#: ia64-gen.c:1045 +#, c-format +msgid "overlapping field %s->%s\n" +msgstr "" + +#: ia64-gen.c:1236 +#, c-format +msgid "overwriting note %d with note %d (IC:%s)\n" +msgstr "" + +#: ia64-gen.c:1435 +#, c-format +msgid "don't know how to specify %% dependency %s\n" +msgstr "" + +#: ia64-gen.c:1457 +#, c-format +msgid "Don't know how to specify # dependency %s\n" +msgstr "" + +#: ia64-gen.c:1496 +#, c-format +msgid "IC:%s [%s] has no terminals or sub-classes\n" +msgstr "" + +#: ia64-gen.c:1499 +#, c-format +msgid "IC:%s has no terminals or sub-classes\n" +msgstr "" + +#: ia64-gen.c:1508 +#, c-format +msgid "no insns mapped directly to terminal IC %s [%s]" +msgstr "" + +#: ia64-gen.c:1511 +#, c-format +msgid "no insns mapped directly to terminal IC %s\n" +msgstr "" + +#: ia64-gen.c:1522 +#, c-format +msgid "class %s is defined but not used\n" +msgstr "" + +#: ia64-gen.c:1533 +#, c-format +msgid "Warning: rsrc %s (%s) has no chks%s\n" +msgstr "" + +#: ia64-gen.c:1537 +#, c-format +msgid "rsrc %s (%s) has no regs\n" +msgstr "" + +#: ia64-gen.c:2436 +#, c-format +msgid "IC note %d in opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "" + +#: ia64-gen.c:2464 +#, c-format +msgid "IC note %d for opcode %s (IC:%s) conflicts with resource %s note %d\n" +msgstr "" + +#: ia64-gen.c:2478 +#, c-format +msgid "opcode %s has no class (ops %d %d %d)\n" +msgstr "" + +#: ia64-gen.c:2789 +#, c-format +msgid "unable to change directory to \"%s\", errno = %s\n" +msgstr "" + +#. We've been passed a w. Return with an error message so that +#. cgen will try the next parsing option. +#: ip2k-asm.c:92 +msgid "W keyword invalid in FR operand slot." +msgstr "" + +#. Invalid offset present. +#: ip2k-asm.c:122 +msgid "offset(IP) is not a valid form" +msgstr "" + +#. Found something there in front of (DP) but it's out +#. of range. +#: ip2k-asm.c:175 +msgid "(DP) offset out of range." +msgstr "" + +#. Found something there in front of (SP) but it's out +#. of range. +#: ip2k-asm.c:221 +msgid "(SP) offset out of range." +msgstr "" + +#: ip2k-asm.c:241 +msgid "illegal use of parentheses" +msgstr "" + +#: ip2k-asm.c:248 +msgid "operand out of range (not between 1 and 255)" +msgstr "" + +#. Something is very wrong. opindex has to be one of the above. +#: ip2k-asm.c:273 +msgid "parse_addr16: invalid opindex." +msgstr "" + +#: ip2k-asm.c:353 +msgid "Byte address required. - must be even." +msgstr "" + +#: ip2k-asm.c:362 +msgid "cgen_parse_address returned a symbol. Literal required." +msgstr "" + +#: ip2k-asm.c:420 +#, c-format +msgid "%operator operand is not a symbol" +msgstr "" + +#: ip2k-asm.c:474 +msgid "Attempt to find bit index of 0" +msgstr "" + +#: iq2000-asm.c:110 iq2000-asm.c:141 +msgid "immediate value cannot be register" +msgstr "" + +#: iq2000-asm.c:120 iq2000-asm.c:151 +msgid "immediate value out of range" +msgstr "" + +#: iq2000-asm.c:180 +msgid "21-bit offset out of range" +msgstr "" + +#: iq2000-asm.c:205 iq2000-asm.c:235 iq2000-asm.c:272 iq2000-asm.c:305 +msgid "missing `)'" +msgstr "" + #: m10200-dis.c:199 #, c-format msgid "unknown\t0x%02x" @@ -237,7 +417,7 @@ msgstr "" msgid "unknown\t0x%04lx" msgstr "" -#: m10300-dis.c:685 +#: m10300-dis.c:766 #, c-format msgid "unknown\t0x%04x" msgstr "" @@ -252,21 +432,99 @@ msgstr "" msgid "<function code %d>" msgstr "" -#: m88k-dis.c:255 +#: m88k-dis.c:746 #, c-format msgid "# <dis error: %08x>" msgstr "" -#: mips-dis.c:337 +#: mips-dis.c:703 +msgid "# internal error, incomplete extension sequence (+)" +msgstr "" + +#: mips-dis.c:746 +#, c-format +msgid "# internal error, undefined extension sequence (+%c)" +msgstr "" + +#: mips-dis.c:1004 #, c-format msgid "# internal error, undefined modifier(%c)" msgstr "" -#: mips-dis.c:1209 +#: mips-dis.c:1755 #, c-format msgid "# internal disassembler error, unrecognised modifier (%c)" msgstr "" +#: mips-dis.c:1767 +msgid "" +"\n" +"The following MIPS specific disassembler options are supported for use\n" +"with the -M switch (multiple options should be separated by commas):\n" +msgstr "" + +#: mips-dis.c:1771 +msgid "" +"\n" +" gpr-names=ABI Print GPR names according to specified ABI.\n" +" Default: based on binary being disassembled.\n" +msgstr "" + +#: mips-dis.c:1775 +msgid "" +"\n" +" fpr-names=ABI Print FPR names according to specified ABI.\n" +" Default: numeric.\n" +msgstr "" + +#: mips-dis.c:1779 +msgid "" +"\n" +" cp0-names=ARCH Print CP0 register names according to\n" +" specified architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" + +#: mips-dis.c:1784 +msgid "" +"\n" +" hwr-names=ARCH Print HWR names according to specified \n" +"\t\t\t architecture.\n" +" Default: based on binary being disassembled.\n" +msgstr "" + +#: mips-dis.c:1789 +msgid "" +"\n" +" reg-names=ABI Print GPR and FPR names according to\n" +" specified ABI.\n" +msgstr "" + +#: mips-dis.c:1793 +msgid "" +"\n" +" reg-names=ARCH Print CP0 register and HWR names according to\n" +" specified architecture.\n" +msgstr "" + +#: mips-dis.c:1797 +msgid "" +"\n" +" For the options above, the following values are supported for \"ABI\":\n" +" " +msgstr "" + +#: mips-dis.c:1802 mips-dis.c:1810 mips-dis.c:1812 +msgid "\n" +msgstr "" + +#: mips-dis.c:1804 +msgid "" +"\n" +" For the options above, The following values are supported for \"ARCH\":\n" +" " +msgstr "" + #: mmix-dis.c:34 #, c-format msgid "Bad case %d (%s) in %s:%d\n" @@ -281,7 +539,7 @@ msgstr "" msgid "(unknown)" msgstr "" -#: mmix-dis.c:517 +#: mmix-dis.c:519 #, c-format msgid "*unknown operands type: %d*" msgstr "" @@ -292,76 +550,116 @@ msgstr "" #. * aoffsetp by since whatever generated this is broken #. * anyway! #. -#: ns32k-dis.c:628 +#: ns32k-dis.c:631 msgid "$<undefined>" msgstr "" -#: ppc-opc.c:777 ppc-opc.c:810 +#: ppc-opc.c:781 ppc-opc.c:809 msgid "invalid conditional option" msgstr "" -#: ppc-opc.c:812 +#: ppc-opc.c:811 msgid "attempt to set y bit when using + or - modifier" msgstr "" -#: ppc-opc.c:844 ppc-opc.c:896 +#: ppc-opc.c:840 +msgid "offset not a multiple of 16" +msgstr "" + +#: ppc-opc.c:860 +msgid "offset not a multiple of 2" +msgstr "" + +#: ppc-opc.c:862 +msgid "offset greater than 62" +msgstr "" + +#: ppc-opc.c:881 ppc-opc.c:927 ppc-opc.c:975 msgid "offset not a multiple of 4" msgstr "" -#: ppc-opc.c:869 +#: ppc-opc.c:883 +msgid "offset greater than 124" +msgstr "" + +#: ppc-opc.c:902 +msgid "offset not a multiple of 8" +msgstr "" + +#: ppc-opc.c:904 +msgid "offset greater than 248" +msgstr "" + +#: ppc-opc.c:950 msgid "offset not between -2048 and 2047" msgstr "" -#: ppc-opc.c:894 +#: ppc-opc.c:973 msgid "offset not between -8192 and 8191" msgstr "" -#: ppc-opc.c:922 +#: ppc-opc.c:1011 +msgid "ignoring invalid mfcr mask" +msgstr "" + +#: ppc-opc.c:1059 msgid "ignoring least significant bits in branch offset" msgstr "" -#: ppc-opc.c:956 ppc-opc.c:993 +#: ppc-opc.c:1090 ppc-opc.c:1125 msgid "illegal bitmask" msgstr "" -#: ppc-opc.c:1066 +#: ppc-opc.c:1192 msgid "value out of range" msgstr "" -#: ppc-opc.c:1142 +#: ppc-opc.c:1262 msgid "index register in load range" msgstr "" -#: ppc-opc.c:1158 +#: ppc-opc.c:1279 +msgid "source and target register operands must be different" +msgstr "" + +#: ppc-opc.c:1294 msgid "invalid register operand when updating" msgstr "" -#. Mark as non-valid instruction -#: sparc-dis.c:750 +#: ppc-opc.c:1335 +msgid "target register operand must be even" +msgstr "" + +#: ppc-opc.c:1350 +msgid "source register operand must be even" +msgstr "" + +#. Mark as non-valid instruction. +#: sparc-dis.c:760 msgid "unknown" msgstr "" -#: sparc-dis.c:825 +#: sparc-dis.c:835 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "" -#: sparc-dis.c:836 +#: sparc-dis.c:846 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n" msgstr "" -#: sparc-dis.c:885 +#: sparc-dis.c:895 #, c-format msgid "Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n" msgstr "" -#: v850-dis.c:224 +#: v850-dis.c:221 #, c-format msgid "unknown operand shift: %x\n" msgstr "" -#: v850-dis.c:236 +#: v850-dis.c:233 #, c-format msgid "unknown pop reg: %d\n" msgstr "" @@ -415,30 +713,42 @@ msgstr "" msgid "immediate value must be even" msgstr "" -#: xstormy16-asm.c:74 +#: xstormy16-asm.c:76 msgid "Bad register in preincrement" msgstr "" -#: xstormy16-asm.c:79 +#: xstormy16-asm.c:81 msgid "Bad register in postincrement" msgstr "" -#: xstormy16-asm.c:81 +#: xstormy16-asm.c:83 msgid "Bad register name" msgstr "" -#: xstormy16-asm.c:85 +#: xstormy16-asm.c:87 msgid "Label conflicts with register name" msgstr "" -#: xstormy16-asm.c:89 +#: xstormy16-asm.c:91 msgid "Label conflicts with `Rx'" msgstr "" -#: xstormy16-asm.c:91 +#: xstormy16-asm.c:93 msgid "Bad immediate expression" msgstr "" -#: xstormy16-asm.c:120 +#: xstormy16-asm.c:115 +msgid "No relocation for small immediate" +msgstr "" + +#: xstormy16-asm.c:125 msgid "Small operand was not an immediate number" msgstr "" + +#: xstormy16-asm.c:164 +msgid "Operand is not a symbol" +msgstr "" + +#: xstormy16-asm.c:172 +msgid "Syntax error: No trailing ')'" +msgstr "" diff --git a/contrib/binutils/opcodes/ppc-dis.c b/contrib/binutils/opcodes/ppc-dis.c index 35726ae..4d48b9d 100644 --- a/contrib/binutils/opcodes/ppc-dis.c +++ b/contrib/binutils/opcodes/ppc-dis.c @@ -1,5 +1,6 @@ /* ppc-dis.c -- Disassemble PowerPC instructions - Copyright 1994, 1995, 2000, 2001, 2002 Free Software Foundation, Inc. + Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004 + Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -29,18 +30,19 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * in both big and little endian mode and also for the POWER (RS/6000) chip. */ -static int print_insn_powerpc PARAMS ((bfd_vma, struct disassemble_info *, - int bigendian, int dialect)); +static int print_insn_powerpc (bfd_vma, struct disassemble_info *, int, int); -static int powerpc_dialect PARAMS ((struct disassemble_info *)); +struct dis_private { + /* Stash the result of parsing disassembler_options here. */ + int dialect; +}; /* Determine which set of machines to disassemble for. PPC403/601 or BookE. For convenience, also disassemble instructions supported by the AltiVec vector unit. */ -int -powerpc_dialect(info) - struct disassemble_info *info; +static int +powerpc_dialect (struct disassemble_info *info) { int dialect = PPC_OPCODE_PPC | PPC_OPCODE_ALTIVEC; @@ -48,17 +50,39 @@ powerpc_dialect(info) dialect |= PPC_OPCODE_64; if (info->disassembler_options - && (strcmp (info->disassembler_options, "booke") == 0 - || strcmp (info->disassembler_options, "booke32") == 0 - || strcmp (info->disassembler_options, "booke64") == 0)) + && strstr (info->disassembler_options, "booke") != NULL) dialect |= PPC_OPCODE_BOOKE | PPC_OPCODE_BOOKE64; - else - dialect |= PPC_OPCODE_403 | PPC_OPCODE_601; + else if ((info->mach == bfd_mach_ppc_e500) + || (info->disassembler_options + && strstr (info->disassembler_options, "e500") != NULL)) + { + dialect |= PPC_OPCODE_BOOKE + | PPC_OPCODE_SPE | PPC_OPCODE_ISEL + | PPC_OPCODE_EFS | PPC_OPCODE_BRLOCK + | PPC_OPCODE_PMR | PPC_OPCODE_CACHELCK + | PPC_OPCODE_RFMCI; + /* efs* and AltiVec conflict. */ + dialect &= ~PPC_OPCODE_ALTIVEC; + } + else if (info->disassembler_options + && strstr (info->disassembler_options, "efs") != NULL) + { + dialect |= PPC_OPCODE_EFS; + /* efs* and AltiVec conflict. */ + dialect &= ~PPC_OPCODE_ALTIVEC; + } + else + dialect |= (PPC_OPCODE_403 | PPC_OPCODE_601 | PPC_OPCODE_CLASSIC + | PPC_OPCODE_COMMON); if (info->disassembler_options - && strcmp (info->disassembler_options, "power4") == 0) + && strstr (info->disassembler_options, "power4") != NULL) dialect |= PPC_OPCODE_POWER4; + if (info->disassembler_options + && strstr (info->disassembler_options, "any") != NULL) + dialect |= PPC_OPCODE_ANY; + if (info->disassembler_options) { if (strstr (info->disassembler_options, "32") != NULL) @@ -67,35 +91,32 @@ powerpc_dialect(info) dialect |= PPC_OPCODE_64; } + ((struct dis_private *) &info->private_data)->dialect = dialect; return dialect; } /* Print a big endian PowerPC instruction. */ int -print_insn_big_powerpc (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_big_powerpc (bfd_vma memaddr, struct disassemble_info *info) { - return print_insn_powerpc (memaddr, info, 1, powerpc_dialect(info)); + int dialect = ((struct dis_private *) &info->private_data)->dialect; + return print_insn_powerpc (memaddr, info, 1, dialect); } /* Print a little endian PowerPC instruction. */ int -print_insn_little_powerpc (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_little_powerpc (bfd_vma memaddr, struct disassemble_info *info) { - return print_insn_powerpc (memaddr, info, 0, powerpc_dialect(info)); + int dialect = ((struct dis_private *) &info->private_data)->dialect; + return print_insn_powerpc (memaddr, info, 0, dialect); } /* Print a POWER (RS/6000) instruction. */ int -print_insn_rs6000 (memaddr, info) - bfd_vma memaddr; - struct disassemble_info *info; +print_insn_rs6000 (bfd_vma memaddr, struct disassemble_info *info) { return print_insn_powerpc (memaddr, info, 1, PPC_OPCODE_POWER); } @@ -103,11 +124,10 @@ print_insn_rs6000 (memaddr, info) /* Print a PowerPC or POWER instruction. */ static int -print_insn_powerpc (memaddr, info, bigendian, dialect) - bfd_vma memaddr; - struct disassemble_info *info; - int bigendian; - int dialect; +print_insn_powerpc (bfd_vma memaddr, + struct disassemble_info *info, + int bigendian, + int dialect) { bfd_byte buffer[4]; int status; @@ -116,6 +136,9 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) const struct powerpc_opcode *opcode_end; unsigned long op; + if (dialect == 0) + dialect = powerpc_dialect (info); + status = (*info->read_memory_func) (memaddr, buffer, 4, info); if (status != 0) { @@ -134,6 +157,7 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) /* Find the first match in the opcode table. We could speed this up a bit by doing a binary search on the major opcode. */ opcode_end = powerpc_opcodes + powerpc_num_opcodes; + again: for (opcode = powerpc_opcodes; opcode < opcode_end; opcode++) { unsigned long table_op; @@ -167,9 +191,10 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) continue; /* The instruction is valid. */ - (*info->fprintf_func) (info->stream, "%s", opcode->name); if (opcode->operands[0] != 0) - (*info->fprintf_func) (info->stream, "\t"); + (*info->fprintf_func) (info->stream, "%-7s ", opcode->name); + else + (*info->fprintf_func) (info->stream, "%s", opcode->name); /* Now extract and print the operands. */ need_comma = 0; @@ -188,7 +213,7 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) /* Extract the value from the instruction. */ if (operand->extract) - value = (*operand->extract) (insn, dialect, (int *) NULL); + value = (*operand->extract) (insn, dialect, &invalid); else { value = (insn >> operand->shift) & ((1 << operand->bits) - 1); @@ -211,7 +236,8 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) } /* Print the operand as directed by the flags. */ - if ((operand->flags & PPC_OPERAND_GPR) != 0) + if ((operand->flags & PPC_OPERAND_GPR) != 0 + || ((operand->flags & PPC_OPERAND_GPR_0) != 0 && value != 0)) (*info->fprintf_func) (info->stream, "r%ld", value); else if ((operand->flags & PPC_OPERAND_FPR) != 0) (*info->fprintf_func) (info->stream, "f%ld", value); @@ -236,14 +262,9 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) cr = value >> 2; if (cr != 0) - (*info->fprintf_func) (info->stream, "4*cr%d", cr); + (*info->fprintf_func) (info->stream, "4*cr%d+", cr); cc = value & 3; - if (cc != 0) - { - if (cr != 0) - (*info->fprintf_func) (info->stream, "+"); - (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); - } + (*info->fprintf_func) (info->stream, "%s", cbnames[cc]); } } @@ -266,6 +287,12 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) return 4; } + if ((dialect & PPC_OPCODE_ANY) != 0) + { + dialect = ~PPC_OPCODE_ANY; + goto again; + } + /* We could not find a match. */ (*info->fprintf_func) (info->stream, ".long 0x%lx", insn); @@ -273,13 +300,15 @@ print_insn_powerpc (memaddr, info, bigendian, dialect) } void -print_ppc_disassembler_options (FILE * stream) +print_ppc_disassembler_options (FILE *stream) { fprintf (stream, "\n\ The following PPC specific disassembler options are supported for use with\n\ the -M switch:\n"); - + fprintf (stream, " booke|booke32|booke64 Disassemble the BookE instructions\n"); + fprintf (stream, " e500|e500x2 Disassemble the e500 instructions\n"); + fprintf (stream, " efs Disassemble the EFS instructions\n"); fprintf (stream, " power4 Disassemble the Power4 instructions\n"); fprintf (stream, " 32 Do not disassemble 64-bit instructions\n"); fprintf (stream, " 64 Allow disassembly of 64-bit instructions\n"); diff --git a/contrib/binutils/opcodes/ppc-opc.c b/contrib/binutils/opcodes/ppc-opc.c index 98ca1d2..2d0dee5 100644 --- a/contrib/binutils/opcodes/ppc-opc.c +++ b/contrib/binutils/opcodes/ppc-opc.c @@ -1,24 +1,24 @@ /* ppc-opc.c -- PowerPC opcode list - Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002 + Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support -This file is part of GDB, GAS, and the GNU binutils. + This file is part of GDB, GAS, and the GNU binutils. -GDB, GAS, and the GNU binutils are free software; you can redistribute -them and/or modify them under the terms of the GNU General Public -License as published by the Free Software Foundation; either version -2, or (at your option) any later version. + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public + License as published by the Free Software Foundation; either version + 2, or (at your option) any later version. -GDB, GAS, and the GNU binutils are distributed in the hope that they -will be useful, but WITHOUT ANY WARRANTY; without even the implied -warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See -the GNU General Public License for more details. + GDB, GAS, and the GNU binutils are distributed in the hope that they + will be useful, but WITHOUT ANY WARRANTY; without even the implied + warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See + the GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this file; see the file COPYING. If not, write to the Free -Software Foundation, 59 Temple Place - Suite 330, Boston, MA -02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this file; see the file COPYING. If not, write to the Free + Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ #include <stdio.h> #include "sysdep.h" @@ -38,90 +38,60 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA /* Local insertion and extraction functions. */ -static unsigned long insert_bat - PARAMS ((unsigned long, long, int, const char **)); -static long extract_bat - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_bba - PARAMS ((unsigned long, long, int, const char **)); -static long extract_bba - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_bd - PARAMS ((unsigned long, long, int, const char **)); -static long extract_bd - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_bdm - PARAMS ((unsigned long, long, int, const char **)); -static long extract_bdm - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_bdp - PARAMS ((unsigned long, long, int, const char **)); -static long extract_bdp - PARAMS ((unsigned long, int, int *)); -static int valid_bo - PARAMS ((long, int)); -static unsigned long insert_bo - PARAMS ((unsigned long, long, int, const char **)); -static long extract_bo - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_boe - PARAMS ((unsigned long, long, int, const char **)); -static long extract_boe - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_ds - PARAMS ((unsigned long, long, int, const char **)); -static long extract_ds - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_de - PARAMS ((unsigned long, long, int, const char **)); -static long extract_de - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_des - PARAMS ((unsigned long, long, int, const char **)); -static long extract_des - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_li - PARAMS ((unsigned long, long, int, const char **)); -static long extract_li - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_mbe - PARAMS ((unsigned long, long, int, const char **)); -static long extract_mbe - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_mb6 - PARAMS ((unsigned long, long, int, const char **)); -static long extract_mb6 - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_nb - PARAMS ((unsigned long, long, int, const char **)); -static long extract_nb - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_nsi - PARAMS ((unsigned long, long, int, const char **)); -static long extract_nsi - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_ral - PARAMS ((unsigned long, long, int, const char **)); -static unsigned long insert_ram - PARAMS ((unsigned long, long, int, const char **)); -static unsigned long insert_ras - PARAMS ((unsigned long, long, int, const char **)); -static unsigned long insert_rbs - PARAMS ((unsigned long, long, int, const char **)); -static long extract_rbs - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_sh6 - PARAMS ((unsigned long, long, int, const char **)); -static long extract_sh6 - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_spr - PARAMS ((unsigned long, long, int, const char **)); -static long extract_spr - PARAMS ((unsigned long, int, int *)); -static unsigned long insert_tbr - PARAMS ((unsigned long, long, int, const char **)); -static long extract_tbr - PARAMS ((unsigned long, int, int *)); +static unsigned long insert_bat (unsigned long, long, int, const char **); +static long extract_bat (unsigned long, int, int *); +static unsigned long insert_bba (unsigned long, long, int, const char **); +static long extract_bba (unsigned long, int, int *); +static unsigned long insert_bd (unsigned long, long, int, const char **); +static long extract_bd (unsigned long, int, int *); +static unsigned long insert_bdm (unsigned long, long, int, const char **); +static long extract_bdm (unsigned long, int, int *); +static unsigned long insert_bdp (unsigned long, long, int, const char **); +static long extract_bdp (unsigned long, int, int *); +static unsigned long insert_bo (unsigned long, long, int, const char **); +static long extract_bo (unsigned long, int, int *); +static unsigned long insert_boe (unsigned long, long, int, const char **); +static long extract_boe (unsigned long, int, int *); +static unsigned long insert_dq (unsigned long, long, int, const char **); +static long extract_dq (unsigned long, int, int *); +static unsigned long insert_ds (unsigned long, long, int, const char **); +static long extract_ds (unsigned long, int, int *); +static unsigned long insert_de (unsigned long, long, int, const char **); +static long extract_de (unsigned long, int, int *); +static unsigned long insert_des (unsigned long, long, int, const char **); +static long extract_des (unsigned long, int, int *); +static unsigned long insert_fxm (unsigned long, long, int, const char **); +static long extract_fxm (unsigned long, int, int *); +static unsigned long insert_li (unsigned long, long, int, const char **); +static long extract_li (unsigned long, int, int *); +static unsigned long insert_mbe (unsigned long, long, int, const char **); +static long extract_mbe (unsigned long, int, int *); +static unsigned long insert_mb6 (unsigned long, long, int, const char **); +static long extract_mb6 (unsigned long, int, int *); +static unsigned long insert_nb (unsigned long, long, int, const char **); +static long extract_nb (unsigned long, int, int *); +static unsigned long insert_nsi (unsigned long, long, int, const char **); +static long extract_nsi (unsigned long, int, int *); +static unsigned long insert_ral (unsigned long, long, int, const char **); +static unsigned long insert_ram (unsigned long, long, int, const char **); +static unsigned long insert_raq (unsigned long, long, int, const char **); +static unsigned long insert_ras (unsigned long, long, int, const char **); +static unsigned long insert_rbs (unsigned long, long, int, const char **); +static long extract_rbs (unsigned long, int, int *); +static unsigned long insert_rsq (unsigned long, long, int, const char **); +static unsigned long insert_rtq (unsigned long, long, int, const char **); +static unsigned long insert_sh6 (unsigned long, long, int, const char **); +static long extract_sh6 (unsigned long, int, int *); +static unsigned long insert_spr (unsigned long, long, int, const char **); +static long extract_spr (unsigned long, int, int *); +static unsigned long insert_tbr (unsigned long, long, int, const char **); +static long extract_tbr (unsigned long, int, int *); +static unsigned long insert_ev2 (unsigned long, long, int, const char **); +static long extract_ev2 (unsigned long, int, int *); +static unsigned long insert_ev4 (unsigned long, long, int, const char **); +static long extract_ev4 (unsigned long, int, int *); +static unsigned long insert_ev8 (unsigned long, long, int, const char **); +static long extract_ev8 (unsigned long, int, int *); /* The operands table. @@ -235,8 +205,20 @@ const struct powerpc_operand powerpc_operands[] = #define CR BT + 1 { 3, 18, 0, 0, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL }, + /* The CRB field in an X form instruction. */ +#define CRB CR + 1 + { 5, 6, 0, 0, 0 }, + + /* The CRFD field in an X form instruction. */ +#define CRFD CRB + 1 + { 3, 23, 0, 0, PPC_OPERAND_CR }, + + /* The CRFS field in an X form instruction. */ +#define CRFS CRFD + 1 + { 3, 0, 0, 0, PPC_OPERAND_CR }, + /* The CT field in an X form instruction. */ -#define CT CR + 1 +#define CT CRFS + 1 { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL }, /* The D field in a D form instruction. This is a displacement off @@ -255,9 +237,15 @@ const struct powerpc_operand powerpc_operands[] = #define DES DE + 1 { 14, 0, insert_des, extract_des, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED }, + /* The DQ field in a DQ form instruction. This is like D, but the + lower four bits are forced to zero. */ +#define DQ DES + 1 + { 16, 0, insert_dq, extract_dq, + PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ }, + /* The DS field in a DS form instruction. This is like D, but the lower two bits are forced to zero. */ -#define DS DES + 1 +#define DS DQ + 1 { 16, 0, insert_ds, extract_ds, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS }, @@ -301,10 +289,14 @@ const struct powerpc_operand powerpc_operands[] = /* The FXM field in an XFX instruction. */ #define FXM FRS + 1 #define FXM_MASK (0xff << 12) - { 8, 12, 0, 0, 0 }, + { 8, 12, insert_fxm, extract_fxm, 0 }, + + /* Power4 version for mfcr. */ +#define FXM4 FXM + 1 + { 8, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL }, /* The L field in a D or X form instruction. */ -#define L FXM + 1 +#define L FXM4 + 1 { 1, 21, 0, 0, PPC_OPERAND_OPTIONAL }, /* The LEV field in a POWER SC form instruction. */ @@ -352,7 +344,7 @@ const struct powerpc_operand powerpc_operands[] = /* The MO field in an mbar instruction. */ #define MO MB6 + 1 - { 5, 21, 0, 0, 0 }, + { 5, 21, 0, 0, PPC_OPERAND_OPTIONAL }, /* The NB field in an X form instruction. The value 32 is stored as 0. */ @@ -365,30 +357,43 @@ const struct powerpc_operand powerpc_operands[] = { 16, 0, insert_nsi, extract_nsi, PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED }, - /* The RA field in an D, DS, X, XO, M, or MDS form instruction. */ + /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction. */ #define RA NSI + 1 #define RA_MASK (0x1f << 16) { 5, 16, 0, 0, PPC_OPERAND_GPR }, + /* As above, but 0 in the RA field means zero, not r0. */ +#define RA0 RA + 1 + { 5, 16, 0, 0, PPC_OPERAND_GPR_0 }, + + /* The RA field in the DQ form lq instruction, which has special + value restrictions. */ +#define RAQ RA0 + 1 + { 5, 16, insert_raq, 0, PPC_OPERAND_GPR_0 }, + /* The RA field in a D or X form instruction which is an updating load, which means that the RA field may not be zero and may not equal the RT field. */ -#define RAL RA + 1 - { 5, 16, insert_ral, 0, PPC_OPERAND_GPR }, +#define RAL RAQ + 1 + { 5, 16, insert_ral, 0, PPC_OPERAND_GPR_0 }, /* The RA field in an lmw instruction, which has special value restrictions. */ #define RAM RAL + 1 - { 5, 16, insert_ram, 0, PPC_OPERAND_GPR }, + { 5, 16, insert_ram, 0, PPC_OPERAND_GPR_0 }, /* The RA field in a D or X form instruction which is an updating store or an updating floating point load, which means that the RA field may not be zero. */ #define RAS RAM + 1 - { 5, 16, insert_ras, 0, PPC_OPERAND_GPR }, + { 5, 16, insert_ras, 0, PPC_OPERAND_GPR_0 }, + + /* The RA field of the tlbwe instruction, which is optional. */ +#define RAOPT RAS + 1 + { 5, 16, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, /* The RB field in an X, XO, M, or MDS form instruction. */ -#define RB RAS + 1 +#define RB RAOPT + 1 #define RB_MASK (0x1f << 11) { 5, 11, 0, 0, PPC_OPERAND_GPR }, @@ -406,8 +411,22 @@ const struct powerpc_operand powerpc_operands[] = #define RT_MASK (0x1f << 21) { 5, 21, 0, 0, PPC_OPERAND_GPR }, + /* The RS field of the DS form stq instruction, which has special + value restrictions. */ +#define RSQ RS + 1 + { 5, 21, insert_rsq, 0, PPC_OPERAND_GPR_0 }, + + /* The RT field of the DQ form lq instruction, which has special + value restrictions. */ +#define RTQ RSQ + 1 + { 5, 21, insert_rtq, 0, PPC_OPERAND_GPR_0 }, + + /* The RS field of the tlbwe instruction, which is optional. */ +#define RSO RTQ + 1 + { 5, 21, 0, 0, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL }, + /* The SH field in an X or M form instruction. */ -#define SH RS + 1 +#define SH RSO + 1 #define SH_MASK (0x1f << 11) { 5, 11, 0, 0, 0 }, @@ -416,8 +435,12 @@ const struct powerpc_operand powerpc_operands[] = #define SH6_MASK ((0x1f << 11) | (1 << 1)) { 6, 1, insert_sh6, extract_sh6, 0 }, + /* The SH field of the tlbwe instruction, which is optional. */ +#define SHO SH6 + 1 + { 5, 11,0, 0, PPC_OPERAND_OPTIONAL }, + /* The SI field in a D form instruction. */ -#define SI SH6 + 1 +#define SI SHO + 1 { 16, 0, 0, 0, PPC_OPERAND_SIGNED }, /* The SI field in a D form instruction when we accept a wide range @@ -428,6 +451,7 @@ const struct powerpc_operand powerpc_operands[] = /* The SPR field in an XFX form instruction. This is flipped--the lower 5 bits are stored in the upper 5 and vice- versa. */ #define SPR SISIGNOPT + 1 +#define PMR SPR #define SPR_MASK (0x3ff << 11) { 10, 11, insert_spr, extract_spr, 0 }, @@ -472,41 +496,57 @@ const struct powerpc_operand powerpc_operands[] = #define UI U + 1 { 16, 0, 0, 0, 0 }, - /* The VA field in a VA, VX or VXR form instruction. */ + /* The VA field in a VA, VX or VXR form instruction. */ #define VA UI + 1 #define VA_MASK (0x1f << 16) { 5, 16, 0, 0, PPC_OPERAND_VR }, - /* The VB field in a VA, VX or VXR form instruction. */ + /* The VB field in a VA, VX or VXR form instruction. */ #define VB VA + 1 #define VB_MASK (0x1f << 11) { 5, 11, 0, 0, PPC_OPERAND_VR }, - /* The VC field in a VA form instruction. */ + /* The VC field in a VA form instruction. */ #define VC VB + 1 #define VC_MASK (0x1f << 6) { 5, 6, 0, 0, PPC_OPERAND_VR }, - /* The VD or VS field in a VA, VX, VXR or X form instruction. */ + /* The VD or VS field in a VA, VX, VXR or X form instruction. */ #define VD VC + 1 #define VS VD #define VD_MASK (0x1f << 21) { 5, 21, 0, 0, PPC_OPERAND_VR }, - /* The SIMM field in a VX form instruction. */ + /* The SIMM field in a VX form instruction. */ #define SIMM VD + 1 { 5, 16, 0, 0, PPC_OPERAND_SIGNED}, - /* The UIMM field in a VX form instruction. */ + /* The UIMM field in a VX form instruction. */ #define UIMM SIMM + 1 { 5, 16, 0, 0, 0 }, - /* The SHB field in a VA form instruction. */ + /* The SHB field in a VA form instruction. */ #define SHB UIMM + 1 { 4, 6, 0, 0, 0 }, + /* The other UIMM field in a EVX form instruction. */ +#define EVUIMM SHB + 1 + { 5, 11, 0, 0, 0 }, + + /* The other UIMM field in a half word EVX form instruction. */ +#define EVUIMM_2 EVUIMM + 1 + { 32, 11, insert_ev2, extract_ev2, PPC_OPERAND_PARENS }, + + /* The other UIMM field in a word EVX form instruction. */ +#define EVUIMM_4 EVUIMM_2 + 1 + { 32, 11, insert_ev4, extract_ev4, PPC_OPERAND_PARENS }, + + /* The other UIMM field in a double EVX form instruction. */ +#define EVUIMM_8 EVUIMM_4 + 1 + { 32, 11, insert_ev8, extract_ev8, PPC_OPERAND_PARENS }, + /* The WS field. */ -#define WS SHB + 1 +#define WS EVUIMM_8 + 1 #define WS_MASK (0x7 << 11) { 3, 11, 0, 0, 0 }, @@ -524,25 +564,21 @@ const struct powerpc_operand powerpc_operands[] = and the extraction function just checks that the fields are the same. */ -/*ARGSUSED*/ static unsigned long -insert_bat (insn, value, dialect, errmsg) - unsigned long insn; - long value ATTRIBUTE_UNUSED; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; +insert_bat (unsigned long insn, + long value ATTRIBUTE_UNUSED, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { return insn | (((insn >> 21) & 0x1f) << 16); } static long -extract_bat (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid; +extract_bat (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid) { - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) + if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f)) *invalid = 1; return 0; } @@ -553,25 +589,21 @@ extract_bat (insn, dialect, invalid) and the extraction function just checks that the fields are the same. */ -/*ARGSUSED*/ static unsigned long -insert_bba (insn, value, dialect, errmsg) - unsigned long insn; - long value ATTRIBUTE_UNUSED; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; +insert_bba (unsigned long insn, + long value ATTRIBUTE_UNUSED, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { return insn | (((insn >> 16) & 0x1f) << 11); } static long -extract_bba (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid; +extract_bba (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid) { - if (invalid != (int *) NULL - && ((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) + if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f)) *invalid = 1; return 0; } @@ -579,23 +611,19 @@ extract_bba (insn, dialect, invalid) /* The BD field in a B form instruction. The lower two bits are forced to zero. */ -/*ARGSUSED*/ static unsigned long -insert_bd (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; +insert_bd (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { return insn | (value & 0xfffc); } -/*ARGSUSED*/ static long -extract_bd (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid ATTRIBUTE_UNUSED; +extract_bd (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) { return ((insn & 0xfffc) ^ 0x8000) - 0x8000; } @@ -613,13 +641,11 @@ extract_bd (insn, dialect, invalid) in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000 for branch on CTR. We only handle the taken/not-taken hint here. */ -/*ARGSUSED*/ static unsigned long -insert_bdm (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect; - const char **errmsg ATTRIBUTE_UNUSED; +insert_bdm (unsigned long insn, + long value, + int dialect, + const char **errmsg ATTRIBUTE_UNUSED) { if ((dialect & PPC_OPCODE_POWER4) == 0) { @@ -637,25 +663,22 @@ insert_bdm (insn, value, dialect, errmsg) } static long -extract_bdm (insn, dialect, invalid) - unsigned long insn; - int dialect; - int *invalid; +extract_bdm (unsigned long insn, + int dialect, + int *invalid) { - if (invalid != (int *) NULL) + if ((dialect & PPC_OPCODE_POWER4) == 0) { - if ((dialect & PPC_OPCODE_POWER4) == 0) - { - if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) - *invalid = 1; - } - else - { - if ((insn & (0x17 << 21)) != (0x06 << 21) - && (insn & (0x1d << 21)) != (0x18 << 21)) - *invalid = 1; - } + if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0)) + *invalid = 1; + } + else + { + if ((insn & (0x17 << 21)) != (0x06 << 21) + && (insn & (0x1d << 21)) != (0x18 << 21)) + *invalid = 1; } + return ((insn & 0xfffc) ^ 0x8000) - 0x8000; } @@ -663,13 +686,11 @@ extract_bdm (insn, dialect, invalid) This is like BDM, above, except that the branch is expected to be taken. */ -/*ARGSUSED*/ static unsigned long -insert_bdp (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect; - const char **errmsg ATTRIBUTE_UNUSED; +insert_bdp (unsigned long insn, + long value, + int dialect, + const char **errmsg ATTRIBUTE_UNUSED) { if ((dialect & PPC_OPCODE_POWER4) == 0) { @@ -687,34 +708,29 @@ insert_bdp (insn, value, dialect, errmsg) } static long -extract_bdp (insn, dialect, invalid) - unsigned long insn; - int dialect; - int *invalid; +extract_bdp (unsigned long insn, + int dialect, + int *invalid) { - if (invalid != (int *) NULL) + if ((dialect & PPC_OPCODE_POWER4) == 0) { - if ((dialect & PPC_OPCODE_POWER4) == 0) - { - if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) - *invalid = 1; - } - else - { - if ((insn & (0x17 << 21)) != (0x07 << 21) - && (insn & (0x1d << 21)) != (0x19 << 21)) - *invalid = 1; - } + if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0)) + *invalid = 1; + } + else + { + if ((insn & (0x17 << 21)) != (0x07 << 21) + && (insn & (0x1d << 21)) != (0x19 << 21)) + *invalid = 1; } + return ((insn & 0xfffc) ^ 0x8000) - 0x8000; } /* Check for legal values of a BO field. */ static int -valid_bo (value, dialect) - long value; - int dialect; +valid_bo (long value, int dialect) { if ((dialect & PPC_OPCODE_POWER4) == 0) { @@ -766,29 +782,25 @@ valid_bo (value, dialect) the field to an illegal value. */ static unsigned long -insert_bo (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect; - const char **errmsg; +insert_bo (unsigned long insn, + long value, + int dialect, + const char **errmsg) { - if (errmsg != (const char **) NULL - && ! valid_bo (value, dialect)) + if (!valid_bo (value, dialect)) *errmsg = _("invalid conditional option"); return insn | ((value & 0x1f) << 21); } static long -extract_bo (insn, dialect, invalid) - unsigned long insn; - int dialect; - int *invalid; +extract_bo (unsigned long insn, + int dialect, + int *invalid) { long value; value = (insn >> 21) & 0x1f; - if (invalid != (int *) NULL - && ! valid_bo (value, dialect)) + if (!valid_bo (value, dialect)) *invalid = 1; return value; } @@ -798,137 +810,262 @@ extract_bo (insn, dialect, invalid) extracting it, we force it to be even. */ static unsigned long -insert_boe (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect; - const char **errmsg; +insert_boe (unsigned long insn, + long value, + int dialect, + const char **errmsg) { - if (errmsg != (const char **) NULL) - { - if (! valid_bo (value, dialect)) - *errmsg = _("invalid conditional option"); - else if ((value & 1) != 0) - *errmsg = _("attempt to set y bit when using + or - modifier"); - } + if (!valid_bo (value, dialect)) + *errmsg = _("invalid conditional option"); + else if ((value & 1) != 0) + *errmsg = _("attempt to set y bit when using + or - modifier"); + return insn | ((value & 0x1f) << 21); } static long -extract_boe (insn, dialect, invalid) - unsigned long insn; - int dialect; - int *invalid; +extract_boe (unsigned long insn, + int dialect, + int *invalid) { long value; value = (insn >> 21) & 0x1f; - if (invalid != (int *) NULL - && ! valid_bo (value, dialect)) + if (!valid_bo (value, dialect)) *invalid = 1; return value & 0x1e; } +/* The DQ field in a DQ form instruction. This is like D, but the + lower four bits are forced to zero. */ + +static unsigned long +insert_dq (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if ((value & 0xf) != 0) + *errmsg = _("offset not a multiple of 16"); + return insn | (value & 0xfff0); +} + +static long +extract_dq (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return ((insn & 0xfff0) ^ 0x8000) - 0x8000; +} + +static unsigned long +insert_ev2 (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if ((value & 1) != 0) + *errmsg = _("offset not a multiple of 2"); + if ((value > 62) != 0) + *errmsg = _("offset greater than 62"); + return insn | ((value & 0x3e) << 10); +} + +static long +extract_ev2 (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return (insn >> 10) & 0x3e; +} + +static unsigned long +insert_ev4 (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if ((value & 3) != 0) + *errmsg = _("offset not a multiple of 4"); + if ((value > 124) != 0) + *errmsg = _("offset greater than 124"); + return insn | ((value & 0x7c) << 9); +} + +static long +extract_ev4 (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return (insn >> 9) & 0x7c; +} + +static unsigned long +insert_ev8 (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if ((value & 7) != 0) + *errmsg = _("offset not a multiple of 8"); + if ((value > 248) != 0) + *errmsg = _("offset greater than 248"); + return insn | ((value & 0xf8) << 8); +} + +static long +extract_ev8 (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) +{ + return (insn >> 8) & 0xf8; +} + /* The DS field in a DS form instruction. This is like D, but the lower two bits are forced to zero. */ -/*ARGSUSED*/ static unsigned long -insert_ds (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg; +insert_ds (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) { - if ((value & 3) != 0 && errmsg != NULL) + if ((value & 3) != 0) *errmsg = _("offset not a multiple of 4"); return insn | (value & 0xfffc); } -/*ARGSUSED*/ static long -extract_ds (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid ATTRIBUTE_UNUSED; +extract_ds (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) { return ((insn & 0xfffc) ^ 0x8000) - 0x8000; } /* The DE field in a DE form instruction. */ -/*ARGSUSED*/ static unsigned long -insert_de (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg; +insert_de (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) { - if ((value > 2047 || value < -2048) && errmsg != NULL) + if (value > 2047 || value < -2048) *errmsg = _("offset not between -2048 and 2047"); return insn | ((value << 4) & 0xfff0); } -/*ARGSUSED*/ static long -extract_de (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid ATTRIBUTE_UNUSED; +extract_de (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) { return (insn & 0xfff0) >> 4; } /* The DES field in a DES form instruction. */ -/*ARGSUSED*/ static unsigned long -insert_des (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg; +insert_des (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) { - if ((value > 8191 || value < -8192) && errmsg != NULL) + if (value > 8191 || value < -8192) *errmsg = _("offset not between -8192 and 8191"); - else if ((value & 3) != 0 && errmsg != NULL) + else if ((value & 3) != 0) *errmsg = _("offset not a multiple of 4"); return insn | ((value << 2) & 0xfff0); } -/*ARGSUSED*/ static long -extract_des (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid ATTRIBUTE_UNUSED; +extract_des (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) { return (((insn >> 2) & 0x3ffc) ^ 0x2000) - 0x2000; } +/* FXM mask in mfcr and mtcrf instructions. */ + +static unsigned long +insert_fxm (unsigned long insn, + long value, + int dialect, + const char **errmsg) +{ + /* If the optional field on mfcr is missing that means we want to use + the old form of the instruction that moves the whole cr. In that + case we'll have VALUE zero. There doesn't seem to be a way to + distinguish this from the case where someone writes mfcr %r3,0. */ + if (value == 0) + ; + + /* If only one bit of the FXM field is set, we can use the new form + of the instruction, which is faster. Unlike the Power4 branch hint + encoding, this is not backward compatible. */ + else if ((dialect & PPC_OPCODE_POWER4) != 0 && (value & -value) == value) + insn |= 1 << 20; + + /* Any other value on mfcr is an error. */ + else if ((insn & (0x3ff << 1)) == 19 << 1) + { + *errmsg = _("ignoring invalid mfcr mask"); + value = 0; + } + + return insn | ((value & 0xff) << 12); +} + +static long +extract_fxm (unsigned long insn, + int dialect, + int *invalid) +{ + long mask = (insn >> 12) & 0xff; + + /* Is this a Power4 insn? */ + if ((insn & (1 << 20)) != 0) + { + if ((dialect & PPC_OPCODE_POWER4) == 0) + *invalid = 1; + else + { + /* Exactly one bit of MASK should be set. */ + if (mask == 0 || (mask & -mask) != mask) + *invalid = 1; + } + } + + /* Check that non-power4 form of mfcr has a zero MASK. */ + else if ((insn & (0x3ff << 1)) == 19 << 1) + { + if (mask != 0) + *invalid = 1; + } + + return mask; +} + /* The LI field in an I form instruction. The lower two bits are forced to zero. */ -/*ARGSUSED*/ static unsigned long -insert_li (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg; +insert_li (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) { - if ((value & 3) != 0 && errmsg != (const char **) NULL) + if ((value & 3) != 0) *errmsg = _("ignoring least significant bits in branch offset"); return insn | (value & 0x3fffffc); } -/*ARGSUSED*/ static long -extract_li (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid ATTRIBUTE_UNUSED; +extract_li (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) { return ((insn & 0x3fffffc) ^ 0x2000000) - 0x2000000; } @@ -939,11 +1076,10 @@ extract_li (insn, dialect, invalid) instruction which uses a field of this type. */ static unsigned long -insert_mbe (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg; +insert_mbe (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) { unsigned long uval, mask; int mb, me, mx, count, last; @@ -952,8 +1088,7 @@ insert_mbe (insn, value, dialect, errmsg) if (uval == 0) { - if (errmsg != (const char **) NULL) - *errmsg = _("illegal bitmask"); + *errmsg = _("illegal bitmask"); return insn; } @@ -969,7 +1104,7 @@ insert_mbe (insn, value, dialect, errmsg) /* me: location of last 1->0 transition */ /* count: # transitions */ - for (mx = 0, mask = (long) 1 << 31; mx < 32; ++mx, mask >>= 1) + for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1) { if ((uval & mask) && !last) { @@ -988,26 +1123,21 @@ insert_mbe (insn, value, dialect, errmsg) me = 32; if (count != 2 && (count != 0 || ! last)) - { - if (errmsg != (const char **) NULL) - *errmsg = _("illegal bitmask"); - } + *errmsg = _("illegal bitmask"); return insn | (mb << 6) | ((me - 1) << 1); } static long -extract_mbe (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid; +extract_mbe (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid) { long ret; int mb, me; int i; - if (invalid != (int *) NULL) - *invalid = 1; + *invalid = 1; mb = (insn >> 6) & 0x1f; me = (insn >> 1) & 0x1f; @@ -1015,15 +1145,15 @@ extract_mbe (insn, dialect, invalid) { ret = 0; for (i = mb; i <= me; i++) - ret |= (long) 1 << (31 - i); + ret |= 1L << (31 - i); } else if (mb == me + 1) ret = ~0; else /* (mb > me + 1) */ { - ret = ~ (long) 0; + ret = ~0; for (i = me + 1; i < mb; i++) - ret &= ~ ((long) 1 << (31 - i)); + ret &= ~(1L << (31 - i)); } return ret; } @@ -1031,23 +1161,19 @@ extract_mbe (insn, dialect, invalid) /* The MB or ME field in an MD or MDS form instruction. The high bit is wrapped to the low end. */ -/*ARGSUSED*/ static unsigned long -insert_mb6 (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; +insert_mb6 (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { return insn | ((value & 0x1f) << 6) | (value & 0x20); } -/*ARGSUSED*/ static long -extract_mb6 (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid ATTRIBUTE_UNUSED; +extract_mb6 (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) { return ((insn >> 6) & 0x1f) | (insn & 0x20); } @@ -1056,11 +1182,10 @@ extract_mb6 (insn, dialect, invalid) 0. */ static unsigned long -insert_nb (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg; +insert_nb (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) { if (value < 0 || value > 32) *errmsg = _("value out of range"); @@ -1069,12 +1194,10 @@ insert_nb (insn, value, dialect, errmsg) return insn | ((value & 0x1f) << 11); } -/*ARGSUSED*/ static long -extract_nb (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid ATTRIBUTE_UNUSED; +extract_nb (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) { long ret; @@ -1089,26 +1212,22 @@ extract_nb (insn, dialect, invalid) invalid, since we never want to recognize an instruction which uses a field of this type. */ -/*ARGSUSED*/ static unsigned long -insert_nsi (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; +insert_nsi (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { - return insn | ((- value) & 0xffff); + return insn | (-value & 0xffff); } static long -extract_nsi (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid; +extract_nsi (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid) { - if (invalid != (int *) NULL) - *invalid = 1; - return - (((insn & 0xffff) ^ 0x8000) - 0x8000); + *invalid = 1; + return -(((insn & 0xffff) ^ 0x8000) - 0x8000); } /* The RA field in a D or X form instruction which is an updating @@ -1116,11 +1235,10 @@ extract_nsi (insn, dialect, invalid) equal the RT field. */ static unsigned long -insert_ral (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg; +insert_ral (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) { if (value == 0 || (unsigned long) value == ((insn >> 21) & 0x1f)) @@ -1132,27 +1250,41 @@ insert_ral (insn, value, dialect, errmsg) restrictions. */ static unsigned long -insert_ram (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg; +insert_ram (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) { if ((unsigned long) value >= ((insn >> 21) & 0x1f)) *errmsg = _("index register in load range"); return insn | ((value & 0x1f) << 16); } +/* The RA field in the DQ form lq instruction, which has special + value restrictions. */ + +static unsigned long +insert_raq (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + long rtvalue = (insn & RT_MASK) >> 21; + + if (value == rtvalue) + *errmsg = _("source and target register operands must be different"); + return insn | ((value & 0x1f) << 16); +} + /* The RA field in a D or X form instruction which is an updating store or an updating floating point load, which means that the RA field may not be zero. */ static unsigned long -insert_ras (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg; +insert_ras (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) { if (value == 0) *errmsg = _("invalid register operand when updating"); @@ -1165,48 +1297,68 @@ insert_ras (insn, value, dialect, errmsg) function just copies the BT field into the BA field, and the extraction function just checks that the fields are the same. */ -/*ARGSUSED*/ static unsigned long -insert_rbs (insn, value, dialect, errmsg) - unsigned long insn; - long value ATTRIBUTE_UNUSED; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; +insert_rbs (unsigned long insn, + long value ATTRIBUTE_UNUSED, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { return insn | (((insn >> 21) & 0x1f) << 11); } static long -extract_rbs (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid; +extract_rbs (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid) { - if (invalid != (int *) NULL - && ((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) + if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f)) *invalid = 1; return 0; } +/* The RT field of the DQ form lq instruction, which has special + value restrictions. */ + +static unsigned long +insert_rtq (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if ((value & 1) != 0) + *errmsg = _("target register operand must be even"); + return insn | ((value & 0x1f) << 21); +} + +/* The RS field of the DS form stq instruction, which has special + value restrictions. */ + +static unsigned long +insert_rsq (unsigned long insn, + long value ATTRIBUTE_UNUSED, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg) +{ + if ((value & 1) != 0) + *errmsg = _("source register operand must be even"); + return insn | ((value & 0x1f) << 21); +} + /* The SH field in an MD form instruction. This is split. */ -/*ARGSUSED*/ static unsigned long -insert_sh6 (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; +insert_sh6 (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4); } -/*ARGSUSED*/ static long -extract_sh6 (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid ATTRIBUTE_UNUSED; +extract_sh6 (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) { return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20); } @@ -1215,20 +1367,18 @@ extract_sh6 (insn, dialect, invalid) lower 5 bits are stored in the upper 5 and vice- versa. */ static unsigned long -insert_spr (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; +insert_spr (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6); } static long -extract_spr (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid ATTRIBUTE_UNUSED; +extract_spr (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) { return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0); } @@ -1244,11 +1394,10 @@ extract_spr (insn, dialect, invalid) #define TB (268) static unsigned long -insert_tbr (insn, value, dialect, errmsg) - unsigned long insn; - long value; - int dialect ATTRIBUTE_UNUSED; - const char **errmsg ATTRIBUTE_UNUSED; +insert_tbr (unsigned long insn, + long value, + int dialect ATTRIBUTE_UNUSED, + const char **errmsg ATTRIBUTE_UNUSED) { if (value == 0) value = TB; @@ -1256,10 +1405,9 @@ insert_tbr (insn, value, dialect, errmsg) } static long -extract_tbr (insn, dialect, invalid) - unsigned long insn; - int dialect ATTRIBUTE_UNUSED; - int *invalid ATTRIBUTE_UNUSED; +extract_tbr (unsigned long insn, + int dialect ATTRIBUTE_UNUSED, + int *invalid ATTRIBUTE_UNUSED) { long ret; @@ -1332,6 +1480,14 @@ extract_tbr (insn, dialect, invalid) #define BBOYBI_MASK (BBOYCB_MASK | BI_MASK) #define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK) +/* An Context form instruction. */ +#define CTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7)) +#define CTX_MASK CTX(0x3f, 0x7) + +/* An User Context form instruction. */ +#define UCTX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) +#define UCTX_MASK UCTX(0x3f, 0x1f) + /* The main opcode mask with the RA field clear. */ #define DRA_MASK (OP_MASK | RA_MASK) @@ -1343,6 +1499,10 @@ extract_tbr (insn, dialect, invalid) #define DEO(op, xop) (OP (op) | ((xop) & 0xf)) #define DE_MASK DEO (0x3e, 0xf) +/* An EVSEL form instruction. */ +#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3) +#define EVSEL_MASK EVSEL(0x3f, 0xff) + /* An M form instruction. */ #define M(op, rc) (OP (op) | ((rc) & 1)) #define M_MASK M (0x3f, 1) @@ -1377,22 +1537,22 @@ extract_tbr (insn, dialect, invalid) #define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1)) #define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1) -/* An VX form instruction. */ +/* An VX form instruction. */ #define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff)) -/* The mask for an VX form instruction. */ +/* The mask for an VX form instruction. */ #define VX_MASK VX(0x3f, 0x7ff) -/* An VA form instruction. */ +/* An VA form instruction. */ #define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f)) -/* The mask for an VA form instruction. */ +/* The mask for an VA form instruction. */ #define VXA_MASK VXA(0x3f, 0x3f) -/* An VXR form instruction. */ +/* An VXR form instruction. */ #define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff)) -/* The mask for a VXR form instruction. */ +/* The mask for a VXR form instruction. */ #define VXR_MASK VXR(0x3f, 0x3ff, 1) /* An X form instruction. */ @@ -1416,7 +1576,7 @@ extract_tbr (insn, dialect, invalid) /* An X_MASK with the RA and RB fields fixed. */ #define XRARB_MASK (X_MASK | RA_MASK | RB_MASK) -/* An XRARB_MASK, but with the L bit clear. */ +/* An XRARB_MASK, but with the L bit clear. */ #define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16)) /* An X_MASK with the RT and RA fields fixed. */ @@ -1457,6 +1617,10 @@ extract_tbr (insn, dialect, invalid) #define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1)) #define XFL_MASK (XFL (0x3f, 0x3ff, 1) | (((unsigned long)1) << 25) | (((unsigned long)1) << 16)) +/* An X form isel instruction. */ +#define XISEL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1)) +#define XISEL_MASK XISEL(0x3f, 0x1f) + /* An XL form instruction with the LK field set to 0. */ #define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1)) @@ -1506,7 +1670,7 @@ extract_tbr (insn, dialect, invalid) #define XS_MASK XS (0x3f, 0x1ff, 1) /* A mask for the FXM version of an XFX form instruction. */ -#define XFXFXM_MASK (X_MASK | (((unsigned long)1) << 20) | (((unsigned long)1) << 11)) +#define XFXFXM_MASK (X_MASK | (1 << 11)) /* An XFX form instruction with the FXM field filled in. */ #define XFXM(op, xop, fxm) \ @@ -1528,6 +1692,10 @@ extract_tbr (insn, dialect, invalid) /* An X form instruction with everything filled in except the E field. */ #define XE_MASK (0xffff7fff) +/* An X form user context instruction. */ +#define XUC(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x1f)) +#define XUC_MASK XUC(0x3f, 0x1f) + /* The BO encodings used in extended conditional branch mnemonics. */ #define BODNZF (0x0) #define BODNZFP (0x1) @@ -1585,30 +1753,39 @@ extract_tbr (insn, dialect, invalid) /* Smaller names for the flags so each entry in the opcodes table will fit on a single line. */ #undef PPC -#define PPC PPC_OPCODE_PPC | PPC_OPCODE_ANY -#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY +#define PPC PPC_OPCODE_PPC +#define PPCCOM PPC_OPCODE_PPC | PPC_OPCODE_COMMON #define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM -#define POWER4 PPC_OPCODE_POWER4 | PPCCOM -#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC | PPC_OPCODE_ANY -#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC | PPC_OPCODE_ANY -#define PPCONLY PPC_OPCODE_PPC +#define POWER4 PPC_OPCODE_POWER4 +#define PPC32 PPC_OPCODE_32 | PPC_OPCODE_PPC +#define PPC64 PPC_OPCODE_64 | PPC_OPCODE_PPC #define PPC403 PPC_OPCODE_403 #define PPC405 PPC403 +#define PPC440 PPC_OPCODE_440 #define PPC750 PPC #define PPC860 PPC -#define PPCVEC PPC_OPCODE_ALTIVEC | PPC_OPCODE_ANY | PPC_OPCODE_PPC -#define POWER PPC_OPCODE_POWER | PPC_OPCODE_ANY -#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY -#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 | PPC_OPCODE_ANY -#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_ANY | PPC_OPCODE_32 -#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY -#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_ANY | PPC_OPCODE_32 -#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_ANY -#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON | PPC_OPCODE_ANY +#define PPCVEC PPC_OPCODE_ALTIVEC +#define POWER PPC_OPCODE_POWER +#define POWER2 PPC_OPCODE_POWER | PPC_OPCODE_POWER2 +#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2 +#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32 +#define COM PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON +#define COM32 PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32 +#define M601 PPC_OPCODE_POWER | PPC_OPCODE_601 +#define PWRCOM PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON #define MFDEC1 PPC_OPCODE_POWER -#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 +#define MFDEC2 PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE #define BOOKE PPC_OPCODE_BOOKE #define BOOKE64 PPC_OPCODE_BOOKE64 +#define CLASSIC PPC_OPCODE_CLASSIC +#define PPCSPE PPC_OPCODE_SPE +#define PPCISEL PPC_OPCODE_ISEL +#define PPCEFS PPC_OPCODE_EFS +#define PPCBRLK PPC_OPCODE_BRLOCK +#define PPCPMR PPC_OPCODE_PMR +#define PPCCHLK PPC_OPCODE_CACHELCK +#define PPCCHLK64 PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64 +#define PPCRFMCI PPC_OPCODE_RFMCI /* The opcode table. @@ -1629,6 +1806,7 @@ extract_tbr (insn, dialect, invalid) sorted by major opcode. */ const struct powerpc_opcode powerpc_opcodes[] = { +{ "attn", X(0,256), X_MASK, POWER4, { 0 } }, { "tdlgti", OPTO(2,TOLGT), OPTO_MASK, PPC64, { RA, SI } }, { "tdllti", OPTO(2,TOLLT), OPTO_MASK, PPC64, { RA, SI } }, { "tdeqi", OPTO(2,TOEQ), OPTO_MASK, PPC64, { RA, SI } }, @@ -1676,90 +1854,90 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "twi", OP(3), OP_MASK, PPCCOM, { TO, RA, SI } }, { "ti", OP(3), OP_MASK, PWRCOM, { TO, RA, SI } }, -{ "macchw", XO(4,172,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchws", XO(4,236,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhw", XO(4,44,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhws", XO(4,108,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "mulchw", XRC(4,168,0), X_MASK, PPC405, { RT, RA, RB } }, -{ "mulchw.", XRC(4,168,1), X_MASK, PPC405, { RT, RA, RB } }, -{ "mulchwu", XRC(4,136,0), X_MASK, PPC405, { RT, RA, RB } }, -{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405, { RT, RA, RB } }, -{ "mulhhw", XRC(4,40,0), X_MASK, PPC405, { RT, RA, RB } }, -{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405, { RT, RA, RB } }, -{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405, { RT, RA, RB } }, -{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405, { RT, RA, RB } }, -{ "mullhw", XRC(4,424,0), X_MASK, PPC405, { RT, RA, RB } }, -{ "mullhw.", XRC(4,424,1), X_MASK, PPC405, { RT, RA, RB } }, -{ "mullhwu", XRC(4,392,0), X_MASK, PPC405, { RT, RA, RB } }, -{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405, { RT, RA, RB } }, -{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405, { RT, RA, RB } }, +{ "macchw", XO(4,172,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchw.", XO(4,172,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwo", XO(4,172,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwo.", XO(4,172,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchws", XO(4,236,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchws.", XO(4,236,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwso", XO(4,236,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwso.", XO(4,236,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwsu", XO(4,204,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwsu.", XO(4,204,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwsuo", XO(4,204,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwu", XO(4,140,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwu.", XO(4,140,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwuo", XO(4,140,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "macchwuo.", XO(4,140,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhw", XO(4,44,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhw.", XO(4,44,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwo", XO(4,44,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwo.", XO(4,44,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhws", XO(4,108,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhws.", XO(4,108,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwso", XO(4,108,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwso.", XO(4,108,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwsu", XO(4,76,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwsu.", XO(4,76,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwsuo", XO(4,76,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwsuo.", XO(4,76,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwu", XO(4,12,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwu.", XO(4,12,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwuo", XO(4,12,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "machhwuo.", XO(4,12,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhw", XO(4,428,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhw.", XO(4,428,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwo", XO(4,428,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwo.", XO(4,428,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhws", XO(4,492,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhws.", XO(4,492,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwso", XO(4,492,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwso.", XO(4,492,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwsu", XO(4,460,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwsu.", XO(4,460,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwsuo", XO(4,460,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwu", XO(4,396,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwu.", XO(4,396,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwuo", XO(4,396,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "maclhwuo.", XO(4,396,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulchw", XRC(4,168,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulchw.", XRC(4,168,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulchwu", XRC(4,136,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulchwu.", XRC(4,136,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulhhw", XRC(4,40,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulhhw.", XRC(4,40,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulhhwu", XRC(4,8,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mulhhwu.", XRC(4,8,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mullhw", XRC(4,424,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mullhw.", XRC(4,424,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mullhwu", XRC(4,392,0), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "mullhwu.", XRC(4,392,1), X_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchw", XO(4,174,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchw.", XO(4,174,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchwo", XO(4,174,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchwo.", XO(4,174,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchws", XO(4,238,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchws.", XO(4,238,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchwso", XO(4,238,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhw", XO(4,46,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhw.", XO(4,46,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhwo", XO(4,46,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhwo.", XO(4,46,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhws", XO(4,110,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhws.", XO(4,110,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhwso", XO(4,110,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhw", XO(4,430,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhw.", XO(4,430,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhwo", XO(4,430,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhwo.", XO(4,430,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhws", XO(4,494,0,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhws.", XO(4,494,0,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhwso", XO(4,494,1,0), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, +{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440, { RT, RA, RB } }, { "mfvscr", VX(4, 1540), VX_MASK, PPCVEC, { VD } }, { "mtvscr", VX(4, 1604), VX_MASK, PPCVEC, { VB } }, { "vaddcuw", VX(4, 384), VX_MASK, PPCVEC, { VD, VA, VB } }, @@ -1918,6 +2096,254 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "vupklsh", VX(4, 718), VX_MASK, PPCVEC, { VD, VB } }, { "vxor", VX(4, 1220), VX_MASK, PPCVEC, { VD, VA, VB } }, +{ "evaddw", VX(4, 512), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evaddiw", VX(4, 514), VX_MASK, PPCSPE, { RS, RB, UIMM } }, +{ "evsubfw", VX(4, 516), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evsubw", VX(4, 516), VX_MASK, PPCSPE, { RS, RB, RA } }, +{ "evsubifw", VX(4, 518), VX_MASK, PPCSPE, { RS, UIMM, RB } }, +{ "evsubiw", VX(4, 518), VX_MASK, PPCSPE, { RS, RB, UIMM } }, +{ "evabs", VX(4, 520), VX_MASK, PPCSPE, { RS, RA } }, +{ "evneg", VX(4, 521), VX_MASK, PPCSPE, { RS, RA } }, +{ "evextsb", VX(4, 522), VX_MASK, PPCSPE, { RS, RA } }, +{ "evextsh", VX(4, 523), VX_MASK, PPCSPE, { RS, RA } }, +{ "evrndw", VX(4, 524), VX_MASK, PPCSPE, { RS, RA } }, +{ "evcntlzw", VX(4, 525), VX_MASK, PPCSPE, { RS, RA } }, +{ "evcntlsw", VX(4, 526), VX_MASK, PPCSPE, { RS, RA } }, + +{ "brinc", VX(4, 527), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evand", VX(4, 529), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evandc", VX(4, 530), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmr", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, BBA } }, +{ "evor", VX(4, 535), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evorc", VX(4, 539), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evxor", VX(4, 534), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "eveqv", VX(4, 537), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evnand", VX(4, 542), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evnot", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, BBA } }, +{ "evnor", VX(4, 536), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evrlw", VX(4, 552), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evrlwi", VX(4, 554), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, +{ "evslw", VX(4, 548), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evslwi", VX(4, 550), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, +{ "evsrws", VX(4, 545), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evsrwu", VX(4, 544), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evsrwis", VX(4, 547), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, +{ "evsrwiu", VX(4, 546), VX_MASK, PPCSPE, { RS, RA, EVUIMM } }, +{ "evsplati", VX(4, 553), VX_MASK, PPCSPE, { RS, SIMM } }, +{ "evsplatfi", VX(4, 555), VX_MASK, PPCSPE, { RS, SIMM } }, +{ "evmergehi", VX(4, 556), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmergelo", VX(4, 557), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmergehilo",VX(4,558), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmergelohi",VX(4,559), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evcmpgts", VX(4, 561), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evcmpgtu", VX(4, 560), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evcmplts", VX(4, 563), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evcmpltu", VX(4, 562), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evcmpeq", VX(4, 564), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evsel", EVSEL(4,79),EVSEL_MASK, PPCSPE, { RS, RA, RB, CRFS } }, + +{ "evldd", VX(4, 769), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, +{ "evlddx", VX(4, 768), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evldw", VX(4, 771), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, +{ "evldwx", VX(4, 770), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evldh", VX(4, 773), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, +{ "evldhx", VX(4, 772), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlwhe", VX(4, 785), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evlwhex", VX(4, 784), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlwhou", VX(4, 789), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evlwhoux", VX(4, 788), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlwhos", VX(4, 791), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evlwhosx", VX(4, 790), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlwwsplat",VX(4, 793), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evlwwsplatx",VX(4, 792), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlwhsplat",VX(4, 797), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evlwhsplatx",VX(4, 796), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlhhesplat",VX(4, 777), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, +{ "evlhhesplatx",VX(4, 776), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlhhousplat",VX(4, 781), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, +{ "evlhhousplatx",VX(4, 780), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evlhhossplat",VX(4, 783), VX_MASK, PPCSPE, { RS, EVUIMM_2, RA } }, +{ "evlhhossplatx",VX(4, 782), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evstdd", VX(4, 801), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, +{ "evstddx", VX(4, 800), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evstdw", VX(4, 803), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, +{ "evstdwx", VX(4, 802), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evstdh", VX(4, 805), VX_MASK, PPCSPE, { RS, EVUIMM_8, RA } }, +{ "evstdhx", VX(4, 804), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evstwwe", VX(4, 825), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evstwwex", VX(4, 824), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evstwwo", VX(4, 829), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evstwwox", VX(4, 828), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evstwhe", VX(4, 817), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evstwhex", VX(4, 816), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evstwho", VX(4, 821), VX_MASK, PPCSPE, { RS, EVUIMM_4, RA } }, +{ "evstwhox", VX(4, 820), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evfsabs", VX(4, 644), VX_MASK, PPCSPE, { RS, RA } }, +{ "evfsnabs", VX(4, 645), VX_MASK, PPCSPE, { RS, RA } }, +{ "evfsneg", VX(4, 646), VX_MASK, PPCSPE, { RS, RA } }, +{ "evfsadd", VX(4, 640), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evfssub", VX(4, 641), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evfsmul", VX(4, 648), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evfsdiv", VX(4, 649), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evfscmpgt", VX(4, 652), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evfscmplt", VX(4, 653), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evfscmpeq", VX(4, 654), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evfststgt", VX(4, 668), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evfststlt", VX(4, 669), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evfststeq", VX(4, 670), VX_MASK, PPCSPE, { CRFD, RA, RB } }, +{ "evfscfui", VX(4, 656), VX_MASK, PPCSPE, { RS, RB } }, +{ "evfsctuiz", VX(4, 664), VX_MASK, PPCSPE, { RS, RB } }, +{ "evfscfsi", VX(4, 657), VX_MASK, PPCSPE, { RS, RB } }, +{ "evfscfuf", VX(4, 658), VX_MASK, PPCSPE, { RS, RB } }, +{ "evfscfsf", VX(4, 659), VX_MASK, PPCSPE, { RS, RB } }, +{ "evfsctui", VX(4, 660), VX_MASK, PPCSPE, { RS, RB } }, +{ "evfsctsi", VX(4, 661), VX_MASK, PPCSPE, { RS, RB } }, +{ "evfsctsiz", VX(4, 666), VX_MASK, PPCSPE, { RS, RB } }, +{ "evfsctuf", VX(4, 662), VX_MASK, PPCSPE, { RS, RB } }, +{ "evfsctsf", VX(4, 663), VX_MASK, PPCSPE, { RS, RB } }, + +{ "efsabs", VX(4, 708), VX_MASK, PPCEFS, { RS, RA } }, +{ "efsnabs", VX(4, 709), VX_MASK, PPCEFS, { RS, RA } }, +{ "efsneg", VX(4, 710), VX_MASK, PPCEFS, { RS, RA } }, +{ "efsadd", VX(4, 704), VX_MASK, PPCEFS, { RS, RA, RB } }, +{ "efssub", VX(4, 705), VX_MASK, PPCEFS, { RS, RA, RB } }, +{ "efsmul", VX(4, 712), VX_MASK, PPCEFS, { RS, RA, RB } }, +{ "efsdiv", VX(4, 713), VX_MASK, PPCEFS, { RS, RA, RB } }, +{ "efscmpgt", VX(4, 716), VX_MASK, PPCEFS, { CRFD, RA, RB } }, +{ "efscmplt", VX(4, 717), VX_MASK, PPCEFS, { CRFD, RA, RB } }, +{ "efscmpeq", VX(4, 718), VX_MASK, PPCEFS, { CRFD, RA, RB } }, +{ "efststgt", VX(4, 732), VX_MASK, PPCEFS, { CRFD, RA, RB } }, +{ "efststlt", VX(4, 733), VX_MASK, PPCEFS, { CRFD, RA, RB } }, +{ "efststeq", VX(4, 734), VX_MASK, PPCEFS, { CRFD, RA, RB } }, +{ "efscfui", VX(4, 720), VX_MASK, PPCEFS, { RS, RB } }, +{ "efsctuiz", VX(4, 728), VX_MASK, PPCEFS, { RS, RB } }, +{ "efscfsi", VX(4, 721), VX_MASK, PPCEFS, { RS, RB } }, +{ "efscfuf", VX(4, 722), VX_MASK, PPCEFS, { RS, RB } }, +{ "efscfsf", VX(4, 723), VX_MASK, PPCEFS, { RS, RB } }, +{ "efsctui", VX(4, 724), VX_MASK, PPCEFS, { RS, RB } }, +{ "efsctsi", VX(4, 725), VX_MASK, PPCEFS, { RS, RB } }, +{ "efsctsiz", VX(4, 730), VX_MASK, PPCEFS, { RS, RB } }, +{ "efsctuf", VX(4, 726), VX_MASK, PPCEFS, { RS, RB } }, +{ "efsctsf", VX(4, 727), VX_MASK, PPCEFS, { RS, RB } }, + +{ "evmhossf", VX(4, 1031), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhossfa", VX(4, 1063), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhosmf", VX(4, 1039), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhosmfa", VX(4, 1071), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhosmi", VX(4, 1037), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhosmia", VX(4, 1069), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhoumi", VX(4, 1036), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhoumia", VX(4, 1068), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhessf", VX(4, 1027), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhessfa", VX(4, 1059), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhesmf", VX(4, 1035), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhesmfa", VX(4, 1067), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhesmi", VX(4, 1033), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhesmia", VX(4, 1065), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmheumi", VX(4, 1032), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmheumia", VX(4, 1064), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evmhossfaaw",VX(4, 1287), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhossiaaw",VX(4, 1285), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhosmfaaw",VX(4, 1295), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhosmiaaw",VX(4, 1293), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhousiaaw",VX(4, 1284), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhoumiaaw",VX(4, 1292), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhessfaaw",VX(4, 1283), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhessiaaw",VX(4, 1281), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhesmfaaw",VX(4, 1291), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhesmiaaw",VX(4, 1289), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmheusiaaw",VX(4, 1280), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmheumiaaw",VX(4, 1288), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evmhossfanw",VX(4, 1415), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhossianw",VX(4, 1413), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhosmfanw",VX(4, 1423), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhosmianw",VX(4, 1421), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhousianw",VX(4, 1412), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhoumianw",VX(4, 1420), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhessfanw",VX(4, 1411), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhessianw",VX(4, 1409), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhesmfanw",VX(4, 1419), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhesmianw",VX(4, 1417), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmheusianw",VX(4, 1408), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmheumianw",VX(4, 1416), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evmhogsmfaa",VX(4, 1327), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhogsmiaa",VX(4, 1325), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhogumiaa",VX(4, 1324), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhegsmfaa",VX(4, 1323), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhegsmiaa",VX(4, 1321), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhegumiaa",VX(4, 1320), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evmhogsmfan",VX(4, 1455), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhogsmian",VX(4, 1453), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhogumian",VX(4, 1452), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhegsmfan",VX(4, 1451), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhegsmian",VX(4, 1449), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmhegumian",VX(4, 1448), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evmwhssf", VX(4, 1095), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwhssfa", VX(4, 1127), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwhsmf", VX(4, 1103), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwhsmfa", VX(4, 1135), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwhsmi", VX(4, 1101), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwhsmia", VX(4, 1133), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwhumi", VX(4, 1100), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwhumia", VX(4, 1132), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evmwlumi", VX(4, 1096), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwlumia", VX(4, 1128), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evmwlssiaaw",VX(4, 1345), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwlsmiaaw",VX(4, 1353), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwlusiaaw",VX(4, 1344), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwlumiaaw",VX(4, 1352), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evmwlssianw",VX(4, 1473), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwlsmianw",VX(4, 1481), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwlusianw",VX(4, 1472), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwlumianw",VX(4, 1480), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evmwssf", VX(4, 1107), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwssfa", VX(4, 1139), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwsmf", VX(4, 1115), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwsmfa", VX(4, 1147), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwsmi", VX(4, 1113), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwsmia", VX(4, 1145), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwumi", VX(4, 1112), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwumia", VX(4, 1144), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evmwssfaa", VX(4, 1363), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwsmfaa", VX(4, 1371), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwsmiaa", VX(4, 1369), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwumiaa", VX(4, 1368), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evmwssfan", VX(4, 1491), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwsmfan", VX(4, 1499), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwsmian", VX(4, 1497), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evmwumian", VX(4, 1496), VX_MASK, PPCSPE, { RS, RA, RB } }, + +{ "evaddssiaaw",VX(4, 1217), VX_MASK, PPCSPE, { RS, RA } }, +{ "evaddsmiaaw",VX(4, 1225), VX_MASK, PPCSPE, { RS, RA } }, +{ "evaddusiaaw",VX(4, 1216), VX_MASK, PPCSPE, { RS, RA } }, +{ "evaddumiaaw",VX(4, 1224), VX_MASK, PPCSPE, { RS, RA } }, + +{ "evsubfssiaaw",VX(4, 1219), VX_MASK, PPCSPE, { RS, RA } }, +{ "evsubfsmiaaw",VX(4, 1227), VX_MASK, PPCSPE, { RS, RA } }, +{ "evsubfusiaaw",VX(4, 1218), VX_MASK, PPCSPE, { RS, RA } }, +{ "evsubfumiaaw",VX(4, 1226), VX_MASK, PPCSPE, { RS, RA } }, + +{ "evmra", VX(4, 1220), VX_MASK, PPCSPE, { RS, RA } }, + +{ "evdivws", VX(4, 1222), VX_MASK, PPCSPE, { RS, RA, RB } }, +{ "evdivwu", VX(4, 1223), VX_MASK, PPCSPE, { RS, RA, RB } }, + { "mulli", OP(7), OP_MASK, PPCCOM, { RT, RA, SI } }, { "muli", OP(7), OP_MASK, PWRCOM, { RT, RA, SI } }, @@ -1933,12 +2359,12 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "cmplwi", OPL(10,0), OPL_MASK, PPCCOM, { OBF, RA, UI } }, { "cmpldi", OPL(10,1), OPL_MASK, PPC64, { OBF, RA, UI } }, -{ "cmpli", OP(10), OP_MASK, PPCONLY, { BF, L, RA, UI } }, +{ "cmpli", OP(10), OP_MASK, PPC, { BF, L, RA, UI } }, { "cmpli", OP(10), OP_MASK, PWRCOM, { BF, RA, UI } }, { "cmpwi", OPL(11,0), OPL_MASK, PPCCOM, { OBF, RA, SI } }, { "cmpdi", OPL(11,1), OPL_MASK, PPC64, { OBF, RA, SI } }, -{ "cmpi", OP(11), OP_MASK, PPCONLY, { BF, L, RA, SI } }, +{ "cmpi", OP(11), OP_MASK, PPC, { BF, L, RA, SI } }, { "cmpi", OP(11), OP_MASK, PWRCOM, { BF, RA, SI } }, { "addic", OP(12), OP_MASK, PPCCOM, { RT, RA, SI } }, @@ -1951,45 +2377,45 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "li", OP(14), DRA_MASK, PPCCOM, { RT, SI } }, { "lil", OP(14), DRA_MASK, PWRCOM, { RT, SI } }, -{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA, SI } }, -{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA } }, -{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA, NSI } }, -{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA } }, +{ "addi", OP(14), OP_MASK, PPCCOM, { RT, RA0, SI } }, +{ "cal", OP(14), OP_MASK, PWRCOM, { RT, D, RA0 } }, +{ "subi", OP(14), OP_MASK, PPCCOM, { RT, RA0, NSI } }, +{ "la", OP(14), OP_MASK, PPCCOM, { RT, D, RA0 } }, { "lis", OP(15), DRA_MASK, PPCCOM, { RT, SISIGNOPT } }, { "liu", OP(15), DRA_MASK, PWRCOM, { RT, SISIGNOPT } }, -{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA,SISIGNOPT } }, -{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA,SISIGNOPT } }, -{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA, NSI } }, - -{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, -{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, -{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } }, -{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } }, -{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, -{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, -{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } }, -{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } }, -{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, -{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, -{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } }, -{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } }, -{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, -{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, -{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } }, -{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } }, -{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, -{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, -{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } }, -{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, -{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, -{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } }, -{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, -{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, -{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } }, -{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, -{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, -{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } }, +{ "addis", OP(15), OP_MASK, PPCCOM, { RT,RA0,SISIGNOPT } }, +{ "cau", OP(15), OP_MASK, PWRCOM, { RT,RA0,SISIGNOPT } }, +{ "subis", OP(15), OP_MASK, PPCCOM, { RT, RA0, NSI } }, + +{ "bdnz-", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, +{ "bdnz+", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, +{ "bdnz", BBO(16,BODNZ,0,0), BBOATBI_MASK, PPCCOM, { BD } }, +{ "bdn", BBO(16,BODNZ,0,0), BBOATBI_MASK, PWRCOM, { BD } }, +{ "bdnzl-", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, +{ "bdnzl+", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, +{ "bdnzl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PPCCOM, { BD } }, +{ "bdnl", BBO(16,BODNZ,0,1), BBOATBI_MASK, PWRCOM, { BD } }, +{ "bdnza-", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, +{ "bdnza+", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, +{ "bdnza", BBO(16,BODNZ,1,0), BBOATBI_MASK, PPCCOM, { BDA } }, +{ "bdna", BBO(16,BODNZ,1,0), BBOATBI_MASK, PWRCOM, { BDA } }, +{ "bdnzla-", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, +{ "bdnzla+", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, +{ "bdnzla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PPCCOM, { BDA } }, +{ "bdnla", BBO(16,BODNZ,1,1), BBOATBI_MASK, PWRCOM, { BDA } }, +{ "bdz-", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDM } }, +{ "bdz+", BBO(16,BODZ,0,0), BBOATBI_MASK, PPCCOM, { BDP } }, +{ "bdz", BBO(16,BODZ,0,0), BBOATBI_MASK, COM, { BD } }, +{ "bdzl-", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDM } }, +{ "bdzl+", BBO(16,BODZ,0,1), BBOATBI_MASK, PPCCOM, { BDP } }, +{ "bdzl", BBO(16,BODZ,0,1), BBOATBI_MASK, COM, { BD } }, +{ "bdza-", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDMA } }, +{ "bdza+", BBO(16,BODZ,1,0), BBOATBI_MASK, PPCCOM, { BDPA } }, +{ "bdza", BBO(16,BODZ,1,0), BBOATBI_MASK, COM, { BDA } }, +{ "bdzla-", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDMA } }, +{ "bdzla+", BBO(16,BODZ,1,1), BBOATBI_MASK, PPCCOM, { BDPA } }, +{ "bdzla", BBO(16,BODZ,1,1), BBOATBI_MASK, COM, { BDA } }, { "blt-", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDM } }, { "blt+", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM, { CR, BDP } }, { "blt", BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM, { CR, BD } }, @@ -2238,7 +2664,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "ba", B(18,1,0), B_MASK, COM, { LIA } }, { "bla", B(18,1,1), B_MASK, COM, { LIA } }, -{ "mcrf", XL(19,0), XLBB_MASK|(3<<21)|(3<<16), COM, { BF, BFA } }, +{ "mcrf", XL(19,0), XLBB_MASK|(3 << 21)|(3 << 16), COM, { BF, BFA } }, { "blr", XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, { "br", XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM, { 0 } }, @@ -2246,186 +2672,186 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "brl", XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM, { 0 } }, { "bdnzlr", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, { "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, { "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, { "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, { "bdzlr", XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } }, { "bdzlr-", XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdzlr-", XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdzlr+", XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdzlr+", XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4, { 0 } }, { "bdzlrl", XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } }, { "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, -{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, +{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4, { 0 } }, { "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4, { 0 } }, { "bltlr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bltlr-", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltlr-", XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltlr+", XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltlr+", XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bltr", XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bltlrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bltrl", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bgtlr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgtlr-", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtlr-", XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtlr+", XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtlr+", XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bgtr", XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bgtlrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bgtrl", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "beqlr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "beqlr-", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqlr-", XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqlr+", XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqlr+", XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "beqr", XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "beqlrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "beqrl", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bsolr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bsolr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsolr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsolr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsolr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bsor", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bsolrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bsorl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bunlr", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bunlr-", XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunlr-", XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunlr+", XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunlr+", XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bunlrl", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bgelr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgelr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgelr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgelr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgelr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bger", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bgelrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bgerl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnllr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnllr-", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnllr-", XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnllr+", XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnllr+", XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bnlr", XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnllrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnllrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnllrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnllrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnllrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bnlrl", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "blelr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "blelr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blelr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blelr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blelr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bler", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "blelrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "blelrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blelrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blelrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blelrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "blerl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnglr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnglr-", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnglr-", XLOCB(19,BOFM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnglr+", XLOCB(19,BOFP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnglr+", XLOCB(19,BOFP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bngr", XLOCB(19,BOF,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnglrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnglrl-", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnglrl-", XLOCB(19,BOFM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnglrl+", XLOCB(19,BOFP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnglrl+", XLOCB(19,BOFP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bngrl", XLOCB(19,BOF,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnelr", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnelr-", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnelr-", XLOCB(19,BOFM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnelr+", XLOCB(19,BOFP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnelr+", XLOCB(19,BOFP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bner", XLOCB(19,BOF,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnelrl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnelrl-", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnelrl-", XLOCB(19,BOFM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnelrl+", XLOCB(19,BOFP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnelrl+", XLOCB(19,BOFP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bnerl", XLOCB(19,BOF,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnslr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnslr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnslr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnslr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnslr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bnsr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnslrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnslrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnslrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnslrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnslrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bnsrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } }, { "bnulr", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnulr-", XLOCB(19,BOF,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnulr-", XLOCB(19,BOFM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnulr+", XLOCB(19,BOFP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnulr+", XLOCB(19,BOFP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bnulrl", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnulrl-", XLOCB(19,BOF,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnulrl-", XLOCB(19,BOFM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnulrl+", XLOCB(19,BOFP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnulrl+", XLOCB(19,BOFP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } }, { "btlr", XLO(19,BOT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, { "btlr-", XLO(19,BOT,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "btlr-", XLO(19,BOTM4,16,0), XLBOBB_MASK, POWER4, { BI } }, +{ "btlr+", XLO(19,BOTP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "btlr+", XLO(19,BOTP4,16,0), XLBOBB_MASK, POWER4, { BI } }, { "bbtr", XLO(19,BOT,16,0), XLBOBB_MASK, PWRCOM, { BI } }, { "btlrl", XLO(19,BOT,16,1), XLBOBB_MASK, PPCCOM, { BI } }, { "btlrl-", XLO(19,BOT,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "btlrl-", XLO(19,BOTM4,16,1), XLBOBB_MASK, POWER4, { BI } }, +{ "btlrl+", XLO(19,BOTP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "btlrl+", XLO(19,BOTP4,16,1), XLBOBB_MASK, POWER4, { BI } }, { "bbtrl", XLO(19,BOT,16,1), XLBOBB_MASK, PWRCOM, { BI } }, { "bflr", XLO(19,BOF,16,0), XLBOBB_MASK, PPCCOM, { BI } }, { "bflr-", XLO(19,BOF,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "bflr-", XLO(19,BOFM4,16,0), XLBOBB_MASK, POWER4, { BI } }, +{ "bflr+", XLO(19,BOFP,16,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "bflr+", XLO(19,BOFP4,16,0), XLBOBB_MASK, POWER4, { BI } }, { "bbfr", XLO(19,BOF,16,0), XLBOBB_MASK, PWRCOM, { BI } }, { "bflrl", XLO(19,BOF,16,1), XLBOBB_MASK, PPCCOM, { BI } }, { "bflrl-", XLO(19,BOF,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "bflrl-", XLO(19,BOFM4,16,1), XLBOBB_MASK, POWER4, { BI } }, +{ "bflrl+", XLO(19,BOFP,16,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "bflrl+", XLO(19,BOFP4,16,1), XLBOBB_MASK, POWER4, { BI } }, { "bbfrl", XLO(19,BOF,16,1), XLBOBB_MASK, PWRCOM, { BI } }, { "bdnztlr", XLO(19,BODNZT,16,0), XLBOBB_MASK, PPCCOM, { BI } }, @@ -2467,10 +2893,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "crnot", XL(19,33), XL_MASK, PPCCOM, { BT, BA, BBA } }, { "crnor", XL(19,33), XL_MASK, COM, { BT, BA, BB } }, +{ "rfmci", X(19,38), 0xffffffff, PPCRFMCI, { 0 } }, { "rfi", XL(19,50), 0xffffffff, COM, { 0 } }, -{ "rfci", XL(19,51), 0xffffffff, PPC403, { 0 } }, -{ "rfci", XL(19,51), 0xffffffff, BOOKE, { 0 } }, +{ "rfci", XL(19,51), 0xffffffff, PPC403 | BOOKE, { 0 } }, { "rfsvc", XL(19,82), 0xffffffff, POWER, { 0 } }, @@ -2498,143 +2924,143 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "bctrl", XLO(19,BOU,528,1), XLBOBIBB_MASK, COM, { 0 } }, { "bltctr", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bltctr-", XLOCB(19,BOT,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltctr-", XLOCB(19,BOTM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltctr+", XLOCB(19,BOTP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltctr+", XLOCB(19,BOTP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bltctrl", XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bltctrl-",XLOCB(19,BOT,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltctrl-",XLOCB(19,BOTM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bltctrl+",XLOCB(19,BOTP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bltctrl+",XLOCB(19,BOTP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bgtctr", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgtctr-", XLOCB(19,BOT,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtctr-", XLOCB(19,BOTM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtctr+", XLOCB(19,BOTP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtctr+", XLOCB(19,BOTP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bgtctrl", XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgtctrl-",XLOCB(19,BOT,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtctrl-",XLOCB(19,BOTM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgtctrl+",XLOCB(19,BOTP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgtctrl+",XLOCB(19,BOTP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "beqctr", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "beqctr-", XLOCB(19,BOT,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqctr-", XLOCB(19,BOTM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqctr+", XLOCB(19,BOTP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqctr+", XLOCB(19,BOTP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "beqctrl", XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "beqctrl-",XLOCB(19,BOT,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqctrl-",XLOCB(19,BOTM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "beqctrl+",XLOCB(19,BOTP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "beqctrl+",XLOCB(19,BOTP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bsoctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bsoctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsoctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsoctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsoctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bsoctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bsoctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsoctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bsoctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bsoctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bunctr", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bunctr-", XLOCB(19,BOT,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunctr-", XLOCB(19,BOTM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunctr+", XLOCB(19,BOTP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunctr+", XLOCB(19,BOTP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bunctrl", XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bunctrl-",XLOCB(19,BOT,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunctrl-",XLOCB(19,BOTM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bunctrl+",XLOCB(19,BOTP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bunctrl+",XLOCB(19,BOTP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bgectr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgectr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgectr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgectr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgectr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bgectrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bgectrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgectrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bgectrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bgectrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bnlctr", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnlctr-", XLOCB(19,BOF,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnlctr-", XLOCB(19,BOFM4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnlctr+", XLOCB(19,BOFP,CBLT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnlctr+", XLOCB(19,BOFP4,CBLT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bnlctrl", XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnlctrl-",XLOCB(19,BOF,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnlctrl-",XLOCB(19,BOFM4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnlctrl+",XLOCB(19,BOFP,CBLT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnlctrl+",XLOCB(19,BOFP4,CBLT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "blectr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "blectr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blectr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blectr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blectr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "blectrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "blectrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blectrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "blectrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "blectrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bngctr", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bngctr-", XLOCB(19,BOF,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bngctr-", XLOCB(19,BOFM4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bngctr+", XLOCB(19,BOFP,CBGT,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bngctr+", XLOCB(19,BOFP4,CBGT,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bngctrl", XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bngctrl-",XLOCB(19,BOF,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bngctrl-",XLOCB(19,BOFM4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bngctrl+",XLOCB(19,BOFP,CBGT,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bngctrl+",XLOCB(19,BOFP4,CBGT,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bnectr", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnectr-", XLOCB(19,BOF,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnectr-", XLOCB(19,BOFM4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnectr+", XLOCB(19,BOFP,CBEQ,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnectr+", XLOCB(19,BOFP4,CBEQ,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bnectrl", XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnectrl-",XLOCB(19,BOF,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnectrl-",XLOCB(19,BOFM4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnectrl+",XLOCB(19,BOFP,CBEQ,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnectrl+",XLOCB(19,BOFP4,CBEQ,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bnsctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnsctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnsctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnsctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnsctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bnsctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnsctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnsctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnsctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnsctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "bnuctr", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnuctr-", XLOCB(19,BOF,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnuctr-", XLOCB(19,BOFM4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnuctr+", XLOCB(19,BOFP,CBSO,528,0), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnuctr+", XLOCB(19,BOFP4,CBSO,528,0), XLBOCBBB_MASK, POWER4, { CR } }, { "bnuctrl", XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, PPCCOM, { CR } }, { "bnuctrl-",XLOCB(19,BOF,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, -{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnuctrl-",XLOCB(19,BOFM4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, +{ "bnuctrl+",XLOCB(19,BOFP,CBSO,528,1), XLBOCBBB_MASK, NOPOWER4, { CR } }, { "bnuctrl+",XLOCB(19,BOFP4,CBSO,528,1), XLBOCBBB_MASK, POWER4, { CR } }, { "btctr", XLO(19,BOT,528,0), XLBOBB_MASK, PPCCOM, { BI } }, { "btctr-", XLO(19,BOT,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "btctr-", XLO(19,BOTM4,528,0), XLBOBB_MASK, POWER4, { BI } }, +{ "btctr+", XLO(19,BOTP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "btctr+", XLO(19,BOTP4,528,0), XLBOBB_MASK, POWER4, { BI } }, { "btctrl", XLO(19,BOT,528,1), XLBOBB_MASK, PPCCOM, { BI } }, { "btctrl-", XLO(19,BOT,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "btctrl-", XLO(19,BOTM4,528,1), XLBOBB_MASK, POWER4, { BI } }, +{ "btctrl+", XLO(19,BOTP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "btctrl+", XLO(19,BOTP4,528,1), XLBOBB_MASK, POWER4, { BI } }, { "bfctr", XLO(19,BOF,528,0), XLBOBB_MASK, PPCCOM, { BI } }, { "bfctr-", XLO(19,BOF,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "bfctr-", XLO(19,BOFM4,528,0), XLBOBB_MASK, POWER4, { BI } }, +{ "bfctr+", XLO(19,BOFP,528,0), XLBOBB_MASK, NOPOWER4, { BI } }, { "bfctr+", XLO(19,BOFP4,528,0), XLBOBB_MASK, POWER4, { BI } }, { "bfctrl", XLO(19,BOF,528,1), XLBOBB_MASK, PPCCOM, { BI } }, { "bfctrl-", XLO(19,BOF,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, -{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "bfctrl-", XLO(19,BOFM4,528,1), XLBOBB_MASK, POWER4, { BI } }, +{ "bfctrl+", XLO(19,BOFP,528,1), XLBOBB_MASK, NOPOWER4, { BI } }, { "bfctrl+", XLO(19,BOFP4,528,1), XLBOBB_MASK, POWER4, { BI } }, { "bcctr", XLLK(19,528,0), XLYBB_MASK, PPCCOM, { BO, BI } }, { "bcctr-", XLYLK(19,528,0,0), XLYBB_MASK, PPCCOM, { BOE, BI } }, @@ -2722,7 +3148,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "cmpw", XCMPL(31,0,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, { "cmpd", XCMPL(31,0,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, -{ "cmp", X(31,0), XCMP_MASK, PPCONLY, { BF, L, RA, RB } }, +{ "cmp", X(31,0), XCMP_MASK, PPC, { BF, L, RA, RB } }, { "cmp", X(31,0), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, { "twlgt", XTO(31,4,TOLGT), XTO_MASK, PPCCOM, { RA, RB } }, @@ -2785,15 +3211,22 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mulhwu", XO(31,11,0,0), XO_MASK, PPC, { RT, RA, RB } }, { "mulhwu.", XO(31,11,0,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "mfcr", X(31,19), XRARB_MASK, COM, { RT } }, +{ "isellt", X(31,15), X_MASK, PPCISEL, { RT, RA, RB } }, +{ "iselgt", X(31,47), X_MASK, PPCISEL, { RT, RA, RB } }, +{ "iseleq", X(31,79), X_MASK, PPCISEL, { RT, RA, RB } }, +{ "isel", XISEL(31,15), XISEL_MASK, PPCISEL, { RT, RA, RB, CRB } }, -{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA, RB } }, +{ "mfcr", X(31,19), XRARB_MASK, NOPOWER4, { RT } }, +{ "mfcr", X(31,19), XFXFXM_MASK, POWER4, { RT, FXM4 } }, -{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA, RB } }, +{ "lwarx", X(31,20), X_MASK, PPC, { RT, RA0, RB } }, + +{ "ldx", X(31,21), X_MASK, PPC64, { RT, RA0, RB } }, { "icbt", X(31,22), X_MASK, BOOKE, { CT, RA, RB } }, +{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, -{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA, RB } }, +{ "lwzx", X(31,23), X_MASK, PPCCOM, { RT, RA0, RB } }, { "lx", X(31,23), X_MASK, PWRCOM, { RT, RA, RB } }, { "slw", XRC(31,24,0), X_MASK, PPCCOM, { RA, RS, RB } }, @@ -2817,11 +3250,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "icbte", X(31,30), X_MASK, BOOKE64, { CT, RA, RB } }, -{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA, RB } }, +{ "lwzxe", X(31,31), X_MASK, BOOKE64, { RT, RA0, RB } }, { "cmplw", XCMPL(31,32,0), XCMPL_MASK, PPCCOM, { OBF, RA, RB } }, { "cmpld", XCMPL(31,32,1), XCMPL_MASK, PPC64, { OBF, RA, RB } }, -{ "cmpl", X(31,32), XCMP_MASK, PPCONLY, { BF, L, RA, RB } }, +{ "cmpl", X(31,32), XCMP_MASK, PPC, { BF, L, RA, RB } }, { "cmpl", X(31,32), XCMPL_MASK, PWRCOM, { BF, RA, RB } }, { "subf", XO(31,40,0,0), XO_MASK, PPC, { RT, RA, RB } }, @@ -2872,19 +3305,22 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mulhw", XO(31,75,0,0), XO_MASK, PPC, { RT, RA, RB } }, { "mulhw.", XO(31,75,0,1), XO_MASK, PPC, { RT, RA, RB } }, +{ "dlmzb", XRC(31,78,0), X_MASK, PPC403|PPC440, { RA, RS, RB } }, +{ "dlmzb.", XRC(31,78,1), X_MASK, PPC403|PPC440, { RA, RS, RB } }, + { "mtsrd", X(31,82), XRB_MASK|(1<<20), PPC64, { SR, RS } }, { "mfmsr", X(31,83), XRARB_MASK, COM, { RT } }, -{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA, RB } }, +{ "ldarx", X(31,84), X_MASK, PPC64, { RT, RA0, RB } }, { "dcbf", X(31,86), XRT_MASK, PPC, { RA, RB } }, -{ "lbzx", X(31,87), X_MASK, COM, { RT, RA, RB } }, +{ "lbzx", X(31,87), X_MASK, COM, { RT, RA0, RB } }, { "dcbfe", X(31,94), XRT_MASK, BOOKE64, { RA, RB } }, -{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA, RB } }, +{ "lbzxe", X(31,95), X_MASK, BOOKE64, { RT, RA0, RB } }, { "neg", XO(31,104,0,0), XORB_MASK, COM, { RT, RA } }, { "neg.", XO(31,104,0,1), XORB_MASK, COM, { RT, RA } }, @@ -2907,12 +3343,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "not.", XRC(31,124,1), X_MASK, COM, { RA, RS, RBS } }, { "nor.", XRC(31,124,1), X_MASK, COM, { RA, RS, RB } }, -{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA, RB } }, +{ "lwarxe", X(31,126), X_MASK, BOOKE64, { RT, RA0, RB } }, { "lbzuxe", X(31,127), X_MASK, BOOKE64, { RT, RAL, RB } }, -{ "wrtee", X(31,131), XRARB_MASK, PPC403, { RS } }, -{ "wrtee", X(31,131), XRARB_MASK, BOOKE, { RS } }, +{ "wrtee", X(31,131), XRARB_MASK, PPC403 | BOOKE, { RS } }, + +{ "dcbtstls",X(31,134), X_MASK, PPCCHLK, { CT, RA, RB }}, { "subfe", XO(31,136,0,0), XO_MASK, PPCCOM, { RT, RA, RB } }, { "sfe", XO(31,136,0,0), XO_MASK, PWRCOM, { RT, RA, RB } }, @@ -2932,21 +3369,23 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "addeo.", XO(31,138,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, { "aeo.", XO(31,138,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, -{ "mtcr", XFXM(31,144,0xff), XFXFXM_MASK|FXM_MASK, COM, { RS }}, +{ "dcbtstlse",X(31,142),X_MASK, PPCCHLK64, { CT, RA, RB }}, + +{ "mtcr", XFXM(31,144,0xff), XRARB_MASK, COM, { RS }}, { "mtcrf", X(31,144), XFXFXM_MASK, COM, { FXM, RS } }, { "mtmsr", X(31,146), XRARB_MASK, COM, { RS } }, -{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA, RB } }, +{ "stdx", X(31,149), X_MASK, PPC64, { RS, RA0, RB } }, -{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA, RB } }, +{ "stwcx.", XRC(31,150,1), X_MASK, PPC, { RS, RA0, RB } }, -{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA, RB } }, +{ "stwx", X(31,151), X_MASK, PPCCOM, { RS, RA0, RB } }, { "stx", X(31,151), X_MASK, PWRCOM, { RS, RA, RB } }, -{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA, RB } }, +{ "stwcxe.", XRC(31,158,1), X_MASK, BOOKE64, { RS, RA0, RB } }, -{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA, RB } }, +{ "stwxe", X(31,159), X_MASK, BOOKE64, { RS, RA0, RB } }, { "slq", XRC(31,152,0), X_MASK, M601, { RA, RS, RB } }, { "slq.", XRC(31,152,1), X_MASK, M601, { RA, RS, RB } }, @@ -2954,15 +3393,17 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sle", XRC(31,153,0), X_MASK, M601, { RA, RS, RB } }, { "sle.", XRC(31,153,1), X_MASK, M601, { RA, RS, RB } }, -{ "wrteei", X(31,163), XE_MASK, PPC403, { E } }, -{ "wrteei", X(31,163), XE_MASK, BOOKE, { E } }, +{ "wrteei", X(31,163), XE_MASK, PPC403 | BOOKE, { E } }, + +{ "dcbtls", X(31,166), X_MASK, PPCCHLK, { CT, RA, RB }}, +{ "dcbtlse", X(31,174), X_MASK, PPCCHLK64, { CT, RA, RB }}, { "mtmsrd", X(31,178), XRLARB_MASK, PPC64, { RS, MTMSRD_L } }, { "stdux", X(31,181), X_MASK, PPC64, { RS, RAS, RB } }, { "stwux", X(31,183), X_MASK, PPCCOM, { RS, RAS, RB } }, -{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA, RB } }, +{ "stux", X(31,183), X_MASK, PWRCOM, { RS, RA0, RB } }, { "sliq", XRC(31,184,0), X_MASK, M601, { RA, RS, SH } }, { "sliq.", XRC(31,184,1), X_MASK, M601, { RA, RS, SH } }, @@ -2989,9 +3430,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mtsr", X(31,210), XRB_MASK|(1<<20), COM32, { SR, RS } }, -{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA, RB } }, +{ "stdcx.", XRC(31,214,1), X_MASK, PPC64, { RS, RA0, RB } }, -{ "stbx", X(31,215), X_MASK, COM, { RS, RA, RB } }, +{ "stbx", X(31,215), X_MASK, COM, { RS, RA0, RB } }, { "sllq", XRC(31,216,0), X_MASK, M601, { RA, RS, RB } }, { "sllq.", XRC(31,216,1), X_MASK, M601, { RA, RS, RB } }, @@ -2999,7 +3440,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sleq", XRC(31,217,0), X_MASK, M601, { RA, RS, RB } }, { "sleq.", XRC(31,217,1), X_MASK, M601, { RA, RS, RB } }, -{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA, RB } }, +{ "stbxe", X(31,223), X_MASK, BOOKE64, { RS, RA0, RB } }, + +{ "icblc", X(31,230), X_MASK, PPCCHLK, { CT, RA, RB }}, { "subfme", XO(31,232,0,0), XORB_MASK, PPCCOM, { RT, RA } }, { "sfme", XO(31,232,0,0), XORB_MASK, PWRCOM, { RT, RA } }, @@ -3033,10 +3476,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mullwo.", XO(31,235,1,1), XO_MASK, PPCCOM, { RT, RA, RB } }, { "mulso.", XO(31,235,1,1), XO_MASK, PWRCOM, { RT, RA, RB } }, +{ "icblce", X(31,238), X_MASK, PPCCHLK64, { CT, RA, RB }}, { "mtsrin", X(31,242), XRA_MASK, PPC32, { RS, RB } }, { "mtsri", X(31,242), XRA_MASK, POWER32, { RS, RB } }, -{ "dcbtst", X(31,246), XRT_MASK, PPC, { CT, RA, RB } }, +{ "dcbtst", X(31,246), X_MASK, PPC, { CT, RA, RB } }, { "stbux", X(31,247), X_MASK, COM, { RS, RAS, RB } }, @@ -3049,8 +3493,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfdcrx", X(31,259), X_MASK, BOOKE, { RS, RA } }, -{ "icbt", X(31,262), XRT_MASK, PPC403, { RA, RB } }, - { "doz", XO(31,264,0,0), XO_MASK, M601, { RT, RA, RB } }, { "doz.", XO(31,264,0,1), XO_MASK, M601, { RT, RA, RB } }, { "dozo", XO(31,264,1,0), XO_MASK, M601, { RT, RA, RB } }, @@ -3072,19 +3514,19 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lscbx", XRC(31,277,0), X_MASK, M601, { RT, RA, RB } }, { "lscbx.", XRC(31,277,1), X_MASK, M601, { RT, RA, RB } }, -{ "dcbt", X(31,278), XRT_MASK, PPC, { CT, RA, RB } }, +{ "dcbt", X(31,278), X_MASK, PPC, { CT, RA, RB } }, -{ "lhzx", X(31,279), X_MASK, COM, { RT, RA, RB } }, +{ "lhzx", X(31,279), X_MASK, COM, { RT, RA0, RB } }, { "eqv", XRC(31,284,0), X_MASK, COM, { RA, RS, RB } }, { "eqv.", XRC(31,284,1), X_MASK, COM, { RA, RS, RB } }, { "dcbte", X(31,286), X_MASK, BOOKE64, { CT, RA, RB } }, -{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA, RB } }, +{ "lhzxe", X(31,287), X_MASK, BOOKE64, { RT, RA0, RB } }, { "tlbie", X(31,306), XRTLRA_MASK, PPC, { RB, L } }, -{ "tlbi", X(31,306), XRT_MASK, POWER, { RA, RB } }, +{ "tlbi", X(31,306), XRT_MASK, POWER, { RA0, RB } }, { "eciwx", X(31,310), X_MASK, PPC, { RT, RA, RB } }, @@ -3095,19 +3537,19 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "lhzuxe", X(31,319), X_MASK, BOOKE64, { RT, RAL, RB } }, -{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } }, -{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } }, -{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } }, -{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } }, -{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } }, -{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } }, -{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } }, -{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } }, -{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } }, -{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } }, -{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } }, -{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } }, -{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } }, +{ "mfexisr", XSPR(31,323,64), XSPR_MASK, PPC403, { RT } }, +{ "mfexier", XSPR(31,323,66), XSPR_MASK, PPC403, { RT } }, +{ "mfbr0", XSPR(31,323,128), XSPR_MASK, PPC403, { RT } }, +{ "mfbr1", XSPR(31,323,129), XSPR_MASK, PPC403, { RT } }, +{ "mfbr2", XSPR(31,323,130), XSPR_MASK, PPC403, { RT } }, +{ "mfbr3", XSPR(31,323,131), XSPR_MASK, PPC403, { RT } }, +{ "mfbr4", XSPR(31,323,132), XSPR_MASK, PPC403, { RT } }, +{ "mfbr5", XSPR(31,323,133), XSPR_MASK, PPC403, { RT } }, +{ "mfbr6", XSPR(31,323,134), XSPR_MASK, PPC403, { RT } }, +{ "mfbr7", XSPR(31,323,135), XSPR_MASK, PPC403, { RT } }, +{ "mfbear", XSPR(31,323,144), XSPR_MASK, PPC403, { RT } }, +{ "mfbesr", XSPR(31,323,145), XSPR_MASK, PPC403, { RT } }, +{ "mfiocr", XSPR(31,323,160), XSPR_MASK, PPC403, { RT } }, { "mfdmacr0", XSPR(31,323,192), XSPR_MASK, PPC403, { RT } }, { "mfdmact0", XSPR(31,323,193), XSPR_MASK, PPC403, { RT } }, { "mfdmada0", XSPR(31,323,194), XSPR_MASK, PPC403, { RT } }, @@ -3128,106 +3570,176 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfdmada3", XSPR(31,323,218), XSPR_MASK, PPC403, { RT } }, { "mfdmasa3", XSPR(31,323,219), XSPR_MASK, PPC403, { RT } }, { "mfdmacc3", XSPR(31,323,220), XSPR_MASK, PPC403, { RT } }, -{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } }, -{ "mfdcr", X(31,323), X_MASK, PPC403, { RT, SPR } }, -{ "mfdcr", X(31,323), X_MASK, BOOKE, { RT, SPR } }, +{ "mfdmasr", XSPR(31,323,224), XSPR_MASK, PPC403, { RT } }, +{ "mfdcr", X(31,323), X_MASK, PPC403 | BOOKE, { RT, SPR } }, { "div", XO(31,331,0,0), XO_MASK, M601, { RT, RA, RB } }, { "div.", XO(31,331,0,1), XO_MASK, M601, { RT, RA, RB } }, { "divo", XO(31,331,1,0), XO_MASK, M601, { RT, RA, RB } }, { "divo.", XO(31,331,1,1), XO_MASK, M601, { RT, RA, RB } }, -{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } }, -{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } }, -{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } }, -{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } }, -{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } }, -{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } }, -{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } }, -{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, -{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } }, -{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } }, -{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, -{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, -{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, -{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, -{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, -{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } }, -{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } }, -{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } }, -{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } }, -{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } }, -{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } }, -{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } }, -{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } }, -{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } }, -{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } }, -{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } }, -{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } }, -{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } }, -{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } }, -{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } }, -{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } }, -{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } }, -{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, -{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } }, -{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } }, -{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } }, -{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, -{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, -{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, -{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, -{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } }, -{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } }, -{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } }, -{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } }, -{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } }, -{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } }, -{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } }, -{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } }, -{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } }, -{ "mfm_casid",XSPR(31,339,793), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } }, -{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_dbcam",XSPR(31,339,816), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } }, -{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } }, -{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } }, -{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } }, -{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, -{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } }, -{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } }, -{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } }, -{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } }, -{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } }, -{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } }, +{ "mfpmr", X(31,334), X_MASK, PPCPMR, { RT, PMR }}, + +{ "mfmq", XSPR(31,339,0), XSPR_MASK, M601, { RT } }, +{ "mfxer", XSPR(31,339,1), XSPR_MASK, COM, { RT } }, +{ "mfrtcu", XSPR(31,339,4), XSPR_MASK, COM, { RT } }, +{ "mfrtcl", XSPR(31,339,5), XSPR_MASK, COM, { RT } }, +{ "mfdec", XSPR(31,339,6), XSPR_MASK, MFDEC1, { RT } }, +{ "mfdec", XSPR(31,339,22), XSPR_MASK, MFDEC2, { RT } }, +{ "mflr", XSPR(31,339,8), XSPR_MASK, COM, { RT } }, +{ "mfctr", XSPR(31,339,9), XSPR_MASK, COM, { RT } }, +{ "mftid", XSPR(31,339,17), XSPR_MASK, POWER, { RT } }, +{ "mfdsisr", XSPR(31,339,18), XSPR_MASK, COM, { RT } }, +{ "mfdar", XSPR(31,339,19), XSPR_MASK, COM, { RT } }, +{ "mfsdr0", XSPR(31,339,24), XSPR_MASK, POWER, { RT } }, +{ "mfsdr1", XSPR(31,339,25), XSPR_MASK, COM, { RT } }, +{ "mfsrr0", XSPR(31,339,26), XSPR_MASK, COM, { RT } }, +{ "mfsrr1", XSPR(31,339,27), XSPR_MASK, COM, { RT } }, +{ "mfpid", XSPR(31,339,48), XSPR_MASK, BOOKE, { RT } }, +{ "mfpid", XSPR(31,339,945), XSPR_MASK, PPC403, { RT } }, +{ "mfcsrr0", XSPR(31,339,58), XSPR_MASK, BOOKE, { RT } }, +{ "mfcsrr1", XSPR(31,339,59), XSPR_MASK, BOOKE, { RT } }, +{ "mfdear", XSPR(31,339,61), XSPR_MASK, BOOKE, { RT } }, +{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } }, +{ "mfesr", XSPR(31,339,62), XSPR_MASK, BOOKE, { RT } }, +{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } }, +{ "mfivpr", XSPR(31,339,63), XSPR_MASK, BOOKE, { RT } }, +{ "mfcmpa", XSPR(31,339,144), XSPR_MASK, PPC860, { RT } }, +{ "mfcmpb", XSPR(31,339,145), XSPR_MASK, PPC860, { RT } }, +{ "mfcmpc", XSPR(31,339,146), XSPR_MASK, PPC860, { RT } }, +{ "mfcmpd", XSPR(31,339,147), XSPR_MASK, PPC860, { RT } }, +{ "mficr", XSPR(31,339,148), XSPR_MASK, PPC860, { RT } }, +{ "mfder", XSPR(31,339,149), XSPR_MASK, PPC860, { RT } }, +{ "mfcounta", XSPR(31,339,150), XSPR_MASK, PPC860, { RT } }, +{ "mfcountb", XSPR(31,339,151), XSPR_MASK, PPC860, { RT } }, +{ "mfcmpe", XSPR(31,339,152), XSPR_MASK, PPC860, { RT } }, +{ "mfcmpf", XSPR(31,339,153), XSPR_MASK, PPC860, { RT } }, +{ "mfcmpg", XSPR(31,339,154), XSPR_MASK, PPC860, { RT } }, +{ "mfcmph", XSPR(31,339,155), XSPR_MASK, PPC860, { RT } }, +{ "mflctrl1", XSPR(31,339,156), XSPR_MASK, PPC860, { RT } }, +{ "mflctrl2", XSPR(31,339,157), XSPR_MASK, PPC860, { RT } }, +{ "mfictrl", XSPR(31,339,158), XSPR_MASK, PPC860, { RT } }, +{ "mfbar", XSPR(31,339,159), XSPR_MASK, PPC860, { RT } }, +{ "mfvrsave", XSPR(31,339,256), XSPR_MASK, PPCVEC, { RT } }, +{ "mfusprg0", XSPR(31,339,256), XSPR_MASK, BOOKE, { RT } }, +{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, PPC405, { RT } }, +{ "mfsprg4", XSPR(31,339,260), XSPR_MASK, BOOKE, { RT } }, +{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, PPC405, { RT } }, +{ "mfsprg5", XSPR(31,339,261), XSPR_MASK, BOOKE, { RT } }, +{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, PPC405, { RT } }, +{ "mfsprg6", XSPR(31,339,262), XSPR_MASK, BOOKE, { RT } }, +{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, PPC405, { RT } }, +{ "mfsprg7", XSPR(31,339,263), XSPR_MASK, BOOKE, { RT } }, +{ "mftb", X(31,371), X_MASK, CLASSIC, { RT, TBR } }, +{ "mftb", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, +{ "mftbl", XSPR(31,371,268), XSPR_MASK, CLASSIC, { RT } }, +{ "mftbl", XSPR(31,339,268), XSPR_MASK, BOOKE, { RT } }, +{ "mftbu", XSPR(31,371,269), XSPR_MASK, CLASSIC, { RT } }, +{ "mftbu", XSPR(31,339,269), XSPR_MASK, BOOKE, { RT } }, +{ "mfsprg", XSPR(31,339,272), XSPRG_MASK, PPC, { RT, SPRG } }, +{ "mfsprg0", XSPR(31,339,272), XSPR_MASK, PPC, { RT } }, +{ "mfsprg1", XSPR(31,339,273), XSPR_MASK, PPC, { RT } }, +{ "mfsprg2", XSPR(31,339,274), XSPR_MASK, PPC, { RT } }, +{ "mfsprg3", XSPR(31,339,275), XSPR_MASK, PPC, { RT } }, +{ "mfasr", XSPR(31,339,280), XSPR_MASK, PPC64, { RT } }, +{ "mfear", XSPR(31,339,282), XSPR_MASK, PPC, { RT } }, +{ "mfpir", XSPR(31,339,286), XSPR_MASK, BOOKE, { RT } }, +{ "mfpvr", XSPR(31,339,287), XSPR_MASK, PPC, { RT } }, +{ "mfdbsr", XSPR(31,339,304), XSPR_MASK, BOOKE, { RT } }, +{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } }, +{ "mfdbcr0", XSPR(31,339,308), XSPR_MASK, BOOKE, { RT } }, +{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } }, +{ "mfdbcr1", XSPR(31,339,309), XSPR_MASK, BOOKE, { RT } }, +{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } }, +{ "mfdbcr2", XSPR(31,339,310), XSPR_MASK, BOOKE, { RT } }, +{ "mfiac1", XSPR(31,339,312), XSPR_MASK, BOOKE, { RT } }, +{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } }, +{ "mfiac2", XSPR(31,339,313), XSPR_MASK, BOOKE, { RT } }, +{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } }, +{ "mfiac3", XSPR(31,339,314), XSPR_MASK, BOOKE, { RT } }, { "mfiac3", XSPR(31,339,948), XSPR_MASK, PPC405, { RT } }, +{ "mfiac4", XSPR(31,339,315), XSPR_MASK, BOOKE, { RT } }, { "mfiac4", XSPR(31,339,949), XSPR_MASK, PPC405, { RT } }, +{ "mfdac1", XSPR(31,339,316), XSPR_MASK, BOOKE, { RT } }, +{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } }, +{ "mfdac2", XSPR(31,339,317), XSPR_MASK, BOOKE, { RT } }, +{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } }, +{ "mfdvc1", XSPR(31,339,318), XSPR_MASK, BOOKE, { RT } }, { "mfdvc1", XSPR(31,339,950), XSPR_MASK, PPC405, { RT } }, +{ "mfdvc2", XSPR(31,339,319), XSPR_MASK, BOOKE, { RT } }, { "mfdvc2", XSPR(31,339,951), XSPR_MASK, PPC405, { RT } }, +{ "mftsr", XSPR(31,339,336), XSPR_MASK, BOOKE, { RT } }, +{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } }, +{ "mftcr", XSPR(31,339,340), XSPR_MASK, BOOKE, { RT } }, +{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } }, +{ "mfivor0", XSPR(31,339,400), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor1", XSPR(31,339,401), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor2", XSPR(31,339,402), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor3", XSPR(31,339,403), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor4", XSPR(31,339,404), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor5", XSPR(31,339,405), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor6", XSPR(31,339,406), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor7", XSPR(31,339,407), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor8", XSPR(31,339,408), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor9", XSPR(31,339,409), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor10", XSPR(31,339,410), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor11", XSPR(31,339,411), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor12", XSPR(31,339,412), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor13", XSPR(31,339,413), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor14", XSPR(31,339,414), XSPR_MASK, BOOKE, { RT } }, +{ "mfivor15", XSPR(31,339,415), XSPR_MASK, BOOKE, { RT } }, +{ "mfspefscr", XSPR(31,339,512), XSPR_MASK, PPCSPE, { RT } }, +{ "mfbbear", XSPR(31,339,513), XSPR_MASK, PPCBRLK, { RT } }, +{ "mfbbtar", XSPR(31,339,514), XSPR_MASK, PPCBRLK, { RT } }, +{ "mfivor32", XSPR(31,339,528), XSPR_MASK, PPCSPE, { RT } }, +{ "mfivor33", XSPR(31,339,529), XSPR_MASK, PPCSPE, { RT } }, +{ "mfivor34", XSPR(31,339,530), XSPR_MASK, PPCSPE, { RT } }, +{ "mfivor35", XSPR(31,339,531), XSPR_MASK, PPCPMR, { RT } }, +{ "mfibatu", XSPR(31,339,528), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, +{ "mfibatl", XSPR(31,339,529), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, +{ "mfdbatu", XSPR(31,339,536), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, +{ "mfdbatl", XSPR(31,339,537), XSPRBAT_MASK, PPC, { RT, SPRBAT } }, +{ "mfic_cst", XSPR(31,339,560), XSPR_MASK, PPC860, { RT } }, +{ "mfic_adr", XSPR(31,339,561), XSPR_MASK, PPC860, { RT } }, +{ "mfic_dat", XSPR(31,339,562), XSPR_MASK, PPC860, { RT } }, +{ "mfdc_cst", XSPR(31,339,568), XSPR_MASK, PPC860, { RT } }, +{ "mfdc_adr", XSPR(31,339,569), XSPR_MASK, PPC860, { RT } }, +{ "mfmcsrr0", XSPR(31,339,570), XSPR_MASK, PPCRFMCI, { RT } }, +{ "mfdc_dat", XSPR(31,339,570), XSPR_MASK, PPC860, { RT } }, +{ "mfmcsrr1", XSPR(31,339,571), XSPR_MASK, PPCRFMCI, { RT } }, +{ "mfmcsr", XSPR(31,339,572), XSPR_MASK, PPCRFMCI, { RT } }, +{ "mfmcar", XSPR(31,339,573), XSPR_MASK, PPCRFMCI, { RT } }, +{ "mfdpdr", XSPR(31,339,630), XSPR_MASK, PPC860, { RT } }, +{ "mfdpir", XSPR(31,339,631), XSPR_MASK, PPC860, { RT } }, +{ "mfimmr", XSPR(31,339,638), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_ctr", XSPR(31,339,784), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_ap", XSPR(31,339,786), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_epn", XSPR(31,339,787), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_twc", XSPR(31,339,789), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_rpn", XSPR(31,339,790), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_ctr", XSPR(31,339,792), XSPR_MASK, PPC860, { RT } }, +{ "mfm_casid", XSPR(31,339,793), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_ap", XSPR(31,339,794), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_epn", XSPR(31,339,795), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_twb", XSPR(31,339,796), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_twc", XSPR(31,339,797), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_rpn", XSPR(31,339,798), XSPR_MASK, PPC860, { RT } }, +{ "mfm_tw", XSPR(31,339,799), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_dbcam", XSPR(31,339,816), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_dbram0",XSPR(31,339,817), XSPR_MASK, PPC860, { RT } }, +{ "mfmi_dbram1",XSPR(31,339,818), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_dbcam", XSPR(31,339,824), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_dbram0",XSPR(31,339,825), XSPR_MASK, PPC860, { RT } }, +{ "mfmd_dbram1",XSPR(31,339,826), XSPR_MASK, PPC860, { RT } }, +{ "mfummcr0", XSPR(31,339,936), XSPR_MASK, PPC750, { RT } }, +{ "mfupmc1", XSPR(31,339,937), XSPR_MASK, PPC750, { RT } }, +{ "mfupmc2", XSPR(31,339,938), XSPR_MASK, PPC750, { RT } }, +{ "mfusia", XSPR(31,339,939), XSPR_MASK, PPC750, { RT } }, +{ "mfummcr1", XSPR(31,339,940), XSPR_MASK, PPC750, { RT } }, +{ "mfupmc3", XSPR(31,339,941), XSPR_MASK, PPC750, { RT } }, +{ "mfupmc4", XSPR(31,339,942), XSPR_MASK, PPC750, { RT } }, +{ "mfzpr", XSPR(31,339,944), XSPR_MASK, PPC403, { RT } }, +{ "mfccr0", XSPR(31,339,947), XSPR_MASK, PPC405, { RT } }, { "mfmmcr0", XSPR(31,339,952), XSPR_MASK, PPC750, { RT } }, { "mfpmc1", XSPR(31,339,953), XSPR_MASK, PPC750, { RT } }, { "mfsgr", XSPR(31,339,953), XSPR_MASK, PPC403, { RT } }, @@ -3238,51 +3750,41 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfmmcr1", XSPR(31,339,956), XSPR_MASK, PPC750, { RT } }, { "mfsu0r", XSPR(31,339,956), XSPR_MASK, PPC405, { RT } }, { "mfpmc3", XSPR(31,339,957), XSPR_MASK, PPC750, { RT } }, -{ "mfdbcr1", XSPR(31,339,957), XSPR_MASK, PPC405, { RT } }, { "mfpmc4", XSPR(31,339,958), XSPR_MASK, PPC750, { RT } }, -{ "mfesr", XSPR(31,339,980), XSPR_MASK, PPC403, { RT } }, -{ "mfdear", XSPR(31,339,981), XSPR_MASK, PPC403, { RT } }, -{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } }, -{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } }, -{ "mftsr", XSPR(31,339,984), XSPR_MASK, PPC403, { RT } }, -{ "mftcr", XSPR(31,339,986), XSPR_MASK, PPC403, { RT } }, -{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } }, -{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } }, -{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } }, -{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } }, -{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } }, -{ "mfdbsr", XSPR(31,339,1008), XSPR_MASK, PPC403, { RT } }, -{ "mfdbcr0", XSPR(31,339,1010), XSPR_MASK, PPC405, { RT } }, -{ "mfiac1", XSPR(31,339,1012), XSPR_MASK, PPC403, { RT } }, -{ "mfiac2", XSPR(31,339,1013), XSPR_MASK, PPC403, { RT } }, -{ "mfdac1", XSPR(31,339,1014), XSPR_MASK, PPC403, { RT } }, -{ "mfdac2", XSPR(31,339,1015), XSPR_MASK, PPC403, { RT } }, -{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } }, -{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } }, -{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } }, -{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } }, -{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } }, -{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } }, -{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } }, -{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } }, -{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } }, -{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } }, -{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } }, -{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } }, - -{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA, RB } }, +{ "mficdbdr", XSPR(31,339,979), XSPR_MASK, PPC403, { RT } }, +{ "mfevpr", XSPR(31,339,982), XSPR_MASK, PPC403, { RT } }, +{ "mfcdbcr", XSPR(31,339,983), XSPR_MASK, PPC403, { RT } }, +{ "mfpit", XSPR(31,339,987), XSPR_MASK, PPC403, { RT } }, +{ "mftbhi", XSPR(31,339,988), XSPR_MASK, PPC403, { RT } }, +{ "mftblo", XSPR(31,339,989), XSPR_MASK, PPC403, { RT } }, +{ "mfsrr2", XSPR(31,339,990), XSPR_MASK, PPC403, { RT } }, +{ "mfsrr3", XSPR(31,339,991), XSPR_MASK, PPC403, { RT } }, +{ "mfl2cr", XSPR(31,339,1017), XSPR_MASK, PPC750, { RT } }, +{ "mfdccr", XSPR(31,339,1018), XSPR_MASK, PPC403, { RT } }, +{ "mficcr", XSPR(31,339,1019), XSPR_MASK, PPC403, { RT } }, +{ "mfictc", XSPR(31,339,1019), XSPR_MASK, PPC750, { RT } }, +{ "mfpbl1", XSPR(31,339,1020), XSPR_MASK, PPC403, { RT } }, +{ "mfthrm1", XSPR(31,339,1020), XSPR_MASK, PPC750, { RT } }, +{ "mfpbu1", XSPR(31,339,1021), XSPR_MASK, PPC403, { RT } }, +{ "mfthrm2", XSPR(31,339,1021), XSPR_MASK, PPC750, { RT } }, +{ "mfpbl2", XSPR(31,339,1022), XSPR_MASK, PPC403, { RT } }, +{ "mfthrm3", XSPR(31,339,1022), XSPR_MASK, PPC750, { RT } }, +{ "mfpbu2", XSPR(31,339,1023), XSPR_MASK, PPC403, { RT } }, +{ "mfspr", X(31,339), X_MASK, COM, { RT, SPR } }, + +{ "lwax", X(31,341), X_MASK, PPC64, { RT, RA0, RB } }, { "dst", XDSS(31,342,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, { "dstt", XDSS(31,342,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, -{ "lhax", X(31,343), X_MASK, COM, { RT, RA, RB } }, +{ "lhax", X(31,343), X_MASK, COM, { RT, RA0, RB } }, -{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA, RB } }, +{ "lhaxe", X(31,351), X_MASK, BOOKE64, { RT, RA0, RB } }, { "dstst", XDSS(31,374,0), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, { "dststt", XDSS(31,374,1), XDSS_MASK, PPCVEC, { RA, RB, STRM } }, -{ "dccci", X(31,454), XRT_MASK, PPC403, { RA, RB } }, +{ "dccci", X(31,454), XRT_MASK, PPC403|PPC440, { RA, RB } }, { "abs", XO(31,360,0,0), XORB_MASK, M601, { RT, RA } }, { "abs.", XO(31,360,0,1), XORB_MASK, M601, { RT, RA } }, @@ -3296,10 +3798,6 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "tlbia", X(31,370), 0xffffffff, PPC, { 0 } }, -{ "mftbl", XSPR(31,371,268), XSPR_MASK, PPC, { RT } }, -{ "mftbu", XSPR(31,371,269), XSPR_MASK, PPC, { RT } }, -{ "mftb", X(31,371), X_MASK, PPC, { RT, TBR } }, - { "lwaux", X(31,373), X_MASK, PPC64, { RT, RAL, RB } }, { "lhaux", X(31,375), X_MASK, COM, { RT, RAL, RB } }, @@ -3308,15 +3806,19 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mtdcrx", X(31,387), X_MASK, BOOKE, { RA, RS } }, +{ "dcblc", X(31,390), X_MASK, PPCCHLK, { CT, RA, RB }}, + { "subfe64", XO(31,392,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, { "subfe64o",XO(31,392,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, { "adde64", XO(31,394,0,0), XO_MASK, BOOKE64, { RT, RA, RB } }, { "adde64o", XO(31,394,1,0), XO_MASK, BOOKE64, { RT, RA, RB } }, +{ "dcblce", X(31,398), X_MASK, PPCCHLK64, { CT, RA, RB }}, + { "slbmte", X(31,402), XRA_MASK, PPC64, { RS, RB } }, -{ "sthx", X(31,407), X_MASK, COM, { RS, RA, RB } }, +{ "sthx", X(31,407), X_MASK, COM, { RS, RA0, RB } }, { "lfqx", X(31,791), X_MASK, POWER2, { FRT, RA, RB } }, @@ -3332,7 +3834,7 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sradi", XS(31,413,0), XS_MASK, PPC64, { RA, RS, SH6 } }, { "sradi.", XS(31,413,1), XS_MASK, PPC64, { RA, RS, SH6 } }, -{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA, RB } }, +{ "sthxe", X(31,415), X_MASK, BOOKE64, { RS, RA0, RB } }, { "slbie", X(31,434), XRTRA_MASK, PPC64, { RB } }, @@ -3347,42 +3849,41 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mr.", XRC(31,444,1), X_MASK, COM, { RA, RS, RBS } }, { "or.", XRC(31,444,1), X_MASK, COM, { RA, RS, RB } }, -{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RT } }, -{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RT } }, -{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RT } }, -{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RT } }, -{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RT } }, -{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RT } }, -{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RT } }, -{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RT } }, -{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RT } }, -{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RT } }, -{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RT } }, -{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RT } }, -{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RT } }, -{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RT } }, -{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RT } }, -{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RT } }, -{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RT } }, -{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RT } }, -{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RT } }, -{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RT } }, -{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RT } }, -{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RT } }, -{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RT } }, -{ "mtdcr", X(31,451), X_MASK, PPC403, { SPR, RS } }, -{ "mtdcr", X(31,451), X_MASK, BOOKE, { SPR, RS } }, +{ "mtexisr", XSPR(31,451,64), XSPR_MASK, PPC403, { RS } }, +{ "mtexier", XSPR(31,451,66), XSPR_MASK, PPC403, { RS } }, +{ "mtbr0", XSPR(31,451,128), XSPR_MASK, PPC403, { RS } }, +{ "mtbr1", XSPR(31,451,129), XSPR_MASK, PPC403, { RS } }, +{ "mtbr2", XSPR(31,451,130), XSPR_MASK, PPC403, { RS } }, +{ "mtbr3", XSPR(31,451,131), XSPR_MASK, PPC403, { RS } }, +{ "mtbr4", XSPR(31,451,132), XSPR_MASK, PPC403, { RS } }, +{ "mtbr5", XSPR(31,451,133), XSPR_MASK, PPC403, { RS } }, +{ "mtbr6", XSPR(31,451,134), XSPR_MASK, PPC403, { RS } }, +{ "mtbr7", XSPR(31,451,135), XSPR_MASK, PPC403, { RS } }, +{ "mtbear", XSPR(31,451,144), XSPR_MASK, PPC403, { RS } }, +{ "mtbesr", XSPR(31,451,145), XSPR_MASK, PPC403, { RS } }, +{ "mtiocr", XSPR(31,451,160), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacr0", XSPR(31,451,192), XSPR_MASK, PPC403, { RS } }, +{ "mtdmact0", XSPR(31,451,193), XSPR_MASK, PPC403, { RS } }, +{ "mtdmada0", XSPR(31,451,194), XSPR_MASK, PPC403, { RS } }, +{ "mtdmasa0", XSPR(31,451,195), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacc0", XSPR(31,451,196), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacr1", XSPR(31,451,200), XSPR_MASK, PPC403, { RS } }, +{ "mtdmact1", XSPR(31,451,201), XSPR_MASK, PPC403, { RS } }, +{ "mtdmada1", XSPR(31,451,202), XSPR_MASK, PPC403, { RS } }, +{ "mtdmasa1", XSPR(31,451,203), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacc1", XSPR(31,451,204), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacr2", XSPR(31,451,208), XSPR_MASK, PPC403, { RS } }, +{ "mtdmact2", XSPR(31,451,209), XSPR_MASK, PPC403, { RS } }, +{ "mtdmada2", XSPR(31,451,210), XSPR_MASK, PPC403, { RS } }, +{ "mtdmasa2", XSPR(31,451,211), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacc2", XSPR(31,451,212), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacr3", XSPR(31,451,216), XSPR_MASK, PPC403, { RS } }, +{ "mtdmact3", XSPR(31,451,217), XSPR_MASK, PPC403, { RS } }, +{ "mtdmada3", XSPR(31,451,218), XSPR_MASK, PPC403, { RS } }, +{ "mtdmasa3", XSPR(31,451,219), XSPR_MASK, PPC403, { RS } }, +{ "mtdmacc3", XSPR(31,451,220), XSPR_MASK, PPC403, { RS } }, +{ "mtdmasr", XSPR(31,451,224), XSPR_MASK, PPC403, { RS } }, +{ "mtdcr", X(31,451), X_MASK, PPC403 | BOOKE, { SPR, RS } }, { "subfze64",XO(31,456,0,0), XORB_MASK, BOOKE64, { RT, RA } }, { "subfze64o",XO(31,456,1,0), XORB_MASK, BOOKE64, { RT, RA } }, @@ -3400,110 +3901,158 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "divwuo", XO(31,459,1,0), XO_MASK, PPC, { RT, RA, RB } }, { "divwuo.", XO(31,459,1,1), XO_MASK, PPC, { RT, RA, RB } }, -{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } }, -{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } }, -{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } }, -{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } }, -{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, -{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } }, -{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } }, -{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } }, -{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } }, -{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } }, -{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, -{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, -{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, -{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, -{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RT } }, -{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RT } }, -{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RT } }, -{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RT } }, -{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RT } }, -{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RT } }, -{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RT } }, -{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RT } }, -{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RT } }, -{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RT } }, -{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RT } }, -{ "mtvrsave",XSPR(31,467,256), XSPR_MASK, PPCVEC, { RT } }, -{ "mtsprg", XSPR(31,467,272), XSPRG_MASK, PPC, { SPRG, RS } }, -{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RT } }, -{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RT } }, -{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RT } }, -{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RT } }, -{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405, { RT } }, -{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405, { RT } }, -{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405, { RT } }, -{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405, { RT } }, -{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } }, -{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, -{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, -{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, -{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, -{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RT } }, -{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RT } }, -{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RT } }, -{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RT } }, -{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RT } }, -{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RT } }, -{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RT } }, -{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RT } }, -{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RT } }, -{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RT } }, -{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RT } }, -{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RT } }, -{ "mticdbdr",XSPR(31,467,979), XSPR_MASK, PPC403, { RT } }, -{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RT } }, -{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RT } }, -{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RT } }, -{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RT } }, -{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RT } }, -{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RT } }, -{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RT } }, -{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RT } }, -{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RT } }, -{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RT } }, -{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RT } }, -{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RT } }, -{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RT } }, -{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RT } }, -{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RT } }, -{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RT } }, -{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RT } }, -{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RT } }, -{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RT } }, -{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RT } }, -{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RT } }, -{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RT } }, -{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RT } }, -{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RT } }, -{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RT } }, -{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RT } }, -{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RT } }, -{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RT } }, -{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RT } }, -{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RT } }, -{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RT } }, -{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RT } }, -{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RT } }, -{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RT } }, -{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RT } }, -{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RT } }, -{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RT } }, -{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RT } }, -{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RT } }, -{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RT } }, -{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RT } }, -{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RT } }, -{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } }, +{ "mtmq", XSPR(31,467,0), XSPR_MASK, M601, { RS } }, +{ "mtxer", XSPR(31,467,1), XSPR_MASK, COM, { RS } }, +{ "mtlr", XSPR(31,467,8), XSPR_MASK, COM, { RS } }, +{ "mtctr", XSPR(31,467,9), XSPR_MASK, COM, { RS } }, +{ "mttid", XSPR(31,467,17), XSPR_MASK, POWER, { RS } }, +{ "mtdsisr", XSPR(31,467,18), XSPR_MASK, COM, { RS } }, +{ "mtdar", XSPR(31,467,19), XSPR_MASK, COM, { RS } }, +{ "mtrtcu", XSPR(31,467,20), XSPR_MASK, COM, { RS } }, +{ "mtrtcl", XSPR(31,467,21), XSPR_MASK, COM, { RS } }, +{ "mtdec", XSPR(31,467,22), XSPR_MASK, COM, { RS } }, +{ "mtsdr0", XSPR(31,467,24), XSPR_MASK, POWER, { RS } }, +{ "mtsdr1", XSPR(31,467,25), XSPR_MASK, COM, { RS } }, +{ "mtsrr0", XSPR(31,467,26), XSPR_MASK, COM, { RS } }, +{ "mtsrr1", XSPR(31,467,27), XSPR_MASK, COM, { RS } }, +{ "mtpid", XSPR(31,467,48), XSPR_MASK, BOOKE, { RS } }, +{ "mtpid", XSPR(31,467,945), XSPR_MASK, PPC403, { RS } }, +{ "mtdecar", XSPR(31,467,54), XSPR_MASK, BOOKE, { RS } }, +{ "mtcsrr0", XSPR(31,467,58), XSPR_MASK, BOOKE, { RS } }, +{ "mtcsrr1", XSPR(31,467,59), XSPR_MASK, BOOKE, { RS } }, +{ "mtdear", XSPR(31,467,61), XSPR_MASK, BOOKE, { RS } }, +{ "mtdear", XSPR(31,467,981), XSPR_MASK, PPC403, { RS } }, +{ "mtesr", XSPR(31,467,62), XSPR_MASK, BOOKE, { RS } }, +{ "mtesr", XSPR(31,467,980), XSPR_MASK, PPC403, { RS } }, +{ "mtivpr", XSPR(31,467,63), XSPR_MASK, BOOKE, { RS } }, +{ "mtcmpa", XSPR(31,467,144), XSPR_MASK, PPC860, { RS } }, +{ "mtcmpb", XSPR(31,467,145), XSPR_MASK, PPC860, { RS } }, +{ "mtcmpc", XSPR(31,467,146), XSPR_MASK, PPC860, { RS } }, +{ "mtcmpd", XSPR(31,467,147), XSPR_MASK, PPC860, { RS } }, +{ "mticr", XSPR(31,467,148), XSPR_MASK, PPC860, { RS } }, +{ "mtder", XSPR(31,467,149), XSPR_MASK, PPC860, { RS } }, +{ "mtcounta", XSPR(31,467,150), XSPR_MASK, PPC860, { RS } }, +{ "mtcountb", XSPR(31,467,151), XSPR_MASK, PPC860, { RS } }, +{ "mtcmpe", XSPR(31,467,152), XSPR_MASK, PPC860, { RS } }, +{ "mtcmpf", XSPR(31,467,153), XSPR_MASK, PPC860, { RS } }, +{ "mtcmpg", XSPR(31,467,154), XSPR_MASK, PPC860, { RS } }, +{ "mtcmph", XSPR(31,467,155), XSPR_MASK, PPC860, { RS } }, +{ "mtlctrl1", XSPR(31,467,156), XSPR_MASK, PPC860, { RS } }, +{ "mtlctrl2", XSPR(31,467,157), XSPR_MASK, PPC860, { RS } }, +{ "mtictrl", XSPR(31,467,158), XSPR_MASK, PPC860, { RS } }, +{ "mtbar", XSPR(31,467,159), XSPR_MASK, PPC860, { RS } }, +{ "mtvrsave", XSPR(31,467,256), XSPR_MASK, PPCVEC, { RS } }, +{ "mtusprg0", XSPR(31,467,256), XSPR_MASK, BOOKE, { RS } }, +{ "mtsprg", XSPR(31,467,272), XSPRG_MASK,PPC, { SPRG, RS } }, +{ "mtsprg0", XSPR(31,467,272), XSPR_MASK, PPC, { RS } }, +{ "mtsprg1", XSPR(31,467,273), XSPR_MASK, PPC, { RS } }, +{ "mtsprg2", XSPR(31,467,274), XSPR_MASK, PPC, { RS } }, +{ "mtsprg3", XSPR(31,467,275), XSPR_MASK, PPC, { RS } }, +{ "mtsprg4", XSPR(31,467,276), XSPR_MASK, PPC405 | BOOKE, { RS } }, +{ "mtsprg5", XSPR(31,467,277), XSPR_MASK, PPC405 | BOOKE, { RS } }, +{ "mtsprg6", XSPR(31,467,278), XSPR_MASK, PPC405 | BOOKE, { RS } }, +{ "mtsprg7", XSPR(31,467,279), XSPR_MASK, PPC405 | BOOKE, { RS } }, +{ "mtasr", XSPR(31,467,280), XSPR_MASK, PPC64, { RS } }, +{ "mtear", XSPR(31,467,282), XSPR_MASK, PPC, { RS } }, +{ "mttbl", XSPR(31,467,284), XSPR_MASK, PPC, { RS } }, +{ "mttbu", XSPR(31,467,285), XSPR_MASK, PPC, { RS } }, +{ "mtdbsr", XSPR(31,467,304), XSPR_MASK, BOOKE, { RS } }, +{ "mtdbsr", XSPR(31,467,1008), XSPR_MASK, PPC403, { RS } }, +{ "mtdbcr0", XSPR(31,467,308), XSPR_MASK, BOOKE, { RS } }, +{ "mtdbcr0", XSPR(31,467,1010), XSPR_MASK, PPC405, { RS } }, +{ "mtdbcr1", XSPR(31,467,309), XSPR_MASK, BOOKE, { RS } }, +{ "mtdbcr1", XSPR(31,467,957), XSPR_MASK, PPC405, { RS } }, +{ "mtdbcr2", XSPR(31,467,310), XSPR_MASK, BOOKE, { RS } }, +{ "mtiac1", XSPR(31,467,312), XSPR_MASK, BOOKE, { RS } }, +{ "mtiac1", XSPR(31,467,1012), XSPR_MASK, PPC403, { RS } }, +{ "mtiac2", XSPR(31,467,313), XSPR_MASK, BOOKE, { RS } }, +{ "mtiac2", XSPR(31,467,1013), XSPR_MASK, PPC403, { RS } }, +{ "mtiac3", XSPR(31,467,314), XSPR_MASK, BOOKE, { RS } }, +{ "mtiac3", XSPR(31,467,948), XSPR_MASK, PPC405, { RS } }, +{ "mtiac4", XSPR(31,467,315), XSPR_MASK, BOOKE, { RS } }, +{ "mtiac4", XSPR(31,467,949), XSPR_MASK, PPC405, { RS } }, +{ "mtdac1", XSPR(31,467,316), XSPR_MASK, BOOKE, { RS } }, +{ "mtdac1", XSPR(31,467,1014), XSPR_MASK, PPC403, { RS } }, +{ "mtdac2", XSPR(31,467,317), XSPR_MASK, BOOKE, { RS } }, +{ "mtdac2", XSPR(31,467,1015), XSPR_MASK, PPC403, { RS } }, +{ "mtdvc1", XSPR(31,467,318), XSPR_MASK, BOOKE, { RS } }, +{ "mtdvc1", XSPR(31,467,950), XSPR_MASK, PPC405, { RS } }, +{ "mtdvc2", XSPR(31,467,319), XSPR_MASK, BOOKE, { RS } }, +{ "mtdvc2", XSPR(31,467,951), XSPR_MASK, PPC405, { RS } }, +{ "mttsr", XSPR(31,467,336), XSPR_MASK, BOOKE, { RS } }, +{ "mttsr", XSPR(31,467,984), XSPR_MASK, PPC403, { RS } }, +{ "mttcr", XSPR(31,467,340), XSPR_MASK, BOOKE, { RS } }, +{ "mttcr", XSPR(31,467,986), XSPR_MASK, PPC403, { RS } }, +{ "mtivor0", XSPR(31,467,400), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor1", XSPR(31,467,401), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor2", XSPR(31,467,402), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor3", XSPR(31,467,403), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor4", XSPR(31,467,404), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor5", XSPR(31,467,405), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor6", XSPR(31,467,406), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor7", XSPR(31,467,407), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor8", XSPR(31,467,408), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor9", XSPR(31,467,409), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor10", XSPR(31,467,410), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor11", XSPR(31,467,411), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor12", XSPR(31,467,412), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor13", XSPR(31,467,413), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor14", XSPR(31,467,414), XSPR_MASK, BOOKE, { RS } }, +{ "mtivor15", XSPR(31,467,415), XSPR_MASK, BOOKE, { RS } }, +{ "mtspefscr", XSPR(31,467,512), XSPR_MASK, PPCSPE, { RS } }, +{ "mtbbear", XSPR(31,467,513), XSPR_MASK, PPCBRLK, { RS } }, +{ "mtbbtar", XSPR(31,467,514), XSPR_MASK, PPCBRLK, { RS } }, +{ "mtivor32", XSPR(31,467,528), XSPR_MASK, PPCSPE, { RS } }, +{ "mtivor33", XSPR(31,467,529), XSPR_MASK, PPCSPE, { RS } }, +{ "mtivor34", XSPR(31,467,530), XSPR_MASK, PPCSPE, { RS } }, +{ "mtivor35", XSPR(31,467,531), XSPR_MASK, PPCPMR, { RS } }, +{ "mtibatu", XSPR(31,467,528), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, +{ "mtibatl", XSPR(31,467,529), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, +{ "mtdbatu", XSPR(31,467,536), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, +{ "mtdbatl", XSPR(31,467,537), XSPRBAT_MASK, PPC, { SPRBAT, RS } }, +{ "mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, { RS } }, +{ "mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, { RS } }, +{ "mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, { RS } }, +{ "mtummcr0", XSPR(31,467,936), XSPR_MASK, PPC750, { RS } }, +{ "mtupmc1", XSPR(31,467,937), XSPR_MASK, PPC750, { RS } }, +{ "mtupmc2", XSPR(31,467,938), XSPR_MASK, PPC750, { RS } }, +{ "mtusia", XSPR(31,467,939), XSPR_MASK, PPC750, { RS } }, +{ "mtummcr1", XSPR(31,467,940), XSPR_MASK, PPC750, { RS } }, +{ "mtupmc3", XSPR(31,467,941), XSPR_MASK, PPC750, { RS } }, +{ "mtupmc4", XSPR(31,467,942), XSPR_MASK, PPC750, { RS } }, +{ "mtzpr", XSPR(31,467,944), XSPR_MASK, PPC403, { RS } }, +{ "mtccr0", XSPR(31,467,947), XSPR_MASK, PPC405, { RS } }, +{ "mtmmcr0", XSPR(31,467,952), XSPR_MASK, PPC750, { RS } }, +{ "mtsgr", XSPR(31,467,953), XSPR_MASK, PPC403, { RS } }, +{ "mtpmc1", XSPR(31,467,953), XSPR_MASK, PPC750, { RS } }, +{ "mtdcwr", XSPR(31,467,954), XSPR_MASK, PPC403, { RS } }, +{ "mtpmc2", XSPR(31,467,954), XSPR_MASK, PPC750, { RS } }, +{ "mtsler", XSPR(31,467,955), XSPR_MASK, PPC405, { RS } }, +{ "mtsia", XSPR(31,467,955), XSPR_MASK, PPC750, { RS } }, +{ "mtsu0r", XSPR(31,467,956), XSPR_MASK, PPC405, { RS } }, +{ "mtmmcr1", XSPR(31,467,956), XSPR_MASK, PPC750, { RS } }, +{ "mtpmc3", XSPR(31,467,957), XSPR_MASK, PPC750, { RS } }, +{ "mtpmc4", XSPR(31,467,958), XSPR_MASK, PPC750, { RS } }, +{ "mticdbdr", XSPR(31,467,979), XSPR_MASK, PPC403, { RS } }, +{ "mtevpr", XSPR(31,467,982), XSPR_MASK, PPC403, { RS } }, +{ "mtcdbcr", XSPR(31,467,983), XSPR_MASK, PPC403, { RS } }, +{ "mtpit", XSPR(31,467,987), XSPR_MASK, PPC403, { RS } }, +{ "mttbhi", XSPR(31,467,988), XSPR_MASK, PPC403, { RS } }, +{ "mttblo", XSPR(31,467,989), XSPR_MASK, PPC403, { RS } }, +{ "mtsrr2", XSPR(31,467,990), XSPR_MASK, PPC403, { RS } }, +{ "mtsrr3", XSPR(31,467,991), XSPR_MASK, PPC403, { RS } }, +{ "mtl2cr", XSPR(31,467,1017), XSPR_MASK, PPC750, { RS } }, +{ "mtdccr", XSPR(31,467,1018), XSPR_MASK, PPC403, { RS } }, +{ "mticcr", XSPR(31,467,1019), XSPR_MASK, PPC403, { RS } }, +{ "mtictc", XSPR(31,467,1019), XSPR_MASK, PPC750, { RS } }, +{ "mtpbl1", XSPR(31,467,1020), XSPR_MASK, PPC403, { RS } }, +{ "mtthrm1", XSPR(31,467,1020), XSPR_MASK, PPC750, { RS } }, +{ "mtpbu1", XSPR(31,467,1021), XSPR_MASK, PPC403, { RS } }, +{ "mtthrm2", XSPR(31,467,1021), XSPR_MASK, PPC750, { RS } }, +{ "mtpbl2", XSPR(31,467,1022), XSPR_MASK, PPC403, { RS } }, +{ "mtthrm3", XSPR(31,467,1022), XSPR_MASK, PPC750, { RS } }, +{ "mtpbu2", XSPR(31,467,1023), XSPR_MASK, PPC403, { RS } }, +{ "mtspr", X(31,467), X_MASK, COM, { SPR, RS } }, { "dcbi", X(31,470), XRT_MASK, PPC, { RA, RB } }, @@ -3512,7 +4061,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "dcbie", X(31,478), XRT_MASK, BOOKE64, { RA, RB } }, -{ "dcread", X(31,486), X_MASK, PPC403, { RT, RA, RB }}, +{ "dcread", X(31,486), X_MASK, PPC403|PPC440, { RT, RA, RB }}, + +{ "mtpmr", X(31,462), X_MASK, PPCPMR, { PMR, RS }}, + +{ "icbtls", X(31,486), X_MASK, PPCCHLK, { CT, RA, RB }}, { "nabs", XO(31,488,0,0), XORB_MASK, M601, { RT, RA } }, { "subfme64",XO(31,488,0,0), XORB_MASK, BOOKE64, { RT, RA } }, @@ -3534,6 +4087,8 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "divwo", XO(31,491,1,0), XO_MASK, PPC, { RT, RA, RB } }, { "divwo.", XO(31,491,1,1), XO_MASK, PPC, { RT, RA, RB } }, +{ "icbtlse", X(31,494), X_MASK, PPCCHLK64, { CT, RA, RB }}, + { "slbia", X(31,498), 0xffffffff, PPC64, { 0 } }, { "cli", X(31,502), XRB_MASK, POWER, { RT, RA } }, @@ -3542,17 +4097,18 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mcrxr", X(31,512), XRARB_MASK|(3<<21), COM, { BF } }, -{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE, { BF } }, +{ "bblels", X(31,518), X_MASK, PPCBRLK, { 0 }}, +{ "mcrxr64", X(31,544), XRARB_MASK|(3<<21), BOOKE64, { BF } }, { "clcs", X(31,531), XRB_MASK, M601, { RT, RA } }, -{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA, RB } }, +{ "lswx", X(31,533), X_MASK, PPCCOM, { RT, RA0, RB } }, { "lsx", X(31,533), X_MASK, PWRCOM, { RT, RA, RB } }, -{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA, RB } }, +{ "lwbrx", X(31,534), X_MASK, PPCCOM, { RT, RA0, RB } }, { "lbrx", X(31,534), X_MASK, PWRCOM, { RT, RA, RB } }, -{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA, RB } }, +{ "lfsx", X(31,535), X_MASK, COM, { FRT, RA0, RB } }, { "srw", XRC(31,536,0), X_MASK, PPCCOM, { RA, RS, RB } }, { "sr", XRC(31,536,0), X_MASK, PWRCOM, { RA, RS, RB } }, @@ -3568,9 +4124,11 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "maskir", XRC(31,541,0), X_MASK, M601, { RA, RS, RB } }, { "maskir.", XRC(31,541,1), X_MASK, M601, { RA, RS, RB } }, -{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA, RB } }, +{ "lwbrxe", X(31,542), X_MASK, BOOKE64, { RT, RA0, RB } }, + +{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA0, RB } }, -{ "lfsxe", X(31,543), X_MASK, BOOKE64, { FRT, RA, RB } }, +{ "bbelr", X(31,550), X_MASK, PPCBRLK, { 0 }}, { "tlbsync", X(31,566), 0xffffffff, PPC, { 0 } }, @@ -3580,18 +4138,18 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfsr", X(31,595), XRB_MASK|(1<<20), COM32, { RT, SR } }, -{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA, NB } }, -{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA, NB } }, +{ "lswi", X(31,597), X_MASK, PPCCOM, { RT, RA0, NB } }, +{ "lsi", X(31,597), X_MASK, PWRCOM, { RT, RA0, NB } }, -{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPCONLY, { 0 } }, +{ "lwsync", XSYNC(31,598,1), 0xffffffff, PPC, { 0 } }, { "ptesync", XSYNC(31,598,2), 0xffffffff, PPC64, { 0 } }, +{ "msync", X(31,598), 0xffffffff, BOOKE, { 0 } }, { "sync", X(31,598), XSYNC_MASK, PPCCOM, { LS } }, { "dcs", X(31,598), 0xffffffff, PWRCOM, { 0 } }, -{ "msync", X(31,598), 0xf80007fe, BOOKE, { 0 } }, -{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA, RB } }, +{ "lfdx", X(31,599), X_MASK, COM, { FRT, RA0, RB } }, -{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA, RB } }, +{ "lfdxe", X(31,607), X_MASK, BOOKE64, { FRT, RA0, RB } }, { "mfsri", X(31,627), X_MASK, PWRCOM, { RT, RA, RB } }, @@ -3603,13 +4161,13 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "mfsrin", X(31,659), XRA_MASK, PPC32, { RT, RB } }, -{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA, RB } }, -{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA, RB } }, +{ "stswx", X(31,661), X_MASK, PPCCOM, { RS, RA0, RB } }, +{ "stsx", X(31,661), X_MASK, PWRCOM, { RS, RA0, RB } }, -{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA, RB } }, -{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA, RB } }, +{ "stwbrx", X(31,662), X_MASK, PPCCOM, { RS, RA0, RB } }, +{ "stbrx", X(31,662), X_MASK, PWRCOM, { RS, RA0, RB } }, -{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA, RB } }, +{ "stfsx", X(31,663), X_MASK, COM, { FRS, RA0, RB } }, { "srq", XRC(31,664,0), X_MASK, M601, { RA, RS, RB } }, { "srq.", XRC(31,664,1), X_MASK, M601, { RA, RS, RB } }, @@ -3617,9 +4175,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sre", XRC(31,665,0), X_MASK, M601, { RA, RS, RB } }, { "sre.", XRC(31,665,1), X_MASK, M601, { RA, RS, RB } }, -{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA, RB } }, +{ "stwbrxe", X(31,670), X_MASK, BOOKE64, { RS, RA0, RB } }, -{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA, RB } }, +{ "stfsxe", X(31,671), X_MASK, BOOKE64, { FRS, RA0, RB } }, { "stfsux", X(31,695), X_MASK, COM, { FRS, RAS, RB } }, @@ -3628,10 +4186,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stfsuxe", X(31,703), X_MASK, BOOKE64, { FRS, RAS, RB } }, -{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA, NB } }, -{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA, NB } }, +{ "stswi", X(31,725), X_MASK, PPCCOM, { RS, RA0, NB } }, +{ "stsi", X(31,725), X_MASK, PWRCOM, { RS, RA0, NB } }, -{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA, RB } }, +{ "stfdx", X(31,727), X_MASK, COM, { FRS, RA0, RB } }, { "srlq", XRC(31,728,0), X_MASK, M601, { RA, RS, RB } }, { "srlq.", XRC(31,728,1), X_MASK, M601, { RA, RS, RB } }, @@ -3639,10 +4197,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "sreq", XRC(31,729,0), X_MASK, M601, { RA, RS, RB } }, { "sreq.", XRC(31,729,1), X_MASK, M601, { RA, RS, RB } }, -{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA, RB } }, +{ "stfdxe", X(31,735), X_MASK, BOOKE64, { FRS, RA0, RB } }, -{ "dcba", X(31,758), XRT_MASK, PPC405, { RA, RB } }, -{ "dcba", X(31,758), XRT_MASK, BOOKE, { RA, RB } }, +{ "dcba", X(31,758), XRT_MASK, PPC405 | BOOKE, { RA, RB } }, { "stfdux", X(31,759), X_MASK, COM, { FRS, RAS, RB } }, @@ -3654,9 +4211,9 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stfduxe", X(31,767), X_MASK, BOOKE64, { FRS, RAS, RB } }, { "tlbivax", X(31,786), XRT_MASK, BOOKE, { RA, RB } }, -{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE, { RA, RB } }, +{ "tlbivaxe",X(31,787), XRT_MASK, BOOKE64, { RA, RB } }, -{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA, RB } }, +{ "lhbrx", X(31,790), X_MASK, COM, { RT, RA0, RB } }, { "sraw", XRC(31,792,0), X_MASK, PPCCOM, { RA, RS, RB } }, { "sra", XRC(31,792,0), X_MASK, PWRCOM, { RA, RS, RB } }, @@ -3666,10 +4223,10 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "srad", XRC(31,794,0), X_MASK, PPC64, { RA, RS, RB } }, { "srad.", XRC(31,794,1), X_MASK, PPC64, { RA, RS, RB } }, -{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA, RB } }, +{ "lhbrxe", X(31,798), X_MASK, BOOKE64, { RT, RA0, RB } }, -{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA, RB } }, -{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA, RB } }, +{ "ldxe", X(31,799), X_MASK, BOOKE64, { RT, RA0, RB } }, +{ "lduxe", X(31,831), X_MASK, BOOKE64, { RT, RA0, RB } }, { "rac", X(31,818), X_MASK, PWRCOM, { RT, RA, RB } }, @@ -3683,20 +4240,19 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "slbmfev", X(31,851), XRA_MASK, PPC64, { RT, RB } }, +{ "mbar", X(31,854), X_MASK, BOOKE, { MO } }, { "eieio", X(31,854), 0xffffffff, PPC, { 0 } }, -{ "mbar", X(31,854), 0xffffffff, BOOKE, { MO } }, - -{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } }, -{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } }, { "tlbsx", XRC(31,914,0), X_MASK, BOOKE, { RA, RB } }, +{ "tlbsx", XRC(31,914,0), X_MASK, PPC403, { RT, RA, RB } }, { "tlbsx.", XRC(31,914,1), X_MASK, BOOKE, { RA, RB } }, -{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE, { RA, RB } }, -{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE, { RA, RB } }, +{ "tlbsx.", XRC(31,914,1), X_MASK, PPC403, { RT, RA, RB } }, +{ "tlbsxe", XRC(31,915,0), X_MASK, BOOKE64, { RA, RB } }, +{ "tlbsxe.", XRC(31,915,1), X_MASK, BOOKE64, { RA, RB } }, { "slbmfee", X(31,915), XRA_MASK, PPC64, { RT, RB } }, -{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA, RB } }, +{ "sthbrx", X(31,918), X_MASK, COM, { RS, RA0, RB } }, { "sraq", XRC(31,920,0), X_MASK, M601, { RA, RS, RB } }, { "sraq.", XRC(31,920,1), X_MASK, M601, { RA, RS, RB } }, @@ -3709,14 +4265,14 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "extsh.", XRC(31,922,1), XRB_MASK, PPCCOM, { RA, RS } }, { "exts.", XRC(31,922,1), XRB_MASK, PWRCOM, { RA, RS } }, -{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA, RB } }, - -{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA, RB } }, +{ "sthbrxe", X(31,926), X_MASK, BOOKE64, { RS, RA0, RB } }, -{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } }, +{ "stdxe", X(31,927), X_MASK, BOOKE64, { RS, RA0, RB } }, { "tlbrehi", XTLB(31,946,0), XTLB_MASK, PPC403, { RT, RA } }, { "tlbrelo", XTLB(31,946,1), XTLB_MASK, PPC403, { RT, RA } }, +{ "tlbre", X(31,946), X_MASK, BOOKE, { 0 } }, +{ "tlbre", X(31,946), X_MASK, PPC403, { RS, RA, SH } }, { "sraiq", XRC(31,952,0), X_MASK, M601, { RA, RS, SH } }, { "sraiq.", XRC(31,952,1), X_MASK, M601, { RA, RS, SH } }, @@ -3726,27 +4282,24 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stduxe", X(31,959), X_MASK, BOOKE64, { RS, RAS, RB } }, -{ "iccci", X(31,966), XRT_MASK, PPC403, { RA, RB } }, - -{ "tlbwe", X(31,978), X_MASK, BOOKE, { 0 } }, - -{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, +{ "iccci", X(31,966), XRT_MASK, PPC403|PPC440, { RA, RB } }, { "tlbwehi", XTLB(31,978,0), XTLB_MASK, PPC403, { RT, RA } }, { "tlbwelo", XTLB(31,978,1), XTLB_MASK, PPC403, { RT, RA } }, -{ "tlbwe", X(31,978), X_MASK, PPC403, { RS, RA, SH } }, +{ "tlbwe", X(31,978), X_MASK, PPC403|BOOKE, { RSO, RAOPT, SHO } }, +{ "tlbld", X(31,978), XRTRA_MASK, PPC, { RB } }, { "icbi", X(31,982), XRT_MASK, PPC, { RA, RB } }, -{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA, RB } }, +{ "stfiwx", X(31,983), X_MASK, PPC, { FRS, RA0, RB } }, -{ "extsw", XRC(31,986,0), XRB_MASK, PPC | BOOKE64, { RA, RS } }, -{ "extsw.", XRC(31,986,1), XRB_MASK, PPC | BOOKE64, { RA, RS } }, +{ "extsw", XRC(31,986,0), XRB_MASK, PPC64 | BOOKE64,{ RA, RS } }, +{ "extsw.", XRC(31,986,1), XRB_MASK, PPC64, { RA, RS } }, -{ "icread", X(31,998), XRT_MASK, PPC403, { RA, RB } }, +{ "icread", X(31,998), XRT_MASK, PPC403|PPC440, { RA, RB } }, { "icbie", X(31,990), XRT_MASK, BOOKE64, { RA, RB } }, -{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA, RB } }, +{ "stfiwxe", X(31,991), X_MASK, BOOKE64, { FRS, RA0, RB } }, { "tlbli", X(31,1010), XRTRA_MASK, PPC, { RB } }, @@ -3768,84 +4321,86 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stvx", X(31, 231), X_MASK, PPCVEC, { VS, RA, RB } }, { "stvxl", X(31, 487), X_MASK, PPCVEC, { VS, RA, RB } }, -{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA } }, -{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA } }, +{ "lwz", OP(32), OP_MASK, PPCCOM, { RT, D, RA0 } }, +{ "l", OP(32), OP_MASK, PWRCOM, { RT, D, RA0 } }, { "lwzu", OP(33), OP_MASK, PPCCOM, { RT, D, RAL } }, -{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA } }, +{ "lu", OP(33), OP_MASK, PWRCOM, { RT, D, RA0 } }, -{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA } }, +{ "lbz", OP(34), OP_MASK, COM, { RT, D, RA0 } }, { "lbzu", OP(35), OP_MASK, COM, { RT, D, RAL } }, -{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA } }, -{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA } }, +{ "stw", OP(36), OP_MASK, PPCCOM, { RS, D, RA0 } }, +{ "st", OP(36), OP_MASK, PWRCOM, { RS, D, RA0 } }, { "stwu", OP(37), OP_MASK, PPCCOM, { RS, D, RAS } }, -{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA } }, +{ "stu", OP(37), OP_MASK, PWRCOM, { RS, D, RA0 } }, -{ "stb", OP(38), OP_MASK, COM, { RS, D, RA } }, +{ "stb", OP(38), OP_MASK, COM, { RS, D, RA0 } }, { "stbu", OP(39), OP_MASK, COM, { RS, D, RAS } }, -{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA } }, +{ "lhz", OP(40), OP_MASK, COM, { RT, D, RA0 } }, { "lhzu", OP(41), OP_MASK, COM, { RT, D, RAL } }, -{ "lha", OP(42), OP_MASK, COM, { RT, D, RA } }, +{ "lha", OP(42), OP_MASK, COM, { RT, D, RA0 } }, { "lhau", OP(43), OP_MASK, COM, { RT, D, RAL } }, -{ "sth", OP(44), OP_MASK, COM, { RS, D, RA } }, +{ "sth", OP(44), OP_MASK, COM, { RS, D, RA0 } }, { "sthu", OP(45), OP_MASK, COM, { RS, D, RAS } }, { "lmw", OP(46), OP_MASK, PPCCOM, { RT, D, RAM } }, -{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA } }, +{ "lm", OP(46), OP_MASK, PWRCOM, { RT, D, RA0 } }, -{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA } }, -{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA } }, +{ "stmw", OP(47), OP_MASK, PPCCOM, { RS, D, RA0 } }, +{ "stm", OP(47), OP_MASK, PWRCOM, { RS, D, RA0 } }, -{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA } }, +{ "lfs", OP(48), OP_MASK, COM, { FRT, D, RA0 } }, { "lfsu", OP(49), OP_MASK, COM, { FRT, D, RAS } }, -{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA } }, +{ "lfd", OP(50), OP_MASK, COM, { FRT, D, RA0 } }, { "lfdu", OP(51), OP_MASK, COM, { FRT, D, RAS } }, -{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA } }, +{ "stfs", OP(52), OP_MASK, COM, { FRS, D, RA0 } }, { "stfsu", OP(53), OP_MASK, COM, { FRS, D, RAS } }, -{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA } }, +{ "stfd", OP(54), OP_MASK, COM, { FRS, D, RA0 } }, { "stfdu", OP(55), OP_MASK, COM, { FRS, D, RAS } }, -{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA } }, +{ "lq", OP(56), OP_MASK, POWER4, { RTQ, DQ, RAQ } }, + +{ "lfq", OP(56), OP_MASK, POWER2, { FRT, D, RA0 } }, -{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA } }, +{ "lfqu", OP(57), OP_MASK, POWER2, { FRT, D, RA0 } }, -{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA } }, +{ "lbze", DEO(58,0), DE_MASK, BOOKE64, { RT, DE, RA0 } }, { "lbzue", DEO(58,1), DE_MASK, BOOKE64, { RT, DE, RAL } }, -{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA } }, +{ "lhze", DEO(58,2), DE_MASK, BOOKE64, { RT, DE, RA0 } }, { "lhzue", DEO(58,3), DE_MASK, BOOKE64, { RT, DE, RAL } }, -{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA } }, +{ "lhae", DEO(58,4), DE_MASK, BOOKE64, { RT, DE, RA0 } }, { "lhaue", DEO(58,5), DE_MASK, BOOKE64, { RT, DE, RAL } }, -{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA } }, +{ "lwze", DEO(58,6), DE_MASK, BOOKE64, { RT, DE, RA0 } }, { "lwzue", DEO(58,7), DE_MASK, BOOKE64, { RT, DE, RAL } }, -{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA } }, +{ "stbe", DEO(58,8), DE_MASK, BOOKE64, { RS, DE, RA0 } }, { "stbue", DEO(58,9), DE_MASK, BOOKE64, { RS, DE, RAS } }, -{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA } }, +{ "sthe", DEO(58,10), DE_MASK, BOOKE64, { RS, DE, RA0 } }, { "sthue", DEO(58,11), DE_MASK, BOOKE64, { RS, DE, RAS } }, -{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA } }, +{ "stwe", DEO(58,14), DE_MASK, BOOKE64, { RS, DE, RA0 } }, { "stwue", DEO(58,15), DE_MASK, BOOKE64, { RS, DE, RAS } }, -{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA } }, +{ "ld", DSO(58,0), DS_MASK, PPC64, { RT, DS, RA0 } }, { "ldu", DSO(58,1), DS_MASK, PPC64, { RT, DS, RAL } }, -{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA } }, +{ "lwa", DSO(58,2), DS_MASK, PPC64, { RT, DS, RA0 } }, { "fdivs", A(59,18,0), AFRC_MASK, PPC, { FRT, FRA, FRB } }, { "fdivs.", A(59,18,1), AFRC_MASK, PPC, { FRT, FRA, FRB } }, @@ -3881,23 +4436,25 @@ const struct powerpc_opcode powerpc_opcodes[] = { { "stfqu", OP(61), OP_MASK, POWER2, { FRS, D, RA } }, -{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA } }, -{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA } }, -{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA } }, +{ "lde", DEO(62,0), DE_MASK, BOOKE64, { RT, DES, RA0 } }, +{ "ldue", DEO(62,1), DE_MASK, BOOKE64, { RT, DES, RA0 } }, +{ "lfse", DEO(62,4), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, { "lfsue", DEO(62,5), DE_MASK, BOOKE64, { FRT, DES, RAS } }, -{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA } }, +{ "lfde", DEO(62,6), DE_MASK, BOOKE64, { FRT, DES, RA0 } }, { "lfdue", DEO(62,7), DE_MASK, BOOKE64, { FRT, DES, RAS } }, -{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA } }, +{ "stde", DEO(62,8), DE_MASK, BOOKE64, { RS, DES, RA0 } }, { "stdue", DEO(62,9), DE_MASK, BOOKE64, { RS, DES, RAS } }, -{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA } }, +{ "stfse", DEO(62,12), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, { "stfsue", DEO(62,13), DE_MASK, BOOKE64, { FRS, DES, RAS } }, -{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA } }, +{ "stfde", DEO(62,14), DE_MASK, BOOKE64, { FRS, DES, RA0 } }, { "stfdue", DEO(62,15), DE_MASK, BOOKE64, { FRS, DES, RAS } }, -{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA } }, +{ "std", DSO(62,0), DS_MASK, PPC64, { RS, DS, RA0 } }, { "stdu", DSO(62,1), DS_MASK, PPC64, { RS, DS, RAS } }, +{ "stq", DSO(62,2), DS_MASK, POWER4, { RSQ, DS, RA0 } }, + { "fcmpu", X(63,0), X_MASK|(3<<21), COM, { BF, FRA, FRB } }, { "frsp", XRC(63,12,0), XRA_MASK, COM, { FRT, FRB } }, @@ -4039,8 +4596,8 @@ const struct powerpc_macro powerpc_macros[] = { { "extlwi", 4, PPCCOM, "rlwinm %0,%1,%3,0,(%2)-1" }, { "extlwi.", 4, PPCCOM, "rlwinm. %0,%1,%3,0,(%2)-1" }, -{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,(%2)+(%3),32-(%2),31" }, -{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,(%2)+(%3),32-(%2),31" }, +{ "extrwi", 4, PPCCOM, "rlwinm %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, +{ "extrwi.", 4, PPCCOM, "rlwinm. %0,%1,((%2)+(%3))&((%2)+(%3)<>32),32-(%2),31" }, { "inslwi", 4, PPCCOM, "rlwimi %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1" }, { "inslwi.", 4, PPCCOM, "rlwimi. %0,%1,(-(%3)!31)&((%3)|31),%3,(%2)+(%3)-1"}, { "insrwi", 4, PPCCOM, "rlwimi %0,%1,32-((%2)+(%3)),%3,(%2)+(%3)-1" }, @@ -4059,7 +4616,6 @@ const struct powerpc_macro powerpc_macros[] = { { "clrrwi.", 3, PPCCOM, "rlwinm. %0,%1,0,0,31-(%2)" }, { "clrlslwi",4, PPCCOM, "rlwinm %0,%1,%3,(%2)-(%3),31-(%3)" }, { "clrlslwi.",4, PPCCOM, "rlwinm. %0,%1,%3,(%2)-(%3),31-(%3)" }, - }; const int powerpc_num_macros = diff --git a/contrib/binutils/opcodes/s390-dis.c b/contrib/binutils/opcodes/s390-dis.c index 8745a89..42f5151 100644 --- a/contrib/binutils/opcodes/s390-dis.c +++ b/contrib/binutils/opcodes/s390-dis.c @@ -57,7 +57,7 @@ init_disasm (info) current_arch_mask = 1 << S390_OPCODE_ESA; break; case bfd_mach_s390_64: - current_arch_mask = 1 << S390_OPCODE_ESAME; + current_arch_mask = 1 << S390_OPCODE_ZARCH; break; default: abort (); @@ -89,6 +89,10 @@ s390_extract_operand (insn, operand) val >>= -bits; val &= ((1U << (operand->bits - 1)) << 1) - 1; + /* Check for special long displacement case. */ + if (operand->bits == 20 && operand->shift == 20) + val = (val & 0xff) << 12 | (val & 0xfff00) >> 8; + /* Sign extend value if the operand is signed or pc relative. */ if ((operand->flags & (S390_OPERAND_SIGNED | S390_OPERAND_PCREL)) && (val & (1U << (operand->bits - 1)))) @@ -161,7 +165,7 @@ print_insn_s390 (memaddr, info) const unsigned char *opindex; /* Check architecture. */ - if (!(opcode->architecture & current_arch_mask)) + if (!(opcode->modes & current_arch_mask)) continue; /* Check signature of the opcode. */ if ((buffer[1] & opcode->mask[1]) != opcode->opcode[1] diff --git a/contrib/binutils/opcodes/s390-mkopc.c b/contrib/binutils/opcodes/s390-mkopc.c index d79ff81..34188e62 100644 --- a/contrib/binutils/opcodes/s390-mkopc.c +++ b/contrib/binutils/opcodes/s390-mkopc.c @@ -23,21 +23,29 @@ #include <stdlib.h> #include <string.h> -/* ARCHBITS_ESA and ARCH_ESAME correspond to the bit numbers defined - by s390_opcode_arch_val in include/opcode/s390.h: - ARCHBITS_ESAONLY = (1<<S390_OPCODE_ESA) - ARCHBITS_ESA = (1<<S390_OPCODE_ESA) + (1<<S390_OPCODE_ESAME) - ARCHBITS_ESA = (1<<S390_OPCODE_ESAME). */ -#define ARCHBITS_ESAONLY 1 -#define ARCHBITS_ESA 3 -#define ARCHBITS_ESAME 2 +/* Taken from opcodes/s390.h */ +enum s390_opcode_mode_val + { + S390_OPCODE_ESA = 0, + S390_OPCODE_ZARCH + }; + +enum s390_opcode_cpu_val + { + S390_OPCODE_G5 = 0, + S390_OPCODE_G6, + S390_OPCODE_Z900, + S390_OPCODE_Z990 + }; struct op_struct { char opcode[16]; char mnemonic[16]; char format[16]; - int archbits; + int mode_bits; + int min_cpu; + unsigned long long sort_value; int no_nibbles; }; @@ -57,7 +65,8 @@ createTable (void) /* `insertOpcode': insert an op_struct into sorted opcode array. */ static void -insertOpcode (char *opcode, char *mnemonic, char *format, int archbits) +insertOpcode (char *opcode, char *mnemonic, char *format, + int min_cpu, int mode_bits) { char *str; unsigned long long sort_value; @@ -87,6 +96,7 @@ insertOpcode (char *opcode, char *mnemonic, char *format, int archbits) str ++; } sort_value <<= 4*(16 - ix); + sort_value += (min_cpu << 8) + mode_bits; no_nibbles = ix; for (ix = 0; ix < no_ops; ix++) if (sort_value > op_array[ix].sort_value) @@ -98,7 +108,8 @@ insertOpcode (char *opcode, char *mnemonic, char *format, int archbits) strcpy(op_array[ix].format, format); op_array[ix].sort_value = sort_value; op_array[ix].no_nibbles = no_nibbles; - op_array[ix].archbits = archbits; + op_array[ix].min_cpu = min_cpu; + op_array[ix].mode_bits = mode_bits; no_ops++; } @@ -136,7 +147,8 @@ dumpTable (void) op_array[ix].no_nibbles*4, op_array[ix].opcode); printf ("MASK_%s, INSTR_%s, ", op_array[ix].format, op_array[ix].format); - printf ("%i}", op_array[ix].archbits); + printf ("%i, ", op_array[ix].mode_bits); + printf ("%i}", op_array[ix].min_cpu); if (ix < no_ops-1) printf (",\n"); else @@ -162,24 +174,52 @@ main (void) char mnemonic[16]; char format[16]; char description[64]; - char archtag[16]; - int archbits; + char cpu_string[16]; + char modes_string[16]; + int min_cpu; + int mode_bits; + char *str; if (currentLine[0] == '#') continue; memset (opcode, 0, 8); - if (sscanf (currentLine, "%15s %15s %15s \"%[^\"]\" %15s", - opcode, mnemonic, format, description, archtag) == 5) + if (sscanf (currentLine, "%15s %15s %15s \"%[^\"]\" %15s %15s", + opcode, mnemonic, format, description, + cpu_string, modes_string) == 6) { - if (strcmp (archtag, "esaonly") == 0) - archbits = ARCHBITS_ESAONLY; - else if (strcmp (archtag, "esa") == 0) - archbits = ARCHBITS_ESA; - else if (strcmp (archtag, "esame") == 0) - archbits = ARCHBITS_ESAME; - else - archbits = 0; - insertOpcode (opcode, mnemonic, format, archbits); + if (strcmp (cpu_string, "g5") == 0) + min_cpu = S390_OPCODE_G5; + else if (strcmp (cpu_string, "g6") == 0) + min_cpu = S390_OPCODE_G6; + else if (strcmp (cpu_string, "z900") == 0) + min_cpu = S390_OPCODE_Z900; + else if (strcmp (cpu_string, "z990") == 0) + min_cpu = S390_OPCODE_Z990; + else { + fprintf (stderr, "Couldn't parse cpu string %s\n", cpu_string); + exit (1); + } + + str = modes_string; + mode_bits = 0; + do { + if (strncmp (str, "esa", 3) == 0 + && (str[3] == 0 || str[3] == ',')) { + mode_bits |= 1 << S390_OPCODE_ESA; + str += 3; + } else if (strncmp (str, "zarch", 5) == 0 + && (str[5] == 0 || str[5] == ',')) { + mode_bits |= 1 << S390_OPCODE_ZARCH; + str += 5; + } else { + fprintf (stderr, "Couldn't parse modes string %s\n", + modes_string); + exit (1); + } + if (*str == ',') + str++; + } while (*str != 0); + insertOpcode (opcode, mnemonic, format, min_cpu, mode_bits); } else fprintf (stderr, "Couldn't scan line %s\n", currentLine); diff --git a/contrib/binutils/opcodes/s390-opc.c b/contrib/binutils/opcodes/s390-opc.c index 7cd8231..1a4b276 100644 --- a/contrib/binutils/opcodes/s390-opc.c +++ b/contrib/binutils/opcodes/s390-opc.c @@ -98,33 +98,35 @@ const struct s390_operand s390_operands[] = { 12, 20, S390_OPERAND_DISP }, #define D_36 25 /* Displacement starting at position 36 */ { 12, 36, S390_OPERAND_DISP }, +#define D20_20 26 /* 20 bit displacement starting at 20 */ + { 20, 20, S390_OPERAND_DISP|S390_OPERAND_SIGNED }, -#define L4_8 26 /* 4 bit length starting at position 8 */ +#define L4_8 27 /* 4 bit length starting at position 8 */ { 4, 8, S390_OPERAND_LENGTH }, -#define L4_12 27 /* 4 bit length starting at position 12 */ +#define L4_12 28 /* 4 bit length starting at position 12 */ { 4, 12, S390_OPERAND_LENGTH }, -#define L8_8 28 /* 8 bit length starting at position 8 */ +#define L8_8 29 /* 8 bit length starting at position 8 */ { 8, 8, S390_OPERAND_LENGTH }, -#define U4_8 29 /* 4 bit unsigned value starting at 8 */ +#define U4_8 30 /* 4 bit unsigned value starting at 8 */ { 4, 8, 0 }, -#define U4_12 30 /* 4 bit unsigned value starting at 12 */ +#define U4_12 31 /* 4 bit unsigned value starting at 12 */ { 4, 12, 0 }, -#define U4_16 31 /* 4 bit unsigned value starting at 16 */ +#define U4_16 32 /* 4 bit unsigned value starting at 16 */ { 4, 16, 0 }, -#define U4_20 32 /* 4 bit unsigned value starting at 20 */ +#define U4_20 33 /* 4 bit unsigned value starting at 20 */ { 4, 20, 0 }, -#define U8_8 33 /* 8 bit unsigned value starting at 8 */ +#define U8_8 34 /* 8 bit unsigned value starting at 8 */ { 8, 8, 0 }, -#define U8_16 34 /* 8 bit unsigned value starting at 16 */ +#define U8_16 35 /* 8 bit unsigned value starting at 16 */ { 8, 16, 0 }, -#define I16_16 35 /* 16 bit signed value starting at 16 */ +#define I16_16 36 /* 16 bit signed value starting at 16 */ { 16, 16, S390_OPERAND_SIGNED }, -#define U16_16 36 /* 16 bit unsigned value starting at 16 */ +#define U16_16 37 /* 16 bit unsigned value starting at 16 */ { 16, 16, 0 }, -#define J16_16 37 /* PC relative jump offset at 16 */ +#define J16_16 38 /* PC relative jump offset at 16 */ { 16, 16, S390_OPERAND_PCREL }, -#define J32_16 38 /* PC relative long offset at 16 */ +#define J32_16 39 /* PC relative long offset at 16 */ { 32, 16, S390_OPERAND_PCREL } }; @@ -194,6 +196,7 @@ const struct s390_operand s390_operands[] = #define INSTR_RRF_F0FF 4, { F_16,F_24,F_28,0,0,0 } /* e.g. madbr */ #define INSTR_RRF_FUFF 4, { F_24,F_16,F_28,U4_20,0,0 } /* e.g. didbr */ #define INSTR_RRF_RURR 4, { R_24,R_28,R_16,U4_20,0,0 } /* e.g. .insn */ +#define INSTR_RRF_R0RR 4, { R_24,R_28,R_16,0,0,0 } /* e.g. idte */ #define INSTR_RRF_U0FF 4, { F_24,U4_16,F_28,0,0,0 } /* e.g. cfxbr */ #define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfebr */ #define INSTR_RRF_U0FR 4, { F_24,U4_16,R_28,0,0,0 } /* e.g. cfxbr */ @@ -205,7 +208,11 @@ const struct s390_operand s390_operands[] = #define INSTR_RR_UR 2, { U4_8,R_12,0,0,0,0 } /* e.g. bcr */ #define INSTR_RSE_RRRD 6, { R_8,R_12,D_20,B_16,0,0 } /* e.g. lmh */ #define INSTR_RSE_RURD 6, { R_8,U4_12,D_20,B_16,0,0 } /* e.g. icmh */ +#define INSTR_RSL_R0RD 6, { R_8,D_20,B_16,0,0,0 } /* e.g. tp */ #define INSTR_RSI_RRP 4, { R_8,R_12,J16_16,0,0,0 } /* e.g. brxh */ +#define INSTR_RSY_RRRD 6, { R_8,R_12,D20_20,B_16,0,0 } /* e.g. stmy */ +#define INSTR_RSY_RURD 6, { R_8,U4_12,D20_20,B_16,0,0 } /* e.g. icmh */ +#define INSTR_RSY_AARD 6, { A_8,A_12,D20_20,B_16,0,0 } /* e.g. lamy */ #define INSTR_RS_AARD 4, { A_8,A_12,D_20,B_16,0,0 } /* e.g. lam */ #define INSTR_RS_CCRD 4, { C_8,C_12,D_20,B_16,0,0 } /* e.g. lctl */ #define INSTR_RS_R0RD 4, { R_8,D_20,B_16,0,0,0 } /* e.g. sll */ @@ -215,11 +222,14 @@ const struct s390_operand s390_operands[] = #define INSTR_RXE_RRRD 6, { R_8,D_20,X_12,B_16,0,0 } /* e.g. lg */ #define INSTR_RXF_FRRDF 6, { F_32,F_8,D_20,X_12,B_16,0 } /* e.g. madb */ #define INSTR_RXF_RRRDR 6, { R_32,R_8,D_20,X_12,B_16,0 } /* e.g. .insn */ +#define INSTR_RXY_RRRD 6, { R_8,D20_20,X_12,B_16,0,0 } /* e.g. ly */ +#define INSTR_RXY_FRRD 6, { F_8,D20_20,X_12,B_16,0,0 } /* e.g. ley */ #define INSTR_RX_0RRD 4, { D_20,X_12,B_16,0,0,0 } /* e.g. be */ #define INSTR_RX_FRRD 4, { F_8,D_20,X_12,B_16,0,0 } /* e.g. ae */ #define INSTR_RX_RRRD 4, { R_8,D_20,X_12,B_16,0,0 } /* e.g. l */ #define INSTR_RX_URRD 4, { U4_8,D_20,X_12,B_16,0,0 } /* e.g. bc */ #define INSTR_SI_URD 4, { D_20,B_16,U8_8,0,0,0 } /* e.g. cli */ +#define INSTR_SIY_URD 6, { D20_20,B_16,U8_8,0,0,0 } /* e.g. tmy */ #define INSTR_SSE_RDRD 6, { D_20,B_16,D_36,B_32,0,0 } /* e.g. mvsdk */ #define INSTR_SS_L0RDRD 6, { D_20,L8_8,B_16,D_36,B_32,0 } /* e.g. mvc */ #define INSTR_SS_LIRDRD 6, { D_20,L4_8,B_16,D_36,B_32,U4_12 } /* e.g. srp */ @@ -253,6 +263,7 @@ const struct s390_operand s390_operands[] = #define MASK_RRF_F0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_FUFF { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_RURR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RRF_R0RR { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_RRF_U0FF { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } #define MASK_RRF_U0FR { 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00 } @@ -264,21 +275,28 @@ const struct s390_operand s390_operands[] = #define MASK_RR_UR { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RSE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSE_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSL_R0RD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RSI_RRP { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RS_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RS_CCRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RS_R0RD { 0xff, 0x0f, 0x00, 0x00, 0x00, 0x00 } #define MASK_RS_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RS_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_RSY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_RURD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RSY_AARD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RXE_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RXE_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RXF_FRRDF { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RXF_RRRDR { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXY_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } +#define MASK_RXY_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_RX_0RRD { 0xff, 0xf0, 0x00, 0x00, 0x00, 0x00 } #define MASK_RX_FRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RX_RRRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_RX_URRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SI_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } +#define MASK_SIY_URD { 0xff, 0x00, 0x00, 0x00, 0x00, 0xff } #define MASK_SSE_RDRD { 0xff, 0xff, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_L0RDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } #define MASK_SS_LIRDRD { 0xff, 0x00, 0x00, 0x00, 0x00, 0x00 } @@ -293,23 +311,26 @@ const struct s390_operand s390_operands[] = const struct s390_opcode s390_opformats[] = { - { "e", OP8(0x00LL), MASK_E, INSTR_E, 3 }, - { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3 }, - { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3 }, - { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3 }, - { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3 }, - { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3 }, - { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3 }, - { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3 }, - { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3 }, - { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3 }, - { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3 }, - { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3 }, - { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3 }, - { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3 }, - { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3 }, - { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3 }, - { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3 }, + { "e", OP8(0x00LL), MASK_E, INSTR_E, 3, 0 }, + { "ri", OP8(0x00LL), MASK_RI_RI, INSTR_RI_RI, 3, 0 }, + { "rie", OP8(0x00LL), MASK_RIE_RRP, INSTR_RIE_RRP, 3, 0 }, + { "ril", OP8(0x00LL), MASK_RIL_RP, INSTR_RIL_RP, 3, 0 }, + { "rr", OP8(0x00LL), MASK_RR_RR, INSTR_RR_RR, 3, 0 }, + { "rre", OP8(0x00LL), MASK_RRE_RR, INSTR_RRE_RR, 3, 0 }, + { "rrf", OP8(0x00LL), MASK_RRF_RURR, INSTR_RRF_RURR, 3, 0 }, + { "rs", OP8(0x00LL), MASK_RS_RRRD, INSTR_RS_RRRD, 3, 0 }, + { "rse", OP8(0x00LL), MASK_RSE_RRRD, INSTR_RSE_RRRD, 3, 0 }, + { "rsi", OP8(0x00LL), MASK_RSI_RRP, INSTR_RSI_RRP, 3, 0 }, + { "rsy", OP8(0x00LL), MASK_RSY_RRRD, INSTR_RSY_RRRD, 3, 3 }, + { "rx", OP8(0x00LL), MASK_RX_RRRD, INSTR_RX_RRRD, 3, 0 }, + { "rxe", OP8(0x00LL), MASK_RXE_RRRD, INSTR_RXE_RRRD, 3, 0 }, + { "rxf", OP8(0x00LL), MASK_RXF_RRRDR, INSTR_RXF_RRRDR,3, 0 }, + { "rxy", OP8(0x00LL), MASK_RXY_RRRD, INSTR_RXY_RRRD, 3, 3 }, + { "s", OP8(0x00LL), MASK_S_RD, INSTR_S_RD, 3, 0 }, + { "si", OP8(0x00LL), MASK_SI_URD, INSTR_SI_URD, 3, 0 }, + { "siy", OP8(0x00LL), MASK_SIY_URD, INSTR_SIY_URD, 3, 3 }, + { "ss", OP8(0x00LL), MASK_SS_RRRDRD, INSTR_SS_RRRDRD,3, 0 }, + { "sse", OP8(0x00LL), MASK_SSE_RDRD, INSTR_SSE_RDRD, 3, 0 }, }; const int s390_num_opformats = diff --git a/contrib/binutils/opcodes/s390-opc.txt b/contrib/binutils/opcodes/s390-opc.txt index ddcf089..be08c82 100644 --- a/contrib/binutils/opcodes/s390-opc.txt +++ b/contrib/binutils/opcodes/s390-opc.txt @@ -1,626 +1,793 @@ # S/390 opcodes list. Use s390-mkopc to convert it into the opcode table. # Copyright 2000, 2001 Free Software Foundation, Inc. # Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). -5a a RX_RRRD "add" esa -6a ad RX_FRRD "add normalized (long)" esa -2a adr RR_FF "add normalized (long)" esa -7a ae RX_FRRD "add normalized (short)" esa -3a aer RR_FF "add normalized (short)" esa -4a ah RX_RRRD "add halfword" esa -5e al RX_RRRD "add logical" esa -1e alr RR_RR "add logical" esa -fa ap SS_LLRDRD "add decimal" esa -1a ar RR_RR "add" esa -7e au RX_FRRD "add unnormalized (short)" esa -3e aur RR_FF "add unnormalized (short)" esa -6e aw RX_FRRD "add unnormalized (long)" esa -2e awr RR_FF "add unnormalized (long)" esa -36 axr RR_FF "add normalized" esa -b240 bakr RRE_RR "branch and stack" esa -45 bal RX_RRRD "branch and link" esa -05 balr RR_RR "branch and link" esa -4d bas RX_RRRD "branch and save" esa -0d basr RR_RR "branch and save" esa -0c bassm RR_RR "branch and save and set mode" esa -47 bc RX_URRD "branch on condition" esa -07 bcr RR_UR "branch on condition" esa -46 bct RX_RRRD "branch on count" esa -06 bctr RR_RR "branch on count" esa -b258 bsg RRE_RR "branch in subspace group" esa -0b bsm RR_RR "branch and set mode" esa -86 bxh RS_RRRD "branch on index high" esa -87 bxle RS_RRRD "branch on index low or equal" esa -59 c RX_RRRD "compare" esa -69 cd RX_FRRD "compare (long)" esa -29 cdr RR_FF "compare (long)" esa -bb cds RS_RRRD "compare double and swap" esa -79 ce RX_FRRD "compare (short)" esa -39 cer RR_FF "compare (short)" esa -b21a cfc S_RD "compare and form codeword" esa -49 ch RX_RRRD "compare halfword" esa -55 cl RX_RRRD "compare logical" esa -d5 clc SS_L0RDRD "compare logical" esa -0f clcl RR_RR "compare logical long" esa -95 cli SI_URD "compare logical" esa -bd clm RS_RURD "compare logical characters under mask" esa -15 clr RR_RR "compare logical" esa -b25d clst RRE_RR "compare logical string" esa -b263 cmpsc RRE_RR "compression call" esa -f9 cp SS_LLRDRD "compare decimal" esa -b24d cpya RRE_AA "copy access" esa -19 cr RR_RR "compare" esa -ba cs RS_RRRD "compare and swap" esa -b230 csch S_00 "clear subchannel" esa -b257 cuse RRE_RR "compare until substring equal" esa -b250 csp RRE_RR "compare and swap and purge" esa -4f cvb RX_RRRD "convert to binary" esa -4e cvd RX_RRRD "convert to decimal" esa -5d d RX_RRRD "divide" esa -6d dd RX_FRRD "divide (long)" esa -2d ddr RR_FF "divide (long)" esa -7d de RX_FRRD "divide (short)" esa -3d der RR_FF "divide (short)" esa -83 diag RS_RRRD "diagnose" esa -fd dp SS_LLRDRD "divide decimal" esa -1d dr RR_RR "divide" esa -b22d dxr RRE_F0 "divide (ext.)" esa -b24f ear RRE_RA "extract access" esa -de ed SS_L0RDRD "edit" esa -df edmk SS_L0RDRD "edit and mark" esa -b226 epar RRE_R0 "extract primary ASN" esa -b249 ereg RRE_RR "extract stacked registers" esa -b227 esar RRE_R0 "extract secondary ASN" esa -b24a esta RRE_RR "extract stacked state" esa -44 ex RX_RRRD "execute" esa -24 hdr RR_FF "halve (long)" esa -34 her RR_FF "halve (short)" esa -b231 hsch S_00 "halt subchannel" esa -b224 iac RRE_R0 "insert address space control" esa -43 ic RX_RRRD "insert character" esa -bf icm RS_RURD "insert characters under mask" esa -b20b ipk S_00 "insert PSW key" esa -b222 ipm RRE_R0 "insert program mask" esa -b221 ipte RRE_RR "invalidate page table entry" esa -b229 iske RRE_RR "insert storage key extended" esa -b223 ivsk RRE_RR "insert virtual storage key" esa -58 l RX_RRRD "load" esa -41 la RX_RRRD "load address" esa -51 lae RX_RRRD "load address extended" esa -9a lam RS_AARD "load access multiple" esa -e500 lasp SSE_RDRD "load address space parameters" esa -23 lcdr RR_FF "load complement (long)" esa -33 lcer RR_FF "load complement (short)" esa -13 lcr RR_RR "load complement" esa -b7 lctl RS_CCRD "load control" esa -68 ld RX_FRRD "load (long)" esa -28 ldr RR_FF "load (long)" esa -78 le RX_FRRD "load (short)" esa -38 ler RR_FF "load (short)" esa -48 lh RX_RRRD "load halfword" esa -98 lm RS_RRRD "load multiple" esa -21 lndr RR_FF "load negative (long)" esa -31 lner RR_FF "load negative (short)" esa -11 lnr RR_RR "load negative" esa -20 lpdr RR_FF "load positive (long)" esa -30 lper RR_FF "load positive (short)" esa -10 lpr RR_RR "load positive" esa -82 lpsw S_RD "load PSW" esa -18 lr RR_RR "load" esa -b1 lra RX_RRRD "load real address" esa -25 lrdr RR_FF "load rounded (ext. to long)" esa -35 lrer RR_FF "load rounded (long to short)" esa -22 ltdr RR_FF "load and test (long)" esa -32 lter RR_FF "load and test (short)" esa -12 ltr RR_RR "load and test" esa -b24b lura RRE_RR "load using real address" esa -5c m RX_RRRD "multiply" esa -af mc SI_URD "monitor call" esa -6c md RX_FRRD "multiply (long)" esa -2c mdr RR_FF "multiply (long)" esa -7c me RX_FRRD "multiply (short to long)" esa -3c mer RR_FF "multiply (short to long)" esa -4c mh RX_RRRD "multiply halfword" esa -fc mp SS_LLRDRD "multiply decimal" esa -1c mr RR_RR "multiply" esa -b232 msch S_RD "modify subchannel" esa -b247 msta RRE_R0 "modify stacked state" esa -d2 mvc SS_L0RDRD "move" esa -e50f mvcdk SSE_RDRD "move with destination key" esa -e8 mvcin SS_L0RDRD "move inverse" esa -d9 mvck SS_RRRDRD "move with key" esa -0e mvcl RR_RR "move long" esa -da mvcp SS_RRRDRD "move to primary" esa -db mvcs SS_RRRDRD "move to secondary" esa -e50e mvcsk SSE_RDRD "move with source key" esa -92 mvi SI_URD "move" esa -d1 mvn SS_L0RDRD "move numerics" esa -f1 mvo SS_LLRDRD "move with offset" esa -b254 mvpg RRE_RR "move page" esa -b255 mvst RRE_RR "move string" esa -d3 mvz SS_L0RDRD "move zones" esa -67 mxd RX_FRRD "multiply (long to ext.)" esa -27 mxdr RR_FF "multiply (long to ext.)" esa -26 mxr RR_FF "multiply (ext.)" esa -54 n RX_RRRD "AND" esa -d4 nc SS_L0RDRD "AND" esa -94 ni SI_URD "AND" esa -14 nr RR_RR "AND" esa -56 o RX_RRRD "OR" esa -d6 oc SS_L0RDRD "OR" esa -96 oi SI_URD "OR" esa -16 or RR_RR "OR" esa -f2 pack SS_LLRDRD "pack" esa -b248 palb RRE_00 "purge ALB" esa -b218 pc S_RD "program call" esa -0101 pr E "program return" esa -b228 pt RRE_RR "program transfer" esa -b20d ptlb S_00 "purge TLB" esa -b23b rchp S_00 "reset channel path" esa -b22a rrbe RRE_RR "reset reference bit extended" esa -b238 rsch S_00 "resume subchannel" esa -5b s RX_RRRD "subtract" esa -b219 sac S_RD "set address space control" esa -b279 sacf S_RD "set address space control fast" esa -b237 sal S_00 "set address limit" esa -b24e sar RRE_AR "set access" esa -b23c schm S_00 "set channel monitor" esa -b204 sck S_RD "set clock" esa -b206 sckc S_RD "set clock comparator" esa -6b sd RX_FRRD "subtract normalized (long)" esa -2b sdr RR_FF "subtract normalized (long)" esa -7b se RX_FRRD "subtract normalized (short)" esa -3b ser RR_FF "subtract normalized (short)" esa -4b sh RX_RRRD "subtract halfword" esa -b214 sie S_RD "start interpretive execution" esa -ae sigp RS_RRRD "signal processor" esa -5f sl RX_RRRD "subtract logical" esa -8b sla RS_R0RD "shift left single" esa -8f slda RS_R0RD "shift left double (long)" esa -8d sldl RS_R0RD "shift left double logical (long)" esa -89 sll RS_R0RD "shift left single logical" esa -1f slr RR_RR "subtract logical" esa -fb sp SS_LLRDRD "subtract decimal" esa -b20a spka S_RD "set PSW key from address" esa -04 spm RR_R0 "set program mask" esa -b208 spt S_RD "set CPU timer" esa -b210 spx S_RD "set prefix" esa -b244 sqdr RRE_F0 "square root (long)" esa -b245 sqer RRE_F0 "square root (short)" esa -1b sr RR_RR "subtract" esa -8a sra RS_R0RD "shift right single" esa -8e srda RS_R0RD "shift right double (long)" esa -8c srdl RS_R0RD "shift right double logical (long)" esa -88 srl RS_R0RD "shift right single logical" esa -f0 srp SS_LIRDRD "shift and round decimal" esa -b25e srst RRE_RR "search string" esa -b225 ssar RRE_R0 "set secondary ASN" esa -b233 ssch S_RD "start subchannel" esa -b22b sske RRE_RR "set storage key extended" esa -80 ssm S_RD "set system mask" esa -50 st RX_RRRD "store" esa -9b stam RS_AARD "store access multiple" esa -b212 stap S_RD "store CPU address" esa -42 stc RX_RRRD "store character" esa -b205 stck S_RD "store clock" esa -b207 stckc S_RD "store clock comparator" esa -be stcm RS_RURD "store characters under mask" esa -b23a stcps S_RD "store channel path status" esa -b239 stcrw S_RD "store channel report word" esa -b6 stctl RS_CCRD "store control" esa -60 std RX_FRRD "store (long)" esa -70 ste RX_FRRD "store (short)" esa -40 sth RX_RRRD "store halfword" esa -b202 stidp S_RD "store CPU id" esa -90 stm RS_RRRD "store multiple" esa -ac stnsm SI_URD "store then AND system mask" esa -ad stosm SI_URD "store then OR system mask" esa -b209 stpt S_RD "store CPU timer" esa -b211 stpx S_RD "store prefix" esa -b234 stsch S_RD "store subchannel" esa -b246 stura RRE_RR "store using real address" esa -7f su RX_FRRD "subtract unnormalized (short)" esa -3f sur RR_FF "subtract unnormalized (short)" esa -0a svc RR_U0 "supervisor call" esa -6f sw RX_FRRD "subtract unnormalized (long)" esa -2f swr RR_FF "subtract unnormalized (long)" esa -37 sxr RR_FF "subtract normalized (ext.)" esa -b24c tar RRE_AR "test access" esa -b22c tb RRE_0R "test block" esa -91 tm SI_URD "test under mask" esa -b236 tpi S_RD "test pending interruption" esa -e501 tprot SSE_RDRD "test protection" esa -dc tr SS_L0RDRD "translate" esa -99 trace RS_RRRD "trace" esa -dd trt SS_L0RDRD "translate and test" esa -93 ts S_RD "test and set" esa -b235 tsch S_RD "test subchannel" esa -f3 unpk SS_LLRDRD "unpack" esa -0102 upt E "update tree" esa -57 x RX_RRRD "exclusive OR" esa -d7 xc SS_L0RDRD "exclusive OR" esa -97 xi SI_URD "exclusive OR" esa -17 xr RR_RR "exclusive OR" esa -f8 zap SS_LLRDRD "zero and add" esa -a70a ahi RI_RI "add halfword immediate" esa -84 brxh RSI_RRP "branch relative on index high" esa -85 brxle RSI_RRP "branch relative on index low or equal" esa -a705 bras RI_RP "branch relative and save" esa -a704 brc RI_UP "branch relative on condition" esa -a706 brct RI_RP "branch relative on count" esa -b241 cksm RRE_RR "checksum" esa -a70e chi RI_RI "compare halfword immediate" esa -a9 clcle RS_RRRD "compare logical long extended" esa -a708 lhi RI_RI "load halfword immediate" esa -a8 mvcle RS_RRRD "move long extended" esa -a70c mhi RI_RI "multiply halfword immediate" esa -b252 msr RRE_RR "multiply single" esa -71 ms RX_RRRD "multiply single" esa -a700 tmh RI_RU "test under mask high" esa -a701 tml RI_RU "test under mask low" esa -0700 nopr RR_0R "no operation" esa -0710 bor RR_0R "branch on overflow / if ones" esa -0720 bhr RR_0R "branch on high" esa -0720 bpr RR_0R "branch on plus" esa -0730 bnler RR_0R "branch on not low or equal" esa -0740 blr RR_0R "branch on low" esa -0740 bmr RR_0R "branch on minus / if mixed" esa -0750 bnher RR_0R "branch on not high or equal" esa -0760 blhr RR_0R "branch on low or high" esa -0770 bner RR_0R "branch on not equal" esa -0770 bnzr RR_0R "branch on not zero / if not zeros" esa -0780 ber RR_0R "branch on equal" esa -0780 bzr RR_0R "branch on zero / if zeros" esa -0790 bnlhr RR_0R "branch on not low or high" esa -07a0 bher RR_0R "branch on high or equal" esa -07b0 bnlr RR_0R "branch on not low" esa -07b0 bnmr RR_0R "branch on not minus / if not mixed" esa -07c0 bler RR_0R "brach on low or equal" esa -07d0 bnhr RR_0R "branch on not high" esa -07d0 bnpr RR_0R "branch on not plus" esa -07e0 bnor RR_0R "branch on not overflow / if not ones" esa -07f0 br RR_0R "unconditional branch" esa -4700 nop RX_0RRD "no operation" esa -4710 bo RX_0RRD "branch on overflow / if ones" esa -4720 bh RX_0RRD "branch on high" esa -4720 bp RX_0RRD "branch on plus" esa -4730 bnle RX_0RRD "branch on not low or equal" esa -4740 bl RX_0RRD "branch on low" esa -4740 bm RX_0RRD "branch on minus / if mixed" esa -4750 bnhe RX_0RRD "branch on not high or equal" esa -4760 blh RX_0RRD "branch on low or high" esa -4770 bne RX_0RRD "branch on not equal" esa -4770 bnz RX_0RRD "branch on not zero / if not zeros" esa -4780 be RX_0RRD "branch on equal" esa -4780 bz RX_0RRD "branch on zero / if zeros" esa -4790 bnlh RX_0RRD "branch on not low or high" esa -47a0 bhe RX_0RRD "branch on high or equal" esa -47b0 bnl RX_0RRD "branch on not low" esa -47b0 bnm RX_0RRD "branch on not minus / if not mixed" esa -47c0 ble RX_0RRD "branch on low or equal" esa -47d0 bnh RX_0RRD "branch on not high" esa -47d0 bnp RX_0RRD "branch on not plus" esa -47e0 bno RX_0RRD "branch on not overflow / if not ones" esa -47f0 b RX_0RRD "unconditional branch" esa -a714 jo RI_0P "jump on overflow / if ones" esa -a724 jh RI_0P "jump on A high" esa -a724 jp RI_0P "jump on plus" esa -a734 jnle RI_0P "jump on not low or equal" esa -a744 jl RI_0P "jump on A low" esa -a744 jm RI_0P "jump on minus / if mixed" esa -a754 jnhe RI_0P "jump on not high or equal" esa -a764 jlh RI_0P "jump on low or high" esa -a774 jne RI_0P "jump on A not equal B" esa -a774 jnz RI_0P "jump on not zero / if not zeros" esa -a784 je RI_0P "jump on A equal B" esa -a784 jz RI_0P "jump on zero / if zeros" esa -a794 jnlh RI_0P "jump on not low or high" esa -a7a4 jhe RI_0P "jump on high or equal" esa -a7b4 jnl RI_0P "jump on A not low" esa -a7b4 jnm RI_0P "jump on not minus / if not mixed" esa -a7c4 jle RI_0P "jump on low or equal" esa -a7d4 jnh RI_0P "jump on A not high" esa -a7d4 jnp RI_0P "jump on not plus" esa -a7e4 jno RI_0P "jump on not overflow / if not ones" esa -a7f4 j RI_0P "jump" esa -b34a axbr RRE_FF "add extended bfp" esa -b31a adbr RRE_FF "add long bfp" esa -ed000000001a adb RXE_FRRD "add long bfp" esa -b30a aebr RRE_FF "add short bfp" esa -ed000000000a aeb RXE_FRRD "add short bfp" esa -b349 cxbr RRE_FF "compare extended bfp" esa -b319 cdbr RRE_FF "compare long bfp" esa -ed0000000019 cdb RXE_FRRD "compare long bfp" esa -b309 cebr RRE_FF "compare short bfp" esa -ed0000000009 ceb RXE_FRRD "compare short bfp" esa -b348 kxbr RRE_FF "compare and signal extended bfp" esa -b318 kdbr RRE_FF "compare and signal long bfp" esa -ed0000000018 kdb RXE_FRRD "compare and signal long bfp" esa -b308 kebr RRE_FF "compare and signal short bfp" esa -ed0000000008 keb RXE_FRRD "compare and signal short bfp" esa -b396 cxfbr RRE_RF "convert from fixed 32 to extended bfp" esa -b395 cdfbr RRE_RF "convert from fixed 32 to long bfp" esa -b394 cefbr RRE_RF "convert from fixed 32 to short bfp" esa -b39a cfxbr RRF_U0FR "convert to fixed extended bfp to 32" esa -b399 cfdbr RRF_U0FR "convert to fixed long bfp to 32" esa -b398 cfebr RRF_U0FR "convert to fixed short bfp to 32" esa -b34d dxbr RRE_FF "divide extended bfp" esa -b31d ddbr RRE_FF "divide long bfp" esa -ed000000001d ddb RXE_FRRD "divide long bfp" esa -b30d debr RRE_FF "divide short bfp" esa -ed000000000d deb RXE_FRRD "divide short bfp" esa -b35b didbr RRF_FUFF "divide to integer long bfp" esa -b353 diebr RRF_FUFF "divide to integer short bfp" esa -b38c efpc RRE_RR "extract fpc" esa -b342 ltxbr RRE_FF "load and test extended bfp" esa -b312 ltdbr RRE_FF "load and test long bfp" esa -b302 ltebr RRE_FF "load and test short bfp" esa -b343 lcxbr RRE_FF "load complement extended bfp" esa -b313 lcdbr RRE_FF "load complement long bfp" esa -b303 lcebr RRE_FF "load complement short bfp" esa -b347 fixbr RRF_U0FF "load fp integer extended bfp" esa -b35f fidbr RRF_U0FF "load fp integer long bfp" esa -b357 fiebr RRF_U0FF "load fp integer short bfp" esa -b29d lfpc S_RD "load fpc" esa -b305 lxdbr RRE_FF "load lengthened long to extended bfp" esa -ed0000000005 lxdb RXE_FRRD "load lengthened long to extended bfp" esa -b306 lxebr RRE_FF "load lengthened short to extended bfp" esa -ed0000000006 lxeb RXE_FRRD "load lengthened short to extended bfp" esa -b304 ldebr RRE_FF "load lengthened short to long bfp" esa -ed0000000004 ldeb RXE_FRRD "load lengthened short to long bfp" esa -b341 lnxbr RRE_FF "load negative extended bfp" esa -b311 lndbr RRE_FF "load negative long bfp" esa -b301 lnebr RRE_FF "load negative short bfp" esa -b340 lpxbr RRE_FF "load positive extended bfp" esa -b310 lpdbr RRE_FF "load positive long bfp" esa -b300 lpebr RRE_FF "load positive short bfp" esa -b345 ldxbr RRE_FF "load rounded extended to long bfp" esa -b346 lexbr RRE_FF "load rounded extended to short bfp" esa -b344 ledbr RRE_FF "load rounded long to short bfp" esa -b34c mxbr RRE_FF "multiply extended bfp" esa -b31c mdbr RRE_FF "multiply long bfp" esa -ed000000001c mdb RXE_FRRD "multiply long bfp" esa -b307 mxdbr RRE_FF "multiply long to extended bfp" esa -ed0000000007 mxdb RXE_FRRD "multiply long to extended bfp" esa -b317 meebr RRE_FF "multiply short bfp" esa -ed0000000017 meeb RXE_FRRD "multiply short bfp" esa -b30c mdebr RRE_FF "multiply short to long bfp" esa -ed000000000c mdeb RXE_FRRD "multiply short to long bfp" esa -b31e madbr RRF_F0FF "multiply and add long bfp" esa -ed000000001e madb RXF_FRRDF "multiply and add long bfp" esa -b30e maebr RRF_F0FF "multiply and add short bfp" esa -ed000000000e maeb RXF_FRRDF "multiply and add short bfp" esa -b31f msdbr RRF_F0FF "multiply and subtract long bfp" esa -ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" esa -b30f msebr RRF_F0FF "multiply and subtract short bfp" esa -ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" esa -b384 sfpc RRE_RR "set fpc" esa -b299 srnm S_RD "set rounding mode" esa -b316 sqxbr RRE_FF "square root extended bfp" esa -b315 sqdbr RRE_FF "square root long bfp" esa -ed0000000015 sqdb RXE_FRRD "square root long bfp" esa -b314 sqebr RRE_FF "square root short bfp" esa -ed0000000014 sqeb RXE_FRRD "square root short bfp" esa -b29c stfpc S_RD "store fpc" esa -b34b sxbr RRE_FF "subtract extended bfp" esa -b31b sdbr RRE_FF "subtract long bfp" esa -ed000000001b sdb RXE_FRRD "subtract long bfp" esa -b30b sebr RRE_FF "subtract short bfp" esa -ed000000000b seb RXE_FRRD "subtract short bfp" esa -ed0000000012 tcxb RXE_FRRD "test data class extended bfp" esa -ed0000000011 tcdb RXE_FRRD "test data class long bfp" esa -ed0000000010 tceb RXE_FRRD "test data class short bfp" esa -b274 siga S_RD "signal adapter" esa -# are the following instructions confidential ?? -b2a6 cuutf RRE_RR "convert unicode to utf-8" esa -b2a7 cutfu RRE_RR "convert utf-8 to unicode" esa -ee plo SS_RRRDRD2 "perform locked operation" esa -b25a bsa RRE_RR "branch and set authority" esa -b277 rp S_RD "resume program" esa -0107 sckpf E "set clock programmable field" esa -b27d stsi S_RD "store system information" esa -01ff trap2 E "trap" esa -b2ff trap4 S_RD "trap4" esa +5a a RX_RRRD "add" g5 esa,zarch +6a ad RX_FRRD "add normalized (long)" g5 esa,zarch +2a adr RR_FF "add normalized (long)" g5 esa,zarch +7a ae RX_FRRD "add normalized (short)" g5 esa,zarch +3a aer RR_FF "add normalized (short)" g5 esa,zarch +4a ah RX_RRRD "add halfword" g5 esa,zarch +5e al RX_RRRD "add logical" g5 esa,zarch +1e alr RR_RR "add logical" g5 esa,zarch +fa ap SS_LLRDRD "add decimal" g5 esa,zarch +1a ar RR_RR "add" g5 esa,zarch +7e au RX_FRRD "add unnormalized (short)" g5 esa,zarch +3e aur RR_FF "add unnormalized (short)" g5 esa,zarch +6e aw RX_FRRD "add unnormalized (long)" g5 esa,zarch +2e awr RR_FF "add unnormalized (long)" g5 esa,zarch +36 axr RR_FF "add normalized" g5 esa,zarch +b240 bakr RRE_RR "branch and stack" g5 esa,zarch +45 bal RX_RRRD "branch and link" g5 esa,zarch +05 balr RR_RR "branch and link" g5 esa,zarch +4d bas RX_RRRD "branch and save" g5 esa,zarch +0d basr RR_RR "branch and save" g5 esa,zarch +0c bassm RR_RR "branch and save and set mode" g5 esa,zarch +47 bc RX_URRD "branch on condition" g5 esa,zarch +07 bcr RR_UR "branch on condition" g5 esa,zarch +46 bct RX_RRRD "branch on count" g5 esa,zarch +06 bctr RR_RR "branch on count" g5 esa,zarch +b258 bsg RRE_RR "branch in subspace group" g5 esa,zarch +0b bsm RR_RR "branch and set mode" g5 esa,zarch +86 bxh RS_RRRD "branch on index high" g5 esa,zarch +87 bxle RS_RRRD "branch on index low or equal" g5 esa,zarch +59 c RX_RRRD "compare" g5 esa,zarch +69 cd RX_FRRD "compare (long)" g5 esa,zarch +29 cdr RR_FF "compare (long)" g5 esa,zarch +bb cds RS_RRRD "compare double and swap" g5 esa,zarch +79 ce RX_FRRD "compare (short)" g5 esa,zarch +39 cer RR_FF "compare (short)" g5 esa,zarch +b21a cfc S_RD "compare and form codeword" g5 esa,zarch +49 ch RX_RRRD "compare halfword" g5 esa,zarch +55 cl RX_RRRD "compare logical" g5 esa,zarch +d5 clc SS_L0RDRD "compare logical" g5 esa,zarch +0f clcl RR_RR "compare logical long" g5 esa,zarch +95 cli SI_URD "compare logical" g5 esa,zarch +bd clm RS_RURD "compare logical characters under mask" g5 esa,zarch +15 clr RR_RR "compare logical" g5 esa,zarch +b25d clst RRE_RR "compare logical string" g5 esa,zarch +b263 cmpsc RRE_RR "compression call" g5 esa,zarch +f9 cp SS_LLRDRD "compare decimal" g5 esa,zarch +b24d cpya RRE_AA "copy access" g5 esa,zarch +19 cr RR_RR "compare" g5 esa,zarch +ba cs RS_RRRD "compare and swap" g5 esa,zarch +b230 csch S_00 "clear subchannel" g5 esa,zarch +b257 cuse RRE_RR "compare until substring equal" g5 esa,zarch +b250 csp RRE_RR "compare and swap and purge" g5 esa,zarch +4f cvb RX_RRRD "convert to binary" g5 esa,zarch +4e cvd RX_RRRD "convert to decimal" g5 esa,zarch +5d d RX_RRRD "divide" g5 esa,zarch +6d dd RX_FRRD "divide (long)" g5 esa,zarch +2d ddr RR_FF "divide (long)" g5 esa,zarch +7d de RX_FRRD "divide (short)" g5 esa,zarch +3d der RR_FF "divide (short)" g5 esa,zarch +83 diag RS_RRRD "diagnose" g5 esa,zarch +fd dp SS_LLRDRD "divide decimal" g5 esa,zarch +1d dr RR_RR "divide" g5 esa,zarch +b22d dxr RRE_F0 "divide (ext.)" g5 esa,zarch +b24f ear RRE_RA "extract access" g5 esa,zarch +de ed SS_L0RDRD "edit" g5 esa,zarch +df edmk SS_L0RDRD "edit and mark" g5 esa,zarch +b226 epar RRE_R0 "extract primary ASN" g5 esa,zarch +b249 ereg RRE_RR "extract stacked registers" g5 esa,zarch +b227 esar RRE_R0 "extract secondary ASN" g5 esa,zarch +b24a esta RRE_RR "extract stacked state" g5 esa,zarch +44 ex RX_RRRD "execute" g5 esa,zarch +24 hdr RR_FF "halve (long)" g5 esa,zarch +34 her RR_FF "halve (short)" g5 esa,zarch +b231 hsch S_00 "halt subchannel" g5 esa,zarch +b224 iac RRE_R0 "insert address space control" g5 esa,zarch +43 ic RX_RRRD "insert character" g5 esa,zarch +bf icm RS_RURD "insert characters under mask" g5 esa,zarch +b20b ipk S_00 "insert PSW key" g5 esa,zarch +b222 ipm RRE_R0 "insert program mask" g5 esa,zarch +b221 ipte RRE_RR "invalidate page table entry" g5 esa,zarch +b229 iske RRE_RR "insert storage key extended" g5 esa,zarch +b223 ivsk RRE_RR "insert virtual storage key" g5 esa,zarch +58 l RX_RRRD "load" g5 esa,zarch +41 la RX_RRRD "load address" g5 esa,zarch +51 lae RX_RRRD "load address extended" g5 esa,zarch +9a lam RS_AARD "load access multiple" g5 esa,zarch +e500 lasp SSE_RDRD "load address space parameters" g5 esa,zarch +23 lcdr RR_FF "load complement (long)" g5 esa,zarch +33 lcer RR_FF "load complement (short)" g5 esa,zarch +13 lcr RR_RR "load complement" g5 esa,zarch +b7 lctl RS_CCRD "load control" g5 esa,zarch +68 ld RX_FRRD "load (long)" g5 esa,zarch +28 ldr RR_FF "load (long)" g5 esa,zarch +78 le RX_FRRD "load (short)" g5 esa,zarch +38 ler RR_FF "load (short)" g5 esa,zarch +48 lh RX_RRRD "load halfword" g5 esa,zarch +98 lm RS_RRRD "load multiple" g5 esa,zarch +21 lndr RR_FF "load negative (long)" g5 esa,zarch +31 lner RR_FF "load negative (short)" g5 esa,zarch +11 lnr RR_RR "load negative" g5 esa,zarch +20 lpdr RR_FF "load positive (long)" g5 esa,zarch +30 lper RR_FF "load positive (short)" g5 esa,zarch +10 lpr RR_RR "load positive" g5 esa,zarch +82 lpsw S_RD "load PSW" g5 esa,zarch +18 lr RR_RR "load" g5 esa,zarch +b1 lra RX_RRRD "load real address" g5 esa,zarch +25 lrdr RR_FF "load rounded (ext. to long)" g5 esa,zarch +35 lrer RR_FF "load rounded (long to short)" g5 esa,zarch +25 ldxr RR_FF "load rounded (ext. to long)" g5 esa,zarch +35 ledr RR_FF "load rounded (long to short)" g5 esa,zarch +22 ltdr RR_FF "load and test (long)" g5 esa,zarch +32 lter RR_FF "load and test (short)" g5 esa,zarch +12 ltr RR_RR "load and test" g5 esa,zarch +b24b lura RRE_RR "load using real address" g5 esa,zarch +5c m RX_RRRD "multiply" g5 esa,zarch +af mc SI_URD "monitor call" g5 esa,zarch +6c md RX_FRRD "multiply (long)" g5 esa,zarch +2c mdr RR_FF "multiply (long)" g5 esa,zarch +7c me RX_FRRD "multiply (short to long)" g5 esa,zarch +7c mde RX_FRRD "multiply (short to long)" g5 esa,zarch +3c mer RR_FF "multiply (short to long)" g5 esa,zarch +3c mder RR_FF "multiply short to long hfp" g5 esa,zarch +4c mh RX_RRRD "multiply halfword" g5 esa,zarch +fc mp SS_LLRDRD "multiply decimal" g5 esa,zarch +1c mr RR_RR "multiply" g5 esa,zarch +b232 msch S_RD "modify subchannel" g5 esa,zarch +b247 msta RRE_R0 "modify stacked state" g5 esa,zarch +d2 mvc SS_L0RDRD "move" g5 esa,zarch +e50f mvcdk SSE_RDRD "move with destination key" g5 esa,zarch +e8 mvcin SS_L0RDRD "move inverse" g5 esa,zarch +d9 mvck SS_RRRDRD "move with key" g5 esa,zarch +0e mvcl RR_RR "move long" g5 esa,zarch +da mvcp SS_RRRDRD "move to primary" g5 esa,zarch +db mvcs SS_RRRDRD "move to secondary" g5 esa,zarch +e50e mvcsk SSE_RDRD "move with source key" g5 esa,zarch +92 mvi SI_URD "move" g5 esa,zarch +d1 mvn SS_L0RDRD "move numerics" g5 esa,zarch +f1 mvo SS_LLRDRD "move with offset" g5 esa,zarch +b254 mvpg RRE_RR "move page" g5 esa,zarch +b255 mvst RRE_RR "move string" g5 esa,zarch +d3 mvz SS_L0RDRD "move zones" g5 esa,zarch +67 mxd RX_FRRD "multiply (long to ext.)" g5 esa,zarch +27 mxdr RR_FF "multiply (long to ext.)" g5 esa,zarch +26 mxr RR_FF "multiply (ext.)" g5 esa,zarch +54 n RX_RRRD "AND" g5 esa,zarch +d4 nc SS_L0RDRD "AND" g5 esa,zarch +94 ni SI_URD "AND" g5 esa,zarch +14 nr RR_RR "AND" g5 esa,zarch +56 o RX_RRRD "OR" g5 esa,zarch +d6 oc SS_L0RDRD "OR" g5 esa,zarch +96 oi SI_URD "OR" g5 esa,zarch +16 or RR_RR "OR" g5 esa,zarch +f2 pack SS_LLRDRD "pack" g5 esa,zarch +b248 palb RRE_00 "purge ALB" g5 esa,zarch +b218 pc S_RD "program call" g5 esa,zarch +0101 pr E "program return" g5 esa,zarch +b228 pt RRE_RR "program transfer" g5 esa,zarch +b20d ptlb S_00 "purge TLB" g5 esa,zarch +b23b rchp S_00 "reset channel path" g5 esa,zarch +b22a rrbe RRE_RR "reset reference bit extended" g5 esa,zarch +b238 rsch S_00 "resume subchannel" g5 esa,zarch +5b s RX_RRRD "subtract" g5 esa,zarch +b219 sac S_RD "set address space control" g5 esa,zarch +b279 sacf S_RD "set address space control fast" g5 esa,zarch +b237 sal S_00 "set address limit" g5 esa,zarch +b24e sar RRE_AR "set access" g5 esa,zarch +b23c schm S_00 "set channel monitor" g5 esa,zarch +b204 sck S_RD "set clock" g5 esa,zarch +b206 sckc S_RD "set clock comparator" g5 esa,zarch +6b sd RX_FRRD "subtract normalized (long)" g5 esa,zarch +2b sdr RR_FF "subtract normalized (long)" g5 esa,zarch +7b se RX_FRRD "subtract normalized (short)" g5 esa,zarch +3b ser RR_FF "subtract normalized (short)" g5 esa,zarch +4b sh RX_RRRD "subtract halfword" g5 esa,zarch +b214 sie S_RD "start interpretive execution" g5 esa,zarch +ae sigp RS_RRRD "signal processor" g5 esa,zarch +5f sl RX_RRRD "subtract logical" g5 esa,zarch +8b sla RS_R0RD "shift left single" g5 esa,zarch +8f slda RS_R0RD "shift left double (long)" g5 esa,zarch +8d sldl RS_R0RD "shift left double logical (long)" g5 esa,zarch +89 sll RS_R0RD "shift left single logical" g5 esa,zarch +1f slr RR_RR "subtract logical" g5 esa,zarch +fb sp SS_LLRDRD "subtract decimal" g5 esa,zarch +b20a spka S_RD "set PSW key from address" g5 esa,zarch +04 spm RR_R0 "set program mask" g5 esa,zarch +b208 spt S_RD "set CPU timer" g5 esa,zarch +b210 spx S_RD "set prefix" g5 esa,zarch +b244 sqdr RRE_F0 "square root (long)" g5 esa,zarch +b245 sqer RRE_F0 "square root (short)" g5 esa,zarch +1b sr RR_RR "subtract" g5 esa,zarch +8a sra RS_R0RD "shift right single" g5 esa,zarch +8e srda RS_R0RD "shift right double (long)" g5 esa,zarch +8c srdl RS_R0RD "shift right double logical (long)" g5 esa,zarch +88 srl RS_R0RD "shift right single logical" g5 esa,zarch +f0 srp SS_LIRDRD "shift and round decimal" g5 esa,zarch +b25e srst RRE_RR "search string" g5 esa,zarch +b225 ssar RRE_R0 "set secondary ASN" g5 esa,zarch +b233 ssch S_RD "start subchannel" g5 esa,zarch +b22b sske RRE_RR "set storage key extended" g5 esa,zarch +80 ssm S_RD "set system mask" g5 esa,zarch +50 st RX_RRRD "store" g5 esa,zarch +9b stam RS_AARD "store access multiple" g5 esa,zarch +b212 stap S_RD "store CPU address" g5 esa,zarch +42 stc RX_RRRD "store character" g5 esa,zarch +b205 stck S_RD "store clock" g5 esa,zarch +b207 stckc S_RD "store clock comparator" g5 esa,zarch +be stcm RS_RURD "store characters under mask" g5 esa,zarch +b23a stcps S_RD "store channel path status" g5 esa,zarch +b239 stcrw S_RD "store channel report word" g5 esa,zarch +b6 stctl RS_CCRD "store control" g5 esa,zarch +60 std RX_FRRD "store (long)" g5 esa,zarch +70 ste RX_FRRD "store (short)" g5 esa,zarch +40 sth RX_RRRD "store halfword" g5 esa,zarch +b202 stidp S_RD "store CPU id" g5 esa,zarch +90 stm RS_RRRD "store multiple" g5 esa,zarch +ac stnsm SI_URD "store then AND system mask" g5 esa,zarch +ad stosm SI_URD "store then OR system mask" g5 esa,zarch +b209 stpt S_RD "store CPU timer" g5 esa,zarch +b211 stpx S_RD "store prefix" g5 esa,zarch +b234 stsch S_RD "store subchannel" g5 esa,zarch +b246 stura RRE_RR "store using real address" g5 esa,zarch +7f su RX_FRRD "subtract unnormalized (short)" g5 esa,zarch +3f sur RR_FF "subtract unnormalized (short)" g5 esa,zarch +0a svc RR_U0 "supervisor call" g5 esa,zarch +6f sw RX_FRRD "subtract unnormalized (long)" g5 esa,zarch +2f swr RR_FF "subtract unnormalized (long)" g5 esa,zarch +37 sxr RR_FF "subtract normalized (ext.)" g5 esa,zarch +b24c tar RRE_AR "test access" g5 esa,zarch +b22c tb RRE_0R "test block" g5 esa,zarch +91 tm SI_URD "test under mask" g5 esa,zarch +b236 tpi S_RD "test pending interruption" g5 esa,zarch +e501 tprot SSE_RDRD "test protection" g5 esa,zarch +dc tr SS_L0RDRD "translate" g5 esa,zarch +99 trace RS_RRRD "trace" g5 esa,zarch +dd trt SS_L0RDRD "translate and test" g5 esa,zarch +93 ts S_RD "test and set" g5 esa,zarch +b235 tsch S_RD "test subchannel" g5 esa,zarch +f3 unpk SS_LLRDRD "unpack" g5 esa,zarch +0102 upt E "update tree" g5 esa,zarch +57 x RX_RRRD "exclusive OR" g5 esa,zarch +d7 xc SS_L0RDRD "exclusive OR" g5 esa,zarch +97 xi SI_URD "exclusive OR" g5 esa,zarch +17 xr RR_RR "exclusive OR" g5 esa,zarch +f8 zap SS_LLRDRD "zero and add" g5 esa,zarch +a70a ahi RI_RI "add halfword immediate" g5 esa,zarch +84 brxh RSI_RRP "branch relative on index high" g5 esa,zarch +85 brxle RSI_RRP "branch relative on index low or equal" g5 esa,zarch +a705 bras RI_RP "branch relative and save" g5 esa,zarch +a704 brc RI_UP "branch relative on condition" g5 esa,zarch +a706 brct RI_RP "branch relative on count" g5 esa,zarch +b241 cksm RRE_RR "checksum" g5 esa,zarch +a70e chi RI_RI "compare halfword immediate" g5 esa,zarch +a9 clcle RS_RRRD "compare logical long extended" g5 esa,zarch +a708 lhi RI_RI "load halfword immediate" g5 esa,zarch +a8 mvcle RS_RRRD "move long extended" g5 esa,zarch +a70c mhi RI_RI "multiply halfword immediate" g5 esa,zarch +b252 msr RRE_RR "multiply single" g5 esa,zarch +71 ms RX_RRRD "multiply single" g5 esa,zarch +a700 tmh RI_RU "test under mask high" g5 esa,zarch +a701 tml RI_RU "test under mask low" g5 esa,zarch +0700 nopr RR_0R "no operation" g5 esa,zarch +0710 bor RR_0R "branch on overflow / if ones" g5 esa,zarch +0720 bhr RR_0R "branch on high" g5 esa,zarch +0720 bpr RR_0R "branch on plus" g5 esa,zarch +0730 bnler RR_0R "branch on not low or equal" g5 esa,zarch +0740 blr RR_0R "branch on low" g5 esa,zarch +0740 bmr RR_0R "branch on minus / if mixed" g5 esa,zarch +0750 bnher RR_0R "branch on not high or equal" g5 esa,zarch +0760 blhr RR_0R "branch on low or high" g5 esa,zarch +0770 bner RR_0R "branch on not equal" g5 esa,zarch +0770 bnzr RR_0R "branch on not zero / if not zeros" g5 esa,zarch +0780 ber RR_0R "branch on equal" g5 esa,zarch +0780 bzr RR_0R "branch on zero / if zeros" g5 esa,zarch +0790 bnlhr RR_0R "branch on not low or high" g5 esa,zarch +07a0 bher RR_0R "branch on high or equal" g5 esa,zarch +07b0 bnlr RR_0R "branch on not low" g5 esa,zarch +07b0 bnmr RR_0R "branch on not minus / if not mixed" g5 esa,zarch +07c0 bler RR_0R "brach on low or equal" g5 esa,zarch +07d0 bnhr RR_0R "branch on not high" g5 esa,zarch +07d0 bnpr RR_0R "branch on not plus" g5 esa,zarch +07e0 bnor RR_0R "branch on not overflow / if not ones" g5 esa,zarch +07f0 br RR_0R "unconditional branch" g5 esa,zarch +4700 nop RX_0RRD "no operation" g5 esa,zarch +4710 bo RX_0RRD "branch on overflow / if ones" g5 esa,zarch +4720 bh RX_0RRD "branch on high" g5 esa,zarch +4720 bp RX_0RRD "branch on plus" g5 esa,zarch +4730 bnle RX_0RRD "branch on not low or equal" g5 esa,zarch +4740 bl RX_0RRD "branch on low" g5 esa,zarch +4740 bm RX_0RRD "branch on minus / if mixed" g5 esa,zarch +4750 bnhe RX_0RRD "branch on not high or equal" g5 esa,zarch +4760 blh RX_0RRD "branch on low or high" g5 esa,zarch +4770 bne RX_0RRD "branch on not equal" g5 esa,zarch +4770 bnz RX_0RRD "branch on not zero / if not zeros" g5 esa,zarch +4780 be RX_0RRD "branch on equal" g5 esa,zarch +4780 bz RX_0RRD "branch on zero / if zeros" g5 esa,zarch +4790 bnlh RX_0RRD "branch on not low or high" g5 esa,zarch +47a0 bhe RX_0RRD "branch on high or equal" g5 esa,zarch +47b0 bnl RX_0RRD "branch on not low" g5 esa,zarch +47b0 bnm RX_0RRD "branch on not minus / if not mixed" g5 esa,zarch +47c0 ble RX_0RRD "branch on low or equal" g5 esa,zarch +47d0 bnh RX_0RRD "branch on not high" g5 esa,zarch +47d0 bnp RX_0RRD "branch on not plus" g5 esa,zarch +47e0 bno RX_0RRD "branch on not overflow / if not ones" g5 esa,zarch +47f0 b RX_0RRD "unconditional branch" g5 esa,zarch +a714 jo RI_0P "jump on overflow / if ones" g5 esa,zarch +a724 jh RI_0P "jump on A high" g5 esa,zarch +a724 jp RI_0P "jump on plus" g5 esa,zarch +a734 jnle RI_0P "jump on not low or equal" g5 esa,zarch +a744 jl RI_0P "jump on A low" g5 esa,zarch +a744 jm RI_0P "jump on minus / if mixed" g5 esa,zarch +a754 jnhe RI_0P "jump on not high or equal" g5 esa,zarch +a764 jlh RI_0P "jump on low or high" g5 esa,zarch +a774 jne RI_0P "jump on A not equal B" g5 esa,zarch +a774 jnz RI_0P "jump on not zero / if not zeros" g5 esa,zarch +a784 je RI_0P "jump on A equal B" g5 esa,zarch +a784 jz RI_0P "jump on zero / if zeros" g5 esa,zarch +a794 jnlh RI_0P "jump on not low or high" g5 esa,zarch +a7a4 jhe RI_0P "jump on high or equal" g5 esa,zarch +a7b4 jnl RI_0P "jump on A not low" g5 esa,zarch +a7b4 jnm RI_0P "jump on not minus / if not mixed" g5 esa,zarch +a7c4 jle RI_0P "jump on low or equal" g5 esa,zarch +a7d4 jnh RI_0P "jump on A not high" g5 esa,zarch +a7d4 jnp RI_0P "jump on not plus" g5 esa,zarch +a7e4 jno RI_0P "jump on not overflow / if not ones" g5 esa,zarch +a7f4 j RI_0P "jump" g5 esa,zarch +b34a axbr RRE_FF "add extended bfp" g5 esa,zarch +b31a adbr RRE_FF "add long bfp" g5 esa,zarch +ed000000001a adb RXE_FRRD "add long bfp" g5 esa,zarch +b30a aebr RRE_FF "add short bfp" g5 esa,zarch +ed000000000a aeb RXE_FRRD "add short bfp" g5 esa,zarch +b349 cxbr RRE_FF "compare extended bfp" g5 esa,zarch +b319 cdbr RRE_FF "compare long bfp" g5 esa,zarch +ed0000000019 cdb RXE_FRRD "compare long bfp" g5 esa,zarch +b309 cebr RRE_FF "compare short bfp" g5 esa,zarch +ed0000000009 ceb RXE_FRRD "compare short bfp" g5 esa,zarch +b348 kxbr RRE_FF "compare and signal extended bfp" g5 esa,zarch +b318 kdbr RRE_FF "compare and signal long bfp" g5 esa,zarch +ed0000000018 kdb RXE_FRRD "compare and signal long bfp" g5 esa,zarch +b308 kebr RRE_FF "compare and signal short bfp" g5 esa,zarch +ed0000000008 keb RXE_FRRD "compare and signal short bfp" g5 esa,zarch +b396 cxfbr RRE_RF "convert from fixed 32 to extended bfp" g5 esa,zarch +b395 cdfbr RRE_RF "convert from fixed 32 to long bfp" g5 esa,zarch +b394 cefbr RRE_RF "convert from fixed 32 to short bfp" g5 esa,zarch +b39a cfxbr RRF_U0FR "convert to fixed extended bfp to 32" g5 esa,zarch +b399 cfdbr RRF_U0FR "convert to fixed long bfp to 32" g5 esa,zarch +b398 cfebr RRF_U0FR "convert to fixed short bfp to 32" g5 esa,zarch +b34d dxbr RRE_FF "divide extended bfp" g5 esa,zarch +b31d ddbr RRE_FF "divide long bfp" g5 esa,zarch +ed000000001d ddb RXE_FRRD "divide long bfp" g5 esa,zarch +b30d debr RRE_FF "divide short bfp" g5 esa,zarch +ed000000000d deb RXE_FRRD "divide short bfp" g5 esa,zarch +b35b didbr RRF_FUFF "divide to integer long bfp" g5 esa,zarch +b353 diebr RRF_FUFF "divide to integer short bfp" g5 esa,zarch +b38c efpc RRE_RR "extract fpc" g5 esa,zarch +b342 ltxbr RRE_FF "load and test extended bfp" g5 esa,zarch +b312 ltdbr RRE_FF "load and test long bfp" g5 esa,zarch +b302 ltebr RRE_FF "load and test short bfp" g5 esa,zarch +b343 lcxbr RRE_FF "load complement extended bfp" g5 esa,zarch +b313 lcdbr RRE_FF "load complement long bfp" g5 esa,zarch +b303 lcebr RRE_FF "load complement short bfp" g5 esa,zarch +b347 fixbr RRF_U0FF "load fp integer extended bfp" g5 esa,zarch +b35f fidbr RRF_U0FF "load fp integer long bfp" g5 esa,zarch +b357 fiebr RRF_U0FF "load fp integer short bfp" g5 esa,zarch +b29d lfpc S_RD "load fpc" g5 esa,zarch +b305 lxdbr RRE_FF "load lengthened long to extended bfp" g5 esa,zarch +ed0000000005 lxdb RXE_FRRD "load lengthened long to extended bfp" g5 esa,zarch +b306 lxebr RRE_FF "load lengthened short to extended bfp" g5 esa,zarch +ed0000000006 lxeb RXE_FRRD "load lengthened short to extended bfp" g5 esa,zarch +b304 ldebr RRE_FF "load lengthened short to long bfp" g5 esa,zarch +ed0000000004 ldeb RXE_FRRD "load lengthened short to long bfp" g5 esa,zarch +b341 lnxbr RRE_FF "load negative extended bfp" g5 esa,zarch +b311 lndbr RRE_FF "load negative long bfp" g5 esa,zarch +b301 lnebr RRE_FF "load negative short bfp" g5 esa,zarch +b340 lpxbr RRE_FF "load positive extended bfp" g5 esa,zarch +b310 lpdbr RRE_FF "load positive long bfp" g5 esa,zarch +b300 lpebr RRE_FF "load positive short bfp" g5 esa,zarch +b345 ldxbr RRE_FF "load rounded extended to long bfp" g5 esa,zarch +b346 lexbr RRE_FF "load rounded extended to short bfp" g5 esa,zarch +b344 ledbr RRE_FF "load rounded long to short bfp" g5 esa,zarch +b34c mxbr RRE_FF "multiply extended bfp" g5 esa,zarch +b31c mdbr RRE_FF "multiply long bfp" g5 esa,zarch +ed000000001c mdb RXE_FRRD "multiply long bfp" g5 esa,zarch +b307 mxdbr RRE_FF "multiply long to extended bfp" g5 esa,zarch +ed0000000007 mxdb RXE_FRRD "multiply long to extended bfp" g5 esa,zarch +b317 meebr RRE_FF "multiply short bfp" g5 esa,zarch +ed0000000017 meeb RXE_FRRD "multiply short bfp" g5 esa,zarch +b30c mdebr RRE_FF "multiply short to long bfp" g5 esa,zarch +ed000000000c mdeb RXE_FRRD "multiply short to long bfp" g5 esa,zarch +b31e madbr RRF_F0FF "multiply and add long bfp" g5 esa,zarch +ed000000001e madb RXF_FRRDF "multiply and add long bfp" g5 esa,zarch +b30e maebr RRF_F0FF "multiply and add short bfp" g5 esa,zarch +ed000000000e maeb RXF_FRRDF "multiply and add short bfp" g5 esa,zarch +b31f msdbr RRF_F0FF "multiply and subtract long bfp" g5 esa,zarch +ed000000001f msdb RXF_FRRDF "multiply and subtract long bfp" g5 esa,zarch +b30f msebr RRF_F0FF "multiply and subtract short bfp" g5 esa,zarch +ed000000000f mseb RXF_FRRDF "multiply and subtract short bfp" g5 esa,zarch +b384 sfpc RRE_RR "set fpc" g5 esa,zarch +b299 srnm S_RD "set rounding mode" g5 esa,zarch +b316 sqxbr RRE_FF "square root extended bfp" g5 esa,zarch +b315 sqdbr RRE_FF "square root long bfp" g5 esa,zarch +ed0000000015 sqdb RXE_FRRD "square root long bfp" g5 esa,zarch +b314 sqebr RRE_FF "square root short bfp" g5 esa,zarch +ed0000000014 sqeb RXE_FRRD "square root short bfp" g5 esa,zarch +b29c stfpc S_RD "store fpc" g5 esa,zarch +b34b sxbr RRE_FF "subtract extended bfp" g5 esa,zarch +b31b sdbr RRE_FF "subtract long bfp" g5 esa,zarch +ed000000001b sdb RXE_FRRD "subtract long bfp" g5 esa,zarch +b30b sebr RRE_FF "subtract short bfp" g5 esa,zarch +ed000000000b seb RXE_FRRD "subtract short bfp" g5 esa,zarch +ed0000000012 tcxb RXE_FRRD "test data class extended bfp" g5 esa,zarch +ed0000000011 tcdb RXE_FRRD "test data class long bfp" g5 esa,zarch +ed0000000010 tceb RXE_FRRD "test data class short bfp" g5 esa,zarch +b274 siga S_RD "signal adapter" g5 esa,zarch +b2a6 cuutf RRE_RR "convert unicode to utf-8" g5 esa,zarch +b2a7 cutfu RRE_RR "convert utf-8 to unicode" g5 esa,zarch +ee plo SS_RRRDRD2 "perform locked operation" g5 esa,zarch +b25a bsa RRE_RR "branch and set authority" g5 esa,zarch +b277 rp S_RD "resume program" g5 esa,zarch +0107 sckpf E "set clock programmable field" g5 esa,zarch +b27d stsi S_RD "store system information" g5 esa,zarch +01ff trap2 E "trap" g5 esa,zarch +b2ff trap4 S_RD "trap4" g5 esa,zarch +a700 tmlh RI_RU "test under mask low high" g5 esa,zarch +a701 tmll RI_RU "test under mask low low" g5 esa,zarch +b278 stcke S_RD "store clock extended" g5 esa,zarch +b2a5 tre RRE_RR "translate extended" g5 esa,zarch +eb000000008e mvclu RSE_RRRD "move long unicode" g5 esa,zarch +e9 pka SS_L0RDRD "pack ascii" g5 esa,zarch +e1 pku SS_L0RDRD "pack unicode" g5 esa,zarch +b993 troo RRE_RR "translate one to one" g5 esa,zarch +b992 trot RRE_RR "translate one to two" g5 esa,zarch +b991 trto RRE_RR "translate two to one" g5 esa,zarch +b990 trtt RRE_RR "translate two to two" g5 esa,zarch +ea unpka SS_L0RDRD "unpack ascii" g5 esa,zarch +e2 unpku SS_L0RDRD "unpack unicode" g5 esa,zarch +b358 thder RRE_RR "convert short bfp to long hfp" g5 esa,zarch +b359 thdr RRE_RR "convert long bfp to long hfp" g5 esa,zarch +b350 tbedr RRF_U0FF "convert long hfp to short bfp" g5 esa,zarch +b351 tbdr RRF_U0FF "convert long hfp to long bfp" g5 esa,zarch +b374 lzer RRE_R0 "load short zero" g5 esa,zarch +b375 lzdr RRE_R0 "load long zero" g5 esa,zarch +b376 lzxr RRE_R0 "load extended zero" g5 esa,zarch # Here are the new esame instructions: -b946 bctgr RRE_RR "branch on count 64" esame -b900 lpgr RRE_RR "load positive 64" esame -b910 lpgfr RRE_RR "load positive 64<32" esame -b901 lngr RRE_RR "load negative 64" esame -b911 lngfr RRE_RR "load negative 64<32" esame -b902 ltgr RRE_RR "load and test 64" esame -b912 ltgfr RRE_RR "load and test 64<32" esame -b903 lcgr RRE_RR "load complement 64" esame -b913 lcgfr RRE_RR "load complement 64<32" esame -b980 ngr RRE_RR "and 64" esame -b921 clgr RRE_RR "compare logical 64" esame -b931 clgfr RRE_RR "compare logical 64<32" esame -b981 ogr RRE_RR "or 64" esame -b982 xgr RRE_RR "exclusive or 64" esame -b904 lgr RRE_RR "load 64" esame -b914 lgfr RRE_RR "load 64<32" esame -b920 cgr RRE_RR "compare 64" esame -b930 cgfr RRE_RR "compare 64<32" esame -b908 agr RRE_RR "add 64" esame -b918 agfr RRE_RR "add 64<32" esame -b909 sgr RRE_RR "subtract 64" esame -b919 sgfr RRE_RR "subtract 64<32" esame -b90a algr RRE_RR "add logical 64" esame -b91a algfr RRE_RR "add logical 64<32" esame -b90b slgr RRE_RR "subtract logical 64" esame -b91b slgfr RRE_RR "subtract logical 64<32" esame -e30000000046 bctg RXE_RRRD "branch on count 64" esame -e3000000002e cvdg RXE_RRRD "convert to decimal 64" esame -e3000000000e cvbg RXE_RRRD "convert to binary 64" esame -e30000000024 stg RXE_RRRD "store 64" esame -e30000000080 ng RXE_RRRD "and 64" esame -e30000000021 clg RXE_RRRD "compare logical 64" esame -e30000000031 clgf RXE_RRRD "comparee logical 64<32" esame -e30000000081 og RXE_RRRD "or 64" esame -e30000000082 xg RXE_RRRD "exclusive or 64" esame -e30000000004 lg RXE_RRRD "load 64" esame -e30000000014 lgf RXE_RRRD "load 64<32" esame -e30000000015 lgh RXE_RRRD "load halfword 64" esame -e30000000020 cg RXE_RRRD "compare 64" esame -e30000000030 cgf RXE_RRRD "compare 64<32" esame -e30000000008 ag RXE_RRRD "add 64" esame -e30000000018 agf RXE_RRRD "add 64<32" esame -e30000000009 sg RXE_RRRD "subtract 64" esame -e30000000019 sgf RXE_RRRD "subtract 64<32" esame -e3000000000a alg RXE_RRRD "add logical 64" esame -e3000000001a algf RXE_RRRD "add logical 64<32" esame -e3000000000b slg RXE_RRRD "subtract logical 64" esame -e3000000001b slgf RXE_RRRD "subtract logical 64<32" esame -e3000000000c msg RXE_RRRD "multiply single 64" esame -e3000000001c msgf RXE_RRRD "multiply single 64<32" esame -ec0000000044 brxhg RIE_RRP "branch relative on index high 64" esame -ec0000000045 brxlg RIE_RRP "branch relative on index low or equal 64" esame -eb0000000044 bxhg RSE_RRRD "branch on index high 64" esame -eb0000000045 bxleg RSE_RRRD "branch on index low or equal 64" esame -eb000000000c srlg RSE_RRRD "shift right single logical 64" esame -eb000000000d sllg RSE_RRRD "shift left single logical 64" esame -eb000000000a srag RSE_RRRD "shift right single 64" esame -eb000000000b slag RSE_RRRD "shift left single 64" esame -eb0000000024 stmg RSE_RRRD "store multiple 64" esame -eb0000000026 stmh RSE_RRRD "store multiple high" esame -eb0000000004 lmg RSE_RRRD "load multiple 64" esame -eb0000000096 lmh RSE_RRRD "load multiple high" esame -ef lmd SS_RRRDRD3 "load multiple disjoint" esame -eb000000000f tracg RSE_RRRD "trace 64" esame -e30000000003 lrag RXE_RRRD "load real address 64" esame -e50000000002 strag SSE_RDRD "store read address" esame -eb0000000025 stctg RSE_RRRD "store control 64" esame -eb000000002f lctlg RSE_RRRD "load control 64" esame -eb0000000030 csg RSE_RRRD "compare and swap 64" esame -eb000000003e cdsg RSE_RRRD "compare double and swap 64" esame -eb0000000020 clmh RSE_RURD "compare logical characters under mask high" esame -eb000000002c stcmh RSE_RURD "store characters under mask high" esame -eb0000000080 icmh RSE_RURD "insert characters under mask high" esame -a700 tmlh RI_RU "test under mask low high" esame -a702 tmhh RI_RU "test under mask high high" esame -a701 tmll RI_RU "test under mask low low" esame -a703 tmhl RI_RU "test under mask high low" esame -c004 brcl RIL_UP "branch relative on condition long" esame -c014 jgo RIL_0P "jump long on overflow / if ones" esame -c024 jgh RIL_0P "jump long on high" esame -c024 jgp RIL_0P "jump long on plus" esame -c034 jgnle RIL_0P "jump long on not low or equal" esame -c044 jgl RIL_0P "jump long on low" esame -c044 jgm RIL_0P "jump long on minus / if mixed" esame -c054 jgnhe RIL_0P "jump long on not high or equal" esame -c064 jglh RIL_0P "jump long on low or high" esame -c074 jgne RIL_0P "jump long on not equal" esame -c074 jgnz RIL_0P "jump long on not zero / if not zeros" esame -c084 jge RIL_0P "jump long on equal" esame -c084 jgz RIL_0P "jump long on zero / if zeros" esame -c094 jgnlh RIL_0P "jump long on not low or high" esame -c0a4 jghe RIL_0P "jump long on high or equal" esame -c0b4 jgnl RIL_0P "jump long on not low" esame -c0b4 jgnm RIL_0P "jump long on not minus / if not mixed" esame -c0c4 jgle RIL_0P "jump long on low or equal" esame -c0d4 jgnh RIL_0P "jump long on not high" esame -c0d4 jgnp RIL_0P "jump long on not plus" esame -c0e4 jgno RIL_0P "jump long on not overflow / if not ones" esame -c0f4 jg RIL_0P "jump long" esame -c005 brasl RIL_RP "branch relative and save long" esame -a707 brctg RI_RP "branch relative on count 64" esame -a709 lghi RI_RI "load halfword immediate 64" esame -a70b aghi RI_RI "add halfword immediate 64" esame -a70d mghi RI_RI "multiply halfword immediate 64" esame -a70f cghi RI_RI "compare halfword immediate 64" esame -b925 sturg RRE_RR "store using real address 64" esame -b90e eregg RRE_RR "extract stacked registers 64" esame -b905 lurag RRE_RR "load using real address 64" esame -b90c msgr RRE_RR "multiply single 64" esame -b91c msgfr RRE_RR "multiply single 64<32" esame -b3a4 cegbr RRE_RR "convert from fixed 64 to short bfp" esame -b3a5 cdgbr RRE_RR "convert from fixed 64 to long bfp" esame -b3a6 cxgbr RRE_RR "convert from fixed 64 to extended bfp" esame -b3a8 cgebr RRF_U0FR "convert to fixed short bfd to 64" esame -b3a9 cgdbr RRF_U0FR "convert to fixed long bfp to 64" esame -b3aa cgxbr RRF_U0FR "convert to fixed extended bfp to 64" esame -b3c4 cegr RRE_RR "convert from fixed 64 to short hfp" esame -b3c5 cdgr RRE_RR "convert from fixed 64 to long hfp" esame -b3c6 cxgr RRE_RR "convert from fixed 64 to extended hfp" esame -b3c8 cger RRF_U0FR "convert to fixed short hfp to 64" esame -b3c9 cgdr RRF_U0FR "convert to fixed long hfp to 64" esame -b3ca cgxr RRF_U0FR "convert to fixed extended hfp to 64" esame -010b tam E "test addressing mode" esame -010c sam24 E "set addressing mode 24" esame -010d sam31 E "set addressing mode 31" esame -010e sam64 E "set addressing mode 64" esame -a500 iihh RI_RU "insert immediate high high" esame -a501 iihl RI_RU "insert immediate high low" esame -a502 iilh RI_RU "insert immediate low high" esame -a503 iill RI_RU "insert immediate low low" esame -a504 nihh RI_RU "and immediate high high" esame -a505 nihl RI_RU "and immediate high low" esame -a506 nilh RI_RU "and immediate low high" esame -a507 nill RI_RU "and immediate low low" esame -a508 oihh RI_RU "or immediate high high" esame -a509 oihl RI_RU "or immediate high low" esame -a50a oilh RI_RU "or immediate low high" esame -a50b oill RI_RU "or immediate low low" esame -a50c llihh RI_RU "load logical immediate high high" esame -a50d llihl RI_RU "load logical immediate high low" esame -a50e llilh RI_RU "load logical immediate low high" esame -a50f llill RI_RU "load logical immediate low low" esame -b2b1 stfl S_RD "store facility list" esame -b2b2 lpswe S_RD "load psw extended" esame -b90d dsgr RRE_RR "divide single 64" esame -b90f lrvgr RRE_RR "load reversed 64" esame -b916 llgfr RRE_RR "load logical 64<32" esame -b917 llgtr RRE_RR "load logical thirty one bits" esame -b91d dsgfr RRE_RR "divide single 64<32" esame -b91f lrvr RRE_RR "load reversed 32" esame -b986 mlgr RRE_RR "multiply logical 64" esame -b987 dlgr RRE_RR "divide logical 64" esame -b988 alcgr RRE_RR "add logical with carry 64" esame -b989 slbgr RRE_RR "subtract logical with borrow 64" esame -b98d epsw RRE_RR "extract psw" esame -b996 mlr RRE_RR "multiply logical 32" esame -b997 dlr RRE_RR "divide logical 32" esame -b998 alcr RRE_RR "add logical with carry 32" esame -b999 slbr RRE_RR "subtract logical with borrow 32" esame -b99d esea RRE_R0 "extract and set extended authority" esame -c000 larl RIL_RP "load address relative long" esame -e3000000000d dsg RXE_RRRD "divide single 64" esame -e3000000000f lrvg RXE_RRRD "load reversed 64" esame -e30000000016 llgf RXE_RRRD "load logical 64<32" esame -e30000000017 llgt RXE_RRRD "load logical thirty one bits" esame -e3000000001d dsgf RXE_RRRD "divide single 64<32" esame -e3000000001e lrv RXE_RRRD "load reversed 32" esame -e3000000001f lrvh RXE_RRRD "load reversed 16" esame -e3000000002f strvg RXE_RRRD "store reversed 64" esame -e3000000003e strv RXE_RRRD "store reversed 32" esame -e3000000003f strvh RXE_RRRD "store reversed 64" esame -e30000000086 mlg RXE_RRRD "multiply logical 64" esame -e30000000087 dlg RXE_RRRD "divide logical 64" esame -e30000000088 alcg RXE_RRRD "add logical with carry 64" esame -e30000000089 slbg RXE_RRRD "subtract logical with borrow 64" esame -e3000000008e stpq RXE_RRRD "store pair to quadword" esame -e3000000008f lpq RXE_RRRD "load pair from quadword" esame -e30000000096 ml RXE_RRRD "multiply logical 32" esame -e30000000097 dl RXE_RRRD "divide logical 32" esame -e30000000098 alc RXE_RRRD "add logical with carry 32" esame -e30000000099 slb RXE_RRRD "subtract logical with borrow 32" esame -e30000000090 llgc RXE_RRRD "load logical character" esame -e30000000091 llgh RXE_RRRD "load logical halfword" esame -eb000000001c rllg RSE_RRRD "rotate left single logical 64" esame -eb000000001d rll RSE_RRRD "rotate left single logical 32" esame -b278 stcke S_RD "store clock extended" esame -b2a5 tre RRE_RR "translate extended" esame -eb000000008e mvclu RSE_RRRD "move long unicode" esame -e9 pka SS_L0RDRD "pack ascii" esame -e1 pku SS_L0RDRD "pack unicode" esame -b993 troo RRE_RR "translate one to one" esame -b992 trot RRE_RR "translate one to two" esame -b991 trto RRE_RR "translate two to one" esame -b990 trtt RRE_RR "translate two to two" esame -ea unpka SS_L0RDRD "unpack ascii" esame -e2 unpku SS_L0RDRD "unpack unicode" esame -b358 thder RRE_RR "convert short bfp to long hfp" esame -b359 thdr RRE_RR "convert long bfp to long hfp" esame -b350 tbedr RRF_U0FF "convert long hfp to short bfp" esame -b351 tbdr RRF_U0FF "convert long hfp to long bfp" esame -b374 lzer RRE_R0 "load short zero" esame -b375 lzdr RRE_R0 "load long zero" esame -b376 lzxr RRE_R0 "load extended zero" esame +b946 bctgr RRE_RR "branch on count 64" z900 zarch +b900 lpgr RRE_RR "load positive 64" z900 zarch +b910 lpgfr RRE_RR "load positive 64<32" z900 zarch +b901 lngr RRE_RR "load negative 64" z900 zarch +b911 lngfr RRE_RR "load negative 64<32" z900 zarch +b902 ltgr RRE_RR "load and test 64" z900 zarch +b912 ltgfr RRE_RR "load and test 64<32" z900 zarch +b903 lcgr RRE_RR "load complement 64" z900 zarch +b913 lcgfr RRE_RR "load complement 64<32" z900 zarch +b980 ngr RRE_RR "and 64" z900 zarch +b921 clgr RRE_RR "compare logical 64" z900 zarch +b931 clgfr RRE_RR "compare logical 64<32" z900 zarch +b981 ogr RRE_RR "or 64" z900 zarch +b982 xgr RRE_RR "exclusive or 64" z900 zarch +b904 lgr RRE_RR "load 64" z900 zarch +b914 lgfr RRE_RR "load 64<32" z900 zarch +b920 cgr RRE_RR "compare 64" z900 zarch +b930 cgfr RRE_RR "compare 64<32" z900 zarch +b908 agr RRE_RR "add 64" z900 zarch +b918 agfr RRE_RR "add 64<32" z900 zarch +b909 sgr RRE_RR "subtract 64" z900 zarch zarch +b919 sgfr RRE_RR "subtract 64<32" z900 zarch +b90a algr RRE_RR "add logical 64" z900 zarch +b91a algfr RRE_RR "add logical 64<32" z900 zarch +b90b slgr RRE_RR "subtract logical 64" z900 zarch +b91b slgfr RRE_RR "subtract logical 64<32" z900 zarch +e30000000046 bctg RXE_RRRD "branch on count 64" z900 zarch +e3000000002e cvdg RXE_RRRD "convert to decimal 64" z900 zarch +e3000000000e cvbg RXE_RRRD "convert to binary 64" z900 zarch +e30000000024 stg RXE_RRRD "store 64" z900 zarch +e30000000080 ng RXE_RRRD "and 64" z900 zarch +e30000000021 clg RXE_RRRD "compare logical 64" z900 zarch +e30000000031 clgf RXE_RRRD "comparee logical 64<32" z900 zarch +e30000000081 og RXE_RRRD "or 64" z900 zarch +e30000000082 xg RXE_RRRD "exclusive or 64" z900 zarch +e30000000004 lg RXE_RRRD "load 64" z900 zarch +e30000000014 lgf RXE_RRRD "load 64<32" z900 zarch +e30000000015 lgh RXE_RRRD "load halfword 64" z900 zarch +e30000000020 cg RXE_RRRD "compare 64" z900 zarch +e30000000030 cgf RXE_RRRD "compare 64<32" z900 zarch +e30000000008 ag RXE_RRRD "add 64" z900 zarch +e30000000018 agf RXE_RRRD "add 64<32" z900 zarch +e30000000009 sg RXE_RRRD "subtract 64" z900 zarch +e30000000019 sgf RXE_RRRD "subtract 64<32" z900 zarch +e3000000000a alg RXE_RRRD "add logical 64" z900 zarch +e3000000001a algf RXE_RRRD "add logical 64<32" z900 zarch +e3000000000b slg RXE_RRRD "subtract logical 64" z900 zarch +e3000000001b slgf RXE_RRRD "subtract logical 64<32" z900 zarch +e3000000000c msg RXE_RRRD "multiply single 64" z900 zarch +e3000000001c msgf RXE_RRRD "multiply single 64<32" z900 zarch +ec0000000044 brxhg RIE_RRP "branch relative on index high 64" z900 zarch +ec0000000045 brxlg RIE_RRP "branch relative on index low or equal 64" z900 zarch +eb0000000044 bxhg RSE_RRRD "branch on index high 64" z900 zarch +eb0000000045 bxleg RSE_RRRD "branch on index low or equal 64" z900 zarch +eb000000000c srlg RSE_RRRD "shift right single logical 64" z900 zarch +eb000000000d sllg RSE_RRRD "shift left single logical 64" z900 zarch +eb000000000a srag RSE_RRRD "shift right single 64" z900 zarch +eb000000000b slag RSE_RRRD "shift left single 64" z900 zarch +eb0000000024 stmg RSE_RRRD "store multiple 64" z900 zarch +eb0000000026 stmh RSE_RRRD "store multiple high" z900 zarch +eb0000000004 lmg RSE_RRRD "load multiple 64" z900 zarch +eb0000000096 lmh RSE_RRRD "load multiple high" z900 zarch +ef lmd SS_RRRDRD3 "load multiple disjoint" z900 zarch +eb000000000f tracg RSE_RRRD "trace 64" z900 zarch +e30000000003 lrag RXE_RRRD "load real address 64" z900 zarch +e50000000002 strag SSE_RDRD "store read address" z900 zarch +eb0000000025 stctg RSE_RRRD "store control 64" z900 zarch +eb000000002f lctlg RSE_RRRD "load control 64" z900 zarch +eb0000000030 csg RSE_RRRD "compare and swap 64" z900 zarch +eb000000003e cdsg RSE_RRRD "compare double and swap 64" z900 zarch +eb0000000020 clmh RSE_RURD "compare logical characters under mask high" z900 zarch +eb000000002c stcmh RSE_RURD "store characters under mask high" z900 zarch +eb0000000080 icmh RSE_RURD "insert characters under mask high" z900 zarch +a702 tmhh RI_RU "test under mask high high" z900 zarch +a703 tmhl RI_RU "test under mask high low" z900 zarch +c004 brcl RIL_UP "branch relative on condition long" z900 esa,zarch +c014 jgo RIL_0P "jump long on overflow / if ones" z900 esa,zarch +c024 jgh RIL_0P "jump long on high" z900 esa,zarch +c024 jgp RIL_0P "jump long on plus" z900 esa,zarch +c034 jgnle RIL_0P "jump long on not low or equal" z900 esa,zarch +c044 jgl RIL_0P "jump long on low" z900 esa,zarch +c044 jgm RIL_0P "jump long on minus / if mixed" z900 esa,zarch +c054 jgnhe RIL_0P "jump long on not high or equal" z900 esa,zarch +c064 jglh RIL_0P "jump long on low or high" z900 esa,zarch +c074 jgne RIL_0P "jump long on not equal" z900 esa,zarch +c074 jgnz RIL_0P "jump long on not zero / if not zeros" z900 esa,zarch +c084 jge RIL_0P "jump long on equal" z900 esa,zarch +c084 jgz RIL_0P "jump long on zero / if zeros" z900 esa,zarch +c094 jgnlh RIL_0P "jump long on not low or high" z900 esa,zarch +c0a4 jghe RIL_0P "jump long on high or equal" z900 esa,zarch +c0b4 jgnl RIL_0P "jump long on not low" z900 esa,zarch +c0b4 jgnm RIL_0P "jump long on not minus / if not mixed" z900 esa,zarch +c0c4 jgle RIL_0P "jump long on low or equal" z900 esa,zarch +c0d4 jgnh RIL_0P "jump long on not high" z900 esa,zarch +c0d4 jgnp RIL_0P "jump long on not plus" z900 esa,zarch +c0e4 jgno RIL_0P "jump long on not overflow / if not ones" z900 esa,zarch +c0f4 jg RIL_0P "jump long" z900 esa,zarch +c005 brasl RIL_RP "branch relative and save long" z900 esa,zarch +a707 brctg RI_RP "branch relative on count 64" z900 zarch +a709 lghi RI_RI "load halfword immediate 64" z900 zarch +a70b aghi RI_RI "add halfword immediate 64" z900 zarch +a70d mghi RI_RI "multiply halfword immediate 64" z900 zarch +a70f cghi RI_RI "compare halfword immediate 64" z900 zarch +b925 sturg RRE_RR "store using real address 64" z900 zarch +b90e eregg RRE_RR "extract stacked registers 64" z900 zarch +b905 lurag RRE_RR "load using real address 64" z900 zarch +b90c msgr RRE_RR "multiply single 64" z900 zarch +b91c msgfr RRE_RR "multiply single 64<32" z900 zarch +b3a4 cegbr RRE_RR "convert from fixed 64 to short bfp" z900 zarch +b3a5 cdgbr RRE_RR "convert from fixed 64 to long bfp" z900 zarch +b3a6 cxgbr RRE_RR "convert from fixed 64 to extended bfp" z900 zarch +b3a8 cgebr RRF_U0FR "convert to fixed short bfd to 64" z900 zarch +b3a9 cgdbr RRF_U0FR "convert to fixed long bfp to 64" z900 zarch +b3aa cgxbr RRF_U0FR "convert to fixed extended bfp to 64" z900 zarch +b3c4 cegr RRE_RR "convert from fixed 64 to short hfp" z900 zarch +b3c5 cdgr RRE_RR "convert from fixed 64 to long hfp" z900 zarch +b3c6 cxgr RRE_RR "convert from fixed 64 to extended hfp" z900 zarch +b3c8 cger RRF_U0FR "convert to fixed short hfp to 64" z900 zarch +b3c9 cgdr RRF_U0FR "convert to fixed long hfp to 64" z900 zarch +b3ca cgxr RRF_U0FR "convert to fixed extended hfp to 64" z900 zarch +010b tam E "test addressing mode" z900 esa,zarch +010c sam24 E "set addressing mode 24" z900 esa,zarch +010d sam31 E "set addressing mode 31" z900 esa,zarch +010e sam64 E "set addressing mode 64" z900 zarch +a500 iihh RI_RU "insert immediate high high" z900 zarch +a501 iihl RI_RU "insert immediate high low" z900 zarch +a502 iilh RI_RU "insert immediate low high" z900 zarch +a503 iill RI_RU "insert immediate low low" z900 zarch +a504 nihh RI_RU "and immediate high high" z900 zarch +a505 nihl RI_RU "and immediate high low" z900 zarch +a506 nilh RI_RU "and immediate low high" z900 zarch +a507 nill RI_RU "and immediate low low" z900 zarch +a508 oihh RI_RU "or immediate high high" z900 zarch +a509 oihl RI_RU "or immediate high low" z900 zarch +a50a oilh RI_RU "or immediate low high" z900 zarch +a50b oill RI_RU "or immediate low low" z900 zarch +a50c llihh RI_RU "load logical immediate high high" z900 zarch +a50d llihl RI_RU "load logical immediate high low" z900 zarch +a50e llilh RI_RU "load logical immediate low high" z900 zarch +a50f llill RI_RU "load logical immediate low low" z900 zarch +b2b1 stfl S_RD "store facility list" z900 esa,zarch +b2b2 lpswe S_RD "load psw extended" z900 zarch +b90d dsgr RRE_RR "divide single 64" z900 zarch +b90f lrvgr RRE_RR "load reversed 64" z900 zarch +b916 llgfr RRE_RR "load logical 64<32" z900 zarch +b917 llgtr RRE_RR "load logical thirty one bits" z900 zarch +b91d dsgfr RRE_RR "divide single 64<32" z900 zarch +b91f lrvr RRE_RR "load reversed 32" z900 esa,zarch +b986 mlgr RRE_RR "multiply logical 64" z900 zarch +b987 dlgr RRE_RR "divide logical 64" z900 zarch +b988 alcgr RRE_RR "add logical with carry 64" z900 zarch +b989 slbgr RRE_RR "subtract logical with borrow 64" z900 zarch +b98d epsw RRE_RR "extract psw" z900 esa,zarch +b996 mlr RRE_RR "multiply logical 32" z900 esa,zarch +b997 dlr RRE_RR "divide logical 32" z900 esa,zarch +b998 alcr RRE_RR "add logical with carry 32" z900 esa,zarch +b999 slbr RRE_RR "subtract logical with borrow 32" z900 esa,zarch +b99d esea RRE_R0 "extract and set extended authority" z900 zarch +c000 larl RIL_RP "load address relative long" z900 esa,zarch +e3000000000d dsg RXE_RRRD "divide single 64" z900 zarch +e3000000000f lrvg RXE_RRRD "load reversed 64" z900 zarch +e30000000016 llgf RXE_RRRD "load logical 64<32" z900 zarch +e30000000017 llgt RXE_RRRD "load logical thirty one bits" z900 zarch +e3000000001d dsgf RXE_RRRD "divide single 64<32" z900 zarch +e3000000001e lrv RXE_RRRD "load reversed 32" z900 esa,zarch +e3000000001f lrvh RXE_RRRD "load reversed 16" z900 esa,zarch +e3000000002f strvg RXE_RRRD "store reversed 64" z900 zarch +e3000000003e strv RXE_RRRD "store reversed 32" z900 esa,zarch +e3000000003f strvh RXE_RRRD "store reversed 64" z900 esa,zarch +e30000000086 mlg RXE_RRRD "multiply logical 64" z900 zarch +e30000000087 dlg RXE_RRRD "divide logical 64" z900 zarch +e30000000088 alcg RXE_RRRD "add logical with carry 64" z900 zarch +e30000000089 slbg RXE_RRRD "subtract logical with borrow 64" z900 zarch +e3000000008e stpq RXE_RRRD "store pair to quadword" z900 zarch +e3000000008f lpq RXE_RRRD "load pair from quadword" z900 zarch +e30000000096 ml RXE_RRRD "multiply logical 32" z900 esa,zarch +e30000000097 dl RXE_RRRD "divide logical 32" z900 esa,zarch +e30000000098 alc RXE_RRRD "add logical with carry 32" z900 esa,zarch +e30000000099 slb RXE_RRRD "subtract logical with borrow 32" z900 esa,zarch +e30000000090 llgc RXE_RRRD "load logical character" z900 zarch +e30000000091 llgh RXE_RRRD "load logical halfword" z900 zarch +eb000000001c rllg RSE_RRRD "rotate left single logical 64" z900 zarch +eb000000001d rll RSE_RRRD "rotate left single logical 32" z900 esa,zarch +b369 cxr RRE_FF "compare extended hfp" g5 esa,zarch +b3b6 cxfr RRE_RF "convert from fixed 32 to extended hfp" g5 esa,zarch +b3b5 cdfr RRE_RF "convert from fixed 32 to long hfp" g5 esa,zarch +b3b4 cefr RRE_RF "convert from fixed 32 to short hfp" g5 esa,zarch +b3ba cfxr RRF_U0FR "convert to fixed extended hfp to 32" z900 zarch +b3b9 cfdr RRF_U0FR "convert to fixed long hfp to 32" z900 zarch +b3b8 cfer RRF_U0FR "convert to fixed short hfp to 32" z900 zarch +b362 ltxr RRE_FF "load and test extended hfp" g5 esa,zarch +b363 lcxr RRE_FF "load complement extended hfp" g5 esa,zarch +b367 fixr RRF_U0FF "load fp integer extended hfp" g5 esa,zarch +b37f fidr RRF_U0FF "load fp integer long hfp" g5 esa,zarch +b377 fier RRF_U0FF "load fp integer short hfp" g5 esa,zarch +b325 lxdr RRE_FF "load lengthened long to extended hfp" g5 esa,zarch +ed0000000025 lxd RXE_FRRD "load lengthened long to extended hfp" g5 esa,zarch +b326 lxer RRE_FF "load lengthened short to extended hfp" g5 esa,zarch +ed0000000026 lxe RXE_FRRD "load lengthened short to extended hfp" g5 esa,zarch +b324 lder RRE_FF "load lengthened short to long hfp" g5 esa,zarch +ed0000000024 lde RXE_FRRD "load lengthened short to long hfp" g5 esa,zarch +b361 lnxr RRE_FF "load negative long hfp" g5 esa,zarch +b360 lpxr RRE_FF "load positive long hfp" g5 esa,zarch +b366 lexr RRE_FF "load rounded extended to short hfp" g5 esa,zarch +35 ledr RR_FF "load rounded long to short hfp" g5 esa,zarch +b337 meer RRE_FF "multiply short hfp" g5 esa,zarch +ed0000000037 mee RXE_FRRD "multiply short hfp" g5 esa,zarch +b336 sqxr RRE_FF "square root extended hfp" g5 esa,zarch +ed0000000034 sqe RXE_FRRD "square root short hfp" g5 esa,zarch +b263 cmpsc RRE_RR "compression call" g5 esa,zarch +eb00000000c0 tp RSL_R0RD "test decimal" g5 esa,zarch +b365 lxr RRE_RR "load extended hfp" g5 esa,zarch +b22e pgin RRE_RR "page in" g5 esa,zarch +b22f pgout RRE_RR "page out" g5 esa,zarch +b276 xsch S_00 "cancel subchannel" g5 esa,zarch +# New long displacement instructions on z990 +e3000000005a ay RXY_RRRD "add with long offset" z990 zarch +e3000000007a ahy RXY_RRRD "add halfword with long offset" z990 zarch +e3000000005e aly RXY_RRRD "add logical with long offset" z990 zarch +eb0000000054 niy SIY_URD "and immediate with long offset" z990 zarch +e30000000054 ny RXY_RRRD "and with long offset" z990 zarch +e30000000059 cy RXY_RRRD "compare with long offset" z990 zarch +eb0000000014 csy RSY_RRRD "compare and swap with long offset" z990 zarch +eb0000000031 cdsy RSY_RRRD "compare double and swap with long offset" z990 zarch +e30000000079 chy RXY_RRRD "compare halfword with long offset" z990 zarch +e30000000055 cly RXY_RRRD "compare logical with long offset" z990 zarch +eb0000000055 cliy SIY_URD "compare logical immediate with long offset" z990 zarch +eb0000000021 clmy RSY_RURD "compare logical characters under mask with long offset" z990 zarch +e30000000006 cvby RXY_RRRD "convert to binary with long offset" z990 zarch +e30000000026 cvdy RXY_RRRD "convert to decimal with long offset" z990 zarch +eb0000000057 xiy SIY_URD "exclusive or immediate with long offset" z990 zarch +e30000000057 xy RXY_RRRD "exclusive or with long offset" z990 zarch +e30000000073 icy RXY_RRRD "insert character with long offset" z990 zarch +eb0000000081 icmy RSY_RURD "insert characters with long offset" z990 zarch +ed0000000065 ldy RXY_FRRD "load (long) with long offset" z990 zarch +ed0000000064 ley RXY_FRRD "load (short) with long offset" z990 zarch +e30000000058 ly RXY_RRRD "load with long offset" z990 zarch +eb000000009a lamy RSY_AARD "load access multiple" z990 zarch +e30000000071 lay RXY_RRRD "load address with long offset" z990 zarch +e30000000076 lb RXY_RRRD "load byte with long offset" z990 zarch +e30000000077 lgb RXY_RRRD "load byte with long offset 64" z990 zarch +e30000000078 lhy RXY_RRRD "load halfword with long offset" z990 zarch +eb0000000098 lmy RSY_RRRD "load multiple with long offset" z990 zarch +e30000000013 lray RXY_RRRD "load real address with long offset" z990 zarch +eb0000000052 mviy SIY_URD "move immediate with long offset" z990 zarch +e30000000051 msy RXY_RRRD "multiply single with long offset" z990 zarch +eb0000000056 oiy SIY_URD "or immediate with long offset" z990 zarch +e30000000056 oy RXY_RRRD "or with long offset" z990 zarch +ed0000000067 stdy RXY_FRRD "load (long) with long offset" z990 zarch +ed0000000066 stey RXY_FRRD "load (short) with long offset" z990 zarch +e30000000050 sty RXY_RRRD "store with long offset" z990 zarch +eb000000009b stamy RSY_AARD "store access multiple with long offset" z990 zarch +e30000000072 stcy RXY_RRRD "store character with long offset" z990 zarch +eb000000002d stcmy RSY_RURD "store characters under mask with long offset" z990 zarch +e30000000070 sthy RXY_RRRD "store halfword with long offset" z990 zarch +eb0000000090 stmy RSY_RRRD "store multiple with long offset" z990 zarch +e3000000005b sy RXY_RRRD "subtract with long offset" z990 zarch +e3000000007b shy RXY_RRRD "subtract halfword with long offset" z990 zarch +e3000000005f sly RXY_RRRD "subtract logical with long offset" z990 zarch +eb0000000051 tmy SIY_URD "test under mask with long offset" z990 zarch +# 'old' instructions extended to long displacement +# these instructions are entered into the opcode table twice. +e30000000003 lrag RXY_RRRD "load real address with long offset 64" z990 zarch +e30000000004 lg RXY_RRRD " load 64" z990 zarch +e30000000008 ag RXY_RRRD "add with long offset 64" z990 zarch +e30000000009 sg RXY_RRRD "subtract with long offset 64" z990 zarch +e3000000000a alg RXY_RRRD "add logical with long offset 64" z990 zarch +e3000000000b slg RXY_RRRD "subtract logical with long offset 64" z990 zarch +e3000000000c msg RXY_RRRD "multiply single with long offset 64" z990 zarch +e3000000000d dsg RXY_RRRD "divide single 64" z990 zarch +e3000000000e cvbg RXY_RRRD "convert to binary with long offset 64" z990 zarch +e3000000000f lrvg RXY_RRRD "load reversed 64" z990 zarch +e30000000014 lgf RXY_RRRD "load 64<32" z990 zarch +e30000000015 lgh RXY_RRRD "load halfword 64" z990 zarch +e30000000016 llgf RXY_RRRD "load logical 64<32" z990 zarch +e30000000017 llgt RXY_RRRD "load logical thirty one bits" z990 zarch +e30000000018 agf RXY_RRRD "add with long offset 64<32" z990 zarch +e30000000019 sgf RXY_RRRD "subtract with long offset 64<32" z990 zarch +e3000000001a algf RXY_RRRD "add logical with long offset 64<32" z990 zarch +e3000000001b slgf RXY_RRRD "subtract logical with long offset 64<32" z990 zarch +e3000000001c msgf RXY_RRRD "multiply single with long offset 64<32" z990 zarch +e3000000001d dsgf RXY_RRRD "divide single 64<32" z990 zarch +e3000000001e lrv RXY_RRRD "load reversed 32" z990 zarch +e3000000001f lrvh RXY_RRRD "load reversed 16" z990 zarch +e30000000020 cg RXY_RRRD "compare with long offset 64" z990 zarch +e30000000021 clg RXY_RRRD "compare logical with long offset 64" z990 zarch +e30000000024 stg RXY_RRRD "store with long offset 64" z990 zarch +e3000000002e cvdg RXY_RRRD "convert to decimal with long offset 64" z990 zarch +e3000000002f strvg RXY_RRRD "store reversed 64" z990 zarch +e30000000030 cgf RXY_RRRD "compare with long offset 64<32" z990 zarch +e30000000031 clgf RXY_RRRD "compare logical with long offset 64<32" z990 zarch +e3000000003e strv RXY_RRRD "store reversed 32" z990 zarch +e3000000003f strvh RXY_RRRD "store reversed 64" z990 zarch +e30000000046 bctg RXY_RRRD "branch on count 64" z990 zarch +e30000000080 ng RXY_RRRD "and with long offset 64" z990 zarch +e30000000081 og RXY_RRRD "or with long offset 64" z990 zarch +e30000000082 xg RXY_RRRD "exclusive or with long offset 64" z990 zarch +e30000000086 mlg RXY_RRRD "multiply logical 64" z990 zarch +e30000000087 dlg RXY_RRRD "divide logical 64" z990 zarch +e30000000088 alcg RXY_RRRD "add logical with carry 64" z990 zarch +e30000000089 slbg RXY_RRRD "subtract logical with borrow 64" z990 zarch +e3000000008e stpq RXY_RRRD "store pair to quadword" z990 zarch +e3000000008f lpq RXY_RRRD "load pair from quadword" z990 zarch +e30000000090 llgc RXY_RRRD "load logical character" z990 zarch +e30000000091 llgh RXY_RRRD "load logical halfword" z990 zarch +e30000000096 ml RXY_RRRD "multiply logical 32" z990 zarch +e30000000097 dl RXY_RRRD "divide logical 32" z990 zarch +e30000000098 alc RXY_RRRD "add logical with carry 32" z990 zarch +e30000000099 slb RXY_RRRD "subtract logical with borrow 32" z990 zarch +eb0000000004 lmg RSY_RRRD "load multiple with long offset 64" z990 zarch +eb000000000a srag RSY_RRRD "shift right single 64" z990 zarch +eb000000000b slag RSY_RRRD "shift left single 64" z990 zarch +eb000000000c srlg RSY_RRRD "shift right single logical 64" z990 zarch +eb000000000d sllg RSY_RRRD "shift left single logical 64" z990 zarch +eb000000000f tracg RSY_RRRD "trace 64" z990 zarch +eb000000001c rllg RSY_RRRD "rotate left single logical 64" z990 zarch +eb000000001d rll RSY_RRRD "rotate left single logical 32" z990 zarch +eb0000000020 clmh RSY_RURD "compare logical characters under mask high with long offset" z990 zarch +eb0000000024 stmg RSY_RRRD "store multiple with long offset 64" z990 zarch +eb0000000025 stctg RSY_RRRD "store control 64" z990 zarch +eb0000000026 stmh RSY_RRRD "store multiple high" z990 zarch +eb000000002c stcmh RSY_RURD "store characters under mask high with long offset" z990 zarch +eb000000002f lctlg RSY_RRRD "load control 64" z990 zarch +eb0000000030 csg RSY_RRRD "compare and swap with long offset 64" z990 zarch +eb000000003e cdsg RSY_RRRD "compare double and swap with long offset 64" z990 zarch +eb0000000044 bxhg RSY_RRRD "branch on index high 64" z990 zarch +eb0000000045 bxleg RSY_RRRD "branch on index low or equal 64" z990 zarch +eb0000000080 icmh RSY_RURD "insert characters under mask high with long offset" z990 zarch +eb000000008e mvclu RSY_RRRD "move long unicode" z990 zarch +eb000000008f clclu RSY_RRRD "compare logical long unicode with long offset" z990 zarch +eb0000000096 lmh RSY_RRRD "load multiple high" z990 zarch +# new z990 instructions +b98a cspg RRE_RR "compare and swap and purge" z990 zarch +b98e idte RRF_R0RR "invalidate dat table entry" z990 zarch +b33e madr RRF_F0FF "multiply and add long hfp" z990 esa,zarch +ed000000003e mad RXF_FRRDF "multiply and add long hfp" z990 esa,zarch +b32e maer RRF_F0FF "multiply and add short hfp" z990 esa,zarch +ed000000002e mae RXF_FRRDF "multiply and add shoft hfp" z990 esa,zarch +b33f msdr RRF_F0FF "multiply and subtract long hfp" z990 esa,zarch +ed000000003f msd RXF_FRRDF "multiply and subtract long hfp" z990 esa,zarch +b32f mser RRF_F0FF "mutliply and subtract short hfp" z990 esa,zarch +ed000000002f mse RXF_FRRDF "multiply and subttract short hfp" z990 esa,zarch +b92e km RRE_RR "cipher message" z990 esa,zarch +b92f kmc RRE_RR "cipher message with chaining" z990 esa,zarch +b93e kimd RRE_RR "compute intermediate message digest" z990 esa,zarch +b93f klmd RRE_RR "compute last message digest" z990 esa,zarch +b91e kmac RRE_RR "compute message authentication code" z990 esa,zarch diff --git a/contrib/binutils/opcodes/sh-dis.c b/contrib/binutils/opcodes/sh-dis.c index 24d4b41..2512f96 100644 --- a/contrib/binutils/opcodes/sh-dis.c +++ b/contrib/binutils/opcodes/sh-dis.c @@ -1,20 +1,20 @@ /* Disassemble SH instructions. - Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001 + Copyright 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, 2003 Free Software Foundation, Inc. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <stdio.h> #include "sysdep.h" @@ -24,15 +24,19 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "sh-opc.h" #include "dis-asm.h" +#ifdef ARCH_all +#define INCLUDE_SHMEDIA +#endif + static void print_movxy - PARAMS ((sh_opcode_info *, int, int, fprintf_ftype, void *)); + PARAMS ((const sh_opcode_info *, int, int, fprintf_ftype, void *)); static void print_insn_ddt PARAMS ((int, struct disassemble_info *)); static void print_dsp_reg PARAMS ((int, fprintf_ftype, void *)); static void print_insn_ppi PARAMS ((int, struct disassemble_info *)); static void print_movxy (op, rn, rm, fprintf_fn, stream) - sh_opcode_info *op; + const sh_opcode_info *op; int rn, rm; fprintf_ftype fprintf_fn; void *stream; @@ -45,18 +49,28 @@ print_movxy (op, rn, rm, fprintf_fn, stream) switch (op->arg[n]) { case A_IND_N: + case AX_IND_N: + case AXY_IND_N: + case AY_IND_N: + case AYX_IND_N: fprintf_fn (stream, "@r%d", rn); break; case A_INC_N: + case AX_INC_N: + case AXY_INC_N: + case AY_INC_N: + case AYX_INC_N: fprintf_fn (stream, "@r%d+", rn); break; - case A_PMOD_N: + case AX_PMOD_N: + case AXY_PMOD_N: fprintf_fn (stream, "@r%d+r8", rn); break; - case A_PMODY_N: + case AY_PMOD_N: + case AYX_PMOD_N: fprintf_fn (stream, "@r%d+r9", rn); break; - case DSP_REG_M: + case DSP_REG_A_M: fprintf_fn (stream, "a%c", '0' + rm); break; case DSP_REG_X: @@ -65,6 +79,26 @@ print_movxy (op, rn, rm, fprintf_fn, stream) case DSP_REG_Y: fprintf_fn (stream, "y%c", '0' + rm); break; + case DSP_REG_AX: + fprintf_fn (stream, "%c%c", + (rm & 1) ? 'x' : 'a', + (rm & 2) ? '1' : '0'); + break; + case DSP_REG_XY: + fprintf_fn (stream, "%c%c", + (rm & 1) ? 'y' : 'x', + (rm & 2) ? '1' : '0'); + break; + case DSP_REG_AY: + fprintf_fn (stream, "%c%c", + (rm & 2) ? 'y' : 'a', + (rm & 1) ? '1' : '0'); + break; + case DSP_REG_YX: + fprintf_fn (stream, "%c%c", + (rm & 2) ? 'x' : 'y', + (rm & 1) ? '1' : '0'); + break; default: abort (); } @@ -98,11 +132,45 @@ print_insn_ddt (insn, info) /* Check if either the x or y part is invalid. */ if (((insn & 0xc) == 0 && (insn & 0x2a0)) || ((insn & 3) == 0 && (insn & 0x150))) - fprintf_fn (stream, ".word 0x%x", insn); + if (info->mach != bfd_mach_sh_dsp + && info->mach != bfd_mach_sh3_dsp) + { + static const sh_opcode_info *first_movx, *first_movy; + const sh_opcode_info *op; + int is_movy; + + if (! first_movx) + { + for (first_movx = sh_table; first_movx->nibbles[1] != MOVX_NOPY;) + first_movx++; + for (first_movy = first_movx; first_movy->nibbles[1] != MOVY_NOPX;) + first_movy++; + } + + is_movy = ((insn & 3) != 0); + + if (is_movy) + op = first_movy; + else + op = first_movx; + + while (op->nibbles[2] != (unsigned) ((insn >> 4) & 3) + || op->nibbles[3] != (unsigned) (insn & 0xf)) + op++; + + print_movxy (op, + (4 * ((insn & (is_movy ? 0x200 : 0x100)) == 0) + + 2 * is_movy + + 1 * ((insn & (is_movy ? 0x100 : 0x200)) != 0)), + (insn >> 6) & 3, + fprintf_fn, stream); + } + else + fprintf_fn (stream, ".word 0x%x", insn); else { - static sh_opcode_info *first_movx, *first_movy; - sh_opcode_info *opx, *opy; + static const sh_opcode_info *first_movx, *first_movy; + const sh_opcode_info *opx, *opy; unsigned int insn_x, insn_y; if (! first_movx) @@ -187,8 +255,9 @@ print_insn_ppi (field_b, info) fprintf_ftype fprintf_fn = info->fprintf_func; void *stream = info->stream; unsigned int nib1, nib2, nib3; + unsigned int altnib1, nib4; char *dc = NULL; - sh_opcode_info *op; + const sh_opcode_info *op; if ((field_b & 0xe800) == 0) { @@ -213,6 +282,16 @@ print_insn_ppi (field_b, info) sy_tab[(field_b >> 4) & 3], du_tab[(field_b >> 0) & 3]); } + else if ((field_b & 0xf0) == 0x10 + && info->mach != bfd_mach_sh_dsp + && info->mach != bfd_mach_sh3_dsp) + { + fprintf_fn (stream, "pclr %s \t", du_tab[(field_b >> 0) & 3]); + } + else if ((field_b & 0xf3) != 0) + { + fprintf_fn (stream, ".word 0x%x\t", field_b); + } fprintf_fn (stream, "pmuls%c%s,%s,%s", field_b & 0x2000 ? ' ' : '\t', se_tab[(field_b >> 10) & 3], @@ -224,6 +303,7 @@ print_insn_ppi (field_b, info) nib1 = PPIC; nib2 = field_b >> 12 & 0xf; nib3 = field_b >> 8 & 0xf; + nib4 = field_b >> 4 & 0xf; switch (nib3 & 0x3) { case 0: @@ -242,14 +322,41 @@ print_insn_ppi (field_b, info) nib3 -= 2; break; } + if (nib1 == PPI3) + altnib1 = PPI3NC; + else + altnib1 = nib1; for (op = sh_table; op->name; op++) { - if (op->nibbles[1] == nib1 + if ((op->nibbles[1] == nib1 || op->nibbles[1] == altnib1) && op->nibbles[2] == nib2 && op->nibbles[3] == nib3) { int n; + switch (op->nibbles[4]) + { + case HEX_0: + break; + case HEX_XX00: + if ((nib4 & 3) != 0) + continue; + break; + case HEX_1: + if ((nib4 & 3) != 1) + continue; + break; + case HEX_00YY: + if ((nib4 & 0xc) != 0) + continue; + break; + case HEX_4: + if ((nib4 & 0xc) != 4) + continue; + break; + default: + abort (); + } fprintf_fn (stream, "%s%s\t", dc, op->name); for (n = 0; n < 3 && op->arg[n] != A_END; n++) { @@ -290,11 +397,11 @@ print_insn_sh (memaddr, info) { fprintf_ftype fprintf_fn = info->fprintf_func; void *stream = info->stream; - unsigned char insn[2]; + unsigned char insn[4]; unsigned char nibs[4]; int status; bfd_vma relmask = ~(bfd_vma) 0; - sh_opcode_info *op; + const sh_opcode_info *op; int target_arch; switch (info->mach) @@ -311,6 +418,9 @@ print_insn_sh (memaddr, info) case bfd_mach_sh2: target_arch = arch_sh2; break; + case bfd_mach_sh2e: + target_arch = arch_sh2e; + break; case bfd_mach_sh_dsp: target_arch = arch_sh_dsp; break; @@ -324,8 +434,16 @@ print_insn_sh (memaddr, info) target_arch = arch_sh3e; break; case bfd_mach_sh4: + case bfd_mach_sh4_nofpu: target_arch = arch_sh4; break; + case bfd_mach_sh4a: + case bfd_mach_sh4a_nofpu: + target_arch = arch_sh4a; + break; + case bfd_mach_sh4al_dsp: + target_arch = arch_sh4al_dsp; + break; case bfd_mach_sh5: #ifdef INCLUDE_SHMEDIA status = print_insn_sh64 (memaddr, info); @@ -459,12 +577,21 @@ print_insn_sh (memaddr, info) case IMM1_8BY4: imm = ((nibs[2] << 4) | nibs[3]) << 2; goto ok; + case REG_N_D: + if ((nibs[n] & 1) != 0) + goto fail; + /* fall through */ case REG_N: rn = nibs[n]; break; case REG_M: rm = nibs[n]; break; + case REG_N_B01: + if ((nibs[n] & 0x3) != 1 /* binary 01 */) + goto fail; + rn = (nibs[n] & 0xc) >> 2; + break; case REG_NM: rn = (nibs[n] & 0xc) >> 2; rm = (nibs[n] & 0x3); @@ -507,18 +634,21 @@ print_insn_sh (memaddr, info) fprintf_fn (stream, "r%d", rn); break; case A_INC_N: + case AS_INC_N: fprintf_fn (stream, "@r%d+", rn); break; case A_DEC_N: + case AS_DEC_N: fprintf_fn (stream, "@-r%d", rn); break; case A_IND_N: + case AS_IND_N: fprintf_fn (stream, "@r%d", rn); break; case A_DISP_REG_N: fprintf_fn (stream, "@(%d,r%d)", imm, rn); break; - case A_PMOD_N: + case AS_PMOD_N: fprintf_fn (stream, "@r%d+r8", rn); break; case A_REG_M: diff --git a/contrib/binutils/opcodes/sh-opc.h b/contrib/binutils/opcodes/sh-opc.h index abdc464..0ef1fab 100644 --- a/contrib/binutils/opcodes/sh-opc.h +++ b/contrib/binutils/opcodes/sh-opc.h @@ -1,177 +1,222 @@ /* Definitions for SH opcodes. - Copyright 1993, 1994, 1995, 1997, 1999, 2000 + Copyright 1993, 1994, 1995, 1997, 1999, 2000, 2003 Free Software Foundation, Inc. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. - -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -typedef enum { - HEX_0, - HEX_1, - HEX_2, - HEX_3, - HEX_4, - HEX_5, - HEX_6, - HEX_7, - HEX_8, - HEX_9, - HEX_A, - HEX_B, - HEX_C, - HEX_D, - HEX_E, - HEX_F, - REG_N, - REG_M, - SDT_REG_N, - REG_NM, - REG_B, - BRANCH_12, - BRANCH_8, - IMM0_4, - IMM0_4BY2, - IMM0_4BY4, - IMM1_4, - IMM1_4BY2, - IMM1_4BY4, - PCRELIMM_8BY2, - PCRELIMM_8BY4, - IMM0_8, - IMM0_8BY2, - IMM0_8BY4, - IMM1_8, - IMM1_8BY2, - IMM1_8BY4, - PPI, - NOPX, - NOPY, - MOVX, - MOVY, - PSH, - PMUL, - PPI3, - PDC, - PPIC, - REPEAT -} sh_nibble_type; - -typedef enum { - A_END, - A_BDISP12, - A_BDISP8, - A_DEC_M, - A_DEC_N, - A_DISP_GBR, - A_PC, - A_DISP_PC, - A_DISP_PC_ABS, - A_DISP_REG_M, - A_DISP_REG_N, - A_GBR, - A_IMM, - A_INC_M, - A_INC_N, - A_IND_M, - A_IND_N, - A_PMOD_N, - A_PMODY_N, - A_IND_R0_REG_M, - A_IND_R0_REG_N, - A_MACH, - A_MACL, - A_PR, - A_R0, - A_R0_GBR, - A_REG_M, - A_REG_N, - A_REG_B, - A_SR, - A_VBR, - A_MOD, - A_RE, - A_RS, - A_DSR, - DSP_REG_M, - DSP_REG_N, - DSP_REG_X, - DSP_REG_Y, - DSP_REG_E, - DSP_REG_F, - DSP_REG_G, - A_A0, - A_X0, - A_X1, - A_Y0, - A_Y1, - A_SSR, - A_SPC, - A_SGR, - A_DBR, - F_REG_N, - F_REG_M, - D_REG_N, - D_REG_M, - X_REG_N, /* Only used for argument parsing */ - X_REG_M, /* Only used for argument parsing */ - DX_REG_N, - DX_REG_M, - V_REG_N, - V_REG_M, - XMTRX_M4, - F_FR0, - FPUL_N, - FPUL_M, - FPSCR_N, - FPSCR_M -} sh_arg_type; - -typedef enum { - A_A1_NUM = 5, - A_A0_NUM = 7, - A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM, - A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM -} sh_dsp_reg_nums; + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +typedef enum + { + HEX_0, + HEX_1, + HEX_2, + HEX_3, + HEX_4, + HEX_5, + HEX_6, + HEX_7, + HEX_8, + HEX_9, + HEX_A, + HEX_B, + HEX_C, + HEX_D, + HEX_E, + HEX_F, + HEX_XX00, + HEX_00YY, + REG_N, + REG_N_D, /* nnn0 */ + REG_N_B01, /* nn01 */ + REG_M, + SDT_REG_N, + REG_NM, + REG_B, + BRANCH_12, + BRANCH_8, + IMM0_4, + IMM0_4BY2, + IMM0_4BY4, + IMM1_4, + IMM1_4BY2, + IMM1_4BY4, + PCRELIMM_8BY2, + PCRELIMM_8BY4, + IMM0_8, + IMM0_8BY2, + IMM0_8BY4, + IMM1_8, + IMM1_8BY2, + IMM1_8BY4, + PPI, + NOPX, + NOPY, + MOVX, + MOVY, + MOVX_NOPY, + MOVY_NOPX, + PSH, + PMUL, + PPI3, + PPI3NC, + PDC, + PPIC, + REPEAT + } +sh_nibble_type; + +typedef enum + { + A_END, + A_BDISP12, + A_BDISP8, + A_DEC_M, + A_DEC_N, + A_DISP_GBR, + A_PC, + A_DISP_PC, + A_DISP_PC_ABS, + A_DISP_REG_M, + A_DISP_REG_N, + A_GBR, + A_IMM, + A_INC_M, + A_INC_N, + A_IND_M, + A_IND_N, + A_IND_R0_REG_M, + A_IND_R0_REG_N, + A_MACH, + A_MACL, + A_PR, + A_R0, + A_R0_GBR, + A_REG_M, + A_REG_N, + A_REG_B, + A_SR, + A_VBR, + A_MOD, + A_RE, + A_RS, + A_DSR, + DSP_REG_M, + DSP_REG_N, + DSP_REG_X, + DSP_REG_Y, + DSP_REG_E, + DSP_REG_F, + DSP_REG_G, + DSP_REG_A_M, + DSP_REG_AX, + DSP_REG_XY, + DSP_REG_AY, + DSP_REG_YX, + AX_INC_N, + AY_INC_N, + AXY_INC_N, + AYX_INC_N, + AX_IND_N, + AY_IND_N, + AXY_IND_N, + AYX_IND_N, + AX_PMOD_N, + AXY_PMOD_N, + AY_PMOD_N, + AYX_PMOD_N, + AS_DEC_N, + AS_INC_N, + AS_IND_N, + AS_PMOD_N, + A_A0, + A_X0, + A_X1, + A_Y0, + A_Y1, + A_SSR, + A_SPC, + A_SGR, + A_DBR, + F_REG_N, + F_REG_M, + D_REG_N, + D_REG_M, + X_REG_N, /* Only used for argument parsing. */ + X_REG_M, /* Only used for argument parsing. */ + DX_REG_N, + DX_REG_M, + V_REG_N, + V_REG_M, + XMTRX_M4, + F_FR0, + FPUL_N, + FPUL_M, + FPSCR_N, + FPSCR_M + } +sh_arg_type; + +typedef enum + { + A_A1_NUM = 5, + A_A0_NUM = 7, + A_X0_NUM, A_X1_NUM, A_Y0_NUM, A_Y1_NUM, + A_M0_NUM, A_A1G_NUM, A_M1_NUM, A_A0G_NUM + } +sh_dsp_reg_nums; #define arch_sh1 0x0001 #define arch_sh2 0x0002 #define arch_sh3 0x0004 #define arch_sh3e 0x0008 #define arch_sh4 0x0010 +#define arch_sh2e 0x0020 +#define arch_sh4a 0x0040 #define arch_sh_dsp 0x0100 #define arch_sh3_dsp 0x0200 - -#define arch_sh1_up (arch_sh1 | arch_sh2_up) -#define arch_sh2_up (arch_sh2 | arch_sh3_up | arch_sh_dsp) -#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp) +#define arch_sh4al_dsp 0x0400 +#define arch_sh4_nofpu 0x1000 +#define arch_sh4a_nofpu 0x2000 + +#define arch_sh1_up (arch_sh1 | arch_sh2_up) +#define arch_sh2_up (arch_sh2 | arch_sh2e_up | arch_sh3_up | arch_sh_dsp) +#define arch_sh2e_up (arch_sh2e | arch_sh3e_up) +#define arch_sh3_up (arch_sh3 | arch_sh3e_up | arch_sh3_dsp_up \ + | arch_sh4_nofp_up) #define arch_sh3e_up (arch_sh3e | arch_sh4_up) -#define arch_sh4_up arch_sh4 +#define arch_sh4_up (arch_sh4 | arch_sh4a_up) +#define arch_sh4a_up (arch_sh4a) #define arch_sh_dsp_up (arch_sh_dsp | arch_sh3_dsp_up) -#define arch_sh3_dsp_up arch_sh3_dsp +#define arch_sh3_dsp_up (arch_sh3_dsp | arch_sh4al_dsp_up) +#define arch_sh4al_dsp_up (arch_sh4al_dsp) + +#define arch_sh4_nofp_up (arch_sh4_nofpu | arch_sh4_up | arch_sh4a_nofp_up) +#define arch_sh4a_nofp_up (arch_sh4a_nofpu | arch_sh4a_up | arch_sh4al_dsp_up) -typedef struct { +typedef struct +{ char *name; sh_arg_type arg[4]; - sh_nibble_type nibbles[4]; + sh_nibble_type nibbles[5]; int arch; } sh_opcode_info; #ifdef DEFINE_TABLE -sh_opcode_info sh_table[] = { - +const sh_opcode_info sh_table[] = + { /* 0111nnnni8*1.... add #<imm>,<REG_N> */{"add",{A_IMM,A_REG_N},{HEX_7,REG_N,IMM0_8}, arch_sh1_up}, /* 0011nnnnmmmm1100 add <REG_M>,<REG_N> */{"add",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_C}, arch_sh1_up}, @@ -202,6 +247,8 @@ sh_opcode_info sh_table[] = { /* 10001111i8p1.... bf/s <bdisp8> */{"bf/s",{A_BDISP8},{HEX_8,HEX_F,BRANCH_8}, arch_sh2_up}, +/* 0000000010001000 clrdmxy */{"clrdmxy",{0},{HEX_0,HEX_0,HEX_8,HEX_8}, arch_sh4al_dsp_up}, + /* 0000000000101000 clrmac */{"clrmac",{0},{HEX_0,HEX_0,HEX_2,HEX_8}, arch_sh1_up}, /* 0000000001001000 clrs */{"clrs",{0},{HEX_0,HEX_0,HEX_4,HEX_8}, arch_sh1_up}, @@ -240,6 +287,8 @@ sh_opcode_info sh_table[] = { /* 0110nnnnmmmm1101 extu.w <REG_M>,<REG_N>*/{"extu.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_D}, arch_sh1_up}, +/* 0000nnnn11100011 icbi @<REG_N> */{"icbi",{A_IND_N},{HEX_0,REG_N,HEX_E,HEX_3}, arch_sh4a_nofp_up}, + /* 0100nnnn00101011 jmp @<REG_N> */{"jmp",{A_IND_N},{HEX_4,REG_N,HEX_2,HEX_B}, arch_sh1_up}, /* 0100nnnn00001011 jsr @<REG_N> */{"jsr",{A_IND_N},{HEX_4,REG_N,HEX_0,HEX_B}, arch_sh1_up}, @@ -260,7 +309,7 @@ sh_opcode_info sh_table[] = { /* 0100nnnn01001110 ldc <REG_N>,SPC */{"ldc",{A_REG_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_E}, arch_sh3_up}, -/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_up}, +/* 0100nnnn11111010 ldc <REG_N>,DBR */{"ldc",{A_REG_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up}, /* 0100nnnn1xxx1110 ldc <REG_N>,Rn_BANK */{"ldc",{A_REG_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_E}, arch_sh3_up}, @@ -280,10 +329,13 @@ sh_opcode_info sh_table[] = { /* 0100nnnn01000111 ldc.l @<REG_N>+,SPC */{"ldc.l",{A_INC_N,A_SPC},{HEX_4,REG_N,HEX_4,HEX_7}, arch_sh3_up}, -/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_up}, +/* 0100nnnn11110110 ldc.l @<REG_N>+,DBR */{"ldc.l",{A_INC_N,A_DBR},{HEX_4,REG_N,HEX_F,HEX_6}, arch_sh4_nofp_up}, /* 0100nnnn1xxx0111 ldc.l <REG_N>,Rn_BANK */{"ldc.l",{A_INC_N,A_REG_B},{HEX_4,REG_N,REG_B,HEX_7}, arch_sh3_up}, +/* 0100mmmm00110100 ldrc <REG_M> */{"ldrc",{A_REG_M},{HEX_4,REG_M,HEX_3,HEX_4}, arch_sh4al_dsp_up}, +/* 10001010i8*1.... ldrc #<imm> */{"ldrc",{A_IMM},{HEX_8,HEX_A,IMM0_8}, arch_sh4al_dsp_up}, + /* 10001110i8p2.... ldre @(<disp>,PC) */{"ldre",{A_DISP_PC},{HEX_8,HEX_E,PCRELIMM_8BY2}, arch_sh_dsp_up}, /* 10001100i8p2.... ldrs @(<disp>,PC) */{"ldrs",{A_DISP_PC},{HEX_8,HEX_C,PCRELIMM_8BY2}, arch_sh_dsp_up}, @@ -306,9 +358,9 @@ sh_opcode_info sh_table[] = { /* 0100nnnn10111010 lds <REG_N>,Y1 */{"lds",{A_REG_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, -/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh3e_up}, - -/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh3e_up}, +/* 0100nnnn01011010 lds <REG_N>,FPUL */{"lds",{A_REG_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_A}, arch_sh2e_up}, + +/* 0100nnnn01101010 lds <REG_M>,FPSCR */{"lds",{A_REG_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_A}, arch_sh2e_up}, /* 0100nnnn00000110 lds.l @<REG_N>+,MACH*/{"lds.l",{A_INC_N,A_MACH},{HEX_4,REG_N,HEX_0,HEX_6}, arch_sh1_up}, @@ -328,9 +380,9 @@ sh_opcode_info sh_table[] = { /* 0100nnnn10110110 lds.l @<REG_N>+,Y1 */{"lds.l",{A_INC_N,A_Y1},{HEX_4,REG_N,HEX_B,HEX_6}, arch_sh_dsp_up}, -/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh3e_up}, - -/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh3e_up}, +/* 0100nnnn01010110 lds.l @<REG_M>+,FPUL*/{"lds.l",{A_INC_M,FPUL_N},{HEX_4,REG_M,HEX_5,HEX_6}, arch_sh2e_up}, + +/* 0100nnnn01100110 lds.l @<REG_M>+,FPSCR*/{"lds.l",{A_INC_M,FPSCR_N},{HEX_4,REG_M,HEX_6,HEX_6}, arch_sh2e_up}, /* 0000000000111000 ldtlb */{"ldtlb",{0},{HEX_0,HEX_0,HEX_3,HEX_8}, arch_sh3_up}, @@ -405,11 +457,16 @@ sh_opcode_info sh_table[] = { /* 11000001i8*2.... mov.w R0,@(<disp>,GBR)*/{"mov.w",{A_R0,A_DISP_GBR},{HEX_C,HEX_1,IMM1_8BY2}, arch_sh1_up}, /* 11000111i8p4.... mova @(<disp>,PC),R0*/{"mova",{A_DISP_PC,A_R0},{HEX_C,HEX_7,PCRELIMM_8BY4}, arch_sh1_up}, -/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_up}, +/* 0000nnnn11000011 movca.l R0,@<REG_N> */{"movca.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_C,HEX_3}, arch_sh4_nofp_up}, +/* 0000nnnn01110011 movco.l r0,@<REG_N> */{"movco.l",{A_R0,A_IND_N},{HEX_0,REG_N,HEX_7,HEX_3}, arch_sh4a_nofp_up}, +/* 0000mmmm01100011 movli.l @<REG_M>,r0 */{"movli.l",{A_IND_M,A_R0},{HEX_0,REG_M,HEX_6,HEX_3}, arch_sh4a_nofp_up}, /* 0000nnnn00101001 movt <REG_N> */{"movt",{A_REG_N},{HEX_0,REG_N,HEX_2,HEX_9}, arch_sh1_up}, +/* 0100mmmm10101001 movua.l @<REG_M>,r0 */{"movua.l",{A_IND_M,A_R0},{HEX_4,REG_M,HEX_A,HEX_9}, arch_sh4a_nofp_up}, +/* 0100mmmm11101001 movua.l @<REG_M>+,r0 */{"movua.l",{A_INC_M,A_R0},{HEX_4,REG_M,HEX_E,HEX_9}, arch_sh4a_nofp_up}, + /* 0010nnnnmmmm1111 muls.w <REG_M>,<REG_N>*/{"muls.w",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up}, /* 0010nnnnmmmm1111 muls <REG_M>,<REG_N>*/{"muls",{ A_REG_M,A_REG_N},{HEX_2,REG_N,REG_M,HEX_F}, arch_sh1_up}, @@ -425,11 +482,11 @@ sh_opcode_info sh_table[] = { /* 0000000000001001 nop */{"nop",{0},{HEX_0,HEX_0,HEX_0,HEX_9}, arch_sh1_up}, /* 0110nnnnmmmm0111 not <REG_M>,<REG_N> */{"not",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_7}, arch_sh1_up}, -/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_up}, +/* 0000nnnn10010011 ocbi @<REG_N> */{"ocbi",{A_IND_N},{HEX_0,REG_N,HEX_9,HEX_3}, arch_sh4_nofp_up}, -/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_up}, +/* 0000nnnn10100011 ocbp @<REG_N> */{"ocbp",{A_IND_N},{HEX_0,REG_N,HEX_A,HEX_3}, arch_sh4_nofp_up}, -/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_up}, +/* 0000nnnn10110011 ocbwb @<REG_N> */{"ocbwb",{A_IND_N},{HEX_0,REG_N,HEX_B,HEX_3}, arch_sh4_nofp_up}, /* 11001011i8*1.... or #<imm>,R0 */{"or",{A_IMM,A_R0},{HEX_C,HEX_B,IMM0_8}, arch_sh1_up}, @@ -438,7 +495,9 @@ sh_opcode_info sh_table[] = { /* 11001111i8*1.... or.b #<imm>,@(R0,GBR)*/{"or.b",{A_IMM,A_R0_GBR},{HEX_C,HEX_F,IMM0_8}, arch_sh1_up}, -/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_up}, +/* 0000nnnn10000011 pref @<REG_N> */{"pref",{A_IND_N},{HEX_0,REG_N,HEX_8,HEX_3}, arch_sh4_nofp_up}, + +/* 0000nnnn11010011 prefi @<REG_N> */{"prefi",{A_IND_N},{HEX_0,REG_N,HEX_D,HEX_3}, arch_sh4a_nofp_up}, /* 0100nnnn00100100 rotcl <REG_N> */{"rotcl",{A_REG_N},{HEX_4,REG_N,HEX_2,HEX_4}, arch_sh1_up}, @@ -452,6 +511,9 @@ sh_opcode_info sh_table[] = { /* 0000000000001011 rts */{"rts",{0},{HEX_0,HEX_0,HEX_0,HEX_B}, arch_sh1_up}, +/* 0000000010011000 setdmx */{"setdmx",{0},{HEX_0,HEX_0,HEX_9,HEX_8}, arch_sh4al_dsp_up}, +/* 0000000011001000 setdmy */{"setdmy",{0},{HEX_0,HEX_0,HEX_C,HEX_8}, arch_sh4al_dsp_up}, + /* 0000000001011000 sets */{"sets",{0},{HEX_0,HEX_0,HEX_5,HEX_8}, arch_sh1_up}, /* 0000000000011000 sett */{"sett",{0},{HEX_0,HEX_0,HEX_1,HEX_8}, arch_sh1_up}, @@ -505,9 +567,9 @@ sh_opcode_info sh_table[] = { /* 0000nnnn01000010 stc SPC,<REG_N> */{"stc",{A_SPC,A_REG_N},{HEX_0,REG_N,HEX_4,HEX_2}, arch_sh3_up}, -/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_up}, +/* 0000nnnn00111010 stc SGR,<REG_N> */{"stc",{A_SGR,A_REG_N},{HEX_0,REG_N,HEX_3,HEX_A}, arch_sh4_nofp_up}, -/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_up}, +/* 0000nnnn11111010 stc DBR,<REG_N> */{"stc",{A_DBR,A_REG_N},{HEX_0,REG_N,HEX_F,HEX_A}, arch_sh4_nofp_up}, /* 0000nnnn1xxx0010 stc Rn_BANK,<REG_N> */{"stc",{A_REG_B,A_REG_N},{HEX_0,REG_N,REG_B,HEX_2}, arch_sh3_up}, @@ -527,9 +589,9 @@ sh_opcode_info sh_table[] = { /* 0100nnnn00010011 stc.l GBR,@-<REG_N> */{"stc.l",{A_GBR,A_DEC_N},{HEX_4,REG_N,HEX_1,HEX_3}, arch_sh1_up}, -/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_up}, +/* 0100nnnn00110010 stc.l SGR,@-<REG_N> */{"stc.l",{A_SGR,A_DEC_N},{HEX_4,REG_N,HEX_3,HEX_2}, arch_sh4_nofp_up}, -/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_up}, +/* 0100nnnn11110010 stc.l DBR,@-<REG_N> */{"stc.l",{A_DBR,A_DEC_N},{HEX_4,REG_N,HEX_F,HEX_2}, arch_sh4_nofp_up}, /* 0100nnnn1xxx0011 stc.l Rn_BANK,@-<REG_N> */{"stc.l",{A_REG_B,A_DEC_N},{HEX_4,REG_N,REG_B,HEX_3}, arch_sh3_up}, @@ -551,9 +613,9 @@ sh_opcode_info sh_table[] = { /* 0000nnnn10111010 sts Y1,<REG_N> */{"sts",{A_Y1,A_REG_N},{HEX_0,REG_N,HEX_B,HEX_A}, arch_sh_dsp_up}, -/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh3e_up}, - -/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh3e_up}, +/* 0000nnnn01011010 sts FPUL,<REG_N> */{"sts",{FPUL_M,A_REG_N},{HEX_0,REG_N,HEX_5,HEX_A}, arch_sh2e_up}, + +/* 0000nnnn01101010 sts FPSCR,<REG_N> */{"sts",{FPSCR_M,A_REG_N},{HEX_0,REG_N,HEX_6,HEX_A}, arch_sh2e_up}, /* 0100nnnn00000010 sts.l MACH,@-<REG_N>*/{"sts.l",{A_MACH,A_DEC_N},{HEX_4,REG_N,HEX_0,HEX_2}, arch_sh1_up}, @@ -573,9 +635,9 @@ sh_opcode_info sh_table[] = { /* 0100nnnn10110110 sts.l Y1,@-<REG_N> */{"sts.l",{A_Y1,A_DEC_N},{HEX_4,REG_N,HEX_B,HEX_2}, arch_sh_dsp_up}, -/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh3e_up}, - -/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh3e_up}, +/* 0100nnnn01010010 sts.l FPUL,@-<REG_N>*/{"sts.l",{FPUL_M,A_DEC_N},{HEX_4,REG_N,HEX_5,HEX_2}, arch_sh2e_up}, + +/* 0100nnnn01100010 sts.l FPSCR,@-<REG_N>*/{"sts.l",{FPSCR_M,A_DEC_N},{HEX_4,REG_N,HEX_6,HEX_2}, arch_sh2e_up}, /* 0011nnnnmmmm1000 sub <REG_M>,<REG_N> */{"sub",{ A_REG_M,A_REG_N},{HEX_3,REG_N,REG_M,HEX_8}, arch_sh1_up}, @@ -587,6 +649,8 @@ sh_opcode_info sh_table[] = { /* 0110nnnnmmmm1001 swap.w <REG_M>,<REG_N>*/{"swap.w",{ A_REG_M,A_REG_N},{HEX_6,REG_N,REG_M,HEX_9}, arch_sh1_up}, +/* 0000000010101011 synco */{"synco",{0},{HEX_0,HEX_0,HEX_A,HEX_B}, arch_sh4a_nofp_up}, + /* 0100nnnn00011011 tas.b @<REG_N> */{"tas.b",{A_IND_N},{HEX_4,REG_N,HEX_1,HEX_B}, arch_sh1_up}, /* 11000011i8*1.... trapa #<imm> */{"trapa",{A_IMM},{HEX_C,HEX_3,IMM0_8}, arch_sh1_up}, @@ -625,7 +689,7 @@ sh_opcode_info sh_table[] = { /* 111101nnmmmm0010 movs.w @<REG_N>+,<DSP_REG_M> */ {"movs.w",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_8}, arch_sh_dsp_up}, -/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}, +/* 111101nnmmmm0011 movs.w @<REG_N>+r8,<DSP_REG_M> */ {"movs.w",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_C}, arch_sh_dsp_up}, /* 111101nnmmmm0100 movs.w <DSP_REG_M>,@-<REG_N> */ {"movs.w",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_1}, arch_sh_dsp_up}, @@ -633,7 +697,7 @@ sh_opcode_info sh_table[] = { /* 111101nnmmmm0110 movs.w <DSP_REG_M>,@<REG_N>+ */ {"movs.w",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_9}, arch_sh_dsp_up}, -/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}, +/* 111101nnmmmm0111 movs.w <DSP_REG_M>,@<REG_N>+r8 */ {"movs.w",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_D}, arch_sh_dsp_up}, /* 111101nnmmmm1000 movs.l @-<REG_N>,<DSP_REG_M> */ {"movs.l",{A_DEC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_2}, arch_sh_dsp_up}, @@ -641,7 +705,7 @@ sh_opcode_info sh_table[] = { /* 111101nnmmmm1010 movs.l @<REG_N>+,<DSP_REG_M> */ {"movs.l",{A_INC_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_A}, arch_sh_dsp_up}, -/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{A_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}, +/* 111101nnmmmm1011 movs.l @<REG_N>+r8,<DSP_REG_M> */ {"movs.l",{AS_PMOD_N,DSP_REG_M},{HEX_F,SDT_REG_N,REG_M,HEX_E}, arch_sh_dsp_up}, /* 111101nnmmmm1100 movs.l <DSP_REG_M>,@-<REG_N> */ {"movs.l",{DSP_REG_M,A_DEC_N},{HEX_F,SDT_REG_N,REG_M,HEX_3}, arch_sh_dsp_up}, @@ -649,22 +713,51 @@ sh_opcode_info sh_table[] = { /* 111101nnmmmm1110 movs.l <DSP_REG_M>,@<REG_N>+ */ {"movs.l",{DSP_REG_M,A_INC_N},{HEX_F,SDT_REG_N,REG_M,HEX_B}, arch_sh_dsp_up}, -/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,A_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}, +/* 111101nnmmmm1111 movs.l <DSP_REG_M>,@<REG_N>+r8 */ {"movs.l",{DSP_REG_M,AS_PMOD_N},{HEX_F,SDT_REG_N,REG_M,HEX_F}, arch_sh_dsp_up}, /* 0*0*0*00** nopx */ {"nopx",{0},{PPI,NOPX}, arch_sh_dsp_up}, /* *0*0*0**00 nopy */ {"nopy",{0},{PPI,NOPY}, arch_sh_dsp_up}, -/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{A_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}, -/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{A_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}, -/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{A_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}, -/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_M,A_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}, -/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_M,A_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}, -/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_M,A_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}, -/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{A_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}, -/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{A_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}, -/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{A_PMODY_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}, -/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_M,A_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}, -/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_M,A_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}, -/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_M,A_PMODY_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}, +/* n*m*0*01** movx.w @<REG_N>,<DSP_REG_X> */ {"movx.w",{AX_IND_N,DSP_REG_X},{PPI,MOVX,HEX_1}, arch_sh_dsp_up}, +/* n*m*0*10** movx.w @<REG_N>+,<DSP_REG_X> */ {"movx.w",{AX_INC_N,DSP_REG_X},{PPI,MOVX,HEX_2}, arch_sh_dsp_up}, +/* n*m*0*11** movx.w @<REG_N>+r8,<DSP_REG_X> */ {"movx.w",{AX_PMOD_N,DSP_REG_X},{PPI,MOVX,HEX_3}, arch_sh_dsp_up}, +/* n*m*1*01** movx.w <DSP_REG_M>,@<REG_N> */ {"movx.w",{DSP_REG_A_M,AX_IND_N},{PPI,MOVX,HEX_9}, arch_sh_dsp_up}, +/* n*m*1*10** movx.w <DSP_REG_M>,@<REG_N>+ */ {"movx.w",{DSP_REG_A_M,AX_INC_N},{PPI,MOVX,HEX_A}, arch_sh_dsp_up}, +/* n*m*1*11** movx.w <DSP_REG_M>,@<REG_N>+r8 */ {"movx.w",{DSP_REG_A_M,AX_PMOD_N},{PPI,MOVX,HEX_B}, arch_sh_dsp_up}, + +/* nnmm000100 movx.w @<REG_Axy>,<DSP_REG_XY> */ {"movx.w",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_4}, arch_sh4al_dsp_up}, +/* nnmm001000 movx.w @<REG_Axy>+,<DSP_REG_XY> */{"movx.w",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_8}, arch_sh4al_dsp_up}, +/* nnmm001100 movx.w @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.w",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_0,HEX_C}, arch_sh4al_dsp_up}, +/* nnmm100100 movx.w <DSP_REG_AX>,@<REG_Axy> */ {"movx.w",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_2,HEX_4}, arch_sh4al_dsp_up}, +/* nnmm101000 movx.w <DSP_REG_AX>,@<REG_Axy>+ */{"movx.w",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_2,HEX_8}, arch_sh4al_dsp_up}, +/* nnmm101100 movx.w <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.w",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_2,HEX_C}, arch_sh4al_dsp_up}, + +/* nnmm010100 movx.l @<REG_Axy>,<DSP_REG_XY> */ {"movx.l",{AXY_IND_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_4}, arch_sh4al_dsp_up}, +/* nnmm011000 movx.l @<REG_Axy>+,<DSP_REG_XY> */{"movx.l",{AXY_INC_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_8}, arch_sh4al_dsp_up}, +/* nnmm011100 movx.l @<REG_Axy>+r8,<DSP_REG_XY> */{"movx.l",{AXY_PMOD_N,DSP_REG_XY},{PPI,MOVX_NOPY,HEX_1,HEX_C}, arch_sh4al_dsp_up}, +/* nnmm110100 movx.l <DSP_REG_AX>,@<REG_Axy> */ {"movx.l",{DSP_REG_AX,AXY_IND_N},{PPI,MOVX_NOPY,HEX_3,HEX_4}, arch_sh4al_dsp_up}, +/* nnmm111000 movx.l <DSP_REG_AX>,@<REG_Axy>+ */{"movx.l",{DSP_REG_AX,AXY_INC_N},{PPI,MOVX_NOPY,HEX_3,HEX_8}, arch_sh4al_dsp_up}, +/* nnmm111100 movx.l <DSP_REG_AX>,@<REG_Axy>+r8 */{"movx.l",{DSP_REG_AX,AXY_PMOD_N},{PPI,MOVX_NOPY,HEX_3,HEX_C}, arch_sh4al_dsp_up}, + +/* *n*m*0**01 movy.w @<REG_N>,<DSP_REG_Y> */ {"movy.w",{AY_IND_N,DSP_REG_Y},{PPI,MOVY,HEX_1}, arch_sh_dsp_up}, +/* *n*m*0**10 movy.w @<REG_N>+,<DSP_REG_Y> */ {"movy.w",{AY_INC_N,DSP_REG_Y},{PPI,MOVY,HEX_2}, arch_sh_dsp_up}, +/* *n*m*0**11 movy.w @<REG_N>+r9,<DSP_REG_Y> */ {"movy.w",{AY_PMOD_N,DSP_REG_Y},{PPI,MOVY,HEX_3}, arch_sh_dsp_up}, +/* *n*m*1**01 movy.w <DSP_REG_M>,@<REG_N> */ {"movy.w",{DSP_REG_A_M,AY_IND_N},{PPI,MOVY,HEX_9}, arch_sh_dsp_up}, +/* *n*m*1**10 movy.w <DSP_REG_M>,@<REG_N>+ */ {"movy.w",{DSP_REG_A_M,AY_INC_N},{PPI,MOVY,HEX_A}, arch_sh_dsp_up}, +/* *n*m*1**11 movy.w <DSP_REG_M>,@<REG_N>+r9 */ {"movy.w",{DSP_REG_A_M,AY_PMOD_N},{PPI,MOVY,HEX_B}, arch_sh_dsp_up}, + +/* nnmm000001 movy.w @<REG_Ayx>,<DSP_REG_YX> */ {"movy.w",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_1}, arch_sh4al_dsp_up}, +/* nnmm000010 movy.w @<REG_Ayx>+,<DSP_REG_YX> */{"movy.w",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_2}, arch_sh4al_dsp_up}, +/* nnmm000011 movy.w @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.w",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_0,HEX_3}, arch_sh4al_dsp_up}, +/* nnmm010001 movy.w <DSP_REG_AY>,@<REG_Ayx> */ {"movy.w",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_1,HEX_1}, arch_sh4al_dsp_up}, +/* nnmm010010 movy.w <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.w",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_1,HEX_2}, arch_sh4al_dsp_up}, +/* nnmm010011 movy.w <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.w",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_1,HEX_3}, arch_sh4al_dsp_up}, + +/* nnmm100001 movy.l @<REG_Ayx>,<DSP_REG_YX> */ {"movy.l",{AYX_IND_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_1}, arch_sh4al_dsp_up}, +/* nnmm100010 movy.l @<REG_Ayx>+,<DSP_REG_YX> */{"movy.l",{AYX_INC_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_2}, arch_sh4al_dsp_up}, +/* nnmm100011 movy.l @<REG_Ayx>+r8,<DSP_REG_YX> */{"movy.l",{AYX_PMOD_N,DSP_REG_YX},{PPI,MOVY_NOPX,HEX_2,HEX_3}, arch_sh4al_dsp_up}, +/* nnmm110001 movy.l <DSP_REG_AY>,@<REG_Ayx> */ {"movy.l",{DSP_REG_AY,AYX_IND_N},{PPI,MOVY_NOPX,HEX_3,HEX_1}, arch_sh4al_dsp_up}, +/* nnmm110010 movy.l <DSP_REG_AY>,@<REG_Ayx>+ */{"movy.l",{DSP_REG_AY,AYX_INC_N},{PPI,MOVY_NOPX,HEX_3,HEX_2}, arch_sh4al_dsp_up}, +/* nnmm110011 movy.l <DSP_REG_AY>,@<REG_Ayx>+r8 */{"movy.l",{DSP_REG_AY,AYX_PMOD_N},{PPI,MOVY_NOPX,HEX_3,HEX_3}, arch_sh4al_dsp_up}, /* 01aaeeffxxyyggnn pmuls Se,Sf,Dg */ {"pmuls",{DSP_REG_E,DSP_REG_F,DSP_REG_G},{PPI,PMUL}, arch_sh_dsp_up}, /* 10100000xxyynnnn psubc <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ @@ -678,13 +771,21 @@ sh_opcode_info sh_table[] = { /* 10110100xxyynnnn pwad <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"pwad", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_4}, arch_sh_dsp_up}, /* 10001000xxyynnnn pabs <DSP_REG_X>,<DSP_REG_N> */ -{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_8,HEX_8}, arch_sh_dsp_up}, +{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_8,HEX_8}, arch_sh_dsp_up}, +/* 1000100!xx01nnnn pabs <DSP_REG_X>,<DSP_REG_N> */ +{"pabs", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9,HEX_1}, arch_sh4al_dsp_up}, /* 10101000xxyynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ -{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_A,HEX_8}, arch_sh_dsp_up}, +{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_A,HEX_8}, arch_sh_dsp_up}, +/* 1010100!01yynnnn pabs <DSP_REG_Y>,<DSP_REG_N> */ +{"pabs", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9,HEX_4}, arch_sh4al_dsp_up}, /* 10011000xxyynnnn prnd <DSP_REG_X>,<DSP_REG_N> */ -{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3,HEX_9,HEX_8}, arch_sh_dsp_up}, +{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPI3NC,HEX_9,HEX_8}, arch_sh_dsp_up}, +/* 1001100!xx01nnnn prnd <DSP_REG_X>,<DSP_REG_N> */ +{"prnd", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_1}, arch_sh4al_dsp_up}, /* 10111000xxyynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ -{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3,HEX_B,HEX_8}, arch_sh_dsp_up}, +{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPI3NC,HEX_B,HEX_8}, arch_sh_dsp_up}, +/* 1011100!01yynnnn prnd <DSP_REG_Y>,<DSP_REG_N> */ +{"prnd", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_4}, arch_sh4al_dsp_up}, {"dct",{0},{PPI,PDC,HEX_1}, arch_sh_dsp_up}, {"dcf",{0},{PPI,PDC,HEX_2}, arch_sh_dsp_up}, @@ -697,6 +798,8 @@ sh_opcode_info sh_table[] = { /* 00010iiiiiiinnnn psha #<imm>,<DSP_REG_N> */ {"psha",{A_IMM,DSP_REG_N},{PPI,PSH,HEX_1}, arch_sh_dsp_up}, /* 10100001xxyynnnn psub <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"psub", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_1}, arch_sh_dsp_up}, +/* 10000101xxyynnnn psub <DSP_REG_Y>,<DSP_REG_X>,<DSP_REG_N> */ +{"psub", {DSP_REG_Y,DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_5}, arch_sh4al_dsp_up}, /* 10110001xxyynnnn padd <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ {"padd", {DSP_REG_X,DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_1}, arch_sh_dsp_up}, /* 10010101xxyynnnn pand <DSP_REG_X>,<DSP_REG_Y>,<DSP_REG_N> */ @@ -709,16 +812,16 @@ sh_opcode_info sh_table[] = { {"pdec", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_8,HEX_9}, arch_sh_dsp_up}, /* 10101001xxyynnnn pdec <DSP_REG_Y>,<DSP_REG_N> */ {"pdec", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_A,HEX_9}, arch_sh_dsp_up}, -/* 10011001xxyynnnn pinc <DSP_REG_X>,<DSP_REG_N> */ -{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9}, arch_sh_dsp_up}, -/* 10111001xxyynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ -{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9}, arch_sh_dsp_up}, +/* 10011001xx00nnnn pinc <DSP_REG_X>,<DSP_REG_N> */ +{"pinc", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_9,HEX_XX00}, arch_sh_dsp_up}, +/* 1011100100yynnnn pinc <DSP_REG_Y>,<DSP_REG_N> */ +{"pinc", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_9,HEX_00YY}, arch_sh_dsp_up}, /* 10001101xxyynnnn pclr <DSP_REG_N> */ {"pclr", {DSP_REG_N},{PPI,PPIC,HEX_8,HEX_D}, arch_sh_dsp_up}, -/* 10011101xxyynnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ -{"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D}, arch_sh_dsp_up}, -/* 10111101xxyynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ -{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D}, arch_sh_dsp_up}, +/* 10011101xx00nnnn pdmsb <DSP_REG_X>,<DSP_REG_N> */ +{"pdmsb", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_XX00}, arch_sh_dsp_up}, +/* 1011110100yynnnn pdmsb <DSP_REG_Y>,<DSP_REG_N> */ +{"pdmsb", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_00YY}, arch_sh_dsp_up}, /* 11001001xxyynnnn pneg <DSP_REG_X>,<DSP_REG_N> */ {"pneg", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_C,HEX_9}, arch_sh_dsp_up}, /* 11101001xxyynnnn pneg <DSP_REG_Y>,<DSP_REG_N> */ @@ -735,106 +838,116 @@ sh_opcode_info sh_table[] = { {"plds", {DSP_REG_N,A_MACH},{PPI,PPIC,HEX_E,HEX_D}, arch_sh_dsp_up}, /* 11111101xxyynnnn plds <DSP_REG_N>,MACL */ {"plds", {DSP_REG_N,A_MACL},{PPI,PPIC,HEX_F,HEX_D}, arch_sh_dsp_up}, +/* 10011101xx01zzzz pswap <DSP_REG_X>,<DSP_REG_N> */ +{"pswap", {DSP_REG_X,DSP_REG_N},{PPI,PPIC,HEX_9,HEX_D,HEX_1}, arch_sh4al_dsp_up}, +/* 1011110101yyzzzz pswap <DSP_REG_Y>,<DSP_REG_N> */ +{"pswap", {DSP_REG_Y,DSP_REG_N},{PPI,PPIC,HEX_B,HEX_D,HEX_4}, arch_sh4al_dsp_up}, -/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh3e_up}, -/* 1111nnnn01011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up}, +/* 1111nnnn01011101 fabs <F_REG_N> */{"fabs",{F_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh2e_up}, +/* 1111nnn001011101 fabs <D_REG_N> */{"fabs",{D_REG_N},{HEX_F,REG_N,HEX_5,HEX_D}, arch_sh4_up}, -/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh3e_up}, +/* 1111nnnnmmmm0000 fadd <F_REG_M>,<F_REG_N>*/{"fadd",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh2e_up}, /* 1111nnn0mmm00000 fadd <D_REG_M>,<D_REG_N>*/{"fadd",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_0}, arch_sh4_up}, -/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh3e_up}, +/* 1111nnnnmmmm0100 fcmp/eq <F_REG_M>,<F_REG_N>*/{"fcmp/eq",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh2e_up}, /* 1111nnn0mmm00100 fcmp/eq <D_REG_M>,<D_REG_N>*/{"fcmp/eq",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_4}, arch_sh4_up}, -/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh3e_up}, +/* 1111nnnnmmmm0101 fcmp/gt <F_REG_M>,<F_REG_N>*/{"fcmp/gt",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh2e_up}, /* 1111nnn0mmm00101 fcmp/gt <D_REG_M>,<D_REG_N>*/{"fcmp/gt",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_5}, arch_sh4_up}, -/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_B,HEX_D}, arch_sh4_up}, +/* 1111nnn010111101 fcnvds <D_REG_N>,FPUL*/{"fcnvds",{D_REG_N,FPUL_M},{HEX_F,REG_N_D,HEX_B,HEX_D}, arch_sh4_up}, -/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_A,HEX_D}, arch_sh4_up}, +/* 1111nnn010101101 fcnvsd FPUL,<D_REG_N>*/{"fcnvsd",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_A,HEX_D}, arch_sh4_up}, -/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh3e_up}, +/* 1111nnnnmmmm0011 fdiv <F_REG_M>,<F_REG_N>*/{"fdiv",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh2e_up}, /* 1111nnn0mmm00011 fdiv <D_REG_M>,<D_REG_N>*/{"fdiv",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_3}, arch_sh4_up}, /* 1111nnmm11101101 fipr <V_REG_M>,<V_REG_N>*/{"fipr",{V_REG_M,V_REG_N},{HEX_F,REG_NM,HEX_E,HEX_D}, arch_sh4_up}, -/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh3e_up}, +/* 1111nnnn10001101 fldi0 <F_REG_N> */{"fldi0",{F_REG_N},{HEX_F,REG_N,HEX_8,HEX_D}, arch_sh2e_up}, -/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh3e_up}, +/* 1111nnnn10011101 fldi1 <F_REG_N> */{"fldi1",{F_REG_N},{HEX_F,REG_N,HEX_9,HEX_D}, arch_sh2e_up}, -/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh3e_up}, +/* 1111nnnn00011101 flds <F_REG_N>,FPUL*/{"flds",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_1,HEX_D}, arch_sh2e_up}, -/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh3e_up}, -/* 1111nnnn00101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up}, +/* 1111nnnn00101101 float FPUL,<F_REG_N>*/{"float",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh2e_up}, +/* 1111nnn000101101 float FPUL,<D_REG_N>*/{"float",{FPUL_M,D_REG_N},{HEX_F,REG_N,HEX_2,HEX_D}, arch_sh4_up}, -/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh3e_up}, +/* 1111nnnnmmmm1110 fmac FR0,<F_REG_M>,<F_REG_N>*/{"fmac",{F_FR0,F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_E}, arch_sh2e_up}, -/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh3e_up}, -/* 1111nnnnmmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up}, +/* 1111nnnnmmmm1100 fmov <F_REG_M>,<F_REG_N>*/{"fmov",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh2e_up}, +/* 1111nnn1mmmm1100 fmov <DX_REG_M>,<DX_REG_N>*/{"fmov",{DX_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_C}, arch_sh4_up}, -/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh3e_up}, -/* 1111nnnnmmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up}, +/* 1111nnnnmmmm1000 fmov @<REG_M>,<F_REG_N>*/{"fmov",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, +/* 1111nnn1mmmm1000 fmov @<REG_M>,<DX_REG_N>*/{"fmov",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up}, -/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh3e_up}, -/* 1111nnnnmmmm1010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up}, +/* 1111nnnnmmmm1010 fmov <F_REG_M>,@<REG_N>*/{"fmov",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, +/* 1111nnnnmmm11010 fmov <DX_REG_M>,@<REG_N>*/{"fmov",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up}, -/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh3e_up}, -/* 1111nnnnmmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up}, +/* 1111nnnnmmmm1001 fmov @<REG_M>+,<F_REG_N>*/{"fmov",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, +/* 1111nnn1mmmm1001 fmov @<REG_M>+,<DX_REG_N>*/{"fmov",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up}, -/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh3e_up}, -/* 1111nnnnmmmm1011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up}, +/* 1111nnnnmmmm1011 fmov <F_REG_M>,@-<REG_N>*/{"fmov",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, +/* 1111nnnnmmm11011 fmov <DX_REG_M>,@-<REG_N>*/{"fmov",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up}, -/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh3e_up}, -/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up}, +/* 1111nnnnmmmm0110 fmov @(R0,<REG_M>),<F_REG_N>*/{"fmov",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, +/* 1111nnn1mmmm0110 fmov @(R0,<REG_M>),<DX_REG_N>*/{"fmov",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up}, -/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh3e_up}, -/* 1111nnnnmmmm0111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up}, +/* 1111nnnnmmmm0111 fmov <F_REG_M>,@(R0,<REG_N>)*/{"fmov",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, +/* 1111nnnnmmm10111 fmov <DX_REG_M>,@(R0,<REG_N>)*/{"fmov",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up}, -/* 1111nnnnmmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up}, +/* 1111nnn1mmmm1000 fmov.d @<REG_M>,<DX_REG_N>*/{"fmov.d",{A_IND_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh4_up}, -/* 1111nnnnmmmm1010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up}, +/* 1111nnnnmmm11010 fmov.d <DX_REG_M>,@<REG_N>*/{"fmov.d",{DX_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh4_up}, -/* 1111nnnnmmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up}, +/* 1111nnn1mmmm1001 fmov.d @<REG_M>+,<DX_REG_N>*/{"fmov.d",{A_INC_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh4_up}, -/* 1111nnnnmmmm1011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up}, +/* 1111nnnnmmm11011 fmov.d <DX_REG_M>,@-<REG_N>*/{"fmov.d",{DX_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh4_up}, -/* 1111nnnnmmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up}, +/* 1111nnn1mmmm0110 fmov.d @(R0,<REG_M>),<DX_REG_N>*/{"fmov.d",{A_IND_R0_REG_M,DX_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh4_up}, -/* 1111nnnnmmmm0111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up}, +/* 1111nnnnmmm10111 fmov.d <DX_REG_M>,@(R0,<REG_N>)*/{"fmov.d",{DX_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh4_up}, -/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh3e_up}, +/* 1111nnnnmmmm1000 fmov.s @<REG_M>,<F_REG_N>*/{"fmov.s",{A_IND_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_8}, arch_sh2e_up}, -/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh3e_up}, +/* 1111nnnnmmmm1010 fmov.s <F_REG_M>,@<REG_N>*/{"fmov.s",{F_REG_M,A_IND_N},{HEX_F,REG_N,REG_M,HEX_A}, arch_sh2e_up}, -/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh3e_up}, +/* 1111nnnnmmmm1001 fmov.s @<REG_M>+,<F_REG_N>*/{"fmov.s",{A_INC_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_9}, arch_sh2e_up}, -/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh3e_up}, +/* 1111nnnnmmmm1011 fmov.s <F_REG_M>,@-<REG_N>*/{"fmov.s",{F_REG_M,A_DEC_N},{HEX_F,REG_N,REG_M,HEX_B}, arch_sh2e_up}, -/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh3e_up}, +/* 1111nnnnmmmm0110 fmov.s @(R0,<REG_M>),<F_REG_N>*/{"fmov.s",{A_IND_R0_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_6}, arch_sh2e_up}, -/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh3e_up}, +/* 1111nnnnmmmm0111 fmov.s <F_REG_M>,@(R0,<REG_N>)*/{"fmov.s",{F_REG_M,A_IND_R0_REG_N},{HEX_F,REG_N,REG_M,HEX_7}, arch_sh2e_up}, -/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh3e_up}, +/* 1111nnnnmmmm0010 fmul <F_REG_M>,<F_REG_N>*/{"fmul",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh2e_up}, /* 1111nnn0mmm00010 fmul <D_REG_M>,<D_REG_N>*/{"fmul",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_2}, arch_sh4_up}, -/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh3e_up}, -/* 1111nnnn01001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up}, +/* 1111nnnn01001101 fneg <F_REG_N> */{"fneg",{F_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh2e_up}, +/* 1111nnn001001101 fneg <D_REG_N> */{"fneg",{D_REG_N},{HEX_F,REG_N,HEX_4,HEX_D}, arch_sh4_up}, + +/* 1111011111111101 fpchg */{"fpchg",{0},{HEX_F,HEX_7,HEX_F,HEX_D}, arch_sh4a_up}, /* 1111101111111101 frchg */{"frchg",{0},{HEX_F,HEX_B,HEX_F,HEX_D}, arch_sh4_up}, +/* 1111nnn011111101 fsca FPUL,<D_REG_N> */{"fsca",{FPUL_M,D_REG_N},{HEX_F,REG_N_D,HEX_F,HEX_D}, arch_sh4_up}, + /* 1111001111111101 fschg */{"fschg",{0},{HEX_F,HEX_3,HEX_F,HEX_D}, arch_sh4_up}, /* 1111nnnn01101101 fsqrt <F_REG_N> */{"fsqrt",{F_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh3e_up}, -/* 1111nnnn01101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up}, +/* 1111nnn001101101 fsqrt <D_REG_N> */{"fsqrt",{D_REG_N},{HEX_F,REG_N,HEX_6,HEX_D}, arch_sh4_up}, + +/* 1111nnnn01111101 fsrra <F_REG_N> */{"fsrra",{F_REG_N},{HEX_F,REG_N,HEX_7,HEX_D}, arch_sh4_up}, -/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh3e_up}, +/* 1111nnnn00001101 fsts FPUL,<F_REG_N>*/{"fsts",{FPUL_M,F_REG_N},{HEX_F,REG_N,HEX_0,HEX_D}, arch_sh2e_up}, -/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh3e_up}, +/* 1111nnnnmmmm0001 fsub <F_REG_M>,<F_REG_N>*/{"fsub",{F_REG_M,F_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh2e_up}, /* 1111nnn0mmm00001 fsub <D_REG_M>,<D_REG_N>*/{"fsub",{D_REG_M,D_REG_N},{HEX_F,REG_N,REG_M,HEX_1}, arch_sh4_up}, -/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh3e_up}, +/* 1111nnnn00111101 ftrc <F_REG_N>,FPUL*/{"ftrc",{F_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh2e_up}, /* 1111nnnn00111101 ftrc <D_REG_N>,FPUL*/{"ftrc",{D_REG_N,FPUL_M},{HEX_F,REG_N,HEX_3,HEX_D}, arch_sh4_up}, -/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_NM,HEX_F,HEX_D}, arch_sh4_up}, +/* 1111nn0111111101 ftrv XMTRX_M4,<V_REG_n>*/{"ftrv",{XMTRX_M4,V_REG_N},{HEX_F,REG_N_B01,HEX_F,HEX_D}, arch_sh4_up}, { 0, {0}, {0}, 0 } }; diff --git a/contrib/binutils/opcodes/sparc-dis.c b/contrib/binutils/opcodes/sparc-dis.c index 47ebb31..6f360c6 100644 --- a/contrib/binutils/opcodes/sparc-dis.c +++ b/contrib/binutils/opcodes/sparc-dis.c @@ -1,20 +1,20 @@ /* Print SPARC instructions. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2002 Free Software Foundation, Inc. + 2000, 2002, 2003, 2004 Free Software Foundation, Inc. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include <stdio.h> @@ -46,7 +46,8 @@ static const struct sparc_opcode **sorted_opcodes; static int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 }; #define HASH_INSN(INSN) \ ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19)) -struct opcode_hash { +struct opcode_hash +{ struct opcode_hash *next; const struct sparc_opcode *opcode; }; @@ -223,7 +224,7 @@ print_insn_sparc (memaddr, info) static int opcodes_initialized = 0; /* bfd mach number of last call. */ static unsigned long current_mach = 0; - bfd_vma (*getword) PARAMS ((const unsigned char *)); + bfd_vma (*getword) (const void *); if (!opcodes_initialized || info->mach != current_mach) @@ -257,7 +258,7 @@ print_insn_sparc (memaddr, info) } /* On SPARClite variants such as DANlite (sparc86x), instructions - are always big-endian even when the machine is in little-endian mode. */ + are always big-endian even when the machine is in little-endian mode. */ if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite) getword = bfd_getb32; else @@ -265,10 +266,10 @@ print_insn_sparc (memaddr, info) insn = getword (buffer); - info->insn_info_valid = 1; /* We do return this info */ - info->insn_type = dis_nonbranch; /* Assume non branch insn */ - info->branch_delay_insns = 0; /* Assume no delay */ - info->target = 0; /* Assume no target known */ + info->insn_info_valid = 1; /* We do return this info. */ + info->insn_type = dis_nonbranch; /* Assume non branch insn. */ + info->branch_delay_insns = 0; /* Assume no delay. */ + info->target = 0; /* Assume no target known. */ for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next) { @@ -316,32 +317,34 @@ print_insn_sparc (memaddr, info) if (opcode->args[0] != ',') (*info->fprintf_func) (stream, " "); + for (s = opcode->args; *s != '\0'; ++s) { while (*s == ',') { (*info->fprintf_func) (stream, ","); ++s; - switch (*s) { - case 'a': - (*info->fprintf_func) (stream, "a"); - is_annulled = 1; - ++s; - continue; - case 'N': - (*info->fprintf_func) (stream, "pn"); - ++s; - continue; - - case 'T': - (*info->fprintf_func) (stream, "pt"); - ++s; - continue; - - default: - break; - } /* switch on arg */ - } /* while there are comma started args */ + switch (*s) + { + case 'a': + (*info->fprintf_func) (stream, "a"); + is_annulled = 1; + ++s; + continue; + case 'N': + (*info->fprintf_func) (stream, "pn"); + ++s; + continue; + + case 'T': + (*info->fprintf_func) (stream, "pt"); + ++s; + continue; + + default: + break; + } + } (*info->fprintf_func) (stream, " "); @@ -682,26 +685,33 @@ print_insn_sparc (memaddr, info) unsigned long prev_insn; int errcode; - errcode = - (*info->read_memory_func) + if (memaddr >= 4) + errcode = + (*info->read_memory_func) (memaddr - 4, buffer, sizeof (buffer), info); + else + errcode = 1; + prev_insn = getword (buffer); if (errcode == 0) { /* If it is a delayed branch, we need to look at the instruction before the delayed branch. This handles - sequences such as + sequences such as: sethi %o1, %hi(_foo), %o1 call _printf - or %o1, %lo(_foo), %o1 - */ + or %o1, %lo(_foo), %o1 */ if (is_delayed_branch (prev_insn)) { - errcode = (*info->read_memory_func) - (memaddr - 8, buffer, sizeof (buffer), info); + if (memaddr >= 8) + errcode = (*info->read_memory_func) + (memaddr - 8, buffer, sizeof (buffer), info); + else + errcode = 1; + prev_insn = getword (buffer); } } @@ -746,7 +756,7 @@ print_insn_sparc (memaddr, info) } } - info->insn_type = dis_noninsn; /* Mark as non-valid instruction */ + info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */ (*info->fprintf_func) (stream, _("unknown")); return sizeof (buffer); } diff --git a/contrib/binutils/opcodes/sparc-opc.c b/contrib/binutils/opcodes/sparc-opc.c index 0010232..22f18fa 100644 --- a/contrib/binutils/opcodes/sparc-opc.c +++ b/contrib/binutils/opcodes/sparc-opc.c @@ -1,6 +1,6 @@ /* Table of opcodes for the sparc. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000 + 2000, 2002, 2004 Free Software Foundation, Inc. This file is part of the BFD library. @@ -1525,17 +1525,17 @@ CONDFC ("fbule", "cb013", 0xe, F_CONDBR), { "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 }, { "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 }, -{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,g", F_FLOAT, v9 }, -{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,g", F_FLOAT, v9 }, -{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,g", F_FLOAT, v9 }, +{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, v9 }, +{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, v9 }, +{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, v9 }, { "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 }, { "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 }, { "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 }, -{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "f,H", F_FLOAT, v9 }, -{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "f,g", F_FLOAT, v9 }, -{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "f,J", F_FLOAT, v9 }, +{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, v9 }, +{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, v9 }, +{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, v9 }, { "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 }, { "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 }, |
