diff options
| author | dim <dim@FreeBSD.org> | 2010-11-01 19:35:33 +0000 |
|---|---|---|
| committer | dim <dim@FreeBSD.org> | 2010-11-01 19:35:33 +0000 |
| commit | 3f5c947f4453c6016a2a6a9636367ee3f48fc6fc (patch) | |
| tree | 461aafc934d462eb9b9221308f8e25238c0ada62 /contrib/binutils/include | |
| parent | e6be3e7867eb43d220575baee2ce5662fb03e46c (diff) | |
| parent | d0f678fa0ff3f08a4eca29daf4d1ac39797b6326 (diff) | |
| download | FreeBSD-src-3f5c947f4453c6016a2a6a9636367ee3f48fc6fc.zip FreeBSD-src-3f5c947f4453c6016a2a6a9636367ee3f48fc6fc.tar.gz | |
Merge ^/vendor/binutils/dist@214571 into contrib/binutils, which brings
us up to version 2.17.50.20070703, at the last GPLv2 commit.
Amongst others, this added upstream support for some FreeBSD-specific
things that we previously had to manually hack in, such as the OSABI
label support, and so on.
There are also quite a number of new files, some for cpu's (e.g. SPU)
that we may or may not be interested in, but those can be cleaned up
later on, if needed.
Diffstat (limited to 'contrib/binutils/include')
41 files changed, 3205 insertions, 1878 deletions
diff --git a/contrib/binutils/include/ChangeLog b/contrib/binutils/include/ChangeLog index 0a3787a..275d729 100644 --- a/contrib/binutils/include/ChangeLog +++ b/contrib/binutils/include/ChangeLog @@ -1,3 +1,146 @@ +2007-07-03 Nathan Sidwell <nathan@codesourcery.com> + + * opcode/m68k.h: Document j K & E. + +2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> + + * dis-asm.h (print_insn_cr16): New prototype. + +2007-06-01 Noah Misch <noah@cs.caltech.edu> + Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_link_info): Add input_bfds_tail. + +2007-05-07 Nathan Froyd <froydnj@codesourcery.com> + + * libiberty.h (writeargv): Declare. + +2007-04-30 Alan Modra <amodra@bigpond.net.au> + + * bfdlink.h (struct bfd_link_info): Add "info" and "minfo". + +2007-04-25 Mark Mitchell <mark@codesourcery.com> + + * demangle.h: Change license to LGPL + exception. + +2007-04-10 Richard Henderson <rth@redhat.com> + + * bfdlink.h (struct bfd_link_info): Add relax_trip. + +2007-03-29 Joel Brobecker <brobecker@adacore.com> + + * filenames.h (FILENAME_CMP): Adjust define to call filename_cmp + regardless of the type of file system. + +2007-03-06 Jan Hubicka <jh@suse.cz> + + * ansidecl.h (ATTRIBUTE_COLD, ATTRIBUTE_HOT): New. + +2007-02-21 Nick Clifton <nickc@redhat.com> + + * bfdlink.h (struct bfd_link_callbacks): Add + override_segment_assignment field. + +2007-02-17 Mark Mitchell <mark@codesourcery.com> + Nathan Sidwell <nathan@codesourcery.com> + Vladimir Prus <vladimir@codesourcery.com + Joseph Myers <joseph@codesourcery.com> + + * bin-bugs.h: Remove. + +2007-02-09 Joseph S. Myers <joseph@codesourcery.com> + + * libiberty.h (pex_write_input): Remove prototype. + +2007-02-05 Dave Brolley <brolley@redhat.com> + + * Contribute the following changes: + 2001-03-26 Ben Elliston <bje@redhat.com> + + * dis-asm.h (print_insn_mep): Declare. + +2007-02-02 H.J. Lu <hongjiu.lu@intel.com> + + * dis-asm.h (print_i386_disassembler_options): New. + +2007-01-31 Vladimir Prus <vladimir@codesourcery.com> + + * libiberty.h (PEX_STDERR_TO_PIPE): New define. + (PEX_BINARY_ERROR): New define. + (pex_read_err): New function. + +2007-01-29 Simon Baldwin <simonb@google.com> + + * demangle.h: New cplus_demangle_print_callback, + cplus_demangle_v3_callback, and java_demangle_v3_callback function + prototypes, and demangle_callbackref type definition. + +2007-01-16 H.J. Lu <hongjiu.lu@intel.com> + + PR ld/3831 + * bfdlink.h (bfd_link_info): Rename dynamic to dynamic_list. + Add dynamic and dynamic_data. + +2006-12-05 Michael Tautschnig <tautschn@model.in.tum.de> + Nick Clifton <nickc@redhat.com> + + * ansidecl.h (ATTRIBUTE_PACKED): Define. + +2006-11-30 Andrew Stubbs <andrew.stubbs@st.com> + J"orn Rennecke <joern.rennecke@st.com> + + PR driver/29931 + * libiberty.h (make_relative_prefix_ignore_links): Declare. + +2006-11-27 Bob Wilson <bob.wilson@acm.org> + + * xtensa-config.h (XSHAL_ABI): New. + (XTHAL_ABI_WINDOWED, XTHAL_ABI_CALL0): New. + +2006-11-27 Bob Wilson <bob.wilson@acm.org> + + * xtensa-isa.h (STATIC_LIBISA): Delete. + +2006-10-30 Paul Brook <paul@codesourcery.com> + + * dis-asm.h (disassemble_info): Add symtab, symtab_pos and + symtab_size. + +2006-10-30 H.J. Lu <hongjiu.lu@intel.com> + + PR ld/3111 + * bfdlink.h (bfd_link_info): Add reduce_memory_overheads. + +2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> + Yukishige Shibata <shibata@rd.scei.sony.co.jp> + Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> + Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> + Alan Modra <amodra@bigpond.net.au> + + * dis-asm.h (print_insn_spu): Declare. + +2006-10-17 Mark Shinwell <shinwell@codesourcery.com> + + * elf/arm.h: Define TAG_CPU_ARCH_* constants. + +2006-09-17 Mei Ligang <ligang@sunnorth.com.cn> + + * dis-asm.h: Add prototypes for Score disassembler routines. + +2006-09-07 H.J. Lu <hongjiu.lu@intel.com> + + * bfdlink.h (bfd_elf_dynamic_list): New. + (bfd_link_info): Add a dynamic field. + +2006-08-04 Marcelo Tosatti <marcelo@kvack.org> + + * bfdlink.h (struct bfd_link_info): New field: print_gc_sections. + +2006-07-10 Jakub Jelinek <jakub@redhat.com> + + * bfdlink.h (struct bfd_link_info): Add emit_hash and + emit_gnu_hash bitfields. + 2006-04-11 Jim Blandy <jimb@codesourcery.com> * libiberty.h (pex_input_file, pex_input_pipe): New declarations. @@ -17,6 +160,11 @@ R_BFIN_GOTOFFLO): New relocs. (EF_BFIN_PIC, EF_BFIN_FDPIC, EF_BFIN_PIC_FLAGS): New macros. +2006-03-23 Michael Matz <matz@suse.de> + + * elf/x86-64.h: Add the new relocations with their official + numbers. + 2006-02-17 Shrirang Khisti <shrirangk@kpitcummins.com> Anil Paranjape <anilp1@kpitcummins.com> Shilin Shakti <shilins@kpitcummins.com> diff --git a/contrib/binutils/include/ansidecl.h b/contrib/binutils/include/ansidecl.h index a1a765d..c19955a 100644 --- a/contrib/binutils/include/ansidecl.h +++ b/contrib/binutils/include/ansidecl.h @@ -361,6 +361,28 @@ So instead we use the macro below and test it against specific values. */ # endif /* GNUC >= 3.0 */ #endif /* ATTRIBUTE_ALIGNED_ALIGNOF */ +/* Useful for structures whose layout must much some binary specification + regardless of the alignment and padding qualities of the compiler. */ +#ifndef ATTRIBUTE_PACKED +# define ATTRIBUTE_PACKED __attribute__ ((packed)) +#endif + +/* Attribute `hot' and `cold' was valid as of gcc 4.3. */ +#ifndef ATTRIBUTE_COLD +# if (GCC_VERSION >= 4003) +# define ATTRIBUTE_COLD __attribute__ ((__cold__)) +# else +# define ATTRIBUTE_COLD +# endif /* GNUC >= 4.3 */ +#endif /* ATTRIBUTE_COLD */ +#ifndef ATTRIBUTE_HOT +# if (GCC_VERSION >= 4003) +# define ATTRIBUTE_HOT __attribute__ ((__hot__)) +# else +# define ATTRIBUTE_HOT +# endif /* GNUC >= 4.3 */ +#endif /* ATTRIBUTE_HOT */ + /* We use __extension__ in some places to suppress -pedantic warnings about GCC extensions. This feature didn't work properly before gcc 2.8. */ diff --git a/contrib/binutils/include/bfdlink.h b/contrib/binutils/include/bfdlink.h index f4b7aa7..a373225 100644 --- a/contrib/binutils/include/bfdlink.h +++ b/contrib/binutils/include/bfdlink.h @@ -1,6 +1,6 @@ /* bfdlink.h -- header file for BFD link routines Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, - 2003, 2004, 2005 Free Software Foundation, Inc. + 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. Written by Steve Chamberlain and Ian Lance Taylor, Cygnus Support. This file is part of BFD, the Binary File Descriptor library. @@ -221,6 +221,8 @@ enum report_method RM_GENERATE_ERROR }; +struct bfd_elf_dynamic_list; + /* This structure holds all the information needed to communicate between BFD and the linker when doing a link. */ @@ -324,6 +326,27 @@ struct bfd_link_info /* TRUE if unreferenced sections should be removed. */ unsigned int gc_sections: 1; + /* TRUE if user shoudl be informed of removed unreferenced sections. */ + unsigned int print_gc_sections: 1; + + /* TRUE if .hash section should be created. */ + unsigned int emit_hash: 1; + + /* TRUE if .gnu.hash section should be created. */ + unsigned int emit_gnu_hash: 1; + + /* If TRUE reduce memory overheads, at the expense of speed. This will + cause map file generation to use an O(N^2) algorithm and disable + caching ELF symbol buffer. */ + unsigned int reduce_memory_overheads: 1; + + /* TRUE if all data symbols should be dynamic. */ + unsigned int dynamic_data: 1; + + /* TRUE if some symbols have to be dynamic, controlled by + --dynamic-list command line options. */ + unsigned int dynamic: 1; + /* What to do with unresolved symbols in an object file. When producing executables the default is GENERATE_ERROR. When producing shared libraries the default is IGNORE. The @@ -372,6 +395,7 @@ struct bfd_link_info /* The list of input BFD's involved in the link. These are chained together via the link_next field. */ bfd *input_bfds; + bfd **input_bfds_tail; /* If a symbol should be created for each input BFD, this is section where those symbols should be placed. It must be a section in @@ -401,6 +425,11 @@ struct bfd_link_info current pass, starting from 0. */ int relax_pass; + /* Number of relaxation trips. This number is incremented every + time the relaxation pass is restarted due to a previous + relaxation returning true in *AGAIN. */ + int relax_trip; + /* Non-zero if auto-import thunks for DATA items in pei386 DLLs should be generated/linked against. Set to 1 if this feature is explicitly requested by the user, -1 if enabled by default. */ @@ -422,10 +451,13 @@ struct bfd_link_info /* Start and end of RELRO region. */ bfd_vma relro_start, relro_end; + + /* List of symbols should be dynamic. */ + struct bfd_elf_dynamic_list *dynamic_list; }; -/* This structures holds a set of callback functions. These are - called by the BFD linker routines. Except for einfo, the first +/* This structures holds a set of callback functions. These are called + by the BFD linker routines. Except for the info functions, the first argument to each callback function is the bfd_link_info structure being used and each function returns a boolean value. If the function returns FALSE, then the BFD function which called it should @@ -537,9 +569,22 @@ struct bfd_link_callbacks bfd_boolean (*notice) (struct bfd_link_info *, const char *name, bfd *abfd, asection *section, bfd_vma address); - /* General link info message. */ + /* Error or warning link info message. */ void (*einfo) (const char *fmt, ...); + /* General link info message. */ + void (*info) + (const char *fmt, ...); + /* Message to be printed in linker map file. */ + void (*minfo) + (const char *fmt, ...); + /* This callback provides a chance for users of the BFD library to + override its decision about whether to place two adjacent sections + into the same segment. */ + bfd_boolean (*override_segment_assignment) + (struct bfd_link_info *, bfd * abfd, + asection * current_section, asection * previous_section, + bfd_boolean new_segment); }; /* The linker builds link_order structures which tell the code how to @@ -715,4 +760,12 @@ struct bfd_elf_version_tree struct bfd_elf_version_expr *prev, const char *sym); }; +struct bfd_elf_dynamic_list +{ + struct bfd_elf_version_expr_head head; + struct bfd_elf_version_expr *(*match) + (struct bfd_elf_version_expr_head *head, + struct bfd_elf_version_expr *prev, const char *sym); +}; + #endif diff --git a/contrib/binutils/include/bin-bugs.h b/contrib/binutils/include/bin-bugs.h deleted file mode 100644 index 63901b0..0000000 --- a/contrib/binutils/include/bin-bugs.h +++ /dev/null @@ -1,3 +0,0 @@ -#ifndef REPORT_BUGS_TO -#define REPORT_BUGS_TO "<URL:http://www.sourceware.org/bugzilla/>" -#endif diff --git a/contrib/binutils/include/coff/ChangeLog b/contrib/binutils/include/coff/ChangeLog index f41c115..3fa22bf 100644 --- a/contrib/binutils/include/coff/ChangeLog +++ b/contrib/binutils/include/coff/ChangeLog @@ -1,3 +1,41 @@ +2007-04-27 Alan Modra <amodra@bigpond.net.au> + + * rs6000.h: Write Mimi's name in ASCII. + +2007-03-19 H.J. Lu <hongjiu.lu@intel.com> + + * internal.h (internal_extra_pe_aouthdr): Add Magic, + MajorLinkerVersion, MinorLinkerVersion, SizeOfCode, + SizeOfInitializedData, SizeOfUninitializedData, + AddressOfEntryPoint, BaseOfCode and BaseOfData. + +2006-12-05 Michael Tautschnig <tautschn@model.in.tum.de> + Nick Clifton <nickc@redhat.com> + + * external.h (struct external_aouthdr): Add ATTRIBUTE_PACKED. + (struct external_syment): Likewise. + (union external_auxent): Likewise. + +2006-11-14 Phil Lello <phil.lello@homecall.co.uk> + + * pe.h: Added defines for IMAGE_SUBSYSTEM_EFI_ROM and + IMAGE_SUBSYSTEM_XBOX. + * internal.h: Added defines for PE directory entry types. + NB: in internal.h because IMAGE_NUMBEROF_DIRECTORY_ENTRYIES is in + pe.h + +2006-09-20 Kai Tietz <Kai.Tietz@onevision.com> + + * external.h: Add proper external_aouthdr64 structure (without + data_start member). + (AOUTHDRSZ64): Set according structure size. + (AOUTHDR64): As typedef of external_aouthdr64 structure. + * internal.h: Add relocation identifiers for coff. + * pe.h: Add define IMAGE_FILE_MACHINE_AMD64 the coff signature. + (PEPAOUTHDR): Adjust structure to have proper size (using AOUTHDR64). + (PEPAOUTSZ): Calculated size of 240. + * x86_64.h: Coff information for x86_64 (AMD64). + 2006-02-05 Arnold Metselaar <arnold.metselaar@planet.nl> * internal.h: Add relocation number R_IMM24 for Z80. diff --git a/contrib/binutils/include/coff/external.h b/contrib/binutils/include/coff/external.h index 9e760bd..8dabc8a 100644 --- a/contrib/binutils/include/coff/external.h +++ b/contrib/binutils/include/coff/external.h @@ -1,6 +1,6 @@ /* external.h -- External COFF structures - Copyright 2001 Free Software Foundation, Inc. + Copyright 2001, 2006 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -50,12 +50,26 @@ typedef struct external_aouthdr char entry[4]; /* entry pt. */ char text_start[4]; /* base of text used for this file */ char data_start[4]; /* base of data used for this file */ - } + } ATTRIBUTE_PACKED AOUTHDR; #define AOUTHDRSZ 28 #define AOUTSZ 28 -#endif + +typedef struct external_aouthdr64 +{ + char magic[2]; /* Type of file. */ + char vstamp[2]; /* Version stamp. */ + char tsize[4]; /* Text size in bytes, padded to FW bdry*/ + char dsize[4]; /* Initialized data " ". */ + char bsize[4]; /* Uninitialized data " ". */ + char entry[4]; /* Entry pt. */ + char text_start[4]; /* Base of text used for this file. */ +} +AOUTHDR64; +#define AOUTHDRSZ64 24 + +#endif /* not DO_NOT_DEFINE_AOUTHDR */ #ifndef DO_NOT_DEFINE_SCNHDR /********************** SECTION HEADER **********************/ @@ -150,7 +164,7 @@ struct external_syment char e_type[2]; char e_sclass[1]; char e_numaux[1]; -}; +} ATTRIBUTE_PACKED ; #define SYMENT struct external_syment #define SYMESZ 18 @@ -242,7 +256,7 @@ union external_auxent char x_tvlen[2]; /* length of .tv */ char x_tvran[2][2]; /* tv range */ } x_tv; /* info about .tv section (in auxent of symbol .tv)) */ -}; +} ATTRIBUTE_PACKED ; #define AUXENT union external_auxent #define AUXESZ 18 diff --git a/contrib/binutils/include/coff/pe.h b/contrib/binutils/include/coff/pe.h index 643cea4..277621c 100644 --- a/contrib/binutils/include/coff/pe.h +++ b/contrib/binutils/include/coff/pe.h @@ -1,6 +1,6 @@ /* pe.h - PE COFF header information - Copyright 1999, 2000, 2001, 2003, 2004 Free Software Foundation, Inc. + Copyright 1999, 2000, 2001, 2003, 2004, 2006 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -119,6 +119,7 @@ #define IMAGE_FILE_MACHINE_THUMB 0x01c2 #define IMAGE_FILE_MACHINE_TRICORE 0x0520 #define IMAGE_FILE_MACHINE_WCEMIPSV2 0x0169 +#define IMAGE_FILE_MACHINE_AMD64 0x8664 #define IMAGE_SUBSYSTEM_UNKNOWN 0 #define IMAGE_SUBSYSTEM_NATIVE 1 @@ -129,6 +130,8 @@ #define IMAGE_SUBSYSTEM_EFI_APPLICATION 10 #define IMAGE_SUBSYSTEM_EFI_BOOT_SERVICE_DRIVER 11 #define IMAGE_SUBSYSTEM_EFI_RUNTIME_DRIVER 12 +#define IMAGE_SUBSYSTEM_EFI_ROM 13 +#define IMAGE_SUBSYSTEM_XBOX 14 /* Magic values that are true for all dos/nt implementations. */ #define DOSMAGIC 0x5a4d @@ -259,6 +262,7 @@ typedef struct /* IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; */ char DataDirectory[16][2][4]; /* 16 entries, 2 elements/entry, 4 chars. */ } PEAOUTHDR; + #undef AOUTSZ #define AOUTSZ (AOUTHDRSZ + 196) @@ -267,8 +271,11 @@ typedef struct of just 4 bytes long. */ typedef struct { +#ifdef AOUTHDRSZ64 + AOUTHDR64 standard; +#else AOUTHDR standard; - +#endif /* NT extra fields; see internal.h for descriptions. */ char ImageBase[8]; char SectionAlignment[4]; @@ -294,7 +301,12 @@ typedef struct /* IMAGE_DATA_DIRECTORY DataDirectory[IMAGE_NUMBEROF_DIRECTORY_ENTRIES]; */ char DataDirectory[16][2][4]; /* 16 entries, 2 elements/entry, 4 chars. */ } PEPAOUTHDR; + +#ifdef AOUTHDRSZ64 +#define PEPAOUTSZ (AOUTHDRSZ64 + 196 + 5 * 4) /* = 240 */ +#else #define PEPAOUTSZ 240 +#endif #undef E_FILNMLEN #define E_FILNMLEN 18 /* # characters in a file name. */ diff --git a/contrib/binutils/include/coff/rs6000.h b/contrib/binutils/include/coff/rs6000.h index 5323662..a4e6eb5 100644 --- a/contrib/binutils/include/coff/rs6000.h +++ b/contrib/binutils/include/coff/rs6000.h @@ -1,10 +1,6 @@ /* IBM RS/6000 "XCOFF" file definitions for BFD. Copyright (C) 1990, 1991, 2001 Free Software Foundation, Inc. - FIXME: Can someone provide a transliteration of this name into ASCII? - Using the following chars caused a compiler warning on HIUX (so I replaced - them with octal escapes), and isn't useful without an understanding of what - character set it is. - Written by Mimi Ph\373\364ng-Th\345o V\365 of IBM + Written by Mimi Phuong-Thao Vo of IBM and John Gilmore of Cygnus Support. */ /********************** FILE HEADER **********************/ diff --git a/contrib/binutils/include/demangle.h b/contrib/binutils/include/demangle.h index af29467..49f23e5 100644 --- a/contrib/binutils/include/demangle.h +++ b/contrib/binutils/include/demangle.h @@ -1,21 +1,30 @@ /* Defs for interface to demanglers. Copyright 1992, 1993, 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, - 2003, 2004 Free Software Foundation, Inc. + 2003, 2004, 2005, 2007 Free Software Foundation, Inc. - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2, or (at your option) - any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin Street - Fifth Floor, - Boston, MA 02110-1301, USA. */ + This program is free software; you can redistribute it and/or + modify it under the terms of the GNU Library General Public License + as published by the Free Software Foundation; either version 2, or + (at your option) any later version. + + In addition to the permissions in the GNU Library General Public + License, the Free Software Foundation gives you unlimited + permission to link the compiled version of this file into + combinations with other programs, and to distribute those + combinations without any restriction coming from the use of this + file. (The Library Public License restrictions do apply in other + respects; for example, they cover modification of the file, and + distribution when not linked into a combined executable.) + + This program is distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Library General Public License for more details. + + You should have received a copy of the GNU Library General Public + License along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ #if !defined (DEMANGLE_H) @@ -131,13 +140,25 @@ cplus_demangle_set_style (enum demangling_styles style); extern enum demangling_styles cplus_demangle_name_to_style (const char *name); -/* V3 ABI demangling entry points, defined in cp-demangle.c. */ -extern char* -cplus_demangle_v3 (const char* mangled, int options); +/* Callback typedef for allocation-less demangler interfaces. */ +typedef void (*demangle_callbackref) (const char *, size_t, void *); + +/* V3 ABI demangling entry points, defined in cp-demangle.c. Callback + variants return non-zero on success, zero on error. char* variants + return a string allocated by malloc on success, NULL on error. */ +extern int +cplus_demangle_v3_callback (const char *mangled, int options, + demangle_callbackref callback, void *opaque); extern char* -java_demangle_v3 (const char* mangled); +cplus_demangle_v3 (const char *mangled, int options); +extern int +java_demangle_v3_callback (const char *mangled, + demangle_callbackref callback, void *opaque); + +extern char* +java_demangle_v3 (const char *mangled); enum gnu_v3_ctor_kinds { gnu_v3_complete_object_ctor = 1, @@ -529,6 +550,25 @@ cplus_demangle_print (int options, int estimated_length, size_t *p_allocated_size); +/* This function takes a struct demangle_component tree and passes back + a demangled string in one or more calls to a callback function. + The first argument is DMGL_* options. The second is the tree to + demangle. The third is a pointer to a callback function; on each call + this receives an element of the demangled string, its length, and an + opaque value. The fourth is the opaque value passed to the callback. + The callback is called once or more to return the full demangled + string. The demangled element string is always nul-terminated, though + its length is also provided for convenience. In contrast to + cplus_demangle_print(), this function does not allocate heap memory + to grow output strings (except perhaps where alloca() is implemented + by malloc()), and so is normally safe for use where the heap has been + corrupted. On success, this function returns 1; on failure, 0. */ + +extern int +cplus_demangle_print_callback (int options, + const struct demangle_component *tree, + demangle_callbackref callback, void *opaque); + #ifdef __cplusplus } #endif /* __cplusplus */ diff --git a/contrib/binutils/include/dis-asm.h b/contrib/binutils/include/dis-asm.h index bdbf9f8..40afe17 100644 --- a/contrib/binutils/include/dis-asm.h +++ b/contrib/binutils/include/dis-asm.h @@ -1,6 +1,6 @@ /* Interface between the opcode library and its callers. - Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005 + Copyright 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc. This program is free software; you can redistribute it and/or modify @@ -35,9 +35,10 @@ extern "C" { #include <stdio.h> #include "bfd.h" -typedef int (*fprintf_ftype) (void *, const char*, ...) ATTRIBUTE_FPTR_PRINTF_2; + typedef int (*fprintf_ftype) (void *, const char*, ...) /*ATTRIBUTE_FPTR_PRINTF_2*/; -enum dis_insn_type { +enum dis_insn_type +{ dis_noninsn, /* Not a valid instruction */ dis_nonbranch, /* Not a branch instruction */ dis_branch, /* Unconditional branch */ @@ -58,7 +59,8 @@ enum dis_insn_type { It must be initialized before it is first passed; this can be done by hand, or using one of the initialization macros below. */ -typedef struct disassemble_info { +typedef struct disassemble_info +{ fprintf_ftype fprintf_func; void *stream; void *application_data; @@ -94,6 +96,12 @@ typedef struct disassemble_info { /* Number of symbols in array. */ int num_symbols; + /* Symbol table provided for targets that want to look at it. This is + used on Arm to find mapping symbols and determine Arm/Thumb code. */ + asymbol **symtab; + int symtab_pos; + int symtab_size; + /* For use by the disassembler. The top 16 bits are reserved for public use (and are documented here). The bottom 16 bits are for the internal use of the disassembler. */ @@ -201,59 +209,66 @@ typedef struct disassemble_info { target address. Return number of octets processed. */ typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *); -extern int print_insn_big_mips (bfd_vma, disassemble_info *); -extern int print_insn_little_mips (bfd_vma, disassemble_info *); -extern int print_insn_i386 (bfd_vma, disassemble_info *); -extern int print_insn_i386_att (bfd_vma, disassemble_info *); -extern int print_insn_i386_intel (bfd_vma, disassemble_info *); -extern int print_insn_ia64 (bfd_vma, disassemble_info *); -extern int print_insn_i370 (bfd_vma, disassemble_info *); -extern int print_insn_m68hc11 (bfd_vma, disassemble_info *); -extern int print_insn_m68hc12 (bfd_vma, disassemble_info *); -extern int print_insn_m68k (bfd_vma, disassemble_info *); -extern int print_insn_z80 (bfd_vma, disassemble_info *); -extern int print_insn_z8001 (bfd_vma, disassemble_info *); -extern int print_insn_z8002 (bfd_vma, disassemble_info *); -extern int print_insn_h8300 (bfd_vma, disassemble_info *); -extern int print_insn_h8300h (bfd_vma, disassemble_info *); -extern int print_insn_h8300s (bfd_vma, disassemble_info *); -extern int print_insn_h8500 (bfd_vma, disassemble_info *); extern int print_insn_alpha (bfd_vma, disassemble_info *); -extern int print_insn_big_arm (bfd_vma, disassemble_info *); -extern int print_insn_little_arm (bfd_vma, disassemble_info *); -extern int print_insn_sparc (bfd_vma, disassemble_info *); extern int print_insn_avr (bfd_vma, disassemble_info *); extern int print_insn_bfin (bfd_vma, disassemble_info *); +extern int print_insn_big_arm (bfd_vma, disassemble_info *); +extern int print_insn_big_mips (bfd_vma, disassemble_info *); +extern int print_insn_big_or32 (bfd_vma, disassemble_info *); +extern int print_insn_big_powerpc (bfd_vma, disassemble_info *); +extern int print_insn_big_score (bfd_vma, disassemble_info *); +extern int print_insn_cr16 (bfd_vma, disassemble_info *); +extern int print_insn_crx (bfd_vma, disassemble_info *); extern int print_insn_d10v (bfd_vma, disassemble_info *); extern int print_insn_d30v (bfd_vma, disassemble_info *); extern int print_insn_dlx (bfd_vma, disassemble_info *); extern int print_insn_fr30 (bfd_vma, disassemble_info *); +extern int print_insn_frv (bfd_vma, disassemble_info *); +extern int print_insn_h8300 (bfd_vma, disassemble_info *); +extern int print_insn_h8300h (bfd_vma, disassemble_info *); +extern int print_insn_h8300s (bfd_vma, disassemble_info *); +extern int print_insn_h8500 (bfd_vma, disassemble_info *); extern int print_insn_hppa (bfd_vma, disassemble_info *); +extern int print_insn_i370 (bfd_vma, disassemble_info *); +extern int print_insn_i386 (bfd_vma, disassemble_info *); +extern int print_insn_i386_att (bfd_vma, disassemble_info *); +extern int print_insn_i386_intel (bfd_vma, disassemble_info *); extern int print_insn_i860 (bfd_vma, disassemble_info *); extern int print_insn_i960 (bfd_vma, disassemble_info *); +extern int print_insn_ia64 (bfd_vma, disassemble_info *); extern int print_insn_ip2k (bfd_vma, disassemble_info *); +extern int print_insn_iq2000 (bfd_vma, disassemble_info *); +extern int print_insn_little_arm (bfd_vma, disassemble_info *); +extern int print_insn_little_mips (bfd_vma, disassemble_info *); +extern int print_insn_little_or32 (bfd_vma, disassemble_info *); +extern int print_insn_little_powerpc (bfd_vma, disassemble_info *); +extern int print_insn_little_score (bfd_vma, disassemble_info *); +extern int print_insn_m32c (bfd_vma, disassemble_info *); extern int print_insn_m32r (bfd_vma, disassemble_info *); +extern int print_insn_m68hc11 (bfd_vma, disassemble_info *); +extern int print_insn_m68hc12 (bfd_vma, disassemble_info *); +extern int print_insn_m68k (bfd_vma, disassemble_info *); extern int print_insn_m88k (bfd_vma, disassemble_info *); -extern int print_insn_maxq_little (bfd_vma, disassemble_info *); extern int print_insn_maxq_big (bfd_vma, disassemble_info *); +extern int print_insn_maxq_little (bfd_vma, disassemble_info *); extern int print_insn_mcore (bfd_vma, disassemble_info *); +extern int print_insn_mep (bfd_vma, disassemble_info *); extern int print_insn_mmix (bfd_vma, disassemble_info *); extern int print_insn_mn10200 (bfd_vma, disassemble_info *); extern int print_insn_mn10300 (bfd_vma, disassemble_info *); -extern int print_insn_mt (bfd_vma, disassemble_info *); extern int print_insn_msp430 (bfd_vma, disassemble_info *); +extern int print_insn_mt (bfd_vma, disassemble_info *); extern int print_insn_ns32k (bfd_vma, disassemble_info *); -extern int print_insn_crx (bfd_vma, disassemble_info *); extern int print_insn_openrisc (bfd_vma, disassemble_info *); -extern int print_insn_big_or32 (bfd_vma, disassemble_info *); -extern int print_insn_little_or32 (bfd_vma, disassemble_info *); extern int print_insn_pdp11 (bfd_vma, disassemble_info *); extern int print_insn_pj (bfd_vma, disassemble_info *); -extern int print_insn_big_powerpc (bfd_vma, disassemble_info *); -extern int print_insn_little_powerpc (bfd_vma, disassemble_info *); extern int print_insn_rs6000 (bfd_vma, disassemble_info *); extern int print_insn_s390 (bfd_vma, disassemble_info *); extern int print_insn_sh (bfd_vma, disassemble_info *); +extern int print_insn_sh64 (bfd_vma, disassemble_info *); +extern int print_insn_sh64x_media (bfd_vma, disassemble_info *); +extern int print_insn_sparc (bfd_vma, disassemble_info *); +extern int print_insn_spu (bfd_vma, disassemble_info *); extern int print_insn_tic30 (bfd_vma, disassemble_info *); extern int print_insn_tic4x (bfd_vma, disassemble_info *); extern int print_insn_tic54x (bfd_vma, disassemble_info *); @@ -261,25 +276,24 @@ extern int print_insn_tic80 (bfd_vma, disassemble_info *); extern int print_insn_v850 (bfd_vma, disassemble_info *); extern int print_insn_vax (bfd_vma, disassemble_info *); extern int print_insn_w65 (bfd_vma, disassemble_info *); +extern int print_insn_xc16x (bfd_vma, disassemble_info *); extern int print_insn_xstormy16 (bfd_vma, disassemble_info *); extern int print_insn_xtensa (bfd_vma, disassemble_info *); -extern int print_insn_sh64 (bfd_vma, disassemble_info *); -extern int print_insn_sh64x_media (bfd_vma, disassemble_info *); -extern int print_insn_frv (bfd_vma, disassemble_info *); -extern int print_insn_iq2000 (bfd_vma, disassemble_info *); -extern int print_insn_xc16x (bfd_vma, disassemble_info *); -extern int print_insn_m32c (bfd_vma, disassemble_info *); +extern int print_insn_z80 (bfd_vma, disassemble_info *); +extern int print_insn_z8001 (bfd_vma, disassemble_info *); +extern int print_insn_z8002 (bfd_vma, disassemble_info *); extern disassembler_ftype arc_get_disassembler (void *); extern disassembler_ftype cris_get_disassembler (bfd *); +extern void print_i386_disassembler_options (FILE *); extern void print_mips_disassembler_options (FILE *); extern void print_ppc_disassembler_options (FILE *); extern void print_arm_disassembler_options (FILE *); extern void parse_arm_disassembler_option (char *); -extern int get_arm_regname_num_options (void); -extern int set_arm_regname_option (int); -extern int get_arm_regnames (int, const char **, const char **, const char *const **); +extern int get_arm_regname_num_options (void); +extern int set_arm_regname_option (int); +extern int get_arm_regnames (int, const char **, const char **, const char *const **); extern bfd_boolean arm_symbol_is_valid (asymbol *, struct disassemble_info *); /* Fetch the disassembler for a given BFD, if that support is available. */ diff --git a/contrib/binutils/include/elf/ChangeLog b/contrib/binutils/include/elf/ChangeLog index 48ce81c..ba08331 100644 --- a/contrib/binutils/include/elf/ChangeLog +++ b/contrib/binutils/include/elf/ChangeLog @@ -1,3 +1,169 @@ +2007-06-29 Joseph Myers <joseph@codesourcery.com> + + * ppc.h (Tag_GNU_Power_ABI_FP): Define. + +2007-06-29 Joseph Myers <joseph@codesourcery.com> + + * mips.h (Tag_GNU_MIPS_ABI_FP): Define. + +2007-06-29 Joseph Myers <joseph@codesourcery.com> + + * arm.h (elf32_arm_add_eabi_attr_int, + elf32_arm_add_eabi_attr_string, elf32_arm_add_eabi_attr_compat, + elf32_arm_get_eabi_attr_int, elf32_arm_set_eabi_attr_contents, + elf32_arm_eabi_attr_size, Tag_NULL, Tag_File, Tag_Section, + Tag_Symbol, Tag_compatibility): Remove. + * common.h (SHT_GNU_ATTRIBUTES): Define. + +2007-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> + + * common.h (EM_CR16): New entry for CR16 cpu. + * cr16.h: New file. + +2007-06-11 Sterling Augustine <sterling@tensilica.com> + Bob Wilson <bob.wilson@acm.org> + + * xtensa.h (XTENSA_PROP_INSN_NO_TRANSFORM): Renamed to... + (XTENSA_PROP_NO_TRANSFORM): ...this. + +2007-05-18 Caroline Tice <ctice@apple.com> + + * dwarf2.h: (enum dwarf_location_atom): Add new DW_OP, + DW_OP_GNU_uninit. + +2007-05-12 Alan Modra <amodra@bigpond.net.au> + + * spu.h (R_SPU_ADDR16X): Define. + (R_SPU_PPU32, R_SPU_PPU64): Renumber. + +2007-05-11 Alan Modra <amodra@bigpond.net.au> + + * spu.h (R_SPU_PPU32, R_SPU_PPU64): Define. + +2007-05-02 Alan Modra <amodra@bigpond.net.au> + + * internal.h (ELF_IS_SECTION_IN_SEGMENT): Check both file offset + and vma for appropriate sections. + +2007-04-26 Jan Beulich <jbeulich@novell.com> + + * common.h (DT_ENCODING): Correct value (back to spec mandated + value). + +2007-03-08 Alan Modra <amodra@bigpond.net.au> + + * v850.h (V850_OTHER_TDA_BYTE): Delete. + (V850_OTHER_SDA, V850_OTHER_ZDA, V850_OTHER_TDA): Assign bits + that don't clash with visibility bits. + +2007-03-07 Alan Modra <amodra@bigpond.net.au> + + * common.h (ELF_ST_VISIBILITY): Comment typo fix. + +2007-02-05 Dave Brolley <brolley@redhat.com> + Richard Sandiford <rsandifo@redhat.com> + Richard Henderson <rth@redhat.com> + DJ Delorie <dj@redhat.com> + Ben Elliston <bje@redhat.com> + + * mep.h: New file. + * common.h (EM_CYGNUS_MEP): Define. + +2007-02-15 Dave Brolley <brolley@redhat.com> + + From Graydon Hoare <graydon@redhat.com>: + * common.h (STT_RELC, STT_SRELC, R_RELC): New macros. + +2007-01-08 Kazu Hirata <kazu@codesourcery.com> + + * m68k.h (EF_M68K_FIDO): New. + (EF_M68K_ARCH_MASK): OR EF_M68K_FIDO. + (EF_M68K_CPU32_FIDO_A, EF_M68K_CPU32_MASK): Remove. + +2006-12-25 Kazu Hirata <kazu@codesourcery.com> + + * m68k.h (EF_M68K_CPU32_FIDO_A, EF_M68K_CPU32_MASK): New. + +2006-12-19 Kazu Hirata <kazu@codesourcery.com> + + * m68k.h (EF_M68K_ARCH_MASK): New. + +2006-12-19 Nathan Sidwell <nathan@codesourcery.com> + + * internal.h (struct elf_segment_map): Add p_vaddr_offset field. + +2006-12-07 Kazu Hirata <kazu@codesourcery.com> + + * m68k.h (EF_M68K_ISA_MASK, EF_M68K_ISA_A_NODIV, + EF_M68K_ISA_A, EF_M68K_ISA_A_PLUS, EF_M68K_ISA_B_NOUSP, + EF_M68K_ISA_B, EF_M68K_ISA_C, EF_M68K_MAC_MASK, EF_M68K_MAC, + EF_M68K_EMAC, EF_M68K_EMAC_B, EF_M68K_FLOAT): Rename to + EF_M68K_CF_ISA_MASK, EF_M68K_CF_ISA_A_NODIV, EF_M68K_CF_ISA_A, + EF_M68K_CF_ISA_A_PLUS, EF_M68K_CF_ISA_B_NOUSP, + EF_M68K_CF_ISA_B, EF_M68K_CF_ISA_C, EF_M68K_CF_MAC_MASK, + EF_M68K_CF_MAC, EF_M68K_CF_EMAC, EF_M68K_CF_EMAC_B, + EF_M68K_CF_FLOAT, respectively. + +2006-12-05 Michael Tautschnig <tautschn@model.in.tum.de> + Nick Clifton <nickc@redhat.com> + + * external.h (struct Elf_External_Versym): Use ATTRIBUTE_PACKED. + +2006-10-28 Richard Sandiford <richard@codesourcery.com> + + * mips.h (R_MIPS_GLOB_DAT): Define + (R_MIPS_max): Bump by 1. + +2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> + Yukishige Shibata <shibata@rd.scei.sony.co.jp> + Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> + Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> + Alan Modra <amodra@bigpond.net.au> + + * common.h (EM_SPU): Define. + * spu.h: New file. + +2006-10-19 Mei Ligang <ligang@sunnorth.com.cn> + + * score.h (EF_SCORE_PIC): Redefine EF_SCORE_PIC as 0x80000000. + (EF_SCORE_FIXDEP): Redefine EF_SCORE_FIXDEP as 0x40000000. + (EF_SCORE_HASENTRY): Delete. + +2006-09-17 Mei Ligang <ligang@sunnorth.com.cn> + + * score.h: New file. + * common.h: Add Score machine number. + +2006-07-10 Jakub Jelinek <jakub@redhat.com> + + * common.h (SHT_GNU_HASH, DT_GNU_HASH): Define. + +2006-05-31 H.J. Lu <hongjiu.lu@intel.com> + + * internal.h (ELF_SECTION_SIZE): New. + (ELF_IS_SECTION_IN_SEGMENT): Likewise. + (ELF_IS_SECTION_IN_SEGMENT_FILE): Updated. + (ELF_IS_SECTION_IN_SEGMENT_MEMORY): Likewise. + +2006-05-27 H.J. Lu <hongjiu.lu@intel.com> + + * internal.h (struct elf_segment_map): Add p_align and p_align_valid. + +2006-05-24 Carlos O'Donell <carlos@systemhalted.org> + Randolph Chung <randolph@tausq.org> + * hppa.h (R_PARISC_TLS_GD21L, R_PARISC_TLS_GD14R, R_PARISC_TLS_GDCALL, + R_PARISC_TLS_LDM21L, R_PARISC_TLS_LDM14R, R_PARISC_TLS_LDMCALL, + R_PARISC_TLS_LDO21L, R_PARISC_TLS_LDO14R, R_PARISC_TLS_DTPMOD32, + R_PARISC_TLS_DTPMOD64, R_PARISC_TLS_DTPOFF32, R_PARISC_TLS_DTPOFF64): + New TLS relocs. + (R_PARISC_TLS_LE21L, R_PARISC_TLS_LE14R, R_PARISC_TLS_IE21L, + R_PARISC_TLS_IE14R, R_PARISC_TLS_TPREL32, R_PARISC_TLS_TPREL64): + Define TLS relocs using existing equivalents. + +2006-05-24 Bjoern Haase <bjoern.m.haase@web.de> + + * avr.h: Add E_AVR_MACH_AVR6, R_AVR_LO8_LDI_GS and R_AVR_HI8_LDI_GS. + 2006-03-22 Richard Sandiford <richard@codesourcery.com> Daniel Jacobowitz <dan@codesourcery.com> Phil Edwards <phil@codesourcery.com> diff --git a/contrib/binutils/include/elf/arm.h b/contrib/binutils/include/elf/arm.h index 8311c13..e701883 100644 --- a/contrib/binutils/include/elf/arm.h +++ b/contrib/binutils/include/elf/arm.h @@ -84,6 +84,19 @@ #define PF_ARM_PI 0x20000000 /* Segment is position-independent. */ #define PF_ARM_ABS 0x40000000 /* Segment must be loaded at its base address. */ +/* Values for the Tag_CPU_arch EABI attribute. */ +#define TAG_CPU_ARCH_PRE_V4 0 +#define TAG_CPU_ARCH_V4 1 +#define TAG_CPU_ARCH_V4T 2 +#define TAG_CPU_ARCH_V5T 3 +#define TAG_CPU_ARCH_V5TE 4 +#define TAG_CPU_ARCH_V5TEJ 5 +#define TAG_CPU_ARCH_V6 6 +#define TAG_CPU_ARCH_V6KZ 7 +#define TAG_CPU_ARCH_V6T2 8 +#define TAG_CPU_ARCH_V6K 9 +#define TAG_CPU_ARCH_V7 10 + /* Relocation types. */ START_RELOC_NUMBERS (elf_arm_reloc_type) @@ -169,9 +182,9 @@ START_RELOC_NUMBERS (elf_arm_reloc_type) RELOC_NUMBER (R_ARM_LDRS_SB_G0, 78) RELOC_NUMBER (R_ARM_LDRS_SB_G1, 79) RELOC_NUMBER (R_ARM_LDRS_SB_G2, 80) - RELOC_NUMBER (R_ARM_LDC_G0, 81) - RELOC_NUMBER (R_ARM_LDC_G1, 82) - RELOC_NUMBER (R_ARM_LDC_G2, 83) + RELOC_NUMBER (R_ARM_LDC_SB_G0, 81) + RELOC_NUMBER (R_ARM_LDC_SB_G1, 82) + RELOC_NUMBER (R_ARM_LDC_SB_G2, 83) RELOC_NUMBER (R_ARM_MOVW_BREL_NC, 84) RELOC_NUMBER (R_ARM_MOVT_BREL, 85) RELOC_NUMBER (R_ARM_MOVW_BREL, 86) @@ -221,26 +234,15 @@ START_RELOC_NUMBERS (elf_arm_reloc_type) FAKE_RELOC (R_ARM_GOT32, R_ARM_GOT_BREL) /* 32 bit GOT entry. */ FAKE_RELOC (R_ARM_ROSEGREL32, R_ARM_SBREL31) /* ??? */ FAKE_RELOC (R_ARM_AMP_VCALL9, R_ARM_BREL_ADJ) /* Thumb-something. Not used. */ - FAKE_RELOC (R_ARM_PC13, R_ARM_LDR_PC_G0) /* Unclear whether meaning is different. */ END_RELOC_NUMBERS (R_ARM_max) #ifdef BFD_ARCH_SIZE -/* Routines for manipulating EABI object attributes. */ -void elf32_arm_add_eabi_attr_int (bfd *, int, unsigned int); -void elf32_arm_add_eabi_attr_string (bfd *, int, const char *); -void elf32_arm_add_eabi_attr_compat (bfd *, unsigned int, const char *); -int elf32_arm_get_eabi_attr_int (bfd *, int); - -void elf32_arm_set_eabi_attr_contents (bfd *, bfd_byte *, bfd_vma); -bfd_vma elf32_arm_eabi_attr_size (bfd *); +/* EABI object attributes. */ enum { - Tag_NULL, - Tag_File, - Tag_Section, - Tag_Symbol, - Tag_CPU_raw_name, + /* 0-3 are generic. */ + Tag_CPU_raw_name = 4, Tag_CPU_name, Tag_CPU_arch, Tag_CPU_arch_profile, @@ -268,7 +270,7 @@ enum Tag_ABI_WMMX_args, Tag_ABI_optimization_goals, Tag_ABI_FP_optimization_goals, - Tag_compatibility, + /* 32 is generic. */ }; #endif diff --git a/contrib/binutils/include/elf/avr.h b/contrib/binutils/include/elf/avr.h index f160438..d2ffbe0 100644 --- a/contrib/binutils/include/elf/avr.h +++ b/contrib/binutils/include/elf/avr.h @@ -1,5 +1,5 @@ /* AVR ELF support for BFD. - Copyright 1999, 2000, 2004 Free Software Foundation, Inc. + Copyright 1999, 2000, 2004, 2006 Free Software Foundation, Inc. Contributed by Denis Chertykov <denisc@overta.ru> This file is part of BFD, the Binary File Descriptor library. @@ -35,6 +35,7 @@ #define E_AVR_MACH_AVR3 3 #define E_AVR_MACH_AVR4 4 #define E_AVR_MACH_AVR5 5 +#define E_AVR_MACH_AVR6 6 /* Relocations. */ START_RELOC_NUMBERS (elf_avr_reloc_type) @@ -62,6 +63,8 @@ START_RELOC_NUMBERS (elf_avr_reloc_type) RELOC_NUMBER (R_AVR_6_ADIW, 21) RELOC_NUMBER (R_AVR_MS8_LDI, 22) RELOC_NUMBER (R_AVR_MS8_LDI_NEG, 23) + RELOC_NUMBER (R_AVR_LO8_LDI_GS, 24) + RELOC_NUMBER (R_AVR_HI8_LDI_GS, 25) END_RELOC_NUMBERS (R_AVR_max) #endif /* _ELF_AVR_H */ diff --git a/contrib/binutils/include/elf/common.h b/contrib/binutils/include/elf/common.h index b11171b..2eb6853 100644 --- a/contrib/binutils/include/elf/common.h +++ b/contrib/binutils/include/elf/common.h @@ -1,6 +1,6 @@ /* ELF support for BFD. Copyright 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, - 2001, 2002, 2003, 2004, 2005, 2006 + 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. Written by Fred Fish @ Cygnus Support, from information published @@ -118,6 +118,7 @@ #define EM_PPC 20 /* PowerPC */ #define EM_PPC64 21 /* 64-bit PowerPC */ #define EM_S390 22 /* IBM S/390 */ +#define EM_SPU 23 /* Sony/Toshiba/IBM SPU */ #define EM_V800 36 /* NEC V800 series */ #define EM_FR20 37 /* Fujitsu FR20 */ @@ -185,6 +186,8 @@ #define EM_BLACKFIN 106 /* ADI Blackfin */ #define EM_ALTERA_NIOS2 113 /* Altera Nios II soft-core processor */ #define EM_CRX 114 /* National Semiconductor CRX */ +#define EM_CR16 115 /* National Semiconductor CompactRISC - CR16 */ +#define EM_SCORE 135 /* Sunplus Score */ /* If it is necessary to assign new unofficial EM_* values, please pick large random numbers (0x8523, 0xa7f2, etc.) to minimize the chances of collision @@ -278,6 +281,8 @@ /* NIOS magic number - no EABI available. */ #define EM_NIOS32 0xFEBB +#define EM_CYGNUS_MEP 0xF00D /* Toshiba MeP */ + /* See the above comment before you add a new EM_* value here. */ /* Values for e_version. */ @@ -338,6 +343,8 @@ #define SHT_LOOS 0x60000000 /* First of OS specific semantics */ #define SHT_HIOS 0x6fffffff /* Last of OS specific semantics */ +#define SHT_GNU_ATTRIBUTES 0x6ffffff5 /* Object attributes */ +#define SHT_GNU_HASH 0x6ffffff6 /* GNU style symbol hash table */ #define SHT_GNU_LIBLIST 0x6ffffff7 /* List of prelink dependencies */ /* The next three section types are defined by Solaris, and are named @@ -445,7 +452,7 @@ #define ELF64_ST_INFO ELF_ST_INFO /* This macro disassembles and assembles a symbol's visibility into - the st_other field. The STV_ defines specificy the actual visibility. */ + the st_other field. The STV_ defines specify the actual visibility. */ #define ELF_ST_VISIBILITY(v) ((v) & 0x3) /* The remaining bits in the st_other field are not currently used. @@ -472,6 +479,8 @@ #define STT_FILE 4 /* Symbol gives a file name */ #define STT_COMMON 5 /* An uninitialised common block */ #define STT_TLS 6 /* Thread local data object */ +#define STT_RELC 8 /* Complex relocation expression */ +#define STT_SRELC 9 /* Signed Complex relocation expression */ #define STT_LOOS 10 /* OS-specific semantics */ #define STT_HIOS 12 /* OS-specific semantics */ #define STT_LOPROC 13 /* Application-specific semantics */ @@ -543,7 +552,7 @@ #define DT_FINI_ARRAYSZ 28 #define DT_RUNPATH 29 #define DT_FLAGS 30 -#define DT_ENCODING 31 +#define DT_ENCODING 32 #define DT_PREINIT_ARRAY 32 #define DT_PREINIT_ARRAYSZ 33 @@ -577,6 +586,7 @@ #define DT_VALRNGHI 0x6ffffdff #define DT_ADDRRNGLO 0x6ffffe00 +#define DT_GNU_HASH 0x6ffffef5 #define DT_TLSDESC_PLT 0x6ffffef6 #define DT_TLSDESC_GOT 0x6ffffef7 #define DT_GNU_CONFLICT 0x6ffffef8 diff --git a/contrib/binutils/include/elf/cr16.h b/contrib/binutils/include/elf/cr16.h new file mode 100644 index 0000000..e3f6c50 --- /dev/null +++ b/contrib/binutils/include/elf/cr16.h @@ -0,0 +1,56 @@ +/* CR16 ELF support for BFD. + Copyright 2007 Free Software Foundation, Inc. + Contributed by M R Swami Reddy. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_CR16_H +#define _ELF_CR16_H + +#include "elf/reloc-macros.h" + +/* Creating indices for reloc_map_index array. */ +START_RELOC_NUMBERS(elf_cr16_reloc_type) + RELOC_NUMBER (R_CR16_NONE, 0) + RELOC_NUMBER (R_CR16_NUM8, 1) + RELOC_NUMBER (R_CR16_NUM16, 2) + RELOC_NUMBER (R_CR16_NUM32, 3) + RELOC_NUMBER (R_CR16_NUM32a, 4) + RELOC_NUMBER (R_CR16_REGREL4, 5) + RELOC_NUMBER (R_CR16_REGREL4a, 6) + RELOC_NUMBER (R_CR16_REGREL14, 7) + RELOC_NUMBER (R_CR16_REGREL14a, 8) + RELOC_NUMBER (R_CR16_REGREL16, 9) + RELOC_NUMBER (R_CR16_REGREL20, 10) + RELOC_NUMBER (R_CR16_REGREL20a, 11) + RELOC_NUMBER (R_CR16_ABS20, 12) + RELOC_NUMBER (R_CR16_ABS24, 13) + RELOC_NUMBER (R_CR16_IMM4, 14) + RELOC_NUMBER (R_CR16_IMM8, 15) + RELOC_NUMBER (R_CR16_IMM16, 16) + RELOC_NUMBER (R_CR16_IMM20, 17) + RELOC_NUMBER (R_CR16_IMM24, 18) + RELOC_NUMBER (R_CR16_IMM32, 19) + RELOC_NUMBER (R_CR16_IMM32a, 20) + RELOC_NUMBER (R_CR16_DISP4, 21) + RELOC_NUMBER (R_CR16_DISP8, 22) + RELOC_NUMBER (R_CR16_DISP16, 23) + RELOC_NUMBER (R_CR16_DISP24, 24) + RELOC_NUMBER (R_CR16_DISP24a, 25) +END_RELOC_NUMBERS(R_CR16_MAX) + +#endif /* _ELF_CR16_H */ diff --git a/contrib/binutils/include/elf/dwarf2.h b/contrib/binutils/include/elf/dwarf2.h index 264952a..2683f51 100644 --- a/contrib/binutils/include/elf/dwarf2.h +++ b/contrib/binutils/include/elf/dwarf2.h @@ -540,6 +540,7 @@ enum dwarf_location_atom DW_OP_bit_piece = 0x9d, /* GNU extensions. */ DW_OP_GNU_push_tls_address = 0xe0, + DW_OP_GNU_uninit = 0xf0, /* HP extensions. */ DW_OP_HP_unknown = 0xe0, /* Ouch, the same as GNU_push_tls_address. */ DW_OP_HP_is_value = 0xe1, diff --git a/contrib/binutils/include/elf/external.h b/contrib/binutils/include/elf/external.h index 5985e94..21450f0 100644 --- a/contrib/binutils/include/elf/external.h +++ b/contrib/binutils/include/elf/external.h @@ -245,11 +245,7 @@ typedef struct { typedef struct { unsigned char vs_vers[2]; -} -#ifdef __GNUC__ - __attribute__ ((packed)) -#endif - Elf_External_Versym; +} ATTRIBUTE_PACKED Elf_External_Versym; /* Structure for syminfo section. */ typedef struct diff --git a/contrib/binutils/include/elf/hppa.h b/contrib/binutils/include/elf/hppa.h index 15be2d5..c9b3200 100644 --- a/contrib/binutils/include/elf/hppa.h +++ b/contrib/binutils/include/elf/hppa.h @@ -1,22 +1,22 @@ /* HPPA ELF support for BFD. - Copyright 1993, 1994, 1995, 1998, 1999, 2000, 2005 + Copyright 1993, 1994, 1995, 1998, 1999, 2000, 2005, 2006 Free Software Foundation, Inc. -This file is part of BFD, the Binary File Descriptor library. + This file is part of BFD, the Binary File Descriptor library. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ /* This file holds definitions specific to the HPPA ELF ABI. Note that most of this is not actually implemented by BFD. */ @@ -80,10 +80,10 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. /* These are strictly for compatibility with the older elf32-hppa implementation. Hopefully we can eliminate them in the future. */ /* Optional section holding argument location/relocation info. */ -#define SHT_PARISC_SYMEXTN SHT_LOPROC+8 +#define SHT_PARISC_SYMEXTN SHT_LOPROC + 8 /* Option section for linker stubs. */ -#define SHT_PARISC_STUBS SHT_LOPROC+9 +#define SHT_PARISC_STUBS SHT_LOPROC + 9 /* Processor specific section flags. */ @@ -480,8 +480,28 @@ RELOC_NUMBER (R_PARISC_LTOFF_TP16DF, 231) RELOC_NUMBER (R_PARISC_GNU_VTENTRY, 232) RELOC_NUMBER (R_PARISC_GNU_VTINHERIT, 233) +RELOC_NUMBER (R_PARISC_TLS_GD21L, 234) +RELOC_NUMBER (R_PARISC_TLS_GD14R, 235) +RELOC_NUMBER (R_PARISC_TLS_GDCALL, 236) +RELOC_NUMBER (R_PARISC_TLS_LDM21L, 237) +RELOC_NUMBER (R_PARISC_TLS_LDM14R, 238) +RELOC_NUMBER (R_PARISC_TLS_LDMCALL, 239) +RELOC_NUMBER (R_PARISC_TLS_LDO21L, 240) +RELOC_NUMBER (R_PARISC_TLS_LDO14R, 241) +RELOC_NUMBER (R_PARISC_TLS_DTPMOD32, 242) +RELOC_NUMBER (R_PARISC_TLS_DTPMOD64, 243) +RELOC_NUMBER (R_PARISC_TLS_DTPOFF32, 244) +RELOC_NUMBER (R_PARISC_TLS_DTPOFF64, 245) + END_RELOC_NUMBERS (R_PARISC_UNIMPLEMENTED) +#define R_PARISC_TLS_LE21L R_PARISC_TPREL21L +#define R_PARISC_TLS_LE14R R_PARISC_TPREL14R +#define R_PARISC_TLS_IE21L R_PARISC_LTOFF_TP21L +#define R_PARISC_TLS_IE14R R_PARISC_LTOFF_TP14R +#define R_PARISC_TLS_TPREL32 R_PARISC_TPREL32 +#define R_PARISC_TLS_TPREL64 R_PARISC_TPREL64 + #ifndef RELOC_MACROS_GEN_FUNC typedef enum elf_hppa_reloc_type elf_hppa_reloc_type; #endif diff --git a/contrib/binutils/include/elf/internal.h b/contrib/binutils/include/elf/internal.h index e4eba7d..1521711 100644 --- a/contrib/binutils/include/elf/internal.h +++ b/contrib/binutils/include/elf/internal.h @@ -1,6 +1,6 @@ /* ELF support for BFD. Copyright 1991, 1992, 1993, 1994, 1995, 1997, 1998, 2000, 2001, 2002, - 2003 Free Software Foundation, Inc. + 2003, 2006, 2007 Free Software Foundation, Inc. Written by Fred Fish @ Cygnus Support, from information published in "UNIX System V Release 4, Programmers Guide: ANSI C and @@ -235,12 +235,19 @@ struct elf_segment_map unsigned long p_flags; /* Program segment physical address. */ bfd_vma p_paddr; + /* Program segment virtual address offset from section vma. */ + bfd_vma p_vaddr_offset; + /* Program segment alignment. */ + bfd_vma p_align; /* Whether the p_flags field is valid; if not, the flags are based on the section flags. */ unsigned int p_flags_valid : 1; /* Whether the p_paddr field is valid; if not, the physical address is based on the section lma values. */ unsigned int p_paddr_valid : 1; + /* Whether the p_align field is valid; if not, PT_LOAD segment + alignment is based on the default maximum page size. */ + unsigned int p_align_valid : 1; /* Whether this segment includes the file header. */ unsigned int includes_filehdr : 1; /* Whether this segment includes the program headers. */ @@ -251,29 +258,42 @@ struct elf_segment_map asection *sections[1]; }; +/* .tbss is special. It doesn't contribute memory space to normal + segments and it doesn't take file space in normal segments. */ +#define ELF_SECTION_SIZE(sec_hdr, segment) \ + (((sec_hdr->sh_flags & SHF_TLS) == 0 \ + || sec_hdr->sh_type != SHT_NOBITS \ + || segment->p_type == PT_TLS) ? sec_hdr->sh_size : 0) + +/* Decide if the given sec_hdr is in the given segment. PT_TLS segment + contains only SHF_TLS sections. Only PT_LOAD and PT_TLS segments + can contain SHF_TLS sections. */ +#define ELF_IS_SECTION_IN_SEGMENT(sec_hdr, segment) \ + (((((sec_hdr->sh_flags & SHF_TLS) != 0) \ + && (segment->p_type == PT_TLS \ + || segment->p_type == PT_LOAD)) \ + || ((sec_hdr->sh_flags & SHF_TLS) == 0 \ + && segment->p_type != PT_TLS)) \ + /* Any section besides one of type SHT_NOBITS must have a file \ + offset within the segment. */ \ + && (sec_hdr->sh_type == SHT_NOBITS \ + || ((bfd_vma) sec_hdr->sh_offset >= segment->p_offset \ + && (sec_hdr->sh_offset + ELF_SECTION_SIZE(sec_hdr, segment) \ + <= segment->p_offset + segment->p_filesz))) \ + /* SHF_ALLOC sections must have VMAs within the segment. */ \ + && ((sec_hdr->sh_flags & SHF_ALLOC) == 0 \ + || (sec_hdr->sh_addr >= segment->p_vaddr \ + && (sec_hdr->sh_addr + ELF_SECTION_SIZE(sec_hdr, segment) \ + <= segment->p_vaddr + segment->p_memsz)))) + /* Decide if the given sec_hdr is in the given segment in file. */ #define ELF_IS_SECTION_IN_SEGMENT_FILE(sec_hdr, segment) \ (sec_hdr->sh_size > 0 \ - /* PT_TLS segment contains only SHF_TLS sections. */ \ - && (segment->p_type != PT_TLS \ - || (sec_hdr->sh_flags & SHF_TLS) != 0) \ - /* Compare allocated sec_hdrs by VMA, unallocated sec_hdrs \ - by file offset. */ \ - && (sec_hdr->sh_flags & SHF_ALLOC \ - ? (sec_hdr->sh_addr >= segment->p_vaddr \ - && sec_hdr->sh_addr + sec_hdr->sh_size \ - <= segment->p_vaddr + segment->p_memsz) \ - : ((bfd_vma) sec_hdr->sh_offset >= segment->p_offset \ - && (sec_hdr->sh_offset + sec_hdr->sh_size \ - <= segment->p_offset + segment->p_filesz)))) + && ELF_IS_SECTION_IN_SEGMENT (sec_hdr, segment)) /* Decide if the given sec_hdr is in the given segment in memory. */ #define ELF_IS_SECTION_IN_SEGMENT_MEMORY(sec_hdr, segment) \ - (ELF_IS_SECTION_IN_SEGMENT_FILE (sec_hdr, segment) \ - /* .tbss is special. It doesn't contribute memory space to \ - normal segments. */ \ - && (!((sec_hdr->sh_flags & SHF_TLS) != 0 \ - && sec_hdr->sh_type == SHT_NOBITS) \ - || segment->p_type == PT_TLS)) + (ELF_SECTION_SIZE(sec_hdr, segment) > 0 \ + && ELF_IS_SECTION_IN_SEGMENT (sec_hdr, segment)) #endif /* _ELF_INTERNAL_H */ diff --git a/contrib/binutils/include/elf/m68k.h b/contrib/binutils/include/elf/m68k.h index 08d0c44..a9f2203 100644 --- a/contrib/binutils/include/elf/m68k.h +++ b/contrib/binutils/include/elf/m68k.h @@ -52,24 +52,30 @@ START_RELOC_NUMBERS (elf_m68k_reloc_type) RELOC_NUMBER (R_68K_GNU_VTENTRY, 24) END_RELOC_NUMBERS (R_68K_max) +/* We use the top 24 bits to encode information about the + architecture variant. */ #define EF_M68K_CPU32 0x00810000 #define EF_M68K_M68000 0x01000000 #define EF_M68K_CFV4E 0x00008000 +#define EF_M68K_FIDO 0x02000000 +#define EF_M68K_ARCH_MASK \ + (EF_M68K_M68000 | EF_M68K_CPU32 | EF_M68K_CFV4E | EF_M68K_FIDO) /* We use the bottom 8 bits to encode information about the - coldfire variant. */ -#define EF_M68K_ISA_MASK 0x0F /* Which ISA */ -#define EF_M68K_ISA_A_NODIV 0x01 /* ISA A except for div */ -#define EF_M68K_ISA_A 0x02 -#define EF_M68K_ISA_A_PLUS 0x03 -#define EF_M68K_ISA_B_NOUSP 0x04 /* ISA_B except for USP */ -#define EF_M68K_ISA_B 0x05 -#define EF_M68K_ISA_C 0x06 -#define EF_M68K_MAC_MASK 0x30 -#define EF_M68K_MAC 0x10 /* MAC */ -#define EF_M68K_EMAC 0x20 /* EMAC */ -#define EF_M68K_EMAC_B 0x30 /* EMAC_B */ -#define EF_M68K_FLOAT 0x40 /* Has float insns */ + coldfire variant. If we use any of these bits, the top 24 bits are + either 0 or EF_M68K_CFV4E. */ +#define EF_M68K_CF_ISA_MASK 0x0F /* Which ISA */ +#define EF_M68K_CF_ISA_A_NODIV 0x01 /* ISA A except for div */ +#define EF_M68K_CF_ISA_A 0x02 +#define EF_M68K_CF_ISA_A_PLUS 0x03 +#define EF_M68K_CF_ISA_B_NOUSP 0x04 /* ISA_B except for USP */ +#define EF_M68K_CF_ISA_B 0x05 +#define EF_M68K_CF_ISA_C 0x06 +#define EF_M68K_CF_MAC_MASK 0x30 +#define EF_M68K_CF_MAC 0x10 /* MAC */ +#define EF_M68K_CF_EMAC 0x20 /* EMAC */ +#define EF_M68K_CF_EMAC_B 0x30 /* EMAC_B */ +#define EF_M68K_CF_FLOAT 0x40 /* Has float insns */ #define EF_M68K_CF_MASK 0xFF #endif diff --git a/contrib/binutils/include/elf/mep.h b/contrib/binutils/include/elf/mep.h new file mode 100644 index 0000000..51eb8d0 --- /dev/null +++ b/contrib/binutils/include/elf/mep.h @@ -0,0 +1,84 @@ +/* Toshiba MeP ELF support for BFD. + Copyright (C) 2001, 2004, 2005 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, Inc., + 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _ELF_MEP_H +#define _ELF_MEP_H + +/* Bits in the sh_flags field of Elf32_Shdr: */ + +#define SHF_MEP_VLIW 0x10000000 /* contains vliw code */ + +/* This bit is reserved by BFD for processor specific stuff. Name + it properly so that we can easily stay consistent elsewhere. */ +#define SEC_MEP_VLIW SEC_TIC54X_BLOCK + +#include "elf/reloc-macros.h" + +/* Note: The comments in this file are used by bfd/mep-relocs.pl to + build parts of bfd/elf32-mep.c. */ + +/* Relocations. */ +START_RELOC_NUMBERS (elf_mep_reloc_type) + + /* These two must appear first so that they are not processed by bfd/mep-relocs.pl. */ + RELOC_NUMBER (R_MEP_NONE, 0) + RELOC_NUMBER (R_RELC, 1) + + RELOC_NUMBER (R_MEP_8, 2) /* 7654 3210 U */ + RELOC_NUMBER (R_MEP_16, 3) /* fedc ba98 7654 3210 U */ + RELOC_NUMBER (R_MEP_32, 4) /* vuts rqpo nmlk jihg fedc ba98 7654 3210 U */ + + RELOC_NUMBER (R_MEP_PCREL8A2, 5) /* ---- ---- 7654 321- S PC-REL */ + RELOC_NUMBER (R_MEP_PCREL12A2, 6) /* ---- ba98 7654 321- S PC-REL */ + RELOC_NUMBER (R_MEP_PCREL17A2, 7) /* ---- ---- ---- ---- gfed cba9 8765 4321 S PC-REL */ + RELOC_NUMBER (R_MEP_PCREL24A2, 8) /* ---- -765 4321 ---- nmlk jihg fedc ba98 S PC-REL */ + RELOC_NUMBER (R_MEP_PCABS24A2, 9) /* ---- -765 4321 ---- nmlk jihg fedc ba98 U */ + + RELOC_NUMBER (R_MEP_LOW16, 10) /* ---- ---- ---- ---- fedc ba98 7654 3210 U no-overflow */ + RELOC_NUMBER (R_MEP_HI16U, 11) /* ---- ---- ---- ---- vuts rqpo nmlk jihg U no-overflow */ + RELOC_NUMBER (R_MEP_HI16S, 12) /* ---- ---- ---- ---- vuts rqpo nmlk jihg S no-overflow */ + RELOC_NUMBER (R_MEP_GPREL, 13) /* ---- ---- ---- ---- fedc ba98 7654 3210 S GP-REL*/ + RELOC_NUMBER (R_MEP_TPREL, 14) /* ---- ---- ---- ---- fedc ba98 7654 3210 S TP-REL*/ + + RELOC_NUMBER (R_MEP_TPREL7, 15) /* ---- ---- -654 3210 U TP-REL */ + RELOC_NUMBER (R_MEP_TPREL7A2, 16) /* ---- ---- -654 321- U TP-REL */ + RELOC_NUMBER (R_MEP_TPREL7A4, 17) /* ---- ---- -654 32-- U TP-REL */ + + RELOC_NUMBER (R_MEP_UIMM24, 18) /* ---- ---- 7654 3210 nmlk jihg fedc ba98 U */ + RELOC_NUMBER (R_MEP_ADDR24A4, 19) /* ---- ---- 7654 32-- nmlk jihg fedc ba98 U */ + + RELOC_NUMBER (R_MEP_GNU_VTINHERIT, 20) /* ---- ---- ---- ---- U no-overflow */ + RELOC_NUMBER (R_MEP_GNU_VTENTRY, 21) /* ---- ---- ---- ---- U no-overflow */ + +END_RELOC_NUMBERS(R_MEP_max) + +#define EF_MEP_CPU_MASK 0xff000000 /* specific cpu bits */ +#define EF_MEP_CPU_MEP 0x00000000 /* generic MEP */ +#define EF_MEP_CPU_C2 0x01000000 /* MEP c2 */ +#define EF_MEP_CPU_C3 0x02000000 /* MEP c3 */ +#define EF_MEP_CPU_C4 0x04000000 /* MEP c4 */ +#define EF_MEP_CPU_H1 0x10000000 /* MEP h1 */ + +#define EF_MEP_LIBRARY 0x00000100 /* Built as a library */ + +#define EF_MEP_INDEX_MASK 0x000000ff /* Configuration index */ + +#define EF_MEP_ALL_FLAGS 0xff0001ff + +#endif /* _ELF_MEP_H */ diff --git a/contrib/binutils/include/elf/mips.h b/contrib/binutils/include/elf/mips.h index d099bb8..ab1cfac 100644 --- a/contrib/binutils/include/elf/mips.h +++ b/contrib/binutils/include/elf/mips.h @@ -87,7 +87,8 @@ START_RELOC_NUMBERS (elf_mips_reloc_type) RELOC_NUMBER (R_MIPS_TLS_TPREL64, 48) RELOC_NUMBER (R_MIPS_TLS_TPREL_HI16, 49) RELOC_NUMBER (R_MIPS_TLS_TPREL_LO16, 50) - FAKE_RELOC (R_MIPS_max, 51) + RELOC_NUMBER (R_MIPS_GLOB_DAT, 51) + FAKE_RELOC (R_MIPS_max, 52) /* These relocs are used for the mips16. */ FAKE_RELOC (R_MIPS16_min, 100) RELOC_NUMBER (R_MIPS16_26, 100) @@ -1006,4 +1007,15 @@ extern void bfd_mips_elf64_swap_reginfo_out #define OHWA0_R4KEOP_CLEAN 0x00000002 +/* Object attribute tags. */ +enum +{ + /* 0-3 are generic. */ + Tag_GNU_MIPS_ABI_FP = 4, /* Value 1 for hard-float -mdouble-float, 2 + for hard-float -msingle-float, 3 for + soft-float; 0 for not tagged or not + using any ABIs affected by the + differences. */ +}; + #endif /* _ELF_MIPS_H */ diff --git a/contrib/binutils/include/elf/ppc.h b/contrib/binutils/include/elf/ppc.h index ca50352..fe48814 100644 --- a/contrib/binutils/include/elf/ppc.h +++ b/contrib/binutils/include/elf/ppc.h @@ -171,4 +171,15 @@ END_RELOC_NUMBERS (R_PPC_max) builds when those objects \ are not to be furhter \ relocated. */ + +/* Object attribute tags. */ +enum +{ + /* 0-3 are generic. */ + Tag_GNU_Power_ABI_FP = 4, /* Value 1 for hard-float, 2 for + soft-float; 0 for not tagged or not + using any ABIs affected by the + differences. */ +}; + #endif /* _ELF_PPC_H */ diff --git a/contrib/binutils/include/elf/reloc-macros.h b/contrib/binutils/include/elf/reloc-macros.h index 51e86b5..a67419d 100644 --- a/contrib/binutils/include/elf/reloc-macros.h +++ b/contrib/binutils/include/elf/reloc-macros.h @@ -98,4 +98,4 @@ name (unsigned long rtype) \ #endif -#endif /* RELOC_MACROS_H */ +#endif /* _RELOC_MACROS_H */ diff --git a/contrib/binutils/include/elf/score.h b/contrib/binutils/include/elf/score.h new file mode 100644 index 0000000..ec3b32f --- /dev/null +++ b/contrib/binutils/include/elf/score.h @@ -0,0 +1,123 @@ +/* Score ELF support for BFD. + Copyright 2006 Free Software Foundation, Inc. + Contributed by + Mei Ligang (ligang@sunnorth.com.cn) + Pei-Lin Tsai (pltsai@sunplus.com) + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_SCORE_H +#define _ELF_SCORE_H + +#include "elf/reloc-macros.h" + +#define SCORE_SIMULATOR_ACTIVE 1 +#define OPC_PTMASK 0xc0000000 /* Parity-bit Mask. */ +#define OPC16_PTMASK 0x00008000 +/* The parity-bit denotes. */ +#define OPC_32 0xc0000000 /* Denotes 32b instruction, (default). */ +#define OPC_16 0x00000000 /* Denotes 16b instruction. */ +#define OPC_PE 0x8000 /* Denotes parallel-execution instructions. */ +#define GP_DISP_LABEL "_gp_disp" + +/* Processor specific flags for the ELF header e_flags field: */ + +/* File contains position independent code. */ +#define EF_SCORE_PIC 0x80000000 + +/* Fix data dependency. */ +#define EF_SCORE_FIXDEP 0x40000000 + +/* Defined and allocated common symbol. Value is virtual address. If + relocated, alignment must be preserved. */ +#define SHN_SCORE_TEXT 0xff01 +#define SHN_SCORE_DATA 0xff02 +/* Small common symbol. */ +#define SHN_SCORE_SCOMMON 0xff03 + +/* Processor specific section flags. */ + +/* This section must be in the global data area. */ +#define SHF_SCORE_GPREL 0x10000000 + +/* This section should be merged. */ +#define SHF_SCORE_MERGE 0x20000000 + +/* This section contains address data of size implied by section + element size. */ +#define SHF_SCORE_ADDR 0x40000000 + +/* This section contains string data. */ +#define SHF_SCORE_STRING 0x80000000 + +/* This section may not be stripped. */ +#define SHF_SCORE_NOSTRIP 0x08000000 + +/* This section is local to threads. */ +#define SHF_SCORE_LOCAL 0x04000000 + +/* Linker should generate implicit weak names for this section. */ +#define SHF_SCORE_NAMES 0x02000000 + +/* Section contais text/data which may be replicated in other sections. + Linker should retain only one copy. */ +#define SHF_SCORE_NODUPES 0x01000000 + +/* Processor specific dynamic array tags. */ + +/* Base address of the segment. */ +#define DT_SCORE_BASE_ADDRESS 0x70000001 +/* Number of local global offset table entries. */ +#define DT_SCORE_LOCAL_GOTNO 0x70000002 +/* Number of entries in the .dynsym section. */ +#define DT_SCORE_SYMTABNO 0x70000003 +/* Index of first dynamic symbol in global offset table. */ +#define DT_SCORE_GOTSYM 0x70000004 +/* Index of first external dynamic symbol not referenced locally. */ +#define DT_SCORE_UNREFEXTNO 0x70000005 +/* Number of page table entries in global offset table. */ +#define DT_SCORE_HIPAGENO 0x70000006 + + +/* Processor specific section types. */ + + +/* Relocation types. */ +START_RELOC_NUMBERS (elf_score_reloc_type) + RELOC_NUMBER (R_SCORE_NONE, 0) + RELOC_NUMBER (R_SCORE_HI16, 1) + RELOC_NUMBER (R_SCORE_LO16, 2) + RELOC_NUMBER (R_SCORE_DUMMY1, 3) + RELOC_NUMBER (R_SCORE_24, 4) + RELOC_NUMBER (R_SCORE_PC19, 5) + RELOC_NUMBER (R_SCORE16_11, 6) + RELOC_NUMBER (R_SCORE16_PC8, 7) + RELOC_NUMBER (R_SCORE_ABS32, 8) + RELOC_NUMBER (R_SCORE_ABS16, 9) + RELOC_NUMBER (R_SCORE_DUMMY2, 10) + RELOC_NUMBER (R_SCORE_GP15, 11) + RELOC_NUMBER (R_SCORE_GNU_VTINHERIT, 12) + RELOC_NUMBER (R_SCORE_GNU_VTENTRY, 13) + RELOC_NUMBER (R_SCORE_GOT15, 14) + RELOC_NUMBER (R_SCORE_GOT_LO16, 15) + RELOC_NUMBER (R_SCORE_CALL15, 16) + RELOC_NUMBER (R_SCORE_GPREL32, 17) + RELOC_NUMBER (R_SCORE_REL32, 18) + RELOC_NUMBER (R_SCORE_DUMMY_HI16, 19) +END_RELOC_NUMBERS (R_SCORE_max) + +#endif /* _ELF_SCORE_H */ diff --git a/contrib/binutils/include/elf/spu.h b/contrib/binutils/include/elf/spu.h new file mode 100644 index 0000000..ef94980 --- /dev/null +++ b/contrib/binutils/include/elf/spu.h @@ -0,0 +1,60 @@ +/* SPU ELF support for BFD. + + Copyright 2006, 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _ELF_SPU_H +#define _ELF_SPU_H + +#include "elf/reloc-macros.h" + +/* elf32-spu.c depends on these being consecutive. */ +START_RELOC_NUMBERS (elf_spu_reloc_type) + RELOC_NUMBER (R_SPU_NONE, 0) + RELOC_NUMBER (R_SPU_ADDR10, 1) + RELOC_NUMBER (R_SPU_ADDR16, 2) + RELOC_NUMBER (R_SPU_ADDR16_HI, 3) + RELOC_NUMBER (R_SPU_ADDR16_LO, 4) + RELOC_NUMBER (R_SPU_ADDR18, 5) + RELOC_NUMBER (R_SPU_ADDR32, 6) + RELOC_NUMBER (R_SPU_REL16, 7) + RELOC_NUMBER (R_SPU_ADDR7, 8) + RELOC_NUMBER (R_SPU_REL9, 9) + RELOC_NUMBER (R_SPU_REL9I, 10) + RELOC_NUMBER (R_SPU_ADDR10I, 11) + RELOC_NUMBER (R_SPU_ADDR16I, 12) + RELOC_NUMBER (R_SPU_REL32, 13) + RELOC_NUMBER (R_SPU_ADDR16X, 14) + RELOC_NUMBER (R_SPU_PPU32, 15) + RELOC_NUMBER (R_SPU_PPU64, 16) +END_RELOC_NUMBERS (R_SPU_max) + +/* Program header extensions */ + +/* Mark a PT_LOAD segment as containing an overlay which should not + initially be loaded. */ +#define PF_OVERLAY (1 << 27) + +/* SPU Dynamic Object Information. */ +#define PT_SPU_INFO 0x70000000 + +/* SPU plugin information */ +#define SPU_PLUGIN_NAME "SPUNAME" +#define SPU_PTNOTE_SPUNAME ".note.spu_name" + +#endif /* _ELF_SPU_H */ diff --git a/contrib/binutils/include/elf/v850.h b/contrib/binutils/include/elf/v850.h index 95dab49..a88969d 100644 --- a/contrib/binutils/include/elf/v850.h +++ b/contrib/binutils/include/elf/v850.h @@ -1,5 +1,5 @@ /* V850 ELF support for BFD. - Copyright 1997, 1998, 2000, 2002, 2003, 2004 + Copyright 1997, 1998, 2000, 2002, 2003, 2004, 2007 Free Software Foundation, Inc. Created by Michael Meissner, Cygnus Support <meissner@cygnus.com> @@ -41,10 +41,9 @@ /* Flags for the st_other field. */ -#define V850_OTHER_SDA 0x01 /* Symbol had SDA relocations. */ -#define V850_OTHER_ZDA 0x02 /* Symbol had ZDA relocations. */ -#define V850_OTHER_TDA 0x04 /* Symbol had TDA relocations. */ -#define V850_OTHER_TDA_BYTE 0x08 /* Symbol had TDA byte relocations. */ +#define V850_OTHER_SDA 0x10 /* Symbol had SDA relocations. */ +#define V850_OTHER_ZDA 0x20 /* Symbol had ZDA relocations. */ +#define V850_OTHER_TDA 0x40 /* Symbol had TDA relocations. */ #define V850_OTHER_ERROR 0x80 /* Symbol had an error reported. */ /* V850 relocations. */ diff --git a/contrib/binutils/include/elf/xtensa.h b/contrib/binutils/include/elf/xtensa.h index 0de9741..bd83a14 100644 --- a/contrib/binutils/include/elf/xtensa.h +++ b/contrib/binutils/include/elf/xtensa.h @@ -140,7 +140,9 @@ typedef struct property_table_entry_t /* Instruction-only properties about code. */ #define XTENSA_PROP_INSN_NO_DENSITY 0x00000040 #define XTENSA_PROP_INSN_NO_REORDER 0x00000080 -#define XTENSA_PROP_INSN_NO_TRANSFORM 0x00000100 +/* Historically, NO_TRANSFORM was a property of instructions, + but it should apply to literals under certain circumstances. */ +#define XTENSA_PROP_NO_TRANSFORM 0x00000100 /* Branch target alignment information. This transmits information to the linker optimization about the priority of aligning a diff --git a/contrib/binutils/include/filenames.h b/contrib/binutils/include/filenames.h index 6b72fd2..5338208 100644 --- a/contrib/binutils/include/filenames.h +++ b/contrib/binutils/include/filenames.h @@ -5,7 +5,7 @@ use forward- and back-slash in path names interchangeably, and some of them have case-insensitive file names. - Copyright 2000, 2001 Free Software Foundation, Inc. + Copyright 2000, 2001, 2007 Free Software Foundation, Inc. This file is part of BFD, the Binary File Descriptor library. @@ -38,14 +38,15 @@ Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. want to know whether to prepend the current working directory to a file name, which should not be done with a name like d:foo. */ #define IS_ABSOLUTE_PATH(f) (IS_DIR_SEPARATOR((f)[0]) || (((f)[0]) && ((f)[1] == ':'))) -#define FILENAME_CMP(s1, s2) strcasecmp(s1, s2) #else /* not DOSish */ #define IS_DIR_SEPARATOR(c) ((c) == '/') #define IS_ABSOLUTE_PATH(f) (IS_DIR_SEPARATOR((f)[0])) -#define FILENAME_CMP(s1, s2) strcmp(s1, s2) #endif /* not DOSish */ +extern int filename_cmp (const char *s1, const char *s2); +#define FILENAME_CMP(s1, s2) filename_cmp(s1, s2) + #endif /* FILENAMES_H */ diff --git a/contrib/binutils/include/libiberty.h b/contrib/binutils/include/libiberty.h index 6bd318e..4e69734 100644 --- a/contrib/binutils/include/libiberty.h +++ b/contrib/binutils/include/libiberty.h @@ -86,6 +86,10 @@ extern char **dupargv (char **) ATTRIBUTE_MALLOC; extern void expandargv PARAMS ((int *, char ***)); +/* Write argv to an @-file, inserting necessary quoting. */ + +extern int writeargv PARAMS ((char **, FILE *)); + /* Return the last component of a path name. Note that we can't use a prototype here because the parameter is declared inconsistently across different systems, sometimes as "char *" and sometimes as @@ -197,6 +201,13 @@ extern long get_run_time (void); extern char *make_relative_prefix (const char *, const char *, const char *) ATTRIBUTE_MALLOC; +/* Generate a relocated path to some installation directory without + attempting to follow any soft links. Allocates + return value using malloc. */ + +extern char *make_relative_prefix_ignore_links (const char *, const char *, + const char *) ATTRIBUTE_MALLOC; + /* Choose a temporary directory to use for scratch files. */ extern char *choose_temp_base (void) ATTRIBUTE_MALLOC; @@ -393,6 +404,19 @@ extern struct pex_obj *pex_init (int flags, const char *pname, PEX_BINARY_INPUT. */ #define PEX_BINARY_OUTPUT 0x20 +/* Capture stderr to a pipe. The output can be read by + calling pex_read_err and reading from the returned + FILE object. This flag may be specified only for + the last program in a pipeline. + + This flag is supported only on Unix and Windows. */ +#define PEX_STDERR_TO_PIPE 0x40 + +/* Capture stderr in binary mode. This flag is ignored + on Unix. */ +#define PEX_BINARY_ERROR 0x80 + + /* Execute one program. Returns NULL on success. On error returns an error string (typically just the name of a system call); the error string is statically allocated. @@ -448,32 +472,22 @@ extern const char *pex_run (struct pex_obj *obj, int flags, const char *outname, const char *errname, int *err); -/* Return a `FILE' pointer FP for the standard input of the first - program in the pipeline; FP is opened for writing. You must have - passed `PEX_USE_PIPES' to the `pex_init' call that returned OBJ. - You must close FP yourself with `fclose' to indicate that the - pipeline's input is complete. - - The file descriptor underlying FP is marked not to be inherited by - child processes. - - This call is not supported on systems which do not support pipes; - it returns with an error. (We could implement it by writing a - temporary file, but then you would need to write all your data and - close FP before your first call to `pex_run' -- and that wouldn't - work on systems that do support pipes: the pipe would fill up, and - you would block. So there isn't any easy way to conceal the - differences between the two types of systems.) - - If you call both `pex_write_input' and `pex_read_output', be - careful to avoid deadlock. If the output pipe fills up, so that - each program in the pipeline is waiting for the next to read more - data, and you fill the input pipe by writing more data to FP, then - there is no way to make progress: the only process that could read - data from the output pipe is you, but you are blocked on the input - pipe. */ - -extern FILE *pex_write_input (struct pex_obj *obj, int binary); +/* As for pex_run (), but takes an extra parameter to enable the + environment for the child process to be specified. + + ENV The environment for the child process, specified as + an array of character pointers. Each element of the + array should point to a string of the form VAR=VALUE, + with the exception of the last element which must be + a null pointer. +*/ + +extern const char *pex_run_in_environment (struct pex_obj *obj, int flags, + const char *executable, + char * const *argv, + char * const *env, + const char *outname, + const char *errname, int *err); /* Return a stream for a temporary file to pass to the first program in the pipeline as input. The file name is chosen as for pex_run. @@ -497,6 +511,14 @@ extern FILE *pex_input_pipe (struct pex_obj *obj, int binary); extern FILE *pex_read_output (struct pex_obj *, int binary); +/* Read the standard error of the last program to be executed. + pex_run can not be called after this. BINARY should be non-zero if + the file should be opened in binary mode; this is ignored on Unix. + Returns NULL on error. Don't call fclose on the returned FILE; it + will be closed by pex_free. */ + +extern FILE *pex_read_err (struct pex_obj *, int binary); + /* Return exit status of all programs in VECTOR. COUNT indicates the size of VECTOR. The status codes in the vector are in the order of the calls to pex_run. Returns 0 on error, 1 on success. */ diff --git a/contrib/binutils/include/opcode/ChangeLog b/contrib/binutils/include/opcode/ChangeLog index 0c67a5c..689e278 100644 --- a/contrib/binutils/include/opcode/ChangeLog +++ b/contrib/binutils/include/opcode/ChangeLog @@ -1,8 +1,187 @@ -2006-05-26 Richard Sandiford <richard@codesourcery.com> +2006-06-29 M R Swami Reddy <MR.Swami.Reddy@nsc.com> + + * cr16.h: New file for CR16 target. + +2007-05-02 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (PPC_OPERAND_PLUS1): Update comment. + +2007-04-23 Nathan Sidwell <nathan@codesourcery.com> + + * m68k.h (mcfisa_c): New. + (mcfusp, mcf_mask): Adjust. + +2007-04-20 Alan Modra <amodra@bigpond.net.au> + + * ppc.h (struct powerpc_operand): Replace "bits" with "bitm". + (num_powerpc_operands): Declare. + (PPC_OPERAND_SIGNED et al): Redefine as hex. + (PPC_OPERAND_PLUS1): Define. + +2007-03-21 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (REX_MODE64): Renamed to ... + (REX_W): This. + (REX_EXTX): Renamed to ... + (REX_R): This. + (REX_EXTY): Renamed to ... + (REX_X): This. + (REX_EXTZ): Renamed to ... + (REX_B): This. + +2007-03-15 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h: Add entries from config/tc-i386.h and move tables + to opcodes/i386-opc.h. + +2007-03-13 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (FloatDR): Removed. + (i386_optab): Use FloatD and FloatD|FloatR instead of FloatDR. + +2007-03-01 Alan Modra <amodra@bigpond.net.au> + + * spu-insns.h: Add soma double-float insns. + +2007-02-20 Thiemo Seufer <ths@mips.com> + Chao-Ying Fu <fu@mips.com> + + * mips.h (OP_SH_BP, OP_MASK_BP): Add support for balign instruction. + (INSN_DSPR2): Add flag for DSP R2 instructions. + (M_BALIGN): New macro. + +2007-02-14 Alan Modra <amodra@bigpond.net.au> + + * i386.h (i386_optab): Replace all occurrences of Seg2ShortForm + and Seg3ShortFrom with Shortform. + +2007-02-11 H.J. Lu <hongjiu.lu@intel.com> + + PR gas/4027 + * i386.h (i386_optab): Put the real "test" before the pseudo + one. + +2007-01-08 Kazu Hirata <kazu@codesourcery.com> + + * m68k.h (m68010up): OR fido_a. + +2006-12-25 Kazu Hirata <kazu@codesourcery.com> + + * m68k.h (fido_a): New. + +2006-12-24 Kazu Hirata <kazu@codesourcery.com> + + * m68k.h (mcfmac, mcfemac, cfloat, mcfhwdiv, mcfisa_a, + mcfisa_aa, mcfisa_b, mcfusp, mcf_mask): Double the defined + values. + +2006-11-08 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Replace CpuPNI with CpuSSE3. + +2006-10-31 Mei Ligang <ligang@sunnorth.com.cn> + + * score-inst.h (enum score_insn_type): Add Insn_internal. + +2006-10-25 Trevor Smigiel <Trevor_Smigiel@playstation.sony.com> + Yukishige Shibata <shibata@rd.scei.sony.co.jp> + Nobuhisa Fujinami <fnami@rd.scei.sony.co.jp> + Takeaki Fukuoka <fukuoka@rd.scei.sony.co.jp> + Alan Modra <amodra@bigpond.net.au> + + * spu-insns.h: New file. + * spu.h: New file. + +2006-10-24 Andrew Pinski <andrew_pinski@playstation.sony.com> + + * ppc.h (PPC_OPCODE_CELL): Define. + +2006-10-23 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> + + * i386.h : Modify opcode to support for the change in POPCNT opcode + in amdfam10 architecture. + +2006-09-28 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h: Replace CpuMNI with CpuSSSE3. + +2006-09-26 Mark Shinwell <shinwell@codesourcery.com> + Joseph Myers <joseph@codesourcery.com> + Ian Lance Taylor <ian@wasabisystems.com> + Ben Elliston <bje@wasabisystems.com> + + * arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define. + +2006-09-17 Mei Ligang <ligang@sunnorth.com.cn> + + * score-datadep.h: New file. + * score-inst.h: New file. + +2006-07-14 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Remove InvMem from maskmovq, movhlps, + movlhps, movmskps, pextrw, pmovmskb, movmskpd, maskmovdqu, + movdq2q and movq2dq. + +2006-07-10 Dwarakanath Rajagopal <dwarak.rajagopal@amd.com> + Michael Meissner <michael.meissner@amd.com> + + * i386.h: Add amdfam10 new instructions (SSE4a and ABM instructions). + +2006-06-12 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Add "nop" with memory reference. + +2006-06-12 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Update comment for 64bit NOP. + +2006-06-06 Ben Elliston <bje@au.ibm.com> + Anton Blanchard <anton@samba.org> + + * ppc.h (PPC_OPCODE_POWER6): Define. + Adjust whitespace. + +2006-06-05 Thiemo Seufer <ths@mips.com> + + * mips.h: Improve description of MT flags. + +2006-05-25 Richard Sandiford <richard@codesourcery.com> * m68k.h (mcf_mask): Define. -2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> +2006-05-05 Thiemo Seufer <ths@mips.com> + David Ung <davidu@mips.com> + + * mips.h (enum): Add macro M_CACHE_AB. + +2006-05-04 Thiemo Seufer <ths@mips.com> + Nigel Stephens <nigel@mips.com> + David Ung <davidu@mips.com> + + * mips.h: Add INSN_SMARTMIPS define. + +2006-04-30 Thiemo Seufer <ths@mips.com> + David Ung <davidu@mips.com> + + * mips.h: Defines udi bits and masks. Add description of + characters which may appear in the args field of udi + instructions. + +2006-04-26 Thiemo Seufer <ths@networkno.de> + + * mips.h: Improve comments describing the bitfield instruction + fields. + +2006-04-26 Julian Brown <julian@codesourcery.com> + + * arm.h (FPU_VFP_EXT_V3): Define constant. + (FPU_NEON_EXT_V1): Likewise. + (FPU_VFP_HARD): Update. + (FPU_VFP_V3): Define macro. + (FPU_ARCH_VFP_V3, FPU_ARCH_VFP_V3_PLUS_NEON_V1): Define macros. + +2006-04-07 Joerg Wunsch <j.gnu@uriah.heep.sax.de> * avr.h (AVR_ISA_PWMx): New. diff --git a/contrib/binutils/include/opcode/arm.h b/contrib/binutils/include/opcode/arm.h index 1d3aa5a..24a89cf 100644 --- a/contrib/binutils/include/opcode/arm.h +++ b/contrib/binutils/include/opcode/arm.h @@ -49,6 +49,7 @@ #define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */ #define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */ #define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */ +#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */ #define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */ #define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */ @@ -58,6 +59,8 @@ #define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */ #define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */ #define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */ +#define FPU_VFP_EXT_V3 0x01000000 /* VFPv3 insns. */ +#define FPU_NEON_EXT_V1 0x00800000 /* Neon (SIMD) insns. */ /* Architectures are the sum of the base and extensions. The ARM ARM (rev E) defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, @@ -101,11 +104,15 @@ #define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE) #define ARM_ARCH_IWMMXT \ ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT) +#define ARM_ARCH_IWMMXT2 \ + ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2) #define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE) #define FPU_VFP_V1 (FPU_VFP_V1xD | FPU_VFP_EXT_V1) #define FPU_VFP_V2 (FPU_VFP_V1 | FPU_VFP_EXT_V2) -#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2) +#define FPU_VFP_V3 (FPU_VFP_V2 | FPU_VFP_EXT_V3) +#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \ + | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1) #define FPU_FPA (FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2) /* Deprecated */ @@ -117,6 +124,10 @@ #define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD) #define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1) #define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2) +#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3) +#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1) +#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \ + ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1) #define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD) #define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE) diff --git a/contrib/binutils/include/opcode/cr16.h b/contrib/binutils/include/opcode/cr16.h new file mode 100644 index 0000000..b7e3be5 --- /dev/null +++ b/contrib/binutils/include/opcode/cr16.h @@ -0,0 +1,437 @@ +/* cr16.h -- Header file for CR16 opcode and register tables. + Copyright 2007 Free Software Foundation, Inc. + Contributed by M R Swami Reddy + + This file is part of GAS, GDB and the GNU binutils. + + GAS, GDB, and GNU binutils is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2, or (at your + option) any later version. + + GAS, GDB, and GNU binutils are distributed in the hope that they will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +#ifndef _CR16_H_ +#define _CR16_H_ + +/* CR16 core Registers : + The enums are used as indices to CR16 registers table (cr16_regtab). + Therefore, order MUST be preserved. */ + +typedef enum + { + /* 16-bit general purpose registers. */ + r0, r1, r2, r3, + r4, r5, r6, r7, + r8, r9, r10, r11, + r12_L = 12, r13_L = 13, ra = 14, sp_L = 15, + + /* 32-bit general purpose registers. */ + r12 = 12, r13 = 13, r14 = 14, r15 = 15, + era = 14, sp = 15, RA, + + /* Not a register. */ + nullregister, + MAX_REG + } +reg; + +/* CR16 processor registers and special registers : + The enums are used as indices to CR16 processor registers table + (cr16_pregtab). Therefore, order MUST be preserved. */ + +typedef enum + { + /* processor registers. */ + dbs = MAX_REG, + dsr, dcrl, dcrh, + car0l, car0h, car1l, car1h, + cfg, psr, intbasel, intbaseh, + ispl, isph, uspl, usph, + dcr = dcrl, + car0 = car0l, + car1 = car1l, + intbase = intbasel, + isp = ispl, + usp = uspl, + /* Not a processor register. */ + nullpregister = usph + 1, + MAX_PREG + } +preg; + +/* CR16 Register types. */ + +typedef enum + { + CR16_R_REGTYPE, /* r<N> */ + CR16_RP_REGTYPE, /* reg pair */ + CR16_P_REGTYPE /* Processor register */ + } +reg_type; + +/* CR16 argument types : + The argument types correspond to instructions operands + + Argument types : + r - register + rp - register pair + c - constant + i - immediate + idxr - index with register + idxrp - index with register pair + rbase - register base + rpbase - register pair base + pr - processor register */ + +typedef enum + { + arg_r, + arg_c, + arg_cr, + arg_crp, + arg_ic, + arg_icr, + arg_idxr, + arg_idxrp, + arg_rbase, + arg_rpbase, + arg_rp, + arg_pr, + arg_prp, + arg_cc, + arg_ra, + /* Not an argument. */ + nullargs + } +argtype; + +/* CR16 operand types:The operand types correspond to instructions operands.*/ + +typedef enum + { + dummy, + /* N-bit signed immediate. */ + imm3, imm4, imm5, imm6, imm16, imm20, imm32, + /* N-bit unsigned immediate. */ + uimm3, uimm3_1, uimm4, uimm4_1, uimm5, uimm16, uimm20, uimm32, + /* N-bit signed displacement. */ + disps5, disps17, disps25, + /* N-bit unsigned displacement. */ + dispe9, + /* N-bit absolute address. */ + abs20, abs24, + /* Register relative. */ + rra, rbase, rbase_disps20, rbase_dispe20, + /* Register pair relative. */ + rpbase_disps0, rpbase_dispe4, rpbase_disps4, rpbase_disps16, + rpbase_disps20, rpbase_dispe20, + /* Register index. */ + rindex7_abs20, rindex8_abs20, + /* Register pair index. */ + rpindex_disps0, rpindex_disps14, rpindex_disps20, + /* register. */ + regr, + /* register pair. */ + regp, + /* processor register. */ + pregr, + /* processor register 32 bit. */ + pregrp, + /* condition code - 4 bit. */ + cc, + /* Not an operand. */ + nulloperand, + /* Maximum supported operand. */ + MAX_OPRD + } +operand_type; + +/* CR16 instruction types. */ + +#define NO_TYPE_INS 0 +#define ARITH_INS 1 +#define LD_STOR_INS 2 +#define BRANCH_INS 3 +#define ARITH_BYTE_INS 4 +#define SHIFT_INS 5 +#define BRANCH_NEQ_INS 6 +#define LD_STOR_INS_INC 7 +#define STOR_IMM_INS 8 +#define CSTBIT_INS 9 + +/* Maximum value supported for instruction types. */ +#define CR16_INS_MAX (1 << 4) +/* Mask to record an instruction type. */ +#define CR16_INS_MASK (CR16_INS_MAX - 1) +/* Return instruction type, given instruction's attributes. */ +#define CR16_INS_TYPE(attr) ((attr) & CR16_INS_MASK) + +/* Indicates whether this instruction has a register list as parameter. */ +#define REG_LIST CR16_INS_MAX + +/* The operands in binary and assembly are placed in reverse order. + load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ +#define REVERSE_MATCH (1 << 5) + +/* Printing formats, where the instruction prefix isn't consecutive. */ +#define FMT_1 (1 << 9) /* 0xF0F00000 */ +#define FMT_2 (1 << 10) /* 0xFFF0FF00 */ +#define FMT_3 (1 << 11) /* 0xFFF00F00 */ +#define FMT_4 (1 << 12) /* 0xFFF0F000 */ +#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ +#define FMT_CR16 (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) + +/* Indicates whether this instruction can be relaxed. */ +#define RELAXABLE (1 << 14) + +/* Indicates that instruction uses user registers (and not + general-purpose registers) as operands. */ +#define USER_REG (1 << 15) + + +/* Instruction shouldn't allow 'sp' usage. */ +#define NO_SP (1 << 17) + +/* Instruction shouldn't allow to push a register which is used as a rptr. */ +#define NO_RPTR (1 << 18) + +/* Maximum operands per instruction. */ +#define MAX_OPERANDS 5 +/* Maximum register name length. */ +#define MAX_REGNAME_LEN 10 +/* Maximum instruction length. */ +#define MAX_INST_LEN 256 + + +/* Values defined for the flags field of a struct operand_entry. */ + +/* Operand must be an unsigned number. */ +#define OP_UNSIGNED (1 << 0) +/* Operand must be a signed number. */ +#define OP_SIGNED (1 << 1) +/* Operand must be a negative number. */ +#define OP_NEG (1 << 2) +/* A special load/stor 4-bit unsigned displacement operand. */ +#define OP_DEC (1 << 3) +/* Operand must be an even number. */ +#define OP_EVEN (1 << 4) +/* Operand is shifted right. */ +#define OP_SHIFT (1 << 5) +/* Operand is shifted right and decremented. */ +#define OP_SHIFT_DEC (1 << 6) +/* Operand has reserved escape sequences. */ +#define OP_ESC (1 << 7) +/* Operand must be a ABS20 number. */ +#define OP_ABS20 (1 << 8) +/* Operand must be a ABS24 number. */ +#define OP_ABS24 (1 << 9) +/* Operand has reserved escape sequences type 1. */ +#define OP_ESC1 (1 << 10) + +/* Single operand description. */ + +typedef struct + { + /* Operand type. */ + operand_type op_type; + /* Operand location within the opcode. */ + unsigned int shift; + } +operand_desc; + +/* Instruction data structure used in instruction table. */ + +typedef struct + { + /* Name. */ + const char *mnemonic; + /* Size (in words). */ + unsigned int size; + /* Constant prefix (matched by the disassembler). */ + unsigned long match; /* ie opcode */ + /* Match size (in bits). */ + /* MASK: if( (i & match_bits) == match ) then match */ + int match_bits; + /* Attributes. */ + unsigned int flags; + /* Operands (always last, so unreferenced operands are initialized). */ + operand_desc operands[MAX_OPERANDS]; + } +inst; + +/* Data structure for a single instruction's arguments (Operands). */ + +typedef struct + { + /* Register or base register. */ + reg r; + /* Register pair register. */ + reg rp; + /* Index register. */ + reg i_r; + /* Processor register. */ + preg pr; + /* Processor register. 32 bit */ + preg prp; + /* Constant/immediate/absolute value. */ + long constant; + /* CC code. */ + unsigned int cc; + /* Scaled index mode. */ + unsigned int scale; + /* Argument type. */ + argtype type; + /* Size of the argument (in bits) required to represent. */ + int size; + /* The type of the expression. */ + unsigned char X_op; + } +argument; + +/* Internal structure to hold the various entities + corresponding to the current assembling instruction. */ + +typedef struct + { + /* Number of arguments. */ + int nargs; + /* The argument data structure for storing args (operands). */ + argument arg[MAX_OPERANDS]; +/* The following fields are required only by CR16-assembler. */ +#ifdef TC_CR16 + /* Expression used for setting the fixups (if any). */ + expressionS exp; + bfd_reloc_code_real_type rtype; +#endif /* TC_CR16 */ + /* Instruction size (in bytes). */ + int size; + } +ins; + +/* Structure to hold information about predefined operands. */ + +typedef struct + { + /* Size (in bits). */ + unsigned int bit_size; + /* Argument type. */ + argtype arg_type; + /* One bit syntax flags. */ + int flags; + } +operand_entry; + +/* Structure to hold trap handler information. */ + +typedef struct + { + /* Trap name. */ + char *name; + /* Index in dispatch table. */ + unsigned int entry; + } +trap_entry; + +/* Structure to hold information about predefined registers. */ + +typedef struct + { + /* Name (string representation). */ + char *name; + /* Value (enum representation). */ + union + { + /* Register. */ + reg reg_val; + /* processor register. */ + preg preg_val; + } value; + /* Register image. */ + int image; + /* Register type. */ + reg_type type; + } +reg_entry; + +/* CR16 opcode table. */ +extern const inst cr16_instruction[]; +extern const unsigned int cr16_num_opcodes; +#define NUMOPCODES cr16_num_opcodes + +/* CR16 operands table. */ +extern const operand_entry cr16_optab[]; + +/* CR16 registers table. */ +extern const reg_entry cr16_regtab[]; +extern const unsigned int cr16_num_regs; +#define NUMREGS cr16_num_regs + +/* CR16 register pair table. */ +extern const reg_entry cr16_regptab[]; +extern const unsigned int cr16_num_regps; +#define NUMREGPS cr16_num_regps + +/* CR16 processor registers table. */ +extern const reg_entry cr16_pregtab[]; +extern const unsigned int cr16_num_pregs; +#define NUMPREGS cr16_num_pregs + +/* CR16 processor registers - 32 bit table. */ +extern const reg_entry cr16_pregptab[]; +extern const unsigned int cr16_num_pregps; +#define NUMPREGPS cr16_num_pregps + +/* CR16 trap/interrupt table. */ +extern const trap_entry cr16_traps[]; +extern const unsigned int cr16_num_traps; +#define NUMTRAPS cr16_num_traps + +/* CR16 CC - codes bit table. */ +extern const char * cr16_b_cond_tab[]; +extern const unsigned int cr16_num_cc; +#define NUMCC cr16_num_cc; + + +/* Table of instructions with no operands. */ +extern const char * cr16_no_op_insn[]; + +/* Current instruction we're assembling. */ +extern const inst *instruction; + +/* A macro for representing the instruction "constant" opcode, that is, + the FIXED part of the instruction. The "constant" opcode is represented + as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) + over that range. */ +#define BIN(OPC,SHIFT) (OPC << SHIFT) + +/* Is the current instruction type is TYPE ? */ +#define IS_INSN_TYPE(TYPE) \ + (CR16_INS_TYPE (instruction->flags) == TYPE) + +/* Is the current instruction mnemonic is MNEMONIC ? */ +#define IS_INSN_MNEMONIC(MNEMONIC) \ + (strcmp (instruction->mnemonic, MNEMONIC) == 0) + +/* Does the current instruction has register list ? */ +#define INST_HAS_REG_LIST \ + (instruction->flags & REG_LIST) + + +/* Utility macros for string comparison. */ +#define streq(a, b) (strcmp (a, b) == 0) +#define strneq(a, b, c) (strncmp (a, b, c) == 0) + +/* Long long type handling. */ +/* Replace all appearances of 'long long int' with LONGLONG. */ +typedef long long int LONGLONG; +typedef unsigned long long ULONGLONG; + +#endif /* _CR16_H_ */ diff --git a/contrib/binutils/include/opcode/i386.h b/contrib/binutils/include/opcode/i386.h index 2b2c1e0..4fe769a 100644 --- a/contrib/binutils/include/opcode/i386.h +++ b/contrib/binutils/include/opcode/i386.h @@ -1,6 +1,6 @@ -/* opcode/i386.h -- Intel 80386 opcode table +/* opcode/i386.h -- Intel 80386 opcode macros Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003, 2004, 2005 + 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. @@ -31,7 +31,7 @@ This happens with all the non-commutative arithmetic floating point operations with two register operands, where the source register is - %st, and destination register is %st(i). See FloatDR below. + %st, and destination register is %st(i). The affected opcode map is dceX, dcfX, deeX, defX. */ @@ -48,1668 +48,68 @@ #define OLDGCC_COMPAT SYSV386_COMPAT #endif -static const template i386_optab[] = -{ - -#define X None -#define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) -#define b_Suf (No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) -#define w_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) -#define l_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf|No_qSuf) -#define q_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_xSuf) -#define x_Suf (No_bSuf|No_wSuf|No_sSuf|No_lSuf|No_qSuf) -#define bw_Suf (No_lSuf|No_sSuf|No_xSuf|No_qSuf) -#define bl_Suf (No_wSuf|No_sSuf|No_xSuf|No_qSuf) -#define wl_Suf (No_bSuf|No_sSuf|No_xSuf|No_qSuf) -#define wlq_Suf (No_bSuf|No_sSuf|No_xSuf) -#define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf) -#define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf) -#define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf) -#define bwl_Suf (No_sSuf|No_xSuf|No_qSuf) -#define bwlq_Suf (No_sSuf|No_xSuf) -#define FP (NoSuf) -#define l_FP (l_Suf) -#define q_FP (q_Suf|NoRex64) -#define x_FP (x_Suf|FloatMF) -#define sl_FP (sl_Suf|FloatMF) -#if SYSV386_COMPAT -/* Someone forgot that the FloatR bit reverses the operation when not - equal to the FloatD bit. ie. Changing only FloatD results in the - destination being swapped *and* the direction being reversed. */ -#define FloatDR FloatD -#else -#define FloatDR (FloatD|FloatR) -#endif - -/* Move instructions. */ #define MOV_AX_DISP32 0xa0 -/* We put the 64bit displacement first and we only mark constants - larger than 32bit as Disp64. */ -{ "mov", 2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, -{ "mov", 2, 0xa0, X, CpuNo64,bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, -{ "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -/* In the 64bit mode the short form mov immediate is redefined to have - 64bit value. */ -{ "mov", 2, 0xb0, X, 0, bwl_Suf|W|ShortForm, { EncImm, Reg8|Reg16|Reg32, 0 } }, -{ "mov", 2, 0xc6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0 } }, -{ "mov", 2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, -/* The segment register moves accept WordReg so that a segment register - can be copied to a 32 bit register, and vice versa, without using a - size prefix. When moving to a 32 bit register, the upper 16 bits - are set to an implementation defined value (on the Pentium Pro, - the implementation defined value is zero). */ -{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|InvMem, 0 } }, -{ "mov", 2, 0x8c, X, 0, w_Suf|Modrm|IgnoreSize, { SReg2, WordMem, 0 } }, -{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|InvMem, 0 } }, -{ "mov", 2, 0x8c, X, Cpu386, w_Suf|Modrm|IgnoreSize, { SReg3, WordMem, 0 } }, -{ "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg, SReg2, 0 } }, -{ "mov", 2, 0x8e, X, 0, w_Suf|Modrm|IgnoreSize, { WordMem, SReg2, 0 } }, -{ "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg, SReg3, 0 } }, -{ "mov", 2, 0x8e, X, Cpu386, w_Suf|Modrm|IgnoreSize, { WordMem, SReg3, 0 } }, -/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit - mode they are 64bit.*/ -{ "mov", 2, 0x0f20, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Control, Reg32|InvMem, 0} }, -{ "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} }, -{ "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} }, -{ "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} }, -{ "mov", 2, 0x0f24, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, -{ "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, -{ "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, - -/* Move with sign extend. */ -/* "movsbl" & "movsbw" must not be unified into "movsb" to avoid - conflict with the "movs" string move instruction. */ -{"movsbl", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, -{"movsbw", 2, 0x0fbe, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, -{"movswl", 2, 0x0fbf, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem,Reg32, 0} }, -{"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, -{"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} }, -{"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, -/* Intel Syntax next 3 insns */ -{"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} }, -{"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, - -/* Move with zero extend. We can't remove "movzb" since existing - assembly codes may use it. */ -{"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -/* "movzbl" & "movzbw" should not be unified into "movzb" for - consistency with the sign extending moves above. */ -{"movzbl", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, -{"movzbw", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, -{"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, -/* These instructions are not particulary useful, since the zero extend - 32->64 is implicit, but we can encode them. */ -{"movzbq", 2, 0x0fb6, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, -{"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, -/* Intel Syntax next 2 insns (the 64-bit variants are not particulary useful, - since the zero extend 32->64 is implicit, but we can encode them). */ -{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} }, - -/* Push instructions. */ -{"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, -{"push", 1, 0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, -{"push", 1, 0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, -{"push", 1, 0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, -{"push", 1, 0x06, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, -{"push", 1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, -/* In 64bit mode, the operand size is implicitly 64bit. */ -{"push", 1, 0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } }, -{"push", 1, 0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } }, -{"push", 1, 0x6a, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} }, -{"push", 1, 0x68, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} }, -{"push", 1, 0x0fa0, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, - -{"pusha", 0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, - -/* Pop instructions. */ -{"pop", 1, 0x58, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, -{"pop", 1, 0x8f, 0, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, #define POP_SEG_SHORT 0x07 -{"pop", 1, 0x07, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, -{"pop", 1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, -/* In 64bit mode, the operand size is implicitly 64bit. */ -{"pop", 1, 0x58, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } }, -{"pop", 1, 0x8f, 0, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } }, -{"pop", 1, 0x0fa1, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, - -{"popa", 0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, - -/* Exchange instructions. - xchg commutes: we allow both operand orders. - - In the 64bit code, xchg eax, eax is reused for new nop instruction. */ -#if 0 /* While the two entries that are disabled generate shorter code - for xchg eax, reg (on x86_64), the special case xchg eax, eax - does not get handled correctly - it degenerates into nop, but - that way the side effect of zero-extending eax to rax is lost. */ -{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { WordReg, Acc, 0 } }, -{"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { Acc, WordReg, 0 } }, -#else -{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { WordReg, Acc, 0 } }, -{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { Acc, WordReg, 0 } }, -{"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Reg16|Reg64, Acc, 0 } }, -{"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Acc, Reg16|Reg64, 0 } }, -#endif -{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, -{"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, - -/* In/out from ports. */ -/* XXX should reject %rax */ -{"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } }, -{"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, -{"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, -{"in", 1, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, -{"out", 2, 0xe6, X, 0, bwl_Suf|W, { Acc, Imm8, 0 } }, -{"out", 2, 0xee, X, 0, bwl_Suf|W, { Acc, InOutPortReg, 0 } }, -{"out", 1, 0xe6, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, -{"out", 1, 0xee, X, 0, bwl_Suf|W, { InOutPortReg, 0, 0 } }, - -/* Load effective address. */ -{"lea", 2, 0x8d, X, 0, wlq_Suf|Modrm, { WordMem, WordReg, 0 } }, - -/* Load segment registers from memory. */ -{"lds", 2, 0xc5, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} }, -{"les", 2, 0xc4, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lfs", 2, 0x0fb4, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lgs", 2, 0x0fb5, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lss", 2, 0x0fb2, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, - -/* Flags register instructions. */ -{"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} }, -{"cld", 0, 0xfc, X, 0, NoSuf, { 0, 0, 0} }, -{"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} }, -{"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} }, -{"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} }, -{"lahf", 0, 0x9f, X, 0, NoSuf, { 0, 0, 0} }, -{"sahf", 0, 0x9e, X, 0, NoSuf, { 0, 0, 0} }, -{"pushf", 0, 0x9c, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, -{"pushf", 0, 0x9c, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, -{"popf", 0, 0x9d, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, -{"popf", 0, 0x9d, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, -{"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} }, -{"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} }, -{"sti", 0, 0xfb, X, 0, NoSuf, { 0, 0, 0} }, - -/* Arithmetic. */ -{"add", 2, 0x00, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"add", 2, 0x83, 0, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"add", 2, 0x04, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"add", 2, 0x80, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"inc", 1, 0x40, X, CpuNo64,wl_Suf|ShortForm, { WordReg, 0, 0} }, -{"inc", 1, 0xfe, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sub", 2, 0x28, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"sub", 2, 0x83, 5, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"sub", 2, 0x2c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"sub", 2, 0x80, 5, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"dec", 1, 0x48, X, CpuNo64, wl_Suf|ShortForm, { WordReg, 0, 0} }, -{"dec", 1, 0xfe, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sbb", 2, 0x18, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"sbb", 2, 0x83, 3, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"sbb", 2, 0x1c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"sbb", 2, 0x80, 3, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"cmp", 2, 0x38, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"cmp", 2, 0x83, 7, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"cmp", 2, 0x3c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"cmp", 2, 0x80, 7, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0} }, -{"test", 2, 0x84, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"test", 2, 0xa8, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"test", 2, 0xf6, 0, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"and", 2, 0x20, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"and", 2, 0x83, 4, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"and", 2, 0x24, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"and", 2, 0x80, 4, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"or", 2, 0x08, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"or", 2, 0x83, 1, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"or", 2, 0x0c, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"or", 2, 0x80, 1, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"xor", 2, 0x30, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"xor", 2, 0x83, 6, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"xor", 2, 0x34, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"xor", 2, 0x80, 6, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -/* clr with 1 operand is really xor with 2 operands. */ -{"clr", 1, 0x30, X, 0, bwlq_Suf|W|Modrm|regKludge, { Reg, 0, 0 } }, - -{"adc", 2, 0x10, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, -{"adc", 2, 0x83, 2, 0, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, 0} }, -{"adc", 2, 0x14, X, 0, bwlq_Suf|W, { EncImm, Acc, 0} }, -{"adc", 2, 0x80, 2, 0, bwlq_Suf|W|Modrm, { EncImm, Reg|AnyMem, 0} }, - -{"neg", 1, 0xf6, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"not", 1, 0xf6, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"aaa", 0, 0x37, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"aas", 0, 0x3f, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"daa", 0, 0x27, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"das", 0, 0x2f, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"aad", 0, 0xd50a, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"aad", 1, 0xd5, X, CpuNo64, NoSuf, { Imm8, 0, 0} }, -{"aam", 0, 0xd40a, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"aam", 1, 0xd4, X, CpuNo64, NoSuf, { Imm8, 0, 0} }, - -/* Conversion insns. */ -/* Intel naming */ -{"cbw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, -{"cdqe", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, -{"cwde", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, -{"cwd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, -{"cdq", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, -{"cqo", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, -/* AT&T naming */ -{"cbtw", 0, 0x98, X, 0, NoSuf|Size16, { 0, 0, 0} }, -{"cltq", 0, 0x98, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, -{"cwtl", 0, 0x98, X, 0, NoSuf|Size32, { 0, 0, 0} }, -{"cwtd", 0, 0x99, X, 0, NoSuf|Size16, { 0, 0, 0} }, -{"cltd", 0, 0x99, X, 0, NoSuf|Size32, { 0, 0, 0} }, -{"cqto", 0, 0x99, X, Cpu64, NoSuf|Size64, { 0, 0, 0} }, - -/* Warning! the mul/imul (opcode 0xf6) must only have 1 operand! They are - expanding 64-bit multiplies, and *cannot* be selected to accomplish - 'imul %ebx, %eax' (opcode 0x0faf must be used in this case) - These multiplies can only be selected with single operand forms. */ -{"mul", 1, 0xf6, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"imul", 1, 0xf6, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"imul", 2, 0x0faf, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"imul", 3, 0x6b, X, Cpu186, wlq_Suf|Modrm, { Imm8S, WordReg|WordMem, WordReg} }, -{"imul", 3, 0x69, X, Cpu186, wlq_Suf|Modrm, { Imm16|Imm32S|Imm32, WordReg|WordMem, WordReg} }, -/* imul with 2 operands mimics imul with 3 by putting the register in - both i.rm.reg & i.rm.regmem fields. regKludge enables this - transformation. */ -{"imul", 2, 0x6b, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm8S, WordReg, 0} }, -{"imul", 2, 0x69, X, Cpu186, wlq_Suf|Modrm|regKludge,{ Imm16|Imm32S|Imm32, WordReg, 0} }, - -{"div", 1, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"div", 2, 0xf6, 6, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, -{"idiv", 1, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"idiv", 2, 0xf6, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Acc, 0} }, - -{"rol", 2, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"rol", 2, 0xc0, 0, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"rol", 2, 0xd2, 0, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"rol", 1, 0xd0, 0, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"ror", 2, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"ror", 2, 0xc0, 1, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"ror", 2, 0xd2, 1, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"ror", 1, 0xd0, 1, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"rcl", 2, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"rcl", 2, 0xc0, 2, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"rcl", 2, 0xd2, 2, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"rcl", 1, 0xd0, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"rcr", 2, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"rcr", 2, 0xc0, 3, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"rcr", 2, 0xd2, 3, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"rcr", 1, 0xd0, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sal", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"sal", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"sal", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"sal", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"shl", 2, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"shl", 2, 0xc0, 4, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"shl", 2, 0xd2, 4, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"shl", 1, 0xd0, 4, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"shr", 2, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"shr", 2, 0xc0, 5, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"shr", 2, 0xd2, 5, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"shr", 1, 0xd0, 5, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"sar", 2, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Imm1, Reg|AnyMem, 0} }, -{"sar", 2, 0xc0, 7, Cpu186, bwlq_Suf|W|Modrm, { Imm8, Reg|AnyMem, 0} }, -{"sar", 2, 0xd2, 7, 0, bwlq_Suf|W|Modrm, { ShiftCount, Reg|AnyMem, 0} }, -{"sar", 1, 0xd0, 7, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, - -{"shld", 3, 0x0fa4, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, -{"shld", 3, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, -{"shld", 2, 0x0fa5, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, - -{"shrd", 3, 0x0fac, X, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg, WordReg|WordMem} }, -{"shrd", 3, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { ShiftCount, WordReg, WordReg|WordMem} }, -{"shrd", 2, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, - -/* Control transfer instructions. */ -{"call", 1, 0xe8, X, CpuNo64, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, -{"call", 1, 0xe8, X, Cpu64, wq_Suf|JumpDword|DefaultSize|NoRex64, { Disp16|Disp32, 0, 0} }, -{"call", 1, 0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, -{"call", 1, 0xff, 2, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem|LLongMem|JumpAbsolute, 0, 0} }, -/* Intel Syntax */ -{"call", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, -/* Intel Syntax */ -{"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} }, -{"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, {Imm16, Imm16|Imm32, 0} }, -{"lcall", 1, 0xff, 3, 0, wl_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} }, - #define JUMP_PC_RELATIVE 0xeb -{"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp,0, 0} }, -{"jmp", 1, 0xff, 4, CpuNo64, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, -{"jmp", 1, 0xff, 4, Cpu64, wq_Suf|Modrm|NoRex64, { Reg16|Reg64|ShortMem|LLongMem|JumpAbsolute, 0, 0} }, -/* Intel Syntax. */ -{"jmp", 2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -/* Intel Syntax. */ -{"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, -{"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -{"ljmp", 1, 0xff, 5, 0, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, - -{"ret", 0, 0xc3, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, -{"ret", 1, 0xc2, X, CpuNo64,wl_Suf|DefaultSize, { Imm16, 0, 0} }, -{"ret", 0, 0xc3, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, -{"ret", 1, 0xc2, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} }, -{"lret", 0, 0xcb, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, -{"lret", 1, 0xca, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} }, -{"enter", 2, 0xc8, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16, Imm8, 0} }, -{"enter", 2, 0xc8, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm16, Imm8, 0} }, -{"leave", 0, 0xc9, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0} }, -{"leave", 0, 0xc9, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { 0, 0, 0} }, - -/* Conditional jumps. */ -{"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jno", 1, 0x71, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jb", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jc", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnae", 1, 0x72, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnb", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnc", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jae", 1, 0x73, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"je", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jz", 1, 0x74, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jne", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnz", 1, 0x75, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jbe", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jna", 1, 0x76, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnbe", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"ja", 1, 0x77, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"js", 1, 0x78, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jns", 1, 0x79, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jp", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jpe", 1, 0x7a, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnp", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jpo", 1, 0x7b, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jl", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnge", 1, 0x7c, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnl", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jge", 1, 0x7d, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jle", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jng", 1, 0x7e, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jnle", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, -{"jg", 1, 0x7f, X, 0, NoSuf|Jump, { Disp, 0, 0} }, - -/* jcxz vs. jecxz is chosen on the basis of the address size prefix. */ -{"jcxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size16, { Disp, 0, 0} }, -{"jecxz", 1, 0xe3, X, CpuNo64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, -{"jecxz", 1, 0x67e3, X, Cpu64,NoSuf|JumpByte|Size32, { Disp, 0, 0} }, -{"jrcxz", 1, 0xe3, X, Cpu64, NoSuf|JumpByte|Size64|NoRex64, { Disp, 0, 0} }, - -/* The loop instructions also use the address size prefix to select - %cx rather than %ecx for the loop count, so the `w' form of these - instructions emit an address size prefix rather than a data size - prefix. */ -{"loop", 1, 0xe2, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loop", 1, 0xe2, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, -{"loopz", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loopz", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, -{"loope", 1, 0xe1, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loope", 1, 0xe1, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, -{"loopnz", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loopnz", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, -{"loopne", 1, 0xe0, X, CpuNo64,wl_Suf|JumpByte,{ Disp, 0, 0} }, -{"loopne", 1, 0xe0, X, Cpu64, lq_Suf|JumpByte|NoRex64,{ Disp, 0, 0} }, - -/* Set byte on flag instructions. */ -{"seto", 1, 0x0f90, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setno", 1, 0x0f91, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setb", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setc", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnae", 1, 0x0f92, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnb", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnc", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setae", 1, 0x0f93, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"sete", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setz", 1, 0x0f94, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setne", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnz", 1, 0x0f95, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setbe", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setna", 1, 0x0f96, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnbe", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"seta", 1, 0x0f97, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"sets", 1, 0x0f98, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setns", 1, 0x0f99, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setp", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setpe", 1, 0x0f9a, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnp", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setpo", 1, 0x0f9b, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setl", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnge", 1, 0x0f9c, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnl", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setge", 1, 0x0f9d, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setle", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setng", 1, 0x0f9e, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setnle", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, -{"setg", 1, 0x0f9f, 0, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, 0, 0} }, - -/* String manipulation. */ -{"cmps", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"cmps", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, -{"scmp", 0, 0xa6, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"scmp", 2, 0xa6, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, AnyMem, 0} }, -{"ins", 0, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, -{"ins", 2, 0x6c, X, Cpu186, bwl_Suf|W|IsString, { InOutPortReg, AnyMem|EsSeg, 0} }, -{"outs", 0, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { 0, 0, 0} }, -{"outs", 2, 0x6e, X, Cpu186, bwl_Suf|W|IsString, { AnyMem, InOutPortReg, 0} }, -{"lods", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"lods", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, -{"lods", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, -{"slod", 0, 0xac, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"slod", 1, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, 0, 0} }, -{"slod", 2, 0xac, X, 0, bwlq_Suf|W|IsString, { AnyMem, Acc, 0} }, -{"movs", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"movs", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"smov", 0, 0xa4, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"smov", 2, 0xa4, X, 0, bwlq_Suf|W|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"scas", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"scas", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"scas", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, -{"ssca", 0, 0xae, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"ssca", 1, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"ssca", 2, 0xae, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, Acc, 0} }, -{"stos", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"stos", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"stos", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, -{"ssto", 0, 0xaa, X, 0, bwlq_Suf|W|IsString, { 0, 0, 0} }, -{"ssto", 1, 0xaa, X, 0, bwlq_Suf|W|IsString, { AnyMem|EsSeg, 0, 0} }, -{"ssto", 2, 0xaa, X, 0, bwlq_Suf|W|IsString, { Acc, AnyMem|EsSeg, 0} }, -{"xlat", 0, 0xd7, X, 0, b_Suf|IsString, { 0, 0, 0} }, -{"xlat", 1, 0xd7, X, 0, b_Suf|IsString, { AnyMem, 0, 0} }, - -/* Bit manipulation. */ -{"bsf", 2, 0x0fbc, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"bsr", 2, 0x0fbd, X, Cpu386, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"bt", 2, 0x0fa3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"bt", 2, 0x0fba, 4, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, -{"btc", 2, 0x0fbb, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"btc", 2, 0x0fba, 7, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, -{"btr", 2, 0x0fb3, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"btr", 2, 0x0fba, 6, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, -{"bts", 2, 0x0fab, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, -{"bts", 2, 0x0fba, 5, Cpu386, wlq_Suf|Modrm, { Imm8, WordReg|WordMem, 0} }, - -/* Interrupts & op. sys insns. */ -/* See gas/config/tc-i386.c for conversion of 'int $3' into the special - int 3 insn. */ #define INT_OPCODE 0xcd #define INT3_OPCODE 0xcc -{"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} }, -{"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} }, -{"into", 0, 0xce, X, CpuNo64, NoSuf, { 0, 0, 0} }, -{"iret", 0, 0xcf, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, -/* i386sl, i486sl, later 486, and Pentium. */ -{"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} }, - -{"bound", 2, 0x62, X, Cpu186|CpuNo64, wl_Suf|Modrm, { WordReg, WordMem, 0} }, - -{"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} }, -/* nop is actually 'xchgl %eax, %eax'. */ -{"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} }, - -/* Protection control. */ -{"arpl", 2, 0x63, X, Cpu286|CpuNo64, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, -{"lar", 2, 0x0f02, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"lgdt", 1, 0x0f01, 2, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"lgdt", 1, 0x0f01, 2, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"lidt", 1, 0x0f01, 3, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"lidt", 1, 0x0f01, 3, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"lsl", 2, 0x0f03, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, - -{"sgdt", 1, 0x0f01, 0, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"sgdt", 1, 0x0f01, 0, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"sidt", 1, 0x0f01, 1, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, -{"sidt", 1, 0x0f01, 1, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, -{"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, -{"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, -{"smsw", 1, 0x0f01, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, -{"str", 1, 0x0f00, 1, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, -{"str", 1, 0x0f00, 1, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, - -{"verr", 1, 0x0f00, 4, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"verw", 1, 0x0f00, 5, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, - -/* Floating point instructions. */ - -/* load */ -{"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fld", 1, 0xd9, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, -/* Intel Syntax */ -{"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} }, -{"fild", 1, 0xdf, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, -{"fild", 1, 0xdf, 5, 0, q_FP|Modrm, { LLongMem, 0, 0} }, -{"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fbld", 1, 0xdf, 4, 0, x_Suf|Modrm, { LLongMem, 0, 0} }, - -/* store (no pop) */ -{"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fst", 1, 0xd9, 2, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, -{"fist", 1, 0xdf, 2, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -/* store (with pop) */ -{"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fstp", 1, 0xd9, 3, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, -/* Intel Syntax */ -{"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} }, -{"fistp", 1, 0xdf, 3, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, -{"fistp", 1, 0xdf, 7, 0, q_FP|Modrm, { LLongMem, 0, 0} }, -{"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fbstp", 1, 0xdf, 6, 0, x_Suf|Modrm, { LLongMem, 0, 0} }, - -/* exchange %st<n> with %st0 */ -{"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fxch %st(1) */ -{"fxch", 0, 0xd9c9, X, 0, FP, { 0, 0, 0} }, - -/* comparison (without pop) */ -{"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fcom %st(1) */ -{"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} }, -{"fcom", 1, 0xd8, 2, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, -{"ficom", 1, 0xde, 2, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -/* comparison (with pop) */ -{"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fcomp %st(1) */ -{"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} }, -{"fcomp", 1, 0xd8, 3, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, -{"ficomp", 1, 0xde, 3, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, -{"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} }, - -/* unordered comparison (with pop) */ -{"fucom", 1, 0xdde0, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fucom %st(1) */ -{"fucom", 0, 0xdde1, X, Cpu286, FP, { 0, 0, 0} }, -{"fucomp", 1, 0xdde8, X, Cpu286, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for fucomp %st(1) */ -{"fucomp", 0, 0xdde9, X, Cpu286, FP, { 0, 0, 0} }, -{"fucompp",0, 0xdae9, X, Cpu286, FP, { 0, 0, 0} }, - -{"ftst", 0, 0xd9e4, X, 0, FP, { 0, 0, 0} }, -{"fxam", 0, 0xd9e5, X, 0, FP, { 0, 0, 0} }, - -/* load constants into %st0 */ -{"fld1", 0, 0xd9e8, X, 0, FP, { 0, 0, 0} }, -{"fldl2t", 0, 0xd9e9, X, 0, FP, { 0, 0, 0} }, -{"fldl2e", 0, 0xd9ea, X, 0, FP, { 0, 0, 0} }, -{"fldpi", 0, 0xd9eb, X, 0, FP, { 0, 0, 0} }, -{"fldlg2", 0, 0xd9ec, X, 0, FP, { 0, 0, 0} }, -{"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} }, -{"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} }, - -/* Arithmetic. */ - -/* add */ -{"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, -/* alias for fadd %st(i), %st */ -{"fadd", 1, 0xd8c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for faddp */ -{"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fadd", 1, 0xd8, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fiadd", 1, 0xde, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -{"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* alias for faddp %st, %st(1) */ -{"faddp", 0, 0xdec1, X, 0, FP, { 0, 0, 0} }, -{"faddp", 2, 0xdec0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, - -/* subtract */ -{"fsub", 2, 0xd8e0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fsub", 1, 0xd8e0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fsubp */ -{"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fsub", 1, 0xd8, 4, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fisub", 1, 0xde, 4, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -#if SYSV386_COMPAT -{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT -{"fsubp", 2, 0xdee0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif -#else -{"fsubp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, -#endif - -/* subtract reverse */ -{"fsubr", 2, 0xd8e8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fsubr", 1, 0xd8e8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fsubrp */ -{"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fsubr", 1, 0xd8, 5, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fisubr", 1, 0xde, 5, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -#if SYSV386_COMPAT -{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubrp", 1, 0xdee8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubrp", 0, 0xdee9, X, 0, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT -{"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif -#else -{"fsubrp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fsubrp", 1, 0xdee0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fsubrp", 0, 0xdee1, X, 0, FP, { 0, 0, 0} }, -#endif - -/* multiply */ -{"fmul", 2, 0xd8c8, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, -{"fmul", 1, 0xd8c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fmulp */ -{"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fmul", 1, 0xd8, 1, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fimul", 1, 0xde, 1, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fmulp", 0, 0xdec9, X, 0, FP, { 0, 0, 0} }, -{"fmulp", 2, 0xdec8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, - -/* divide */ -{"fdiv", 2, 0xd8f0, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fdiv", 1, 0xd8f0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fdivp */ -{"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fdiv", 1, 0xd8, 6, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fidiv", 1, 0xde, 6, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -#if SYSV386_COMPAT -{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT -{"fdivp", 2, 0xdef0, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif -#else -{"fdivp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, -#endif - -/* divide reverse */ -{"fdivr", 2, 0xd8f8, X, 0, FP|ShortForm|FloatDR, { FloatReg, FloatAcc, 0} }, -{"fdivr", 1, 0xd8f8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -#if SYSV386_COMPAT -/* alias for fdivrp */ -{"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} }, -#endif -{"fdivr", 1, 0xd8, 7, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fidivr", 1, 0xde, 7, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, - -#if SYSV386_COMPAT -{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivrp", 1, 0xdef8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivrp", 0, 0xdef9, X, 0, FP, { 0, 0, 0} }, -#if OLDGCC_COMPAT -{"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm|Ugh, { FloatReg, FloatAcc, 0} }, -#endif -#else -{"fdivrp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, -{"fdivrp", 1, 0xdef0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fdivrp", 0, 0xdef1, X, 0, FP, { 0, 0, 0} }, -#endif - -{"f2xm1", 0, 0xd9f0, X, 0, FP, { 0, 0, 0} }, -{"fyl2x", 0, 0xd9f1, X, 0, FP, { 0, 0, 0} }, -{"fptan", 0, 0xd9f2, X, 0, FP, { 0, 0, 0} }, -{"fpatan", 0, 0xd9f3, X, 0, FP, { 0, 0, 0} }, -{"fxtract",0, 0xd9f4, X, 0, FP, { 0, 0, 0} }, -{"fprem1", 0, 0xd9f5, X, Cpu286, FP, { 0, 0, 0} }, -{"fdecstp",0, 0xd9f6, X, 0, FP, { 0, 0, 0} }, -{"fincstp",0, 0xd9f7, X, 0, FP, { 0, 0, 0} }, -{"fprem", 0, 0xd9f8, X, 0, FP, { 0, 0, 0} }, -{"fyl2xp1",0, 0xd9f9, X, 0, FP, { 0, 0, 0} }, -{"fsqrt", 0, 0xd9fa, X, 0, FP, { 0, 0, 0} }, -{"fsincos",0, 0xd9fb, X, Cpu286, FP, { 0, 0, 0} }, -{"frndint",0, 0xd9fc, X, 0, FP, { 0, 0, 0} }, -{"fscale", 0, 0xd9fd, X, 0, FP, { 0, 0, 0} }, -{"fsin", 0, 0xd9fe, X, Cpu286, FP, { 0, 0, 0} }, -{"fcos", 0, 0xd9ff, X, Cpu286, FP, { 0, 0, 0} }, -{"fchs", 0, 0xd9e0, X, 0, FP, { 0, 0, 0} }, -{"fabs", 0, 0xd9e1, X, 0, FP, { 0, 0, 0} }, - -/* processor control */ -{"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} }, -{"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} }, -{"fldcw", 1, 0xd9, 5, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, -{"fnstcw", 1, 0xd9, 7, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, -{"fstcw", 1, 0xd9, 7, 0, w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} }, -/* XXX should reject %al, %eax, and %rax */ -{"fnstsw", 1, 0xdfe0, X, 0, FP|IgnoreSize, { Acc, 0, 0} }, -{"fnstsw", 1, 0xdd, 7, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, -{"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} }, -/* XXX should reject %al, %eax, and %rax */ -{"fstsw", 1, 0xdfe0, X, 0, FP|FWait|IgnoreSize, { Acc, 0, 0} }, -{"fstsw", 1, 0xdd, 7, 0, w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} }, -{"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} }, -{"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} }, -{"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} }, -/* Short forms of fldenv, fstenv use data size prefix. */ -{"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, -{"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm|DefaultSize, { LLongMem, 0, 0} }, -{"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, -{"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, -{"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm|DefaultSize, { LLongMem, 0, 0} }, -{"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, - -{"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -/* P6:free st(i), pop st */ -{"ffreep", 1, 0xdfc0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, -{"fnop", 0, 0xd9d0, X, 0, FP, { 0, 0, 0} }, +/* The opcode for the fwait instruction, which disassembler treats as a + prefix when it can. */ #define FWAIT_OPCODE 0x9b -{"fwait", 0, 0x9b, X, 0, FP, { 0, 0, 0} }, - -/* Opcode prefixes; we allow them as separate insns too. */ - #define ADDR_PREFIX_OPCODE 0x67 -{"addr16", 0, 0x67, X, Cpu386|CpuNo64, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"addr32", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, -{"aword", 0, 0x67, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"adword", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, #define DATA_PREFIX_OPCODE 0x66 -{"data16", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"data32", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, -{"word", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"dword", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, #define LOCK_PREFIX_OPCODE 0xf0 -{"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define CS_PREFIX_OPCODE 0x2e -{"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define DS_PREFIX_OPCODE 0x3e -{"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define ES_PREFIX_OPCODE 0x26 -{"es", 0, 0x26, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} }, #define FS_PREFIX_OPCODE 0x64 -{"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, #define GS_PREFIX_OPCODE 0x65 -{"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, #define SS_PREFIX_OPCODE 0x36 -{"ss", 0, 0x36, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} }, #define REPNE_PREFIX_OPCODE 0xf2 #define REPE_PREFIX_OPCODE 0xf3 -{"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repe", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repz", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repne", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"repnz", 0, 0xf2, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"ht", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"hnt", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex", 0, 0x40, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexz", 0, 0x41, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexy", 0, 0x42, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexyz", 0, 0x43, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexx", 0, 0x44, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexxz", 0, 0x45, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexxy", 0, 0x46, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rexxyz", 0, 0x47, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64", 0, 0x48, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64z", 0, 0x49, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64y", 0, 0x4a, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64yz",0, 0x4b, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64x", 0, 0x4c, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64xz",0, 0x4d, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64xy",0, 0x4e, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, -{"rex64xyz",0, 0x4f, X, Cpu64, NoSuf|IsPrefix, { 0, 0, 0} }, - -/* 486 extensions. */ - -{"bswap", 1, 0x0fc8, X, Cpu486, lq_Suf|ShortForm, { Reg32|Reg64, 0, 0 } }, -{"xadd", 2, 0x0fc0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, -{"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, -{"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} }, -{"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} }, -{"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm|IgnoreSize, { AnyMem, 0, 0} }, - -/* 586 and late 486 extensions. */ -{"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} }, - -/* Pentium extensions. */ -{"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} }, -{"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} }, -{"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} }, -{"cmpxchg8b",1,0x0fc7, 1, Cpu586, q_Suf|Modrm, { LLongMem, 0, 0} }, - -/* Pentium II/Pentium Pro extensions. */ -{"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} }, -{"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} }, -{"fxsave", 1, 0x0fae, 0, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} }, -{"fxrstor", 1, 0x0fae, 1, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} }, -{"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} }, -/* official undefined instr. */ -{"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, -/* alias for ud2 */ -{"ud2a", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, -/* 2nd. official undefined instr. */ -{"ud2b", 0, 0x0fb9, X, Cpu686, NoSuf, { 0, 0, 0} }, - -{"cmovo", 2, 0x0f40, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovno", 2, 0x0f41, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovb", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovc", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnae", 2, 0x0f42, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovae", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnc", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnb", 2, 0x0f43, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmove", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovz", 2, 0x0f44, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovne", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnz", 2, 0x0f45, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovbe", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovna", 2, 0x0f46, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmova", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnbe", 2, 0x0f47, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovs", 2, 0x0f48, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovns", 2, 0x0f49, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovp", 2, 0x0f4a, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnp", 2, 0x0f4b, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovl", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnge", 2, 0x0f4c, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovge", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnl", 2, 0x0f4d, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovle", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovng", 2, 0x0f4e, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovg", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"cmovnle", 2, 0x0f4f, X, Cpu686, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, - -{"fcmovb", 2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnae",2, 0xdac0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmove", 2, 0xdac8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovbe", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovna", 2, 0xdad0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovu", 2, 0xdad8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovae", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnb", 2, 0xdbc0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovne", 2, 0xdbc8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmova", 2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnbe",2, 0xdbd0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcmovnu", 2, 0xdbd8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, - -{"fcomi", 2, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcomi", 0, 0xdbf1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, -{"fcomi", 1, 0xdbf0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, -{"fucomi", 2, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucomi", 0, 0xdbe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, -{"fucomi", 1, 0xdbe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, -{"fcomip", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcompi", 2, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fcompi", 0, 0xdff1, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, -{"fcompi", 1, 0xdff0, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, -{"fucomip", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucompi", 2, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, FloatAcc, 0} }, -{"fucompi", 0, 0xdfe9, X, Cpu686, FP|ShortForm, { 0, 0, 0} }, -{"fucompi", 1, 0xdfe8, X, Cpu686, FP|ShortForm, { FloatReg, 0, 0} }, - -/* Pentium4 extensions. */ - -{"movnti", 2, 0x0fc3, X, CpuP4, wlq_Suf|Modrm, { WordReg, WordMem, 0 } }, -{"clflush", 1, 0x0fae, 7, CpuP4, NoSuf|Modrm|IgnoreSize, { ByteMem, 0, 0 } }, -{"lfence", 0, 0x0fae, 0xe8, CpuP4, NoSuf|ImmExt, { 0, 0, 0 } }, -{"mfence", 0, 0x0fae, 0xf0, CpuP4, NoSuf|ImmExt, { 0, 0, 0 } }, -{"pause", 0, 0xf390, X, CpuP4, NoSuf, { 0, 0, 0 } }, - -/* MMX/SSE2 instructions. */ - -{"emms", 0, 0x0f77, X, CpuMMX, NoSuf, { 0, 0, 0 } }, -/* These really shouldn't allow for Reg64 (movq is the right mnemonic for - copying between Reg64/Mem64 and RegXMM/RegMMX, as is mandated by Intel's - spec). AMD's spec, having been in existence for much longer, failed to - recognize that and specified movd for 32- and 64-bit operations. */ -{"movd", 2, 0x0f6e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegMMX, 0 } }, -{"movd", 2, 0x0f7e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64|LongMem, 0 } }, -{"movd", 2, 0x660f6e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegXMM, 0 } }, -{"movd", 2, 0x660f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64|LongMem, 0 } }, -/* In the 64bit mode the short form mov immediate is redefined to have - 64bit displacement value. */ -{"movq", 2, 0x0f6f, X, CpuMMX, NoSuf|IgnoreSize|Modrm|NoRex64, { RegMMX|LLongMem, RegMMX, 0 } }, -{"movq", 2, 0x0f7f, X, CpuMMX, NoSuf|IgnoreSize|Modrm|NoRex64, { RegMMX, RegMMX|LLongMem, 0 } }, -{"movq", 2, 0xf30f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm|NoRex64, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movq", 2, 0x660fd6,X,CpuSSE2,NoSuf|IgnoreSize|Modrm|NoRex64, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movq", 2, 0x0f6e, X, Cpu64, NoSuf|IgnoreSize|Modrm, { Reg64|LLongMem, RegMMX, 0 } }, -{"movq", 2, 0x0f7e, X, Cpu64, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg64|LLongMem, 0 } }, -{"movq", 2, 0x660f6e,X,Cpu64, NoSuf|IgnoreSize|Modrm, { Reg64|LLongMem, RegXMM, 0 } }, -{"movq", 2, 0x660f7e,X,Cpu64, NoSuf|IgnoreSize|Modrm, { RegXMM, Reg64|LLongMem, 0 } }, -/* We put the 64bit displacement first and we only mark constants - larger than 32bit as Disp64. */ -{"movq", 2, 0xa0, X, Cpu64, NoSuf|D|W|Size64, { Disp64, Acc, 0 } }, -{"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } }, -{"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } }, -{"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } }, -/* The segment register moves accept Reg64 so that a segment register - can be copied to a 64 bit register, and vice versa. */ -{"movq", 2, 0x8c, X, Cpu64, NoSuf|Modrm|Size64, { SReg2|SReg3, Reg64|InvMem, 0 } }, -{"movq", 2, 0x8e, X, Cpu64, NoSuf|Modrm|Size64, { Reg64, SReg2|SReg3, 0 } }, -/* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit - mode they are 64bit.*/ -{"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} }, -{"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} }, -/* Real MMX instructions. */ -{"packssdw", 2, 0x0f6b, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packssdw", 2, 0x660f6b,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"packsswb", 2, 0x0f63, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packsswb", 2, 0x660f63,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"packuswb", 2, 0x0f67, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packuswb", 2, 0x660f67,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddb", 2, 0x0ffc, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddb", 2, 0x660ffc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddw", 2, 0x0ffd, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddw", 2, 0x660ffd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddd", 2, 0x0ffe, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddd", 2, 0x660ffe,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddq", 2, 0x0fd4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"paddq", 2, 0x660fd4,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddsb", 2, 0x0fec, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsb", 2, 0x660fec,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddsw", 2, 0x0fed, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsw", 2, 0x660fed,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddusb", 2, 0x0fdc, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusb", 2, 0x660fdc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddusw", 2, 0x0fdd, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusw", 2, 0x660fdd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pand", 2, 0x0fdb, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pand", 2, 0x660fdb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pandn", 2, 0x0fdf, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pandn", 2, 0x660fdf,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpeqb", 2, 0x0f74, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqb", 2, 0x660f74,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpeqw", 2, 0x0f75, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqw", 2, 0x660f75,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpeqd", 2, 0x0f76, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqd", 2, 0x660f76,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpgtb", 2, 0x0f64, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtb", 2, 0x660f64,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpgtw", 2, 0x0f65, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtw", 2, 0x660f65,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpgtd", 2, 0x0f66, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtd", 2, 0x660f66,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmaddwd", 2, 0x0ff5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmaddwd", 2, 0x660ff5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmulhw", 2, 0x0fe5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhw", 2, 0x660fe5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmullw", 2, 0x0fd5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmullw", 2, 0x660fd5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"por", 2, 0x0feb, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"por", 2, 0x660feb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psllw", 2, 0x0ff1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllw", 2, 0x660ff1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psllw", 2, 0x0f71, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"psllw", 2, 0x660f71,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"pslld", 2, 0x0ff2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pslld", 2, 0x660ff2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pslld", 2, 0x0f72, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"pslld", 2, 0x660f72,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psllq", 2, 0x0ff3, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllq", 2, 0x660ff3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psllq", 2, 0x0f73, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"psllq", 2, 0x660f73,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psraw", 2, 0x0fe1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psraw", 2, 0x660fe1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psraw", 2, 0x0f71, 4, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"psraw", 2, 0x660f71,4,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psrad", 2, 0x0fe2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrad", 2, 0x660fe2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrad", 2, 0x0f72, 4, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"psrad", 2, 0x660f72,4,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psrlw", 2, 0x0fd1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlw", 2, 0x660fd1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrlw", 2, 0x0f71, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlw", 2, 0x660f71,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psrld", 2, 0x0fd2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrld", 2, 0x660fd2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrld", 2, 0x0f72, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"psrld", 2, 0x660f72,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psrlq", 2, 0x0fd3, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlq", 2, 0x660fd3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrlq", 2, 0x0f73, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlq", 2, 0x660f73,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psubb", 2, 0x0ff8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubb", 2, 0x660ff8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubw", 2, 0x0ff9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubw", 2, 0x660ff9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubd", 2, 0x0ffa, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubd", 2, 0x660ffa,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubq", 2, 0x0ffb, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"psubq", 2, 0x660ffb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubsb", 2, 0x0fe8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsb", 2, 0x660fe8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubsw", 2, 0x0fe9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsw", 2, 0x660fe9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubusb", 2, 0x0fd8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusb", 2, 0x660fd8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubusw", 2, 0x0fd9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusw", 2, 0x660fd9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckhbw",2, 0x0f68, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhbw",2, 0x660f68,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckhwd",2, 0x0f69, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhwd",2, 0x660f69,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckhdq",2, 0x0f6a, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhdq",2, 0x660f6a,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpcklbw",2, 0x0f60, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklbw",2, 0x660f60,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpcklwd",2, 0x0f61, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklwd",2, 0x660f61,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckldq",2, 0x0f62, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckldq",2, 0x660f62,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pxor", 2, 0x0fef, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pxor", 2, 0x660fef,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, - -/* PIII Katmai New Instructions / SIMD instructions. */ - -{"addps", 2, 0x0f58, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"addss", 2, 0xf30f58, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"andnps", 2, 0x0f55, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"andps", 2, 0x0f54, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpeqps", 2, 0x0fc2, 0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpleps", 2, 0x0fc2, 2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpless", 2, 0xf30fc2, 2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpltps", 2, 0x0fc2, 1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpltss", 2, 0xf30fc2, 1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpneqps", 2, 0x0fc2, 4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpnleps", 2, 0x0fc2, 6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnless", 2, 0xf30fc2, 6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpnltps", 2, 0x0fc2, 5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpordps", 2, 0x0fc2, 7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpordss", 2, 0xf30fc2, 7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpunordps",2, 0x0fc2, 3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpunordss",2, 0xf30fc2, 3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpps", 3, 0x0fc2, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"cmpss", 3, 0xf30fc2, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, -{"comiss", 2, 0x0f2f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, -{"cvtps2pi", 2, 0x0f2d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, -{"cvtss2si", 2, 0xf30f2d, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, -{"cvttps2pi", 2, 0x0f2c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvttss2si", 2, 0xf30f2c, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } }, -{"divps", 2, 0x0f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"divss", 2, 0xf30f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } }, -{"maskmovq", 2, 0x0ff7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, -{"maxps", 2, 0x0f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"maxss", 2, 0xf30f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"minps", 2, 0x0f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"minss", 2, 0xf30f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"movaps", 2, 0x0f28, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movaps", 2, 0x0f29, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movhlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, -{"movhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, -{"movhps", 2, 0x0f17, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, -{"movlhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, -{"movlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, -{"movlps", 2, 0x0f13, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, -{"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, -{"movntps", 2, 0x0f2b, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, -{"movntq", 2, 0x0fe7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX, LLongMem, 0 } }, -{"movntdq", 2, 0x660fe7, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, -{"movss", 2, 0xf30f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"movss", 2, 0xf30f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, -{"movups", 2, 0x0f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movups", 2, 0x0f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"mulps", 2, 0x0f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"mulss", 2, 0xf30f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"orps", 2, 0x0f56, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pavgb", 2, 0x0fe0, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pavgb", 2, 0x660fe0, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pavgw", 2, 0x0fe3, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pavgw", 2, 0x660fe3, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pextrw", 3, 0x0fc5, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } }, -{"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } }, -{"pinsrw", 3, 0x0fc4, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } }, -{"pinsrw", 3, 0x660fc4, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } }, -{"pmaxsw", 2, 0x0fee, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pmaxsw", 2, 0x660fee, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmaxub", 2, 0x0fde, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pmaxub", 2, 0x660fde, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pminsw", 2, 0x0fea, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pminsw", 2, 0x660fea, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pminub", 2, 0x0fda, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pminub", 2, 0x660fda, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmovmskb", 2, 0x0fd7, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } }, -{"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, -{"pmulhuw", 2, 0x0fe4, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pmulhuw", 2, 0x660fe4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"prefetchnta", 1, 0x0f18, 0, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht0", 1, 0x0f18, 1, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht1", 1, 0x0f18, 2, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht2", 1, 0x0f18, 3, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, -{"psadbw", 2, 0x0ff6, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"psadbw", 2, 0x660ff6, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pshufw", 3, 0x0f70, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, -{"rcpps", 2, 0x0f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"rcpss", 2, 0xf30f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"rsqrtps", 2, 0x0f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"rsqrtss", 2, 0xf30f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"sfence", 0, 0x0fae, 0xf8, CpuMMX2,NoSuf|IgnoreSize|ImmExt, { 0, 0, 0 } }, -{"shufps", 3, 0x0fc6, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"sqrtps", 2, 0x0f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"sqrtss", 2, 0xf30f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"stmxcsr", 1, 0x0fae, 3, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } }, -{"subps", 2, 0x0f5c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"subss", 2, 0xf30f5c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"ucomiss", 2, 0x0f2e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"unpckhps", 2, 0x0f15, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"unpcklps", 2, 0x0f14, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"xorps", 2, 0x0f57, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, - -/* SSE-2 instructions. */ - -{"addpd", 2, 0x660f58, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"addsd", 2, 0xf20f58, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"andnpd", 2, 0x660f55, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"andpd", 2, 0x660f54, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpeqpd", 2, 0x660fc2, 0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpeqsd", 2, 0xf20fc2, 0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmplepd", 2, 0x660fc2, 2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmplesd", 2, 0xf20fc2, 2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpltpd", 2, 0x660fc2, 1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpltsd", 2, 0xf20fc2, 1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpneqpd", 2, 0x660fc2, 4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpneqsd", 2, 0xf20fc2, 4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpnlepd", 2, 0x660fc2, 6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnlesd", 2, 0xf20fc2, 6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpnltpd", 2, 0x660fc2, 5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnltsd", 2, 0xf20fc2, 5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpordpd", 2, 0x660fc2, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpordsd", 2, 0xf20fc2, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmppd", 3, 0x660fc2, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -/* Intel mode string compare. */ -{"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, -{"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"cmpsd", 3, 0xf20fc2, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LongMem, RegXMM } }, -{"comisd", 2, 0x660f2f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, -{"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, -{"divpd", 2, 0x660f5e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"divsd", 2, 0xf20f5e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"maxpd", 2, 0x660f5f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"maxsd", 2, 0xf20f5f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"minpd", 2, 0x660f5d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"minsd", 2, 0xf20f5d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"movapd", 2, 0x660f28, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movapd", 2, 0x660f29, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movhpd", 2, 0x660f16, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, -{"movhpd", 2, 0x660f17, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, -{"movlpd", 2, 0x660f12, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, -{"movlpd", 2, 0x660f13, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, -{"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, -{"movntpd", 2, 0x660f2b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, -/* Intel mode string move. */ -{"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, -{"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"movsd", 2, 0xf20f10, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"movsd", 2, 0xf20f11, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LongMem, 0 } }, -{"movupd", 2, 0x660f10, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movupd", 2, 0x660f11, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"mulpd", 2, 0x660f59, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"mulsd", 2, 0xf20f59, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"orpd", 2, 0x660f56, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"shufpd", 3, 0x660fc6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"sqrtpd", 2, 0x660f51, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"sqrtsd", 2, 0xf20f51, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"subpd", 2, 0x660f5c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"subsd", 2, 0xf20f5c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"ucomisd", 2, 0x660f2e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"unpckhpd", 2, 0x660f15, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"unpcklpd", 2, 0x660f14, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"xorpd", 2, 0x660f57, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtdq2pd", 2, 0xf30fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtpd2dq", 2, 0xf20fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtdq2ps", 2, 0x0f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtpd2pi", 2, 0x660f2d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtsd2si", 2, 0xf20f2d, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } }, -{"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, -{"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"maskmovdqu",2, 0x660ff7, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, -{"movdqa", 2, 0x660f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movdqa", 2, 0x660f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movdqu", 2, 0xf30f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movdqu", 2, 0xf30f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movdq2q", 2, 0xf20fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegMMX, 0 } }, -{"movq2dq", 2, 0xf30fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegXMM, 0 } }, -{"pmuludq", 2, 0x0ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmuludq", 2, 0x660ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"pshufd", 3, 0x660f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"pshufhw", 3, 0xf30f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"pshuflw", 3, 0xf20f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"pslldq", 2, 0x660f73, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"psrldq", 2, 0x660f73, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, -{"punpckhqdq",2, 0x660f6d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpcklqdq",2, 0x660f6c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, - -/* Prescott New Instructions. */ - -{"addsubpd", 2, 0x660fd0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"addsubps", 2, 0xf20fd0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpxchg16b",1, 0x0fc7, 1, CpuPNI|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} }, -{"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, -{"fisttp", 1, 0xdd, 1, CpuPNI, q_FP|Modrm, { LLongMem, 0, 0} }, -{"fisttpll", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, -{"haddpd", 2, 0x660f7c, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"haddps", 2, 0xf20f7c, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"hsubpd", 2, 0x660f7d, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"hsubps", 2, 0xf20f7d, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"lddqu", 2, 0xf20ff0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, -{"monitor", 0, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt, { 0, 0, 0} }, -/* monitor is very special. CX and DX are always 64bits with zero upper - 32bits in 64bit mode, and 32bits in 16bit and 32bit modes. The - address size override prefix can be used to overrride the AX size in - all modes. */ -/* Need to ensure only "monitor %eax/%ax,%ecx,%edx" is accepted. */ -{"monitor", 3, 0x0f01, 0xc8, CpuPNI|CpuNo64, NoSuf|ImmExt, { Reg16|Reg32, Reg32, Reg32 } }, -/* Need to ensure only "monitor %rax/%eax,%rcx,%rdx" is accepted. */ -{"monitor", 3, 0x0f01, 0xc8, CpuPNI|Cpu64, NoSuf|ImmExt|NoRex64, { Reg32|Reg64, Reg64, Reg64 } }, -{"movddup", 2, 0xf20f12, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movshdup", 2, 0xf30f16, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movsldup", 2, 0xf30f12, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"mwait", 0, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt, { 0, 0, 0} }, -/* mwait is very special. AX and CX are always 64bits with zero upper - 32bits in 64bit mode, and 32bits in 16bit and 32bit modes. */ -/* Need to ensure only "mwait %eax,%ecx" is accepted. */ -{"mwait", 2, 0x0f01, 0xc9, CpuPNI|CpuNo64, NoSuf|ImmExt, { Reg32, Reg32, 0} }, -/* Need to ensure only "mwait %rax,%rcx" is accepted. */ -{"mwait", 2, 0x0f01, 0xc9, CpuPNI|Cpu64, NoSuf|ImmExt|NoRex64, { Reg64, Reg64, 0} }, - -/* VMX instructions. */ -{"vmcall", 0, 0x0f01, 0xc1, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, -{"vmclear", 1, 0x660fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"vmlaunch", 0, 0x0f01, 0xc2, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, -{"vmresume", 0, 0x0f01, 0xc3, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, -{"vmptrld", 1, 0x0fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"vmptrst", 1, 0x0fc7, 7, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, -{"vmread", 2, 0x0f78, X, CpuVMX|CpuNo64, l_Suf|Modrm,{ Reg32, Reg32|LongMem, 0} }, -{"vmread", 2, 0x0f78, X, CpuVMX|Cpu64, q_Suf|Modrm|NoRex64,{ Reg64, Reg64|LLongMem, 0} }, -{"vmwrite", 2, 0x0f79, X, CpuVMX|CpuNo64, l_Suf|Modrm,{ Reg32|LongMem, Reg32, 0} }, -{"vmwrite", 2, 0x0f79, X, CpuVMX|Cpu64, q_Suf|Modrm|NoRex64,{ Reg64|LLongMem, Reg64, 0} }, -{"vmxoff", 0, 0x0f01, 0xc4, CpuVMX, NoSuf|ImmExt, { 0, 0, 0} }, -{"vmxon", 1, 0xf30fc7, 6, CpuVMX, NoSuf|IgnoreSize|Modrm|NoRex64, { LLongMem, 0, 0} }, - -/* Merom New Instructions. */ - -{"phaddw", 2, 0x0f3801,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"phaddw", 2, 0x660f3801,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"phaddd", 2, 0x0f3802,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"phaddd", 2, 0x660f3802,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"phaddsw", 2, 0x0f3803,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"phaddsw", 2, 0x660f3803,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"phsubw", 2, 0x0f3805,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"phsubw", 2, 0x660f3805,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"phsubd", 2, 0x0f3806,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"phsubd", 2, 0x660f3806,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"phsubsw", 2, 0x0f3807,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"phsubsw", 2, 0x660f3807,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmaddubsw", 2, 0x0f3804,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmaddubsw", 2, 0x660f3804,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmulhrsw", 2, 0x0f380b,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhrsw", 2, 0x660f380b,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pshufb", 2, 0x0f3800,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pshufb", 2, 0x660f3800,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psignb", 2, 0x0f3808,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psignb", 2, 0x660f3808,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psignw", 2, 0x0f3809,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psignw", 2, 0x660f3809,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psignd", 2, 0x0f380a,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psignd", 2, 0x660f380a,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"palignr", 3, 0x0f3a0f,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LongMem, RegMMX } }, -{"palignr", 3, 0x660f3a0f,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"pabsb", 2, 0x0f381c,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pabsb", 2, 0x660f381c,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pabsw", 2, 0x0f381d,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pabsw", 2, 0x660f381d,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pabsd", 2, 0x0f381e,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pabsd", 2, 0x660f381e,X, CpuMNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, - -/* AMD 3DNow! instructions. */ - -{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } }, -{"prefetchw",1, 0x0f0d, 1, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } }, -{"femms", 0, 0x0f0e, X, Cpu3dnow, NoSuf, { 0, 0, 0 } }, -{"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -/* AMD extensions. */ -{"syscall", 0, 0x0f05, X, CpuK6, NoSuf, { 0, 0, 0} }, -{"sysret", 0, 0x0f07, X, CpuK6, lq_Suf|DefaultSize, { 0, 0, 0} }, -{"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} }, -{"rdtscp", 0, 0x0f01, 0xf9, CpuSledgehammer,NoSuf|ImmExt, { 0, 0, 0} }, +#define TWO_BYTE_OPCODE_ESCAPE 0x0f +#define NOP_OPCODE (char) 0x90 -/* AMD Pacifica additions. */ -{"clgi", 0, 0x0f01, 0xdd, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -{"invlpga", 0, 0x0f01, 0xdf, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -/* Need to ensure only "invlpga ...,%ecx" is accepted. */ -{"invlpga", 2, 0x0f01, 0xdf, CpuSVME, NoSuf|ImmExt, { AnyMem, Reg32, 0 } }, -{"skinit", 0, 0x0f01, 0xde, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -{"skinit", 1, 0x0f01, 0xde, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, -{"stgi", 0, 0x0f01, 0xdc, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -{"vmload", 0, 0x0f01, 0xda, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -{"vmload", 1, 0x0f01, 0xda, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, -{"vmmcall", 0, 0x0f01, 0xd9, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -{"vmrun", 0, 0x0f01, 0xd8, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -{"vmrun", 1, 0x0f01, 0xd8, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, -{"vmsave", 0, 0x0f01, 0xdb, CpuSVME, NoSuf|ImmExt, { 0, 0, 0 } }, -{"vmsave", 1, 0x0f01, 0xdb, CpuSVME, NoSuf|ImmExt, { AnyMem, 0, 0 } }, +/* register numbers */ +#define EBP_REG_NUM 5 +#define ESP_REG_NUM 4 -/* VIA PadLock extensions. */ -{"xstore-rng",0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcrypt-ecb",0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcrypt-cbc",0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcrypt-ctr",0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcrypt-cfb",0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcrypt-ofb",0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"montmul", 0, 0xf30fa6, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xsha1", 0, 0xf30fa6, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xsha256", 0, 0xf30fa6, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -/* Aliases without hyphens. */ -{"xstorerng", 0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcryptecb", 0, 0xf30fa7, 0xc8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcryptcbc", 0, 0xf30fa7, 0xd0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcryptctr", 0, 0xf30fa7, 0xd8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcryptcfb", 0, 0xf30fa7, 0xe0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -{"xcryptofb", 0, 0xf30fa7, 0xe8, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, -/* Alias for xstore-rng. */ -{"xstore", 0, 0x000fa7, 0xc0, Cpu686|CpuPadLock, NoSuf|IsString|ImmExt, { 0, 0, 0} }, +/* modrm_byte.regmem for twobyte escape */ +#define ESCAPE_TO_TWO_BYTE_ADDRESSING ESP_REG_NUM +/* index_base_byte.index for no index register addressing */ +#define NO_INDEX_REGISTER ESP_REG_NUM +/* index_base_byte.base for no base register addressing */ +#define NO_BASE_REGISTER EBP_REG_NUM +#define NO_BASE_REGISTER_16 6 -/* sentinel */ -{NULL, 0, 0, 0, 0, 0, { 0, 0, 0} } -}; -#undef X -#undef NoSuf -#undef b_Suf -#undef w_Suf -#undef l_Suf -#undef q_Suf -#undef x_Suf -#undef bw_Suf -#undef bl_Suf -#undef wl_Suf -#undef wlq_Suf -#undef sl_Suf -#undef bwl_Suf -#undef bwlq_Suf -#undef FP -#undef l_FP -#undef q_FP -#undef x_FP -#undef sl_FP +/* modrm.mode = REGMEM_FIELD_HAS_REG when a register is in there */ +#define REGMEM_FIELD_HAS_REG 0x3/* always = 0x3 */ +#define REGMEM_FIELD_HAS_MEM (~REGMEM_FIELD_HAS_REG) -#define MAX_MNEM_SIZE 16 /* For parsing insn mnemonics from input. */ +/* x86-64 extension prefix. */ +#define REX_OPCODE 0x40 -/* 386 register table. */ +/* Indicates 64 bit operand size. */ +#define REX_W 8 +/* High extension to reg field of modrm byte. */ +#define REX_R 4 +/* High extension to SIB index field. */ +#define REX_X 2 +/* High extension to base field of modrm or SIB, or reg field of opcode. */ +#define REX_B 1 -static const reg_entry i386_regtab[] = -{ - /* Make %st first as we test for it. */ - {"st", FloatReg|FloatAcc, 0, 0}, - /* 8 bit regs */ -#define REGNAM_AL 1 /* Entry in i386_regtab. */ - {"al", Reg8|Acc, 0, 0}, - {"cl", Reg8|ShiftCount, 0, 1}, - {"dl", Reg8, 0, 2}, - {"bl", Reg8, 0, 3}, - {"ah", Reg8, 0, 4}, - {"ch", Reg8, 0, 5}, - {"dh", Reg8, 0, 6}, - {"bh", Reg8, 0, 7}, - {"axl", Reg8|Acc, RegRex64, 0}, /* Must be in the "al + 8" slot. */ - {"cxl", Reg8, RegRex64, 1}, - {"dxl", Reg8, RegRex64, 2}, - {"bxl", Reg8, RegRex64, 3}, - {"spl", Reg8, RegRex64, 4}, - {"bpl", Reg8, RegRex64, 5}, - {"sil", Reg8, RegRex64, 6}, - {"dil", Reg8, RegRex64, 7}, - {"r8b", Reg8, RegRex64|RegRex, 0}, - {"r9b", Reg8, RegRex64|RegRex, 1}, - {"r10b", Reg8, RegRex64|RegRex, 2}, - {"r11b", Reg8, RegRex64|RegRex, 3}, - {"r12b", Reg8, RegRex64|RegRex, 4}, - {"r13b", Reg8, RegRex64|RegRex, 5}, - {"r14b", Reg8, RegRex64|RegRex, 6}, - {"r15b", Reg8, RegRex64|RegRex, 7}, - /* 16 bit regs */ -#define REGNAM_AX 25 - {"ax", Reg16|Acc, 0, 0}, - {"cx", Reg16, 0, 1}, - {"dx", Reg16|InOutPortReg, 0, 2}, - {"bx", Reg16|BaseIndex, 0, 3}, - {"sp", Reg16, 0, 4}, - {"bp", Reg16|BaseIndex, 0, 5}, - {"si", Reg16|BaseIndex, 0, 6}, - {"di", Reg16|BaseIndex, 0, 7}, - {"r8w", Reg16, RegRex, 0}, - {"r9w", Reg16, RegRex, 1}, - {"r10w", Reg16, RegRex, 2}, - {"r11w", Reg16, RegRex, 3}, - {"r12w", Reg16, RegRex, 4}, - {"r13w", Reg16, RegRex, 5}, - {"r14w", Reg16, RegRex, 6}, - {"r15w", Reg16, RegRex, 7}, - /* 32 bit regs */ -#define REGNAM_EAX 41 - {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot. */ - {"ecx", Reg32|BaseIndex, 0, 1}, - {"edx", Reg32|BaseIndex, 0, 2}, - {"ebx", Reg32|BaseIndex, 0, 3}, - {"esp", Reg32, 0, 4}, - {"ebp", Reg32|BaseIndex, 0, 5}, - {"esi", Reg32|BaseIndex, 0, 6}, - {"edi", Reg32|BaseIndex, 0, 7}, - {"r8d", Reg32|BaseIndex, RegRex, 0}, - {"r9d", Reg32|BaseIndex, RegRex, 1}, - {"r10d", Reg32|BaseIndex, RegRex, 2}, - {"r11d", Reg32|BaseIndex, RegRex, 3}, - {"r12d", Reg32|BaseIndex, RegRex, 4}, - {"r13d", Reg32|BaseIndex, RegRex, 5}, - {"r14d", Reg32|BaseIndex, RegRex, 6}, - {"r15d", Reg32|BaseIndex, RegRex, 7}, - {"rax", Reg64|BaseIndex|Acc, 0, 0}, - {"rcx", Reg64|BaseIndex, 0, 1}, - {"rdx", Reg64|BaseIndex, 0, 2}, - {"rbx", Reg64|BaseIndex, 0, 3}, - {"rsp", Reg64, 0, 4}, - {"rbp", Reg64|BaseIndex, 0, 5}, - {"rsi", Reg64|BaseIndex, 0, 6}, - {"rdi", Reg64|BaseIndex, 0, 7}, - {"r8", Reg64|BaseIndex, RegRex, 0}, - {"r9", Reg64|BaseIndex, RegRex, 1}, - {"r10", Reg64|BaseIndex, RegRex, 2}, - {"r11", Reg64|BaseIndex, RegRex, 3}, - {"r12", Reg64|BaseIndex, RegRex, 4}, - {"r13", Reg64|BaseIndex, RegRex, 5}, - {"r14", Reg64|BaseIndex, RegRex, 6}, - {"r15", Reg64|BaseIndex, RegRex, 7}, - /* Segment registers. */ - {"es", SReg2, 0, 0}, - {"cs", SReg2, 0, 1}, - {"ss", SReg2, 0, 2}, - {"ds", SReg2, 0, 3}, - {"fs", SReg3, 0, 4}, - {"gs", SReg3, 0, 5}, - /* Control registers. */ - {"cr0", Control, 0, 0}, - {"cr1", Control, 0, 1}, - {"cr2", Control, 0, 2}, - {"cr3", Control, 0, 3}, - {"cr4", Control, 0, 4}, - {"cr5", Control, 0, 5}, - {"cr6", Control, 0, 6}, - {"cr7", Control, 0, 7}, - {"cr8", Control, RegRex, 0}, - {"cr9", Control, RegRex, 1}, - {"cr10", Control, RegRex, 2}, - {"cr11", Control, RegRex, 3}, - {"cr12", Control, RegRex, 4}, - {"cr13", Control, RegRex, 5}, - {"cr14", Control, RegRex, 6}, - {"cr15", Control, RegRex, 7}, - /* Debug registers. */ - {"db0", Debug, 0, 0}, - {"db1", Debug, 0, 1}, - {"db2", Debug, 0, 2}, - {"db3", Debug, 0, 3}, - {"db4", Debug, 0, 4}, - {"db5", Debug, 0, 5}, - {"db6", Debug, 0, 6}, - {"db7", Debug, 0, 7}, - {"db8", Debug, RegRex, 0}, - {"db9", Debug, RegRex, 1}, - {"db10", Debug, RegRex, 2}, - {"db11", Debug, RegRex, 3}, - {"db12", Debug, RegRex, 4}, - {"db13", Debug, RegRex, 5}, - {"db14", Debug, RegRex, 6}, - {"db15", Debug, RegRex, 7}, - {"dr0", Debug, 0, 0}, - {"dr1", Debug, 0, 1}, - {"dr2", Debug, 0, 2}, - {"dr3", Debug, 0, 3}, - {"dr4", Debug, 0, 4}, - {"dr5", Debug, 0, 5}, - {"dr6", Debug, 0, 6}, - {"dr7", Debug, 0, 7}, - {"dr8", Debug, RegRex, 0}, - {"dr9", Debug, RegRex, 1}, - {"dr10", Debug, RegRex, 2}, - {"dr11", Debug, RegRex, 3}, - {"dr12", Debug, RegRex, 4}, - {"dr13", Debug, RegRex, 5}, - {"dr14", Debug, RegRex, 6}, - {"dr15", Debug, RegRex, 7}, - /* Test registers. */ - {"tr0", Test, 0, 0}, - {"tr1", Test, 0, 1}, - {"tr2", Test, 0, 2}, - {"tr3", Test, 0, 3}, - {"tr4", Test, 0, 4}, - {"tr5", Test, 0, 5}, - {"tr6", Test, 0, 6}, - {"tr7", Test, 0, 7}, - /* MMX and simd registers. */ - {"mm0", RegMMX, 0, 0}, - {"mm1", RegMMX, 0, 1}, - {"mm2", RegMMX, 0, 2}, - {"mm3", RegMMX, 0, 3}, - {"mm4", RegMMX, 0, 4}, - {"mm5", RegMMX, 0, 5}, - {"mm6", RegMMX, 0, 6}, - {"mm7", RegMMX, 0, 7}, - {"xmm0", RegXMM, 0, 0}, - {"xmm1", RegXMM, 0, 1}, - {"xmm2", RegXMM, 0, 2}, - {"xmm3", RegXMM, 0, 3}, - {"xmm4", RegXMM, 0, 4}, - {"xmm5", RegXMM, 0, 5}, - {"xmm6", RegXMM, 0, 6}, - {"xmm7", RegXMM, 0, 7}, - {"xmm8", RegXMM, RegRex, 0}, - {"xmm9", RegXMM, RegRex, 1}, - {"xmm10", RegXMM, RegRex, 2}, - {"xmm11", RegXMM, RegRex, 3}, - {"xmm12", RegXMM, RegRex, 4}, - {"xmm13", RegXMM, RegRex, 5}, - {"xmm14", RegXMM, RegRex, 6}, - {"xmm15", RegXMM, RegRex, 7}, - /* No type will make this register rejected for all purposes except - for addressing. This saves creating one extra type for RIP. */ - {"rip", BaseIndex, 0, 0} -}; +/* max operands per insn */ +#define MAX_OPERANDS 4 -static const reg_entry i386_float_regtab[] = -{ - {"st(0)", FloatReg|FloatAcc, 0, 0}, - {"st(1)", FloatReg, 0, 1}, - {"st(2)", FloatReg, 0, 2}, - {"st(3)", FloatReg, 0, 3}, - {"st(4)", FloatReg, 0, 4}, - {"st(5)", FloatReg, 0, 5}, - {"st(6)", FloatReg, 0, 6}, - {"st(7)", FloatReg, 0, 7} -}; +/* max immediates per insn (lcall, ljmp, insertq, extrq) */ +#define MAX_IMMEDIATE_OPERANDS 2 -#define MAX_REG_NAME_SIZE 8 /* For parsing register names from input. */ +/* max memory refs per insn (string ops) */ +#define MAX_MEMORY_OPERANDS 2 -/* Segment stuff. */ -static const seg_entry cs = { "cs", 0x2e }; -static const seg_entry ds = { "ds", 0x3e }; -static const seg_entry ss = { "ss", 0x36 }; -static const seg_entry es = { "es", 0x26 }; -static const seg_entry fs = { "fs", 0x64 }; -static const seg_entry gs = { "gs", 0x65 }; +/* max size of insn mnemonics. */ +#define MAX_MNEM_SIZE 16 +/* max size of register name in insn mnemonics. */ +#define MAX_REG_NAME_SIZE 8 diff --git a/contrib/binutils/include/opcode/mips.h b/contrib/binutils/include/opcode/mips.h index 1544854..2d321c8 100644 --- a/contrib/binutils/include/opcode/mips.h +++ b/contrib/binutils/include/opcode/mips.h @@ -171,6 +171,8 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US #define OP_MASK_WRDSP 0x3f #define OP_SH_RDDSP 16 #define OP_MASK_RDDSP 0x3f +#define OP_SH_BP 11 +#define OP_MASK_BP 0x3 /* MIPS MT ASE */ #define OP_SH_MT_U 5 @@ -205,6 +207,16 @@ Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, US #define MDMX_FMTSEL_VEC_QH 0x15 #define MDMX_FMTSEL_VEC_OB 0x16 +/* UDI */ +#define OP_SH_UDI1 6 +#define OP_MASK_UDI1 0x1f +#define OP_SH_UDI2 6 +#define OP_MASK_UDI2 0x3ff +#define OP_SH_UDI3 6 +#define OP_MASK_UDI3 0x7fff +#define OP_SH_UDI4 6 +#define OP_MASK_UDI4 0xfffff + /* This structure holds information for a particular instruction. */ struct mips_opcode @@ -273,19 +285,20 @@ struct mips_opcode "y" 10 bit signed const (OP_*_CODE2) "z" must be zero register "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD) - "+A" 5 bit ins/ext position, which becomes LSB (OP_*_SHAMT). + "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes + LSB (OP_*_SHAMT). Enforces: 0 <= pos < 32. - "+B" 5 bit ins size, which becomes MSB (OP_*_INSMSB). + "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB). Requires that "+A" or "+E" occur first to set position. Enforces: 0 < (pos+size) <= 32. - "+C" 5 bit ext size, which becomes MSBD (OP_*_EXTMSBD). + "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD). Requires that "+A" or "+E" occur first to set position. Enforces: 0 < (pos+size) <= 32. (Also used by "dext" w/ different limits, but limits for that are checked by the M_DEXT macro.) - "+E" 5 bit dins/dext position, which becomes LSB-32 (OP_*_SHAMT). + "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT). Enforces: 32 <= pos < 64. - "+F" 5 bit "dinsm" size, which becomes MSB-32 (OP_*_INSMSB). + "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB). Requires that "+A" or "+E" occur first to set position. Enforces: 32 < (pos+size) <= 64. "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD). @@ -334,6 +347,7 @@ struct mips_opcode "Z" MDMX source register (OP_*_FT) DSP ASE usage: + "2" 2 bit unsigned immediate for byte align (OP_*_BP) "3" 3 bit unsigned immediate (OP_*_SA3) "4" 4 bit unsigned immediate (OP_*_SA4) "5" 8 bit unsigned immediate (OP_*_IMM8) @@ -347,14 +361,20 @@ struct mips_opcode "@" 10 bit signed immediate (OP_*_IMM10) MT ASE usage: - "!" 1 bit immediate at bit 5 - "$" 1 bit immediate at bit 4 + "!" 1 bit usermode flag (OP_*_MT_U) + "$" 1 bit load high flag (OP_*_MT_H) "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T) "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D) "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD) "+t" 5 bit coprocessor 0 destination register (OP_*_RT) "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only + UDI immediates: + "+1" UDI immediate bits 6-10 + "+2" UDI immediate bits 6-15 + "+3" UDI immediate bits 6-20 + "+4" UDI immediate bits 6-25 + Other: "()" parens surrounding optional value "," separates operands @@ -362,13 +382,14 @@ struct mips_opcode "+" Start of extension sequence. Characters used so far, for quick reference when adding more: - "34567890" + "234567890" "%[]<>(),+:'@!$*&^~" "ABCDEFGHIJKLMNOPQRSTUVWXYZ" "abcdefghijklopqrstuvwxyz" Extension character sequences used so far ("+" followed by the following), for quick reference when adding more: + "1234" "ABCDEFGHIT" "t" */ @@ -472,16 +493,15 @@ struct mips_opcode #define INSN_ISA64R2 0x00000100 /* Masks used for MIPS-defined ASEs. */ -#define INSN_ASE_MASK 0x0400f000 +#define INSN_ASE_MASK 0x3c00f000 /* DSP ASE */ #define INSN_DSP 0x00001000 +#define INSN_DSP64 0x00002000 /* MIPS 16 ASE */ -#define INSN_MIPS16 0x00002000 +#define INSN_MIPS16 0x00004000 /* MIPS-3D ASE */ -#define INSN_MIPS3D 0x00004000 -/* MDMX ASE */ -#define INSN_MDMX 0x00008000 +#define INSN_MIPS3D 0x00008000 /* Chip specific instructions. These are bitmasks. */ @@ -505,8 +525,15 @@ struct mips_opcode #define INSN_5400 0x01000000 /* NEC VR5500 instruction. */ #define INSN_5500 0x02000000 + +/* MDMX ASE */ +#define INSN_MDMX 0x04000000 /* MT ASE */ -#define INSN_MT 0x04000000 +#define INSN_MT 0x08000000 +/* SmartMIPS ASE */ +#define INSN_SMARTMIPS 0x10000000 +/* DSP R2 ASE */ +#define INSN_DSPR2 0x20000000 /* Cavium Networks Octeon instruction. */ #define INSN_OCTEON 0x08000000 @@ -595,6 +622,7 @@ enum M_ADD_I, M_ADDU_I, M_AND_I, + M_BALIGN, M_BEQ, M_BEQ_I, M_BEQL_I, @@ -633,6 +661,7 @@ enum M_BNE, M_BNE_I, M_BNEL_I, + M_CACHE_AB, M_DABS, M_DADD_I, M_DADDU_I, diff --git a/contrib/binutils/include/opcode/ppc.h b/contrib/binutils/include/opcode/ppc.h index f662630..6771856 100644 --- a/contrib/binutils/include/opcode/ppc.h +++ b/contrib/binutils/include/opcode/ppc.h @@ -1,6 +1,6 @@ /* ppc.h -- Header file for PowerPC opcode table - Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005 - Free Software Foundation, Inc. + Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, + 2007 Free Software Foundation, Inc. Written by Ian Lance Taylor, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. @@ -135,10 +135,16 @@ extern const int powerpc_num_opcodes; #define PPC_OPCODE_RFMCI 0x800000 /* Opcode is only supported by Power5 architecture. */ -#define PPC_OPCODE_POWER5 0x1000000 +#define PPC_OPCODE_POWER5 0x1000000 /* Opcode is supported by PowerPC e300 family. */ -#define PPC_OPCODE_E300 0x2000000 +#define PPC_OPCODE_E300 0x2000000 + +/* Opcode is only supported by Power6 architecture. */ +#define PPC_OPCODE_POWER6 0x4000000 + +/* Opcode is only supported by PowerPC Cell family. */ +#define PPC_OPCODE_CELL 0x8000000 /* A macro to extract the major opcode from an instruction. */ #define PPC_OP(i) (((i) >> 26) & 0x3f) @@ -147,20 +153,21 @@ extern const int powerpc_num_opcodes; struct powerpc_operand { - /* The number of bits in the operand. */ - int bits; + /* A bitmask of bits in the operand. */ + unsigned int bitm; - /* How far the operand is left shifted in the instruction. */ + /* How far the operand is left shifted in the instruction. + -1 to indicate that BITM and SHIFT cannot be used to determine + where the operand goes in the insn. */ int shift; /* Insertion function. This is used by the assembler. To insert an operand value into an instruction, check this field. If it is NULL, execute - i |= (op & ((1 << o->bits) - 1)) << o->shift; + i |= (op & o->bitm) << o->shift; (i is the instruction which we are filling in, o is a pointer to - this structure, and op is the opcode value; this assumes twos - complement arithmetic). + this structure, and op is the operand value). If this field is not NULL, then simply call it with the instruction and the operand value. It will return the new value @@ -176,12 +183,11 @@ struct powerpc_operand extract this operand type from an instruction, check this field. If it is NULL, compute - op = ((i) >> o->shift) & ((1 << o->bits) - 1); - if ((o->flags & PPC_OPERAND_SIGNED) != 0 - && (op & (1 << (o->bits - 1))) != 0) - op -= 1 << o->bits; + op = (i >> o->shift) & o->bitm; + if ((o->flags & PPC_OPERAND_SIGNED) != 0) + sign_extend (op); (i is the instruction, o is a pointer to this structure, and op - is the result; this assumes twos complement arithmetic). + is the result). If this field is not NULL, then simply call it with the instruction value. It will return the value of the operand. If @@ -199,17 +205,18 @@ struct powerpc_operand the operands field of the powerpc_opcodes table. */ extern const struct powerpc_operand powerpc_operands[]; +extern const unsigned int num_powerpc_operands; /* Values defined for the flags field of a struct powerpc_operand. */ /* This operand takes signed values. */ -#define PPC_OPERAND_SIGNED (01) +#define PPC_OPERAND_SIGNED (0x1) /* This operand takes signed values, but also accepts a full positive range of values when running in 32 bit mode. That is, if bits is 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, this flag is ignored. */ -#define PPC_OPERAND_SIGNOPT (02) +#define PPC_OPERAND_SIGNOPT (0x2) /* This operand does not actually exist in the assembler input. This is used to support extended mnemonics such as mr, for which two @@ -217,14 +224,14 @@ extern const struct powerpc_operand powerpc_operands[]; insert function with any op value. The disassembler should call the extract function, ignore the return value, and check the value placed in the valid argument. */ -#define PPC_OPERAND_FAKE (04) +#define PPC_OPERAND_FAKE (0x4) /* The next operand should be wrapped in parentheses rather than separated from this one by a comma. This is used for the load and store instructions which want their operands to look like reg,displacement(reg) */ -#define PPC_OPERAND_PARENS (010) +#define PPC_OPERAND_PARENS (0x8) /* This operand may use the symbolic names for the CR fields, which are @@ -233,26 +240,26 @@ extern const struct powerpc_operand powerpc_operands[]; cr4 4 cr5 5 cr6 6 cr7 7 These may be combined arithmetically, as in cr2*4+gt. These are only supported on the PowerPC, not the POWER. */ -#define PPC_OPERAND_CR (020) +#define PPC_OPERAND_CR (0x10) /* This operand names a register. The disassembler uses this to print register names with a leading 'r'. */ -#define PPC_OPERAND_GPR (040) +#define PPC_OPERAND_GPR (0x20) /* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0. */ -#define PPC_OPERAND_GPR_0 (0100) +#define PPC_OPERAND_GPR_0 (0x40) /* This operand names a floating point register. The disassembler prints these with a leading 'f'. */ -#define PPC_OPERAND_FPR (0200) +#define PPC_OPERAND_FPR (0x80) /* This operand is a relative branch displacement. The disassembler prints these symbolically if possible. */ -#define PPC_OPERAND_RELATIVE (0400) +#define PPC_OPERAND_RELATIVE (0x100) /* This operand is an absolute branch address. The disassembler prints these symbolically if possible. */ -#define PPC_OPERAND_ABSOLUTE (01000) +#define PPC_OPERAND_ABSOLUTE (0x200) /* This operand is optional, and is zero if omitted. This is used for example, in the optional BF field in the comparison instructions. The @@ -260,7 +267,7 @@ extern const struct powerpc_operand powerpc_operands[]; and the number of operands remaining for the opcode, and decide whether this operand is present or not. The disassembler should print this operand out only if it is not zero. */ -#define PPC_OPERAND_OPTIONAL (02000) +#define PPC_OPERAND_OPTIONAL (0x400) /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand is omitted, then for the next operand use this operand value plus @@ -268,24 +275,27 @@ extern const struct powerpc_operand powerpc_operands[]; hack is needed because the Power rotate instructions can take either 4 or 5 operands. The disassembler should print this operand out regardless of the PPC_OPERAND_OPTIONAL field. */ -#define PPC_OPERAND_NEXT (04000) +#define PPC_OPERAND_NEXT (0x800) /* This operand should be regarded as a negative number for the purposes of overflow checking (i.e., the normal most negative number is disallowed and one more than the normal most positive number is allowed). This flag will only be set for a signed operand. */ -#define PPC_OPERAND_NEGATIVE (010000) +#define PPC_OPERAND_NEGATIVE (0x1000) /* This operand names a vector unit register. The disassembler prints these with a leading 'v'. */ -#define PPC_OPERAND_VR (020000) +#define PPC_OPERAND_VR (0x2000) /* This operand is for the DS field in a DS form instruction. */ -#define PPC_OPERAND_DS (040000) +#define PPC_OPERAND_DS (0x4000) /* This operand is for the DQ field in a DQ form instruction. */ -#define PPC_OPERAND_DQ (0100000) +#define PPC_OPERAND_DQ (0x8000) + +/* Valid range of operand is 0..n rather than 0..n-1. */ +#define PPC_OPERAND_PLUS1 (0x10000) /* The POWER and PowerPC assemblers use a few macros. We keep them with the operands table for simplicity. The macro table is an diff --git a/contrib/binutils/include/opcode/s390.h b/contrib/binutils/include/opcode/s390.h index 7bb30de..ae039ef 100644 --- a/contrib/binutils/include/opcode/s390.h +++ b/contrib/binutils/include/opcode/s390.h @@ -36,7 +36,8 @@ enum s390_opcode_cpu_val S390_OPCODE_G6, S390_OPCODE_Z900, S390_OPCODE_Z990, - S390_OPCODE_Z9_109 + S390_OPCODE_Z9_109, + S390_OPCODE_Z9_EC }; /* The opcode table is an array of struct s390_opcode. */ diff --git a/contrib/binutils/include/opcode/score-datadep.h b/contrib/binutils/include/opcode/score-datadep.h new file mode 100644 index 0000000..8ef35ad --- /dev/null +++ b/contrib/binutils/include/opcode/score-datadep.h @@ -0,0 +1,282 @@ +/* score-datadep.h -- Score Instructions data dependency table + Copyright 2006 Free Software Foundation, Inc. + Contributed by: + Mei Ligang (ligang@sunnorth.com.cn) + Pei-Lin Tsai (pltsai@sunplus.com) + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, Inc., 51 Franklin Street - Fifth Floor, + Boston, MA 02110-1301, USA. */ + +#ifndef SCORE_DATA_DEPENDENCY_H +#define SCORE_DATA_DEPENDENCY_H + +#define INSN_NAME_LEN 16 + +enum insn_type_for_dependency +{ + D_pce, + D_cond_br, + D_cond_mv, + D_cached, + D_cachei, + D_ldst, + D_ldcombine, + D_mtcr, + D_mfcr, + D_mfsr, + D_mftlb, + D_mtptlb, + D_mtrtlb, + D_stlb, + D_all_insn +}; + +struct insn_to_dependency +{ + char *insn_name; + enum insn_type_for_dependency type; +}; + +struct data_dependency +{ + enum insn_type_for_dependency pre_insn_type; + char pre_reg[6]; + enum insn_type_for_dependency cur_insn_type; + char cur_reg[6]; + int bubblenum_7; + int bubblenum_5; + int warn_or_error; /* warning - 0; error - 1 */ +}; + +static const struct insn_to_dependency insn_to_dependency_table[] = +{ + /* pce instruction. */ + {"pce", D_pce}, + /* conditional branch instruction. */ + {"bcs", D_cond_br}, + {"bcc", D_cond_br}, + {"bgtu", D_cond_br}, + {"bleu", D_cond_br}, + {"beq", D_cond_br}, + {"bne", D_cond_br}, + {"bgt", D_cond_br}, + {"ble", D_cond_br}, + {"bge", D_cond_br}, + {"blt", D_cond_br}, + {"bmi", D_cond_br}, + {"bpl", D_cond_br}, + {"bvs", D_cond_br}, + {"bvc", D_cond_br}, + {"bcsl", D_cond_br}, + {"bccl", D_cond_br}, + {"bgtul", D_cond_br}, + {"bleul", D_cond_br}, + {"beql", D_cond_br}, + {"bnel", D_cond_br}, + {"bgtl", D_cond_br}, + {"blel", D_cond_br}, + {"bgel", D_cond_br}, + {"bltl", D_cond_br}, + {"bmil", D_cond_br}, + {"bpll", D_cond_br}, + {"bvsl", D_cond_br}, + {"bvcl", D_cond_br}, + {"bcs!", D_cond_br}, + {"bcc!", D_cond_br}, + {"bgtu!", D_cond_br}, + {"bleu!", D_cond_br}, + {"beq!", D_cond_br}, + {"bne!", D_cond_br}, + {"bgt!", D_cond_br}, + {"ble!", D_cond_br}, + {"bge!", D_cond_br}, + {"blt!", D_cond_br}, + {"bmi!", D_cond_br}, + {"bpl!", D_cond_br}, + {"bvs!", D_cond_br}, + {"bvc!", D_cond_br}, + {"brcs", D_cond_br}, + {"brcc", D_cond_br}, + {"brgtu", D_cond_br}, + {"brleu", D_cond_br}, + {"breq", D_cond_br}, + {"brne", D_cond_br}, + {"brgt", D_cond_br}, + {"brle", D_cond_br}, + {"brge", D_cond_br}, + {"brlt", D_cond_br}, + {"brmi", D_cond_br}, + {"brpl", D_cond_br}, + {"brvs", D_cond_br}, + {"brvc", D_cond_br}, + {"brcsl", D_cond_br}, + {"brccl", D_cond_br}, + {"brgtul", D_cond_br}, + {"brleul", D_cond_br}, + {"breql", D_cond_br}, + {"brnel", D_cond_br}, + {"brgtl", D_cond_br}, + {"brlel", D_cond_br}, + {"brgel", D_cond_br}, + {"brltl", D_cond_br}, + {"brmil", D_cond_br}, + {"brpll", D_cond_br}, + {"brvsl", D_cond_br}, + {"brvcl", D_cond_br}, + {"brcs!", D_cond_br}, + {"brcc!", D_cond_br}, + {"brgtu!", D_cond_br}, + {"brleu!", D_cond_br}, + {"breq!", D_cond_br}, + {"brne!", D_cond_br}, + {"brgt!", D_cond_br}, + {"brle!", D_cond_br}, + {"brge!", D_cond_br}, + {"brlt!", D_cond_br}, + {"brmi!", D_cond_br}, + {"brpl!", D_cond_br}, + {"brvs!", D_cond_br}, + {"brvc!", D_cond_br}, + {"brcsl!", D_cond_br}, + {"brccl!", D_cond_br}, + {"brgtul!", D_cond_br}, + {"brleul!", D_cond_br}, + {"breql!", D_cond_br}, + {"brnel!", D_cond_br}, + {"brgtl!", D_cond_br}, + {"brlel!", D_cond_br}, + {"brgel!", D_cond_br}, + {"brltl!", D_cond_br}, + {"brmil!", D_cond_br}, + {"brpll!", D_cond_br}, + {"brvsl!", D_cond_br}, + {"brvcl!", D_cond_br}, + /* conditional move instruction. */ + {"mvcs", D_cond_mv}, + {"mvcc", D_cond_mv}, + {"mvgtu", D_cond_mv}, + {"mvleu", D_cond_mv}, + {"mveq", D_cond_mv}, + {"mvne", D_cond_mv}, + {"mvgt", D_cond_mv}, + {"mvle", D_cond_mv}, + {"mvge", D_cond_mv}, + {"mvlt", D_cond_mv}, + {"mvmi", D_cond_mv}, + {"mvpl", D_cond_mv}, + {"mvvs", D_cond_mv}, + {"mvvc", D_cond_mv}, + /* move spectial instruction. */ + {"mtcr", D_mtcr}, + {"mftlb", D_mftlb}, + {"mtptlb", D_mtptlb}, + {"mtrtlb", D_mtrtlb}, + {"stlb", D_stlb}, + {"mfcr", D_mfcr}, + {"mfsr", D_mfsr}, + /* cache instruction. */ + {"cache 8", D_cached}, + {"cache 9", D_cached}, + {"cache 10", D_cached}, + {"cache 11", D_cached}, + {"cache 12", D_cached}, + {"cache 13", D_cached}, + {"cache 14", D_cached}, + {"cache 24", D_cached}, + {"cache 26", D_cached}, + {"cache 27", D_cached}, + {"cache 29", D_cached}, + {"cache 30", D_cached}, + {"cache 31", D_cached}, + {"cache 0", D_cachei}, + {"cache 1", D_cachei}, + {"cache 2", D_cachei}, + {"cache 3", D_cachei}, + {"cache 4", D_cachei}, + {"cache 16", D_cachei}, + {"cache 17", D_cachei}, + /* load/store instruction. */ + {"lb", D_ldst}, + {"lbu", D_ldst}, + {"lbu!", D_ldst}, + {"lbup!", D_ldst}, + {"lh", D_ldst}, + {"lhu", D_ldst}, + {"lh!", D_ldst}, + {"lhp!", D_ldst}, + {"lw", D_ldst}, + {"lw!", D_ldst}, + {"lwp!", D_ldst}, + {"sb", D_ldst}, + {"sb!", D_ldst}, + {"sbp!", D_ldst}, + {"sh", D_ldst}, + {"sh!", D_ldst}, + {"shp!", D_ldst}, + {"sw", D_ldst}, + {"sw!", D_ldst}, + {"swp!", D_ldst}, + {"alw", D_ldst}, + {"asw", D_ldst}, + {"push!", D_ldst}, + {"pushhi!", D_ldst}, + {"pop!", D_ldst}, + {"pophi!", D_ldst}, + {"ldc1", D_ldst}, + {"ldc2", D_ldst}, + {"ldc3", D_ldst}, + {"stc1", D_ldst}, + {"stc2", D_ldst}, + {"stc3", D_ldst}, + {"scb", D_ldst}, + {"scw", D_ldst}, + {"sce", D_ldst}, + /* load combine instruction. */ + {"lcb", D_ldcombine}, + {"lcw", D_ldcombine}, + {"lce", D_ldcombine}, +}; + +static const struct data_dependency data_dependency_table[] = +{ + /* Condition register. */ + {D_mtcr, "cr1", D_pce, "", 2, 1, 1}, + {D_mtcr, "cr1", D_cond_br, "", 1, 0, 1}, + {D_mtcr, "cr1", D_cond_mv, "", 1, 0, 1}, + /* Status regiser. */ + {D_mtcr, "cr0", D_all_insn, "", 5, 4, 0}, + /* CCR regiser. */ + {D_mtcr, "cr4", D_all_insn, "", 6, 5, 0}, + /* EntryHi/EntryLo register. */ + {D_mftlb, "", D_mtptlb, "", 1, 1, 1}, + {D_mftlb, "", D_mtrtlb, "", 1, 1, 1}, + {D_mftlb, "", D_stlb, "", 1, 1,1}, + {D_mftlb, "", D_mfcr, "cr11", 1, 1, 1}, + {D_mftlb, "", D_mfcr, "cr12", 1, 1, 1}, + /* Index register. */ + {D_stlb, "", D_mtptlb, "", 1, 1, 1}, + {D_stlb, "", D_mftlb, "", 1, 1, 1}, + {D_stlb, "", D_mfcr, "cr8", 2, 2, 1}, + /* Cache. */ + {D_cached, "", D_ldst, "", 1, 1, 0}, + {D_cached, "", D_ldcombine, "", 1, 1, 0}, + {D_cachei, "", D_all_insn, "", 5, 4, 0}, + /* Load combine. */ + {D_ldcombine, "", D_mfsr, "sr1", 3, 3, 1}, +}; + +#endif diff --git a/contrib/binutils/include/opcode/score-inst.h b/contrib/binutils/include/opcode/score-inst.h new file mode 100644 index 0000000..e87794f --- /dev/null +++ b/contrib/binutils/include/opcode/score-inst.h @@ -0,0 +1,507 @@ +/* score-inst.h -- Score Instructions Table + Copyright 2006 Free Software Foundation, Inc. + Contributed by: + Mei Ligang (ligang@sunnorth.com.cn) + Pei-Lin Tsai (pltsai@sunplus.com) + + This file is part of GAS, the GNU Assembler. + + GAS is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2, or (at your option) + any later version. + + GAS is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GAS; see the file COPYING. If not, write to the Free + Software Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA + 02110-1301, USA. */ + +#ifndef SCORE_INST_H +#define SCORE_INST_H + +#define LDST_UNALIGN_MASK 0x0000007f +#define UA_LCB 0x00000060 +#define UA_LCW 0x00000062 +#define UA_LCE 0x00000066 +#define UA_SCB 0x00000068 +#define UA_SCW 0x0000006a +#define UA_SCE 0x0000006e +#define UA_LL 0x0000000c +#define UA_SC 0x0000000e +#define LDST16_RR_MASK 0x0000000f +#define N16_LW 8 +#define N16_LH 9 +#define N16_POP 10 +#define N16_LBU 11 +#define N16_SW 12 +#define N16_SH 13 +#define N16_PUSH 14 +#define N16_SB 15 +#define LDST16_RI_MASK 0x7007 +#define N16_LWP 0x7000 +#define N16_LHP 0x7001 +#define N16_LBUP 0x7003 +#define N16_SWP 0x7004 +#define N16_SHP 0x7005 +#define N16_SBP 0x7007 +#define N16_LIU 0x5000 + +#define OPC_PSEUDOLDST_MASK 0x00000007 + +enum +{ + INSN_LW = 0, + INSN_LH = 1, + INSN_LHU = 2, + INSN_LB = 3, + INSN_SW = 4, + INSN_SH = 5, + INSN_LBU = 6, + INSN_SB = 7, +}; + +/* Sub opcdoe opcode. */ +enum +{ + INSN16_LBU = 11, + INSN16_LH = 9, + INSN16_LW = 8, + INSN16_SB = 15, + INSN16_SH = 13, + INSN16_SW = 12, +}; + +enum +{ + LDST_NOUPDATE = 0, + LDST_PRE = 1, + LDST_POST = 2, +}; + +enum score_insn_type +{ + Rd_I4, + Rd_I5, + Rd_rvalueBP_I5, + Rd_lvalueBP_I5, + Rd_Rs_I5, + x_Rs_I5, + x_I5_x, + Rd_I8, + Rd_Rs_I14, + I15, + Rd_I16, + Rd_rvalueRs_SI10, + Rd_lvalueRs_SI10, + Rd_rvalueRs_preSI12, + Rd_rvalueRs_postSI12, + Rd_lvalueRs_preSI12, + Rd_lvalueRs_postSI12, + Rd_Rs_SI14, + Rd_rvalueRs_SI15, + Rd_lvalueRs_SI15, + Rd_SI16, + PC_DISP8div2, + PC_DISP11div2, + PC_DISP19div2, + PC_DISP24div2, + Rd_Rs_Rs, + x_Rs_x, + x_Rs_Rs, + Rd_Rs_x, + Rd_x_Rs, + Rd_x_x, + Rd_Rs, + Rd_HighRs, + Rd_lvalueRs, + Rd_rvalueRs, + Rd_lvalue32Rs, + Rd_rvalue32Rs, + x_Rs, + NO_OPD, + NO16_OPD, + OP5_rvalueRs_SI15, + I5_Rs_Rs_I5_OP5, + x_rvalueRs_post4, + Rd_rvalueRs_post4, + Rd_x_I5, + Rd_lvalueRs_post4, + x_lvalueRs_post4, + Rd_LowRs, + Rd_Rs_Rs_imm, + Insn_Type_PCE, + Insn_Type_SYN, + Insn_GP, + Insn_PIC, + Insn_internal, +}; + +enum score_data_type +{ + _IMM4 = 0, + _IMM5, + _IMM8, + _IMM14, + _IMM15, + _IMM16, + _SIMM10 = 6, + _SIMM12, + _SIMM14, + _SIMM15, + _SIMM16, + _SIMM14_NEG = 11, + _IMM16_NEG, + _SIMM16_NEG, + _IMM20, + _IMM25, + _DISP8div2 = 16, + _DISP11div2, + _DISP19div2, + _DISP24div2, + _VALUE, + _VALUE_HI16, + _VALUE_LO16, + _VALUE_LDST_LO16 = 23, + _SIMM16_LA, + _IMM5_RSHIFT_1, + _IMM5_RSHIFT_2, + _SIMM16_LA_POS, + _IMM5_RANGE_8_31, + _IMM10_RSHIFT_2, + _GP_IMM15 = 30, + _GP_IMM14 = 31, + _SIMM16_pic = 42, /* Index in score_df_range. */ + _IMM16_LO16_pic = 43, + _IMM16_pic = 44, +}; + +#define REG_TMP 1 + +#define OP_REG_TYPE (1 << 6) +#define OP_IMM_TYPE (1 << 7) +#define OP_SH_REGD (OP_REG_TYPE |20) +#define OP_SH_REGS1 (OP_REG_TYPE |15) +#define OP_SH_REGS2 (OP_REG_TYPE |10) +#define OP_SH_I (OP_IMM_TYPE | 1) +#define OP_SH_RI15 (OP_IMM_TYPE | 0) +#define OP_SH_I12 (OP_IMM_TYPE | 3) +#define OP_SH_DISP24 (OP_IMM_TYPE | 1) +#define OP_SH_DISP19_p1 (OP_IMM_TYPE |15) +#define OP_SH_DISP19_p2 (OP_IMM_TYPE | 1) +#define OP_SH_I5 (OP_IMM_TYPE |10) +#define OP_SH_I10 (OP_IMM_TYPE | 5) +#define OP_SH_COPID (OP_IMM_TYPE | 5) +#define OP_SH_TRAPI5 (OP_IMM_TYPE |15) +#define OP_SH_I15 (OP_IMM_TYPE |10) + +#define OP16_SH_REGD (OP_REG_TYPE | 8) +#define OP16_SH_REGS1 (OP_REG_TYPE | 4) +#define OP16_SH_I45 (OP_IMM_TYPE | 3) +#define OP16_SH_I8 (OP_IMM_TYPE | 0) +#define OP16_SH_DISP8 (OP_IMM_TYPE | 0) +#define OP16_SH_DISP11 (OP_IMM_TYPE | 1) + +struct datafield_range +{ + int data_type; + int bits; + int range[2]; +}; + +struct datafield_range score_df_range[] = +{ + {_IMM4, 4, {0, (1 << 4) - 1}}, /* ( 0 ~ 15 ) */ + {_IMM5, 5, {0, (1 << 5) - 1}}, /* ( 0 ~ 31 ) */ + {_IMM8, 8, {0, (1 << 8) - 1}}, /* ( 0 ~ 255 ) */ + {_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 16383) */ + {_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */ + {_IMM16, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */ + {_SIMM10, 10, {-(1 << 9), (1 << 9) - 1}}, /* ( -512 ~ 511 ) */ + {_SIMM12, 12, {-(1 << 11), (1 << 11) - 1}}, /* ( -2048 ~ 2047 ) */ + {_SIMM14, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8192 ~ 8191 ) */ + {_SIMM15, 15, {-(1 << 14), (1 << 14) - 1}}, /* (-16384 ~ 16383) */ + {_SIMM16, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ + {_SIMM14_NEG, 14, {-(1 << 13), (1 << 13) - 1}}, /* ( -8191 ~ 8192 ) */ + {_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* (-65535 ~ 0 ) */ + {_SIMM16_NEG, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ + {_IMM20, 20, {0, (1 << 20) - 1}}, + {_IMM25, 25, {0, (1 << 25) - 1}}, + {_DISP8div2, 8, {-(1 << 8), (1 << 8) - 1}}, /* ( -256 ~ 255 ) */ + {_DISP11div2, 11, {0, 0}}, + {_DISP19div2, 19, {-(1 << 19), (1 << 19) - 1}}, /* (-524288 ~ 524287) */ + {_DISP24div2, 24, {0, 0}}, + {_VALUE, 32, {0, ((unsigned int)1 << 31) - 1}}, + {_VALUE_HI16, 16, {0, (1 << 16) - 1}}, + {_VALUE_LO16, 16, {0, (1 << 16) - 1}}, + {_VALUE_LDST_LO16, 16, {0, (1 << 16) - 1}}, + {_SIMM16_LA, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ + {_IMM5_RSHIFT_1, 5, {0, (1 << 6) - 1}}, /* ( 0 ~ 63 ) */ + {_IMM5_RSHIFT_2, 5, {0, (1 << 7) - 1}}, /* ( 0 ~ 127 ) */ + {_SIMM16_LA_POS, 16, {0, (1 << 15) - 1}}, /* ( 0 ~ 32767) */ + {_IMM5_RANGE_8_31, 5, {8, 31}}, /* But for cop0 the valid data : (8 ~ 31). */ + {_IMM10_RSHIFT_2, 10, {-(1 << 11), (1 << 11) - 1}}, /* For ldc#, stc#. */ + {_SIMM10, 10, {0, (1 << 10) - 1}}, /* ( -1024 ~ 1023 ) */ + {_SIMM12, 12, {0, (1 << 12) - 1}}, /* ( -2048 ~ 2047 ) */ + {_SIMM14, 14, {0, (1 << 14) - 1}}, /* ( -8192 ~ 8191 ) */ + {_SIMM15, 15, {0, (1 << 15) - 1}}, /* (-16384 ~ 16383) */ + {_SIMM16, 16, {0, (1 << 16) - 1}}, /* (-65536 ~ 65536) */ + {_SIMM14_NEG, 14, {0, (1 << 16) - 1}}, /* ( -8191 ~ 8192 ) */ + {_IMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */ + {_SIMM16_NEG, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */ + {_IMM20, 20, {0, (1 << 20) - 1}}, /* (-32768 ~ 32767) */ + {_IMM25, 25, {0, (1 << 25) - 1}}, /* (-32768 ~ 32767) */ + {_GP_IMM15, 15, {0, (1 << 15) - 1}}, /* ( 0 ~ 65535) */ + {_GP_IMM14, 14, {0, (1 << 14) - 1}}, /* ( 0 ~ 65535) */ + {_SIMM16_pic, 16, {-(1 << 15), (1 << 15) - 1}}, /* (-32768 ~ 32767) */ + {_IMM16_LO16_pic, 16, {0, (1 << 16) - 1}}, /* ( 65535 ~ 0 ) */ + {_IMM16_pic, 16, {0, (1 << 16) - 1}}, /* ( 0 ~ 65535) */ +}; + +struct shift_bitmask +{ + int opd_type; + int opd_num; + struct datafield_range *df_range; + int sh[4]; + long fieldbits[4]; +}; + +struct shift_bitmask score_sh_bits_map[] = +{ + { + Rd_I4, 2, &score_df_range[_IMM4], + {OP16_SH_REGD, OP16_SH_I45, 0, 0}, + {0xf, 0xf, 0, 0}, + }, + { + Rd_I5, 2, &score_df_range[_IMM5], + {OP16_SH_REGD, OP16_SH_I45, 0, 0}, + {0xf, 0x1f, 0, 0}, + }, + { + Rd_rvalueBP_I5, 2, &score_df_range[_IMM5], + {OP16_SH_REGD, OP16_SH_I45, 0, 0}, + {0xf, 0x1f, 0, 0}, + }, + { + Rd_lvalueBP_I5, 2, &score_df_range[_IMM5], + {OP16_SH_REGD, OP16_SH_I45, 0, 0}, + {0xf, 0x1f, 0, 0}, + }, + { + Rd_Rs_I5, 3, &score_df_range[_IMM5], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I5, 0}, + {0x1f, 0x1f, 0x1f, 0}, + }, + { + x_Rs_I5, 2, &score_df_range[_IMM5], + {OP_SH_REGS1, OP_SH_I5, 0, 0}, + {0x1f, 0x1f, 0, 0}, + }, + { + x_I5_x, 1, &score_df_range[_IMM5], + {OP_SH_TRAPI5, 0, 0, 0}, + {0x1f, 0, 0, 0}, + }, + { + Rd_I8, 2, &score_df_range[_IMM8], + {OP16_SH_REGD, OP16_SH_I8, 0, 0}, + {0xf, 0xff, 0, 0}, + }, + { + Rd_Rs_I14, 3, &score_df_range[_IMM14], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0}, + {0x1f, 0x1f, 0x3fff, 0}, + }, + { + I15, 1, &score_df_range[_IMM15], + {OP_SH_I15, 0, 0, 0}, + {0x7fff, 0, 0, 0}, + }, + { + Rd_I16, 2, &score_df_range[_IMM16], + {OP_SH_REGD, OP_SH_I, 0, 0}, + {0x1f, 0xffff, 0, 0}, + }, + { + Rd_rvalueRs_SI10, 3, &score_df_range[_SIMM10], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0}, + {0x1f, 0x1f, 0x3ff, 0}, + }, + { + Rd_lvalueRs_SI10, 3, &score_df_range[_SIMM10], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I10, 0}, + {0x1f, 0x1f, 0x3ff, 0}, + }, + { + Rd_rvalueRs_preSI12, 3, &score_df_range[_SIMM12], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, + {0xf, 0xf, 0xfff, 0}, + }, + { + Rd_rvalueRs_postSI12, 3, &score_df_range[_SIMM12], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, + {0xf, 0xf, 0xfff, 0}, + }, + { + Rd_lvalueRs_preSI12, 3, &score_df_range[_SIMM12], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, + {0xf, 0xf, 0xfff, 0}, + }, + { + Rd_lvalueRs_postSI12, 3, &score_df_range[_SIMM12], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I12, 0}, + {0xf, 0xf, 0xfff, 0}, + }, + { + Rd_Rs_SI14, 3, &score_df_range[_SIMM14], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_I, 0}, + {0x1f, 0x1f, 0x3fff, 0}, + }, + { + Rd_rvalueRs_SI15, 3, &score_df_range[_SIMM15], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0}, + {0x1f, 0x1f, 0x7fff, 0}, + }, + { + Rd_lvalueRs_SI15, 3, &score_df_range[_SIMM15], + {OP_SH_REGD, OP_SH_REGS1, OP_SH_RI15, 0}, + {0x1f, 0x1f, 0x7fff, 0}, + }, + { + Rd_SI16, 2, &score_df_range[_SIMM16], + {OP_SH_REGD, OP_SH_I, 0, 0}, + {0x1f, 0xffff, 0, 0}, + }, + { + PC_DISP8div2, 1, &score_df_range[_DISP8div2], + {OP16_SH_DISP8, 0, 0, 0}, + {0xff, 0, 0, 0}, + }, + { + PC_DISP11div2, 1, &score_df_range[_DISP11div2], + {OP16_SH_DISP11, 0, 0, 0}, + {0x7ff, 0, 0, 0}, + }, + { + PC_DISP19div2, 2, &score_df_range[_DISP19div2], + {OP_SH_DISP19_p1, OP_SH_DISP19_p2, 0, 0}, + {0x3ff, 0x1ff, 0, 0}, + }, + { + PC_DISP24div2, 1, &score_df_range[_DISP24div2], + {OP_SH_DISP24, 0, 0, 0}, + {0xffffff, 0, 0, 0}, + }, + { + Rd_Rs_Rs, 3, NULL, + {OP_SH_REGD, OP_SH_REGS1, OP_SH_REGS2, 0}, + {0x1f, 0x1f, 0x1f, 0} + }, + { + Rd_Rs_x, 2, NULL, + {OP_SH_REGD, OP_SH_REGS1, 0, 0}, + {0x1f, 0x1f, 0, 0}, + }, + { + Rd_x_Rs, 2, NULL, + {OP_SH_REGD, OP_SH_REGS2, 0, 0}, + {0x1f, 0x1f, 0, 0}, + }, + { + Rd_x_x, 1, NULL, + {OP_SH_REGD, 0, 0, 0}, + {0x1f, 0, 0, 0}, + }, + { + x_Rs_Rs, 2, NULL, + {OP_SH_REGS1, OP_SH_REGS2, 0, 0}, + {0x1f, 0x1f, 0, 0}, + }, + { + x_Rs_x, 1, NULL, + {OP_SH_REGS1, 0, 0, 0}, + {0x1f, 0, 0, 0}, + }, + { + Rd_Rs, 2, NULL, + {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, + {0xf, 0xf, 0, 0}, + }, + { + Rd_HighRs, 2, NULL, + {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, + {0xf, 0xf, 0x1f, 0}, + }, + { + Rd_rvalueRs, 2, NULL, + {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, + {0xf, 0xf, 0, 0}, + }, + { + Rd_lvalueRs, 2, NULL, + {OP16_SH_REGD, OP16_SH_REGS1, 0, 0}, + {0xf, 0xf, 0, 0} + }, + { + Rd_lvalue32Rs, 2, NULL, + {OP_SH_REGD, OP_SH_REGS1, 0, 0}, + {0x1f, 0x1f, 0, 0}, + }, + { + Rd_rvalue32Rs, 2, NULL, + {OP_SH_REGD, OP_SH_REGS1, 0, 0}, + {0x1f, 0x1f, 0, 0}, + }, + { + x_Rs, 1, NULL, + {OP16_SH_REGS1, 0, 0, 0}, + {0xf, 0, 0, 0}, + }, + { + NO_OPD, 0, NULL, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + }, + { + NO16_OPD, 0, NULL, + {0, 0, 0, 0}, + {0, 0, 0, 0}, + }, +}; + +struct asm_opcode +{ + /* Instruction name. */ + const char *template; + + /* Instruction Opcode. */ + unsigned long value; + + /* Instruction bit mask. */ + unsigned long bitmask; + + /* Relax instruction opcode. 0x8000 imply no relaxation. */ + unsigned long relax_value; + + /* Instruction type. */ + enum score_insn_type type; + + /* Function to call to parse args. */ + void (*parms) (char *); +}; + +enum insn_class +{ + INSN_CLASS_16, + INSN_CLASS_32, + INSN_CLASS_PCE, + INSN_CLASS_SYN +}; + +#endif diff --git a/contrib/binutils/include/opcode/spu-insns.h b/contrib/binutils/include/opcode/spu-insns.h new file mode 100644 index 0000000..237d8ab --- /dev/null +++ b/contrib/binutils/include/opcode/spu-insns.h @@ -0,0 +1,417 @@ +/* SPU ELF support for BFD. + + Copyright 2006, 2007 Free Software Foundation, Inc. + + This file is part of BFD, the Binary File Descriptor library. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + +/* SPU Opcode Table + +-=-=-= FORMAT =-=-=- + + +----+-------+-------+-------+-------+ +------------+-------+-------+-------+ +RRR | op | RC | RB | RA | RT | RI7 | op | I7 | RA | RT | + +----+-------+-------+-------+-------+ +------------+-------+-------+-------+ + 0 3 1 1 2 3 0 1 1 2 3 + 0 7 4 1 0 7 4 1 + + +-----------+--------+-------+-------+ +---------+----------+-------+-------+ +RI8 | op | I8 | RA | RT | RI10 | op | I10 | RA | RT | + +-----------+--------+-------+-------+ +---------+----------+-------+-------+ + 0 9 1 2 3 0 7 1 2 3 + 7 4 1 7 4 1 + + +----------+-----------------+-------+ +--------+-------------------+-------+ +RI16 | op | I16 | RT | RI18 | op | I18 | RT | + +----------+-----------------+-------+ +--------+-------------------+-------+ + 0 8 2 3 0 6 2 3 + 4 1 4 1 + + +------------+-------+-------+-------+ +-------+--+-----------------+-------+ +RR | op | RB | RA | RT | LBT | op |RO| I16 | RO | + +------------+-------+-------+-------+ +-------+--+-----------------+-------+ + 0 1 1 2 3 0 6 8 2 3 + 0 7 4 1 4 1 + + +------------+----+--+-------+-------+ + LBTI | op | // |RO| RA | RO | + +------------+----+--+-------+-------+ + 0 1 1 1 2 3 + 0 5 7 4 1 + +-=-=-= OPCODE =-=-=- + +OPCODE field specifies the most significant 11bit of the instruction. Some formats don't have 11bits for opcode field, and in this +case, bit field other than op are defined as 0s. For example, opcode of fma instruction which is RRR format is defined as 0x700, +since 0x700 -> 11'b11100000000, this means opcode is 4'b1110, and other 7bits are defined as 7'b0000000. + +-=-=-= ASM_FORMAT =-=-=- + +RRR category RI7 category + ASM_RRR mnemonic RC, RA, RB, RT ASM_RI4 mnemonic RT, RA, I4 + ASM_RI7 mnemonic RT, RA, I7 + +RI8 category RI10 category + ASM_RUI8 mnemonic RT, RA, UI8 ASM_AI10 mnemonic RA, I10 + ASM_RI10 mnemonic RT, RA, R10 + ASM_RI10IDX mnemonic RT, I10(RA) + +RI16 category RI18 category + ASM_I16W mnemonic I16W ASM_RI18 mnemonic RT, I18 + ASM_RI16 mnemonic RT, I16 + ASM_RI16W mnemonic RT, I16W + +RR category LBT category + ASM_MFSPR mnemonic RT, SA ASM_LBT mnemonic brinst, brtarg + ASM_MTSPR mnemonic SA, RT + ASM_NOOP mnemonic LBTI category + ASM_RA mnemonic RA ASM_LBTI mnemonic brinst, RA + ASM_RAB mnemonic RA, RB + ASM_RDCH mnemonic RT, CA + ASM_RR mnemonic RT, RA, RB + ASM_RT mnemonic RT + ASM_RTA mnemonic RT, RA + ASM_WRCH mnemonic CA, RT + +Note that RRR instructions have the names for RC and RT reversed from +what's in the ISA, in order to put RT in the same position it appears +for other formats. + +-=-=-= DEPENDENCY =-=-=- + +DEPENDENCY filed consists of 5 digits. This represents which register is used as source and which register is used as target. +The first(most significant) digit is always 0. Then it is followd by RC, RB, RA and RT digits. +If the digit is 0, this means the corresponding register is not used in the instruction. +If the digit is 1, this means the corresponding register is used as a source in the instruction. +If the digit is 2, this means the corresponding register is used as a target in the instruction. +If the digit is 3, this means the corresponding register is used as both source and target in the instruction. +For example, fms instruction has 00113 as the DEPENDENCY field. This means RC is not used in this operation, RB and RA are +used as sources and RT is the target. + +-=-=-= PIPE =-=-=- + +This field shows which execution pipe is used for the instruction + +pipe0 execution pipelines: + FP6 SP floating pipeline + FP7 integer operations executed in SP floating pipeline + FPD DP floating pipeline + FX2 FXU pipeline + FX3 Rotate/Shift pipeline + FXB Byte pipeline + NOP No pipeline + +pipe1 execution pipelines: + BR Branch pipeline + LNOP No pipeline + LS Load/Store pipeline + SHUF Shuffle pipeline + SPR SPR/CH pipeline + +*/ + +#define _A0() {0} +#define _A1(a) {1,a} +#define _A2(a,b) {2,a,b} +#define _A3(a,b,c) {3,a,b,c} +#define _A4(a,b,c,d) {4,a,b,c,d} + +/* TAG FORMAT OPCODE MNEMONIC ASM_FORMAT DEPENDENCY PIPE COMMENT */ +/* 0[RC][RB][RA][RT] */ +/* 1:src, 2:target */ + +APUOP(M_BR, RI16, 0x190, "br", _A1(A_R18), 00000, BR) /* BRel IP<-IP+I16 */ +APUOP(M_BRSL, RI16, 0x198, "brsl", _A2(A_T,A_R18), 00002, BR) /* BRelSetLink RT,IP<-IP,IP+I16 */ +APUOP(M_BRA, RI16, 0x180, "bra", _A1(A_S18), 00000, BR) /* BRAbs IP<-I16 */ +APUOP(M_BRASL, RI16, 0x188, "brasl", _A2(A_T,A_S18), 00002, BR) /* BRAbsSetLink RT,IP<-IP,I16 */ +APUOP(M_FSMBI, RI16, 0x194, "fsmbi", _A2(A_T,A_X16), 00002, SHUF) /* FormSelMask%I RT<-fsm(I16) */ +APUOP(M_LQA, RI16, 0x184, "lqa", _A2(A_T,A_S18), 00002, LS) /* LoadQAbs RT<-M[I16] */ +APUOP(M_LQR, RI16, 0x19C, "lqr", _A2(A_T,A_R18), 00002, LS) /* LoadQRel RT<-M[IP+I16] */ +APUOP(M_STOP, RR, 0x000, "stop", _A0(), 00000, BR) /* STOP stop */ +APUOP(M_STOP2, RR, 0x000, "stop", _A1(A_U14), 00000, BR) /* STOP stop */ +APUOP(M_STOPD, RR, 0x140, "stopd", _A3(A_T,A_A,A_B), 00111, BR) /* STOPD stop (with register dependencies) */ +APUOP(M_LNOP, RR, 0x001, "lnop", _A0(), 00000, LNOP) /* LNOP no_operation */ +APUOP(M_SYNC, RR, 0x002, "sync", _A0(), 00000, BR) /* SYNC flush_pipe */ +APUOP(M_DSYNC, RR, 0x003, "dsync", _A0(), 00000, BR) /* DSYNC flush_store_queue */ +APUOP(M_MFSPR, RR, 0x00c, "mfspr", _A2(A_T,A_S), 00002, SPR) /* MFSPR RT<-SA */ +APUOP(M_RDCH, RR, 0x00d, "rdch", _A2(A_T,A_H), 00002, SPR) /* ReaDCHannel RT<-CA:data */ +APUOP(M_RCHCNT, RR, 0x00f, "rchcnt", _A2(A_T,A_H), 00002, SPR) /* ReaDCHanCouNT RT<-CA:count */ +APUOP(M_HBRA, LBT, 0x080, "hbra", _A2(A_S11,A_S18), 00000, LS) /* HBRA BTB[B9]<-M[I16] */ +APUOP(M_HBRR, LBT, 0x090, "hbrr", _A2(A_S11,A_R18), 00000, LS) /* HBRR BTB[B9]<-M[IP+I16] */ +APUOP(M_BRZ, RI16, 0x100, "brz", _A2(A_T,A_R18), 00001, BR) /* BRZ IP<-IP+I16_if(RT) */ +APUOP(M_BRNZ, RI16, 0x108, "brnz", _A2(A_T,A_R18), 00001, BR) /* BRNZ IP<-IP+I16_if(RT) */ +APUOP(M_BRHZ, RI16, 0x110, "brhz", _A2(A_T,A_R18), 00001, BR) /* BRHZ IP<-IP+I16_if(RT) */ +APUOP(M_BRHNZ, RI16, 0x118, "brhnz", _A2(A_T,A_R18), 00001, BR) /* BRHNZ IP<-IP+I16_if(RT) */ +APUOP(M_STQA, RI16, 0x104, "stqa", _A2(A_T,A_S18), 00001, LS) /* SToreQAbs M[I16]<-RT */ +APUOP(M_STQR, RI16, 0x11C, "stqr", _A2(A_T,A_R18), 00001, LS) /* SToreQRel M[IP+I16]<-RT */ +APUOP(M_MTSPR, RR, 0x10c, "mtspr", _A2(A_S,A_T), 00001, SPR) /* MTSPR SA<-RT */ +APUOP(M_WRCH, RR, 0x10d, "wrch", _A2(A_H,A_T), 00001, SPR) /* ChanWRite CA<-RT */ +APUOP(M_LQD, RI10, 0x1a0, "lqd", _A4(A_T,A_S14,A_P,A_A), 00012, LS) /* LoadQDisp RT<-M[Ra+I10] */ +APUOP(M_BI, RR, 0x1a8, "bi", _A1(A_A), 00010, BR) /* BI IP<-RA */ +APUOP(M_BISL, RR, 0x1a9, "bisl", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ +APUOP(M_IRET, RR, 0x1aa, "iret", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ +APUOP(M_IRET2, RR, 0x1aa, "iret", _A0(), 00010, BR) /* IRET IP<-SRR0 */ +APUOP(M_BISLED, RR, 0x1ab, "bisled", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ +APUOP(M_HBR, LBTI, 0x1ac, "hbr", _A2(A_S11I,A_A), 00010, LS) /* HBR BTB[B9]<-M[Ra] */ +APUOP(M_FREST, RR, 0x1b8, "frest", _A2(A_T,A_A), 00012, SHUF) /* FREST RT<-recip(RA) */ +APUOP(M_FRSQEST, RR, 0x1b9, "frsqest", _A2(A_T,A_A), 00012, SHUF) /* FRSQEST RT<-rsqrt(RA) */ +APUOP(M_FSM, RR, 0x1b4, "fsm", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ +APUOP(M_FSMH, RR, 0x1b5, "fsmh", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ +APUOP(M_FSMB, RR, 0x1b6, "fsmb", _A2(A_T,A_A), 00012, SHUF) /* FormSelMask% RT<-expand(Ra) */ +APUOP(M_GB, RR, 0x1b0, "gb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ +APUOP(M_GBH, RR, 0x1b1, "gbh", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ +APUOP(M_GBB, RR, 0x1b2, "gbb", _A2(A_T,A_A), 00012, SHUF) /* GatherBits% RT<-gather(RA) */ +APUOP(M_CBD, RI7, 0x1f4, "cbd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ +APUOP(M_CHD, RI7, 0x1f5, "chd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ +APUOP(M_CWD, RI7, 0x1f6, "cwd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ +APUOP(M_CDD, RI7, 0x1f7, "cdd", _A4(A_T,A_U7,A_P,A_A), 00012, SHUF) /* genCtl%%insD RT<-sta(Ra+I4,siz) */ +APUOP(M_ROTQBII, RI7, 0x1f8, "rotqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* ROTQBII RT<-RA<<<I7 */ +APUOP(M_ROTQBYI, RI7, 0x1fc, "rotqbyi", _A3(A_T,A_A,A_S7N), 00012, SHUF) /* ROTQBYI RT<-RA<<<(I7*8) */ +APUOP(M_ROTQMBII, RI7, 0x1f9, "rotqmbii", _A3(A_T,A_A,A_S3), 00012, SHUF) /* ROTQMBII RT<-RA<<I7 */ +APUOP(M_ROTQMBYI, RI7, 0x1fd, "rotqmbyi", _A3(A_T,A_A,A_S6), 00012, SHUF) /* ROTQMBYI RT<-RA<<I7 */ +APUOP(M_SHLQBII, RI7, 0x1fb, "shlqbii", _A3(A_T,A_A,A_U3), 00012, SHUF) /* SHLQBII RT<-RA<<I7 */ +APUOP(M_SHLQBYI, RI7, 0x1ff, "shlqbyi", _A3(A_T,A_A,A_U5), 00012, SHUF) /* SHLQBYI RT<-RA<<I7 */ +APUOP(M_STQD, RI10, 0x120, "stqd", _A4(A_T,A_S14,A_P,A_A), 00011, LS) /* SToreQDisp M[Ra+I10]<-RT */ +APUOP(M_BIHNZ, RR, 0x12b, "bihnz", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ +APUOP(M_BIHZ, RR, 0x12a, "bihz", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ +APUOP(M_BINZ, RR, 0x129, "binz", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ +APUOP(M_BIZ, RR, 0x128, "biz", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ +APUOP(M_CBX, RR, 0x1d4, "cbx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ +APUOP(M_CHX, RR, 0x1d5, "chx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ +APUOP(M_CWX, RR, 0x1d6, "cwx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ +APUOP(M_CDX, RR, 0x1d7, "cdx", _A3(A_T,A_A,A_B), 00112, SHUF) /* genCtl%%insX RT<-sta(Ra+Rb,siz) */ +APUOP(M_LQX, RR, 0x1c4, "lqx", _A3(A_T,A_A,A_B), 00112, LS) /* LoadQindeX RT<-M[Ra+Rb] */ +APUOP(M_ROTQBI, RR, 0x1d8, "rotqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBI RT<-RA<<<Rb */ +APUOP(M_ROTQMBI, RR, 0x1d9, "rotqmbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBI RT<-RA<<Rb */ +APUOP(M_SHLQBI, RR, 0x1db, "shlqbi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBI RT<-RA<<Rb */ +APUOP(M_ROTQBY, RR, 0x1dc, "rotqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBY RT<-RA<<<(Rb*8) */ +APUOP(M_ROTQMBY, RR, 0x1dd, "rotqmby", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBY RT<-RA<<Rb */ +APUOP(M_SHLQBY, RR, 0x1df, "shlqby", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBY RT<-RA<<Rb */ +APUOP(M_ROTQBYBI, RR, 0x1cc, "rotqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQBYBI RT<-RA<<Rb */ +APUOP(M_ROTQMBYBI, RR, 0x1cd, "rotqmbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* ROTQMBYBI RT<-RA<<Rb */ +APUOP(M_SHLQBYBI, RR, 0x1cf, "shlqbybi", _A3(A_T,A_A,A_B), 00112, SHUF) /* SHLQBYBI RT<-RA<<Rb */ +APUOP(M_STQX, RR, 0x144, "stqx", _A3(A_T,A_A,A_B), 00111, LS) /* SToreQindeX M[Ra+Rb]<-RT */ +APUOP(M_SHUFB, RRR, 0x580, "shufb", _A4(A_C,A_A,A_B,A_T), 02111, SHUF) /* SHUFfleBytes RC<-f(RA,RB,RT) */ +APUOP(M_IL, RI16, 0x204, "il", _A2(A_T,A_S16), 00002, FX2) /* ImmLoad RT<-sxt(I16) */ +APUOP(M_ILH, RI16, 0x20c, "ilh", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadH RT<-I16 */ +APUOP(M_ILHU, RI16, 0x208, "ilhu", _A2(A_T,A_X16), 00002, FX2) /* ImmLoadHUpper RT<-I16<<16 */ +APUOP(M_ILA, RI18, 0x210, "ila", _A2(A_T,A_U18), 00002, FX2) /* ImmLoadAddr RT<-zxt(I18) */ +APUOP(M_NOP, RR, 0x201, "nop", _A1(A_T), 00000, NOP) /* XNOP no_operation */ +APUOP(M_NOP2, RR, 0x201, "nop", _A0(), 00000, NOP) /* XNOP no_operation */ +APUOP(M_IOHL, RI16, 0x304, "iohl", _A2(A_T,A_X16), 00003, FX2) /* AddImmeXt RT<-RT+sxt(I16) */ +APUOP(M_ANDBI, RI10, 0x0b0, "andbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* AND%I RT<-RA&I10 */ +APUOP(M_ANDHI, RI10, 0x0a8, "andhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */ +APUOP(M_ANDI, RI10, 0x0a0, "andi", _A3(A_T,A_A,A_S10), 00012, FX2) /* AND%I RT<-RA&I10 */ +APUOP(M_ORBI, RI10, 0x030, "orbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* OR%I RT<-RA|I10 */ +APUOP(M_ORHI, RI10, 0x028, "orhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */ +APUOP(M_ORI, RI10, 0x020, "ori", _A3(A_T,A_A,A_S10), 00012, FX2) /* OR%I RT<-RA|I10 */ +APUOP(M_ORX, RR, 0x1f0, "orx", _A2(A_T,A_A), 00012, BR) /* ORX RT<-RA.w0|RA.w1|RA.w2|RA.w3 */ +APUOP(M_XORBI, RI10, 0x230, "xorbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* XOR%I RT<-RA^I10 */ +APUOP(M_XORHI, RI10, 0x228, "xorhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */ +APUOP(M_XORI, RI10, 0x220, "xori", _A3(A_T,A_A,A_S10), 00012, FX2) /* XOR%I RT<-RA^I10 */ +APUOP(M_AHI, RI10, 0x0e8, "ahi", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */ +APUOP(M_AI, RI10, 0x0e0, "ai", _A3(A_T,A_A,A_S10), 00012, FX2) /* Add%Immed RT<-RA+I10 */ +APUOP(M_SFHI, RI10, 0x068, "sfhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */ +APUOP(M_SFI, RI10, 0x060, "sfi", _A3(A_T,A_A,A_S10), 00012, FX2) /* SubFrom%Imm RT<-I10-RA */ +APUOP(M_CGTBI, RI10, 0x270, "cgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CGT%I RT<-(RA>I10) */ +APUOP(M_CGTHI, RI10, 0x268, "cgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */ +APUOP(M_CGTI, RI10, 0x260, "cgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CGT%I RT<-(RA>I10) */ +APUOP(M_CLGTBI, RI10, 0x2f0, "clgtbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ +APUOP(M_CLGTHI, RI10, 0x2e8, "clgthi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ +APUOP(M_CLGTI, RI10, 0x2e0, "clgti", _A3(A_T,A_A,A_S10), 00012, FX2) /* CLGT%I RT<-(RA>I10) */ +APUOP(M_CEQBI, RI10, 0x3f0, "ceqbi", _A3(A_T,A_A,A_S10B), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ +APUOP(M_CEQHI, RI10, 0x3e8, "ceqhi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ +APUOP(M_CEQI, RI10, 0x3e0, "ceqi", _A3(A_T,A_A,A_S10), 00012, FX2) /* CEQ%I RT<-(RA=I10) */ +APUOP(M_HGTI, RI10, 0x278, "hgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */ +APUOP(M_HGTI2, RI10, 0x278, "hgti", _A2(A_A,A_S10), 00010, FX2) /* HaltGTI halt_if(RA>I10) */ +APUOP(M_HLGTI, RI10, 0x2f8, "hlgti", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */ +APUOP(M_HLGTI2, RI10, 0x2f8, "hlgti", _A2(A_A,A_S10), 00010, FX2) /* HaltLGTI halt_if(RA>I10) */ +APUOP(M_HEQI, RI10, 0x3f8, "heqi", _A3(A_T,A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */ +APUOP(M_HEQI2, RI10, 0x3f8, "heqi", _A2(A_A,A_S10), 00010, FX2) /* HaltEQImm halt_if(RA=I10) */ +APUOP(M_MPYI, RI10, 0x3a0, "mpyi", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYI RT<-RA*I10 */ +APUOP(M_MPYUI, RI10, 0x3a8, "mpyui", _A3(A_T,A_A,A_S10), 00012, FP7) /* MPYUI RT<-RA*I10 */ +APUOP(M_CFLTS, RI8, 0x3b0, "cflts", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTS RT<-int(RA,I8) */ +APUOP(M_CFLTU, RI8, 0x3b2, "cfltu", _A3(A_T,A_A,A_U7A), 00012, FP7) /* CFLTU RT<-int(RA,I8) */ +APUOP(M_CSFLT, RI8, 0x3b4, "csflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CSFLT RT<-flt(RA,I8) */ +APUOP(M_CUFLT, RI8, 0x3b6, "cuflt", _A3(A_T,A_A,A_U7B), 00012, FP7) /* CUFLT RT<-flt(RA,I8) */ +APUOP(M_FESD, RR, 0x3b8, "fesd", _A2(A_T,A_A), 00012, FPD) /* FESD RT<-double(RA) */ +APUOP(M_FRDS, RR, 0x3b9, "frds", _A2(A_T,A_A), 00012, FPD) /* FRDS RT<-single(RA) */ +APUOP(M_FSCRRD, RR, 0x398, "fscrrd", _A1(A_T), 00002, FPD) /* FSCRRD RT<-FP_status */ +APUOP(M_FSCRWR, RR, 0x3ba, "fscrwr", _A2(A_T,A_A), 00010, FP7) /* FSCRWR FP_status<-RA */ +APUOP(M_FSCRWR2, RR, 0x3ba, "fscrwr", _A1(A_A), 00010, FP7) /* FSCRWR FP_status<-RA */ +APUOP(M_CLZ, RR, 0x2a5, "clz", _A2(A_T,A_A), 00012, FX2) /* CLZ RT<-clz(RA) */ +APUOP(M_CNTB, RR, 0x2b4, "cntb", _A2(A_T,A_A), 00012, FXB) /* CNT RT<-pop(RA) */ +APUOP(M_XSBH, RR, 0x2b6, "xsbh", _A2(A_T,A_A), 00012, FX2) /* eXtSignBtoH RT<-sign_ext(RA) */ +APUOP(M_XSHW, RR, 0x2ae, "xshw", _A2(A_T,A_A), 00012, FX2) /* eXtSignHtoW RT<-sign_ext(RA) */ +APUOP(M_XSWD, RR, 0x2a6, "xswd", _A2(A_T,A_A), 00012, FX2) /* eXtSignWtoD RT<-sign_ext(RA) */ +APUOP(M_ROTI, RI7, 0x078, "roti", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */ +APUOP(M_ROTMI, RI7, 0x079, "rotmi", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROT%MI RT<-RA<<I7 */ +APUOP(M_ROTMAI, RI7, 0x07a, "rotmai", _A3(A_T,A_A,A_S7), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */ +APUOP(M_SHLI, RI7, 0x07b, "shli", _A3(A_T,A_A,A_U6), 00012, FX3) /* SHL%I RT<-RA<<I7 */ +APUOP(M_ROTHI, RI7, 0x07c, "rothi", _A3(A_T,A_A,A_S7N), 00012, FX3) /* ROT%I RT<-RA<<<I7 */ +APUOP(M_ROTHMI, RI7, 0x07d, "rothmi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROT%MI RT<-RA<<I7 */ +APUOP(M_ROTMAHI, RI7, 0x07e, "rotmahi", _A3(A_T,A_A,A_S6), 00012, FX3) /* ROTMA%I RT<-RA<<I7 */ +APUOP(M_SHLHI, RI7, 0x07f, "shlhi", _A3(A_T,A_A,A_U5), 00012, FX3) /* SHL%I RT<-RA<<I7 */ +APUOP(M_A, RR, 0x0c0, "a", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */ +APUOP(M_AH, RR, 0x0c8, "ah", _A3(A_T,A_A,A_B), 00112, FX2) /* Add% RT<-RA+RB */ +APUOP(M_SF, RR, 0x040, "sf", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */ +APUOP(M_SFH, RR, 0x048, "sfh", _A3(A_T,A_A,A_B), 00112, FX2) /* SubFrom% RT<-RB-RA */ +APUOP(M_CGT, RR, 0x240, "cgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ +APUOP(M_CGTB, RR, 0x250, "cgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ +APUOP(M_CGTH, RR, 0x248, "cgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CGT% RT<-(RA>RB) */ +APUOP(M_CLGT, RR, 0x2c0, "clgt", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ +APUOP(M_CLGTB, RR, 0x2d0, "clgtb", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ +APUOP(M_CLGTH, RR, 0x2c8, "clgth", _A3(A_T,A_A,A_B), 00112, FX2) /* CLGT% RT<-(RA>RB) */ +APUOP(M_CEQ, RR, 0x3c0, "ceq", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ +APUOP(M_CEQB, RR, 0x3d0, "ceqb", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ +APUOP(M_CEQH, RR, 0x3c8, "ceqh", _A3(A_T,A_A,A_B), 00112, FX2) /* CEQ% RT<-(RA=RB) */ +APUOP(M_HGT, RR, 0x258, "hgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */ +APUOP(M_HGT2, RR, 0x258, "hgt", _A2(A_A,A_B), 00110, FX2) /* HaltGT halt_if(RA>RB) */ +APUOP(M_HLGT, RR, 0x2d8, "hlgt", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */ +APUOP(M_HLGT2, RR, 0x2d8, "hlgt", _A2(A_A,A_B), 00110, FX2) /* HaltLGT halt_if(RA>RB) */ +APUOP(M_HEQ, RR, 0x3d8, "heq", _A3(A_T,A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */ +APUOP(M_HEQ2, RR, 0x3d8, "heq", _A2(A_A,A_B), 00110, FX2) /* HaltEQ halt_if(RA=RB) */ +APUOP(M_FCEQ, RR, 0x3c2, "fceq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCEQ RT<-(RA=RB) */ +APUOP(M_FCMEQ, RR, 0x3ca, "fcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMEQ RT<-(|RA|=|RB|) */ +APUOP(M_FCGT, RR, 0x2c2, "fcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCGT RT<-(RA<RB) */ +APUOP(M_FCMGT, RR, 0x2ca, "fcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* FCMGT RT<-(|RA|<|RB|) */ +APUOP(M_AND, RR, 0x0c1, "and", _A3(A_T,A_A,A_B), 00112, FX2) /* AND RT<-RA&RB */ +APUOP(M_NAND, RR, 0x0c9, "nand", _A3(A_T,A_A,A_B), 00112, FX2) /* NAND RT<-!(RA&RB) */ +APUOP(M_OR, RR, 0x041, "or", _A3(A_T,A_A,A_B), 00112, FX2) /* OR RT<-RA|RB */ +APUOP(M_NOR, RR, 0x049, "nor", _A3(A_T,A_A,A_B), 00112, FX2) /* NOR RT<-!(RA&RB) */ +APUOP(M_XOR, RR, 0x241, "xor", _A3(A_T,A_A,A_B), 00112, FX2) /* XOR RT<-RA^RB */ +APUOP(M_EQV, RR, 0x249, "eqv", _A3(A_T,A_A,A_B), 00112, FX2) /* EQuiValent RT<-!(RA^RB) */ +APUOP(M_ANDC, RR, 0x2c1, "andc", _A3(A_T,A_A,A_B), 00112, FX2) /* ANDComplement RT<-RA&!RB */ +APUOP(M_ORC, RR, 0x2c9, "orc", _A3(A_T,A_A,A_B), 00112, FX2) /* ORComplement RT<-RA|!RB */ +APUOP(M_ABSDB, RR, 0x053, "absdb", _A3(A_T,A_A,A_B), 00112, FXB) /* ABSoluteDiff RT<-|RA-RB| */ +APUOP(M_AVGB, RR, 0x0d3, "avgb", _A3(A_T,A_A,A_B), 00112, FXB) /* AVG% RT<-(RA+RB+1)/2 */ +APUOP(M_SUMB, RR, 0x253, "sumb", _A3(A_T,A_A,A_B), 00112, FXB) /* SUM% RT<-f(RA,RB) */ +APUOP(M_DFA, RR, 0x2cc, "dfa", _A3(A_T,A_A,A_B), 00112, FPD) /* DFAdd RT<-RA+RB */ +APUOP(M_DFM, RR, 0x2ce, "dfm", _A3(A_T,A_A,A_B), 00112, FPD) /* DFMul RT<-RA*RB */ +APUOP(M_DFS, RR, 0x2cd, "dfs", _A3(A_T,A_A,A_B), 00112, FPD) /* DFSub RT<-RA-RB */ +APUOP(M_FA, RR, 0x2c4, "fa", _A3(A_T,A_A,A_B), 00112, FP6) /* FAdd RT<-RA+RB */ +APUOP(M_FM, RR, 0x2c6, "fm", _A3(A_T,A_A,A_B), 00112, FP6) /* FMul RT<-RA*RB */ +APUOP(M_FS, RR, 0x2c5, "fs", _A3(A_T,A_A,A_B), 00112, FP6) /* FSub RT<-RA-RB */ +APUOP(M_MPY, RR, 0x3c4, "mpy", _A3(A_T,A_A,A_B), 00112, FP7) /* MPY RT<-RA*RB */ +APUOP(M_MPYH, RR, 0x3c5, "mpyh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYH RT<-(RAh*RB)<<16 */ +APUOP(M_MPYHH, RR, 0x3c6, "mpyhh", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHH RT<-RAh*RBh */ +APUOP(M_MPYHHU, RR, 0x3ce, "mpyhhu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYHHU RT<-RAh*RBh */ +APUOP(M_MPYS, RR, 0x3c7, "mpys", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYS RT<-(RA*RB)>>16 */ +APUOP(M_MPYU, RR, 0x3cc, "mpyu", _A3(A_T,A_A,A_B), 00112, FP7) /* MPYU RT<-RA*RB */ +APUOP(M_FI, RR, 0x3d4, "fi", _A3(A_T,A_A,A_B), 00112, FP7) /* FInterpolate RT<-f(RA,RB) */ +APUOP(M_ROT, RR, 0x058, "rot", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */ +APUOP(M_ROTM, RR, 0x059, "rotm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */ +APUOP(M_ROTMA, RR, 0x05a, "rotma", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */ +APUOP(M_SHL, RR, 0x05b, "shl", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */ +APUOP(M_ROTH, RR, 0x05c, "roth", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT% RT<-RA<<<RB */ +APUOP(M_ROTHM, RR, 0x05d, "rothm", _A3(A_T,A_A,A_B), 00112, FX3) /* ROT%M RT<-RA<<Rb */ +APUOP(M_ROTMAH, RR, 0x05e, "rotmah", _A3(A_T,A_A,A_B), 00112, FX3) /* ROTMA% RT<-RA<<Rb */ +APUOP(M_SHLH, RR, 0x05f, "shlh", _A3(A_T,A_A,A_B), 00112, FX3) /* SHL% RT<-RA<<Rb */ +APUOP(M_MPYHHA, RR, 0x346, "mpyhha", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHA RT<-RAh*RBh+RT */ +APUOP(M_MPYHHAU, RR, 0x34e, "mpyhhau", _A3(A_T,A_A,A_B), 00113, FP7) /* MPYHHAU RT<-RAh*RBh+RT */ +APUOP(M_DFMA, RR, 0x35c, "dfma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMAdd RT<-RT+RA*RB */ +APUOP(M_DFMS, RR, 0x35d, "dfms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFMSub RT<-RA*RB-RT */ +APUOP(M_DFNMS, RR, 0x35e, "dfnms", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMSub RT<-RT-RA*RB */ +APUOP(M_DFNMA, RR, 0x35f, "dfnma", _A3(A_T,A_A,A_B), 00113, FPD) /* DFNMAdd RT<-(-RT)-RA*RB */ +APUOP(M_FMA, RRR, 0x700, "fma", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMAdd RC<-RT+RA*RB */ +APUOP(M_FMS, RRR, 0x780, "fms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FMSub RC<-RA*RB-RT */ +APUOP(M_FNMS, RRR, 0x680, "fnms", _A4(A_C,A_A,A_B,A_T), 02111, FP6) /* FNMSub RC<-RT-RA*RB */ +APUOP(M_MPYA, RRR, 0x600, "mpya", _A4(A_C,A_A,A_B,A_T), 02111, FP7) /* MPYA RC<-RA*RB+RT */ +APUOP(M_SELB, RRR, 0x400, "selb", _A4(A_C,A_A,A_B,A_T), 02111, FX2) /* SELectBits RC<-RA&RT|RB&!RT */ +/* for system function call, this uses op-code of mtspr */ +APUOP(M_SYSCALL, RI7, 0x10c, "syscall", _A3(A_T,A_A,A_S7N), 00002, SPR) /* System Call */ +/* +pseudo instruction: +system call +value of I9 operation +0 halt +1 rt[0] = open(MEM[ra[0]], ra[1]) +2 rt[0] = close(ra[0]) +3 rt[0] = read(ra[0], MEM[ra[1]], ra[2]) +4 rt[0] = write(ra[0], MEM[ra[1]], ra[2]) +5 printf(MEM[ra[0]], ra[1], ra[2], ra[3]) +42 rt[0] = clock() +52 rt[0] = lseek(ra0, ra1, ra2) + +*/ + + +/* new multiprecision add/sub */ +APUOP(M_ADDX, RR, 0x340, "addx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */ +APUOP(M_CG, RR, 0x0c2, "cg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */ +APUOP(M_CGX, RR, 0x342, "cgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */ +APUOP(M_SFX, RR, 0x341, "sfx", _A3(A_T,A_A,A_B), 00113, FX2) /* Add_eXtended RT<-RA+RB+RT */ +APUOP(M_BG, RR, 0x042, "bg", _A3(A_T,A_A,A_B), 00112, FX2) /* CarryGenerate RT<-cout(RA+RB) */ +APUOP(M_BGX, RR, 0x343, "bgx", _A3(A_T,A_A,A_B), 00113, FX2) /* CarryGen_eXtd RT<-cout(RA+RB+RT) */ + +/* + +The following ops are a subset of above except with feature bits set. +Feature bits are bits 11-17 of the instruction: + + 11 - C & P feature bit + 12 - disable interrupts + 13 - enable interrupts + +*/ +APUOPFB(M_BID, RR, 0x1a8, 0x20, "bid", _A1(A_A), 00010, BR) /* BI IP<-RA */ +APUOPFB(M_BIE, RR, 0x1a8, 0x10, "bie", _A1(A_A), 00010, BR) /* BI IP<-RA */ +APUOPFB(M_BISLD, RR, 0x1a9, 0x20, "bisld", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ +APUOPFB(M_BISLE, RR, 0x1a9, 0x10, "bisle", _A2(A_T,A_A), 00012, BR) /* BISL RT,IP<-IP,RA */ +APUOPFB(M_IRETD, RR, 0x1aa, 0x20, "iretd", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ +APUOPFB(M_IRETD2, RR, 0x1aa, 0x20, "iretd", _A0(), 00010, BR) /* IRET IP<-SRR0 */ +APUOPFB(M_IRETE, RR, 0x1aa, 0x10, "irete", _A1(A_A), 00010, BR) /* IRET IP<-SRR0 */ +APUOPFB(M_IRETE2, RR, 0x1aa, 0x10, "irete", _A0(), 00010, BR) /* IRET IP<-SRR0 */ +APUOPFB(M_BISLEDD, RR, 0x1ab, 0x20, "bisledd", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ +APUOPFB(M_BISLEDE, RR, 0x1ab, 0x10, "bislede", _A2(A_T,A_A), 00012, BR) /* BISLED RT,IP<-IP,RA_if(ext) */ +APUOPFB(M_BIHNZD, RR, 0x12b, 0x20, "bihnzd", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ +APUOPFB(M_BIHNZE, RR, 0x12b, 0x10, "bihnze", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ +APUOPFB(M_BIHZD, RR, 0x12a, 0x20, "bihzd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ +APUOPFB(M_BIHZE, RR, 0x12a, 0x10, "bihze", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ +APUOPFB(M_BINZD, RR, 0x129, 0x20, "binzd", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ +APUOPFB(M_BINZE, RR, 0x129, 0x10, "binze", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ +APUOPFB(M_BIZD, RR, 0x128, 0x20, "bizd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ +APUOPFB(M_BIZE, RR, 0x128, 0x10, "bize", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ +APUOPFB(M_SYNCC, RR, 0x002, 0x40, "syncc", _A0(), 00000, BR) /* SYNCC flush_pipe */ +APUOPFB(M_HBRP, LBTI, 0x1ac, 0x40, "hbrp", _A0(), 00010, LS) /* HBR BTB[B9]<-M[Ra] */ + +/* Synonyms required by the AS manual. */ +APUOP(M_LR, RI10, 0x020, "lr", _A2(A_T,A_A), 00012, FX2) /* OR%I RT<-RA|I10 */ +APUOP(M_BIHT, RR, 0x12b, "biht", _A2(A_T,A_A), 00011, BR) /* BIHNZ IP<-RA_if(RT) */ +APUOP(M_BIHF, RR, 0x12a, "bihf", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ +APUOP(M_BIT, RR, 0x129, "bit", _A2(A_T,A_A), 00011, BR) /* BINZ IP<-RA_if(RT) */ +APUOP(M_BIF, RR, 0x128, "bif", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ +APUOPFB(M_BIHTD, RR, 0x12b, 0x20, "bihtd", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */ +APUOPFB(M_BIHTE, RR, 0x12b, 0x10, "bihte", _A2(A_T,A_A), 00011, BR) /* BIHNF IP<-RA_if(RT) */ +APUOPFB(M_BIHFD, RR, 0x12a, 0x20, "bihfd", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ +APUOPFB(M_BIHFE, RR, 0x12a, 0x10, "bihfe", _A2(A_T,A_A), 00011, BR) /* BIHZ IP<-RA_if(RT) */ +APUOPFB(M_BITD, RR, 0x129, 0x20, "bitd", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */ +APUOPFB(M_BITE, RR, 0x129, 0x10, "bite", _A2(A_T,A_A), 00011, BR) /* BINF IP<-RA_if(RT) */ +APUOPFB(M_BIFD, RR, 0x128, 0x20, "bifd", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ +APUOPFB(M_BIFE, RR, 0x128, 0x10, "bife", _A2(A_T,A_A), 00011, BR) /* BIZ IP<-RA_if(RT) */ + +/* New soma double-float insns. */ +APUOP(M_DFCEQ, RR, 0x3c3, "dfceq", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCEQ RT<-(RA=RB) */ +APUOP(M_DFCMEQ, RR, 0x3cb, "dfcmeq", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCMEQ RT<-(|RA|=|RB|) */ +APUOP(M_DFCGT, RR, 0x2c3, "dfcgt", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCGT RT<-(RA>RB) */ +APUOP(M_DFCMGT, RR, 0x2cb, "dfcmgt", _A3(A_T,A_A,A_B), 00112, FX2) /* DFCMGT RT<-(|RA|>|RB|) */ +APUOP(M_DFTSV, RI7, 0x3bf, "dftsv", _A3(A_T,A_A,A_U7), 00012, FX2) /* DFTSV RT<-testspecial(RA,I7) */ + +#undef _A0 +#undef _A1 +#undef _A2 +#undef _A3 +#undef _A4 diff --git a/contrib/binutils/include/opcode/spu.h b/contrib/binutils/include/opcode/spu.h new file mode 100644 index 0000000..975b1fd --- /dev/null +++ b/contrib/binutils/include/opcode/spu.h @@ -0,0 +1,126 @@ +/* SPU ELF support for BFD. + + Copyright 2006 Free Software Foundation, Inc. + + This file is part of GDB, GAS, and the GNU binutils. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software Foundation, + Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ + + +/* These two enums are from rel_apu/common/spu_asm_format.h */ +/* definition of instruction format */ +typedef enum { + RRR, + RI18, + RI16, + RI10, + RI8, + RI7, + RR, + LBT, + LBTI, + IDATA, + UNKNOWN_IFORMAT +} spu_iformat; + +/* These values describe assembly instruction arguments. They indicate + * how to encode, range checking and which relocation to use. */ +typedef enum { + A_T, /* register at pos 0 */ + A_A, /* register at pos 7 */ + A_B, /* register at pos 14 */ + A_C, /* register at pos 21 */ + A_S, /* special purpose register at pos 7 */ + A_H, /* channel register at pos 7 */ + A_P, /* parenthesis, this has to separate regs from immediates */ + A_S3, + A_S6, + A_S7N, + A_S7, + A_U7A, + A_U7B, + A_S10B, + A_S10, + A_S11, + A_S11I, + A_S14, + A_S16, + A_S18, + A_R18, + A_U3, + A_U5, + A_U6, + A_U7, + A_U14, + A_X16, + A_U18, + A_MAX +} spu_aformat; + +enum spu_insns { +#define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \ + TAG, +#define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \ + TAG, +#include "opcode/spu-insns.h" +#undef APUOP +#undef APUOPFB + M_SPU_MAX +}; + +struct spu_opcode +{ + spu_iformat insn_type; + unsigned int opcode; + char *mnemonic; + int arg[5]; +}; + +#define SIGNED_EXTRACT(insn,size,pos) (((int)((insn) << (32-size-pos))) >> (32-size)) +#define UNSIGNED_EXTRACT(insn,size,pos) (((insn) >> pos) & ((1 << size)-1)) + +#define DECODE_INSN_RT(insn) (insn & 0x7f) +#define DECODE_INSN_RA(insn) ((insn >> 7) & 0x7f) +#define DECODE_INSN_RB(insn) ((insn >> 14) & 0x7f) +#define DECODE_INSN_RC(insn) ((insn >> 21) & 0x7f) + +#define DECODE_INSN_I10(insn) SIGNED_EXTRACT(insn,10,14) +#define DECODE_INSN_U10(insn) UNSIGNED_EXTRACT(insn,10,14) + +/* For branching, immediate loads, hbr and lqa/stqa. */ +#define DECODE_INSN_I16(insn) SIGNED_EXTRACT(insn,16,7) +#define DECODE_INSN_U16(insn) UNSIGNED_EXTRACT(insn,16,7) + +/* for stop */ +#define DECODE_INSN_U14(insn) UNSIGNED_EXTRACT(insn,14,0) + +/* For ila */ +#define DECODE_INSN_I18(insn) SIGNED_EXTRACT(insn,18,7) +#define DECODE_INSN_U18(insn) UNSIGNED_EXTRACT(insn,18,7) + +/* For rotate and shift and generate control mask */ +#define DECODE_INSN_I7(insn) SIGNED_EXTRACT(insn,7,14) +#define DECODE_INSN_U7(insn) UNSIGNED_EXTRACT(insn,7,14) + +/* For float <-> int conversion */ +#define DECODE_INSN_I8(insn) SIGNED_EXTRACT(insn,8,14) +#define DECODE_INSN_U8(insn) UNSIGNED_EXTRACT(insn,8,14) + +/* For hbr */ +#define DECODE_INSN_I9a(insn) ((SIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0)) +#define DECODE_INSN_I9b(insn) ((SIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0)) +#define DECODE_INSN_U9a(insn) ((UNSIGNED_EXTRACT(insn,2,23) << 7) | UNSIGNED_EXTRACT(insn,7,0)) +#define DECODE_INSN_U9b(insn) ((UNSIGNED_EXTRACT(insn,2,14) << 7) | UNSIGNED_EXTRACT(insn,7,0)) + |
