Proberly support the Promise TX2/4.

Programming info kindly provided by Daniela Engert <dani@ngrt.de>

3 files changed, 51 insertions, 8 deletions

diff --git a/sys/dev/ata/ata-all.h b/sys/dev/ata/ata-all.h
index e78ad7b..f09a19f 100644
--- a/sys/dev/ata/ata-all.h
+++ b/sys/dev/ata/ata-all.h
@@ -133,6 +133,8 @@
 #define ATA_BMCMD_START_STOP		0x01
 #define ATA_BMCMD_WRITE_READ		0x08
 
+#define ATA_BMDEVSPEC_0			0x01
+
 #define ATA_BMSTAT_PORT			0x02
 #define ATA_BMSTAT_ACTIVE		0x01
 #define ATA_BMSTAT_ERROR		0x02
@@ -142,6 +144,8 @@
 #define ATA_BMSTAT_DMA_SLAVE		0x40
 #define ATA_BMSTAT_DMA_SIMPLEX		0x80
 
+#define ATA_BDDEVSPEC_1			0x03
+
 #define ATA_BMDTP_PORT			0x04
 
 /* structure for holding DMA address data */
diff --git a/sys/dev/ata/ata-dma.c b/sys/dev/ata/ata-dma.c
index 15aa9ba..4062f29 100644
--- a/sys/dev/ata/ata-dma.c
+++ b/sys/dev/ata/ata-dma.c
@@ -723,10 +723,48 @@ via_82c586:
 	/* we could set PIO mode timings, but we assume the BIOS did that */
 	break;
 
-    case 0x4d30105a:	/* Promise Ultra/FastTrak 100 controllers */
-    case 0x0d30105a:	/* Promise OEM ATA100 controllers */
     case 0x4d68105a:	/* Promise TX2 ATA100 controllers */
     case 0x6268105a:	/* Promise TX2v2 ATA100 controllers */
+	ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
+	if (udmamode >= 4 && (ATA_INB(scp->r_bmio, ATA_BDDEVSPEC_1) & 0x20)) {
+	    error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
+				ATA_UDMA + max(udmamode, 5), ATA_C_F_SETXFER,
+				ATA_WAIT_READY);
+	    if (bootverbose)
+		ata_printf(scp, device, "%s setting %s on Promise chip\n",
+			   (error) ? "failed" : "success", 
+			   ata_mode2str(ATA_UDMA + max(udmamode, 5)));
+	    if (!error) {
+		scp->mode[ATA_DEV(device)] = ATA_UDMA + (max(udmamode, 5));
+		return;
+	    }
+	}
+	if (udmamode >= 2) {
+	    error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
+				ATA_UDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
+	    if (bootverbose)
+		ata_printf(scp, device, "%s setting %s on Promise chip\n",
+			   (error) ? "failed" : "success", "UDMA2");
+	    if (!error) {
+		scp->mode[ATA_DEV(device)] = ATA_UDMA2;
+		return;
+	    }
+	}
+	if (wdmamode >= 2 && apiomode >= 4) {
+	    error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
+				ATA_WDMA2, ATA_C_F_SETXFER, ATA_WAIT_READY);
+	    if (bootverbose)
+		ata_printf(scp, device, "%s setting %s on Promise chip\n",
+			   (error) ? "failed" : "success", "WDMA2");
+	    if (!error) {
+		scp->mode[ATA_DEV(device)] = ATA_WDMA2;
+		return;
+	    }
+	}
+	break;
+
+    case 0x4d30105a:	/* Promise Ultra/FastTrak 100 controllers */
+    case 0x0d30105a:	/* Promise OEM ATA100 controllers */
 	if (!ATAPI_DEVICE(scp, device) && udmamode >= 5 && 
 	    !(pci_read_config(parent, 0x50, 2)&(scp->channel ? 1<<11 : 1<<10))){
 	    error = ata_command(scp, device, ATA_C_SETFEATURES, 0, 0, 0,
@@ -1058,10 +1096,6 @@ promise_timing(struct ata_softc *scp, int devno, int mode)
 	case ATA_UDMA5: t->pa =  3; t->pb =  7; t->mb = 1; t->mc =  1; break;
 	}
 	break;
-
-    case 0x4d68105a:  /* Promise TX2 ATA 100 */
-    case 0x6268105a:  /* Promise TX2v2 ATA 100 */
-	return;
     }
     pci_write_config(device_get_parent(scp->dev), 0x60 + (devno<<2), timing, 4);
 }
diff --git a/sys/dev/ata/ata-pci.c b/sys/dev/ata/ata-pci.c
index 67d9955..98861db 100644
--- a/sys/dev/ata/ata-pci.c
+++ b/sys/dev/ata/ata-pci.c
@@ -437,12 +437,17 @@ ata_pci_intr(struct ata_softc *scp)
     case 0x4d38105a:	/* Promise Ultra/Fasttrak 66 */
     case 0x4d30105a:	/* Promise Ultra/Fasttrak 100 */
     case 0x0d30105a:	/* Promise OEM ATA100 */
-    case 0x4d68105a:	/* Promise TX2 ATA100 */
-    case 0x6268105a:	/* Promise TX2v2 ATA100 */
 	if (!(ATA_INL(scp->r_bmio, (scp->channel ? 0x14 : 0x1c)) &
 	      (scp->channel ? 0x00004000 : 0x00000400)))
 	    return 1;
     	break;
+
+    case 0x4d68105a:	/* Promise TX2 ATA100 */
+    case 0x6268105a:	/* Promise TX2v2 ATA100 */
+	ATA_OUTB(scp->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
+	if (!(ATA_INB(scp->r_bmio, ATA_BDDEVSPEC_1) & 0x20))
+	    return 1;
+	break;
     }
 
     if (scp->flags & ATA_DMA_ACTIVE) {