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| author | raj <raj@FreeBSD.org> | 2008-10-16 19:06:24 +0000 |
|---|---|---|
| committer | raj <raj@FreeBSD.org> | 2008-10-16 19:06:24 +0000 |
| commit | eece70b41c85532ab7fff01d9abbb753b9c5a271 (patch) | |
| tree | b656fdf470327aabf7ac44f8acccb87abcc14e49 | |
| parent | 85d2767d87eb28294c3d5a4c13d9a00acc3ec318 (diff) | |
| download | FreeBSD-src-eece70b41c85532ab7fff01d9abbb753b9c5a271.zip FreeBSD-src-eece70b41c85532ab7fff01d9abbb753b9c5a271.tar.gz | |
Eliminate flushing of L2 cache in ARM context switch routines.
With VIPT L2 cache such syncing not only is redundant, but also a performance
penalty.
Pointed out by: cognet
| -rw-r--r-- | sys/arm/arm/swtch.S | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/sys/arm/arm/swtch.S b/sys/arm/arm/swtch.S index 59c2b63..8f0f9b2 100644 --- a/sys/arm/arm/swtch.S +++ b/sys/arm/arm/swtch.S @@ -143,8 +143,6 @@ ENTRY(cpu_throw) ldr r9, .Lcpufuncs mov lr, pc ldr pc, [r9, #CF_IDCACHE_WBINV_ALL] - mov lr, pc - ldr pc, [r9, #CF_L2CACHE_WBINV_ALL] ldr r0, [r7, #(PCB_PL1VEC)] ldr r1, [r7, #(PCB_DACR)] /* @@ -174,8 +172,6 @@ ENTRY(cpu_throw) movne r1, #4 movne lr, pc ldrne pc, [r9, #CF_DCACHE_WB_RANGE] - movne lr, pc - ldrne pc, [r9, #CF_L2CACHE_WB_RANGE] #endif /* PMAP_INCLUDE_PTE_SYNC */ /* @@ -332,8 +328,6 @@ ENTRY(cpu_switch) ldr r1, .Lcpufuncs mov lr, pc ldr pc, [r1, #CF_IDCACHE_WBINV_ALL] - mov lr, pc - ldr pc, [r1, #CF_L2CACHE_WBINV_ALL] .Lcs_cache_purge_skipped: /* rem: r6 = lock */ /* rem: r9 = new PCB */ @@ -366,8 +360,6 @@ ENTRY(cpu_switch) mov r1, #4 mov lr, pc ldr pc, [r2, #CF_DCACHE_WB_RANGE] - mov lr, pc - ldr pc, [r2, #CF_L2CACHE_WB_RANGE] .Lcs_same_vector: #endif /* PMAP_INCLUDE_PTE_SYNC */ |
