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| author | gonzo <gonzo@FreeBSD.org> | 2012-11-27 06:39:32 +0000 |
|---|---|---|
| committer | gonzo <gonzo@FreeBSD.org> | 2012-11-27 06:39:32 +0000 |
| commit | ed870aa12f14d550575fecc9a3bf4a63ab4d88c8 (patch) | |
| tree | a29b0b7df953cdd4e37ed0078e183615e562d5ae | |
| parent | d927dc20395a1bdcb9085bb11d037e17b8dff7c4 (diff) | |
| download | FreeBSD-src-ed870aa12f14d550575fecc9a3bf4a63ab4d88c8.zip FreeBSD-src-ed870aa12f14d550575fecc9a3bf4a63ab4d88c8.tar.gz | |
Do not enable data cache until later in kernel init. Stale bits in
cache might cause erroneus behavior on early stage.
Submitted by: Ian Lepore
Tested on: Atmel, Marvell, and Eyxnos
| -rw-r--r-- | sys/arm/arm/locore.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/sys/arm/arm/locore.S b/sys/arm/arm/locore.S index e81912c..8d2da54 100644 --- a/sys/arm/arm/locore.S +++ b/sys/arm/arm/locore.S @@ -181,7 +181,7 @@ Lunmapped: #if defined(CPU_ARM11) || defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) orr r0, r0, #CPU_CONTROL_V6_EXTPAGE #endif - orr r0, r0, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE) + orr r0, r0, #(CPU_CONTROL_MMU_ENABLE) mcr p15, 0, r0, c1, c0, 0 nop nop |
