Use a register to set the cpsr bits. The ip register is safe to be changed

within all of these functions, and is only stored in some to correctly pad
the stack.

This will be needed to build as Thumb-2 as, unlike with ARM instructions,
the msr instruction only takes a register as the input.

2 files changed, 12 insertions, 8 deletions

diff --git a/lib/libc/arm/aeabi/aeabi_asm_double.S b/lib/libc/arm/aeabi/aeabi_asm_double.S
index ab44362..7a5af82 100644
--- a/lib/libc/arm/aeabi/aeabi_asm_double.S
+++ b/lib/libc/arm/aeabi/aeabi_asm_double.S
@@ -56,7 +56,7 @@ ENTRY(__aeabi_cdcmple)
 	cmp	r0, #1
 	bne	1f
 	/* Yes, clear Z and C */
-	msr	cpsr_c, #(0)
+	mov	ip, #(0)
 	b	99f
 
 1:
@@ -70,14 +70,15 @@ ENTRY(__aeabi_cdcmple)
 	cmp	r0, #1
 	bne	2f
 	/* Yes, set Z and C */
-	msr	cpsr_c, #(PCR_Z | PCR_C)
+	mov	ip, #(PCR_Z | PCR_C)
 	b 99f
 
 2:
 	/* Not less than or equal, set C and clear Z */
-	msr	cpsr_c, #(PCR_C)
+	mov	ip, #(PCR_C)
 
 99:
+	msr	cpsr_c, ip
 	pop	{r4, r5, r6, r7, ip, pc}
 END(__aeabi_cdcmple)
 
@@ -112,6 +113,7 @@ ENTRY(__aeabi_cdcmpeq)
 	RET
 
 1:
-	msr	cpsr_c, #(PCR_C)
+	mov	ip, #(PCR_C)
+	msr	cpsr_c, ip
 	RET
 END(__aeabi_cdcmpeq)
diff --git a/lib/libc/arm/aeabi/aeabi_asm_float.S b/lib/libc/arm/aeabi/aeabi_asm_float.S
index bf32af7..e05daa5 100644
--- a/lib/libc/arm/aeabi/aeabi_asm_float.S
+++ b/lib/libc/arm/aeabi/aeabi_asm_float.S
@@ -54,7 +54,7 @@ ENTRY(__aeabi_cfcmple)
 	cmp	r0, #1
 	bne	1f
 	/* Yes, clear Z and C */
-	msr	cpsr_c, #(0)
+	mov	ip, #(0)
 	b	99f
 
 1:
@@ -66,14 +66,15 @@ ENTRY(__aeabi_cfcmple)
 	cmp	r0, #1
 	bne	2f
 	/* Yes, set Z and C */
-	msr	cpsr_c, #(PCR_Z | PCR_C)
+	mov	ip, #(PCR_Z | PCR_C)
 	b 99f
 
 2:
 	/* Not less than or equal, set C and clear Z */
-	msr	cpsr_c, #(PCR_C)
+	mov	ip, #(PCR_C)
 
 99:
+	msr	cpsr_c, ip
 	pop	{r4, r5, ip, pc}
 END(__aeabi_cfcmple)
 
@@ -103,6 +104,7 @@ ENTRY(__aeabi_cfcmpeq)
 	RET
 
 1:
-	msreq	cpsr_c, #(PCR_C)
+	mov	ip, #(PCR_C)
+	msr	cpsr_c, ip
 	RET
 END(__aeabi_cfcmpeq)