- Support for multiple PD6832 controllers. Each found 6832 is assigned

  and initializes the next two ports in order starting at 03e0.  This
  also patches pcic_p.h to reduce the I/O ports mapped from 4 to 2.

Submitted by:	Ted Faber <faber@ISI.EDU>

4 files changed, 44 insertions, 8 deletions

diff --git a/sys/pccard/pcic_pci.c b/sys/pccard/pcic_pci.c
index 6c9240e..f5a6aee 100644
--- a/sys/pccard/pcic_pci.c
+++ b/sys/pccard/pcic_pci.c
@@ -37,6 +37,7 @@
 #include <pci/pcireg.h>
 #include <pci/pcivar.h>
 #include <pci/pcic_p.h>
+#include <pccard/i82365.h>
 #include <vm/vm.h>
 #include <vm/pmap.h>
 
@@ -134,6 +135,19 @@ pd6832_legacy_init(pcici_t tag, int unit)
 {
 	u_long bcr; 		/* to set interrupts */
 	u_short io_port;	/* the io_port to map this slot on */
+	static int num6832 = 0; /* The number of 6832s initialized */
+
+	/*
+	 * Some BIOS leave the legacy address uninitialized.  This
+	 * insures that the PD6832 puts itself where the driver will
+	 * look.  We assume that multiple 6832's should be laid out
+	 * sequentially.  We only initialize the first socket's legacy port,
+	 * the other is a dummy.
+	 */
+	io_port = PCIC_INDEX_0 + num6832 * CLPD6832_NUM_REGS;
+	if (unit == 0)
+	    pci_conf_write(tag, CLPD6832_LEGACY_16BIT_IOADDR,
+		           io_port & ~PCI_MAP_IO);
 
 	/*
 	 * I think this should be a call to pci_map_port, but that
@@ -152,7 +166,7 @@ pd6832_legacy_init(pcici_t tag, int unit)
 	pci_conf_write(tag, CLPD6832_IO_LIMIT0,
 		       (io_port + CLPD6832_NUM_REGS) | 1);
 
-	pci_conf_write(tag, CLPD6832_IO_BASE1, (io_port +0x20) | 1);
+	pci_conf_write(tag, CLPD6832_IO_BASE1, (io_port + 0x20) | 1);
 	pci_conf_write(tag, CLPD6832_IO_LIMIT1, io_port | 1 );
 
 	/*
@@ -170,8 +184,12 @@ pd6832_legacy_init(pcici_t tag, int unit)
 	bcr |= (CLPD6832_BCR_ISA_IRQ|CLPD6832_BCR_MGMT_IRQ_ENA);
 	pci_conf_write(tag, CLPD6832_BRIDGE_CONTROL, bcr);
 
+	/* After initializing 2 sockets, the chip is fully configured */
+	if (unit == 1)
+		num6832++;
+
 	if (bootverbose)
 		printf("CardBus: Legacy PC-card 16bit I/O address [0x%x]\n",
-		   io_port);
+		       io_port);
 }
 #endif /* NPCI > 0 */
diff --git a/sys/pccard/pcic_pci.h b/sys/pccard/pcic_pci.h
index 81145b2..088193c 100644
--- a/sys/pccard/pcic_pci.h
+++ b/sys/pccard/pcic_pci.h
@@ -26,7 +26,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * $Id$
+ * $Id: pcic_p.h,v 1.2 1997/12/02 22:13:59 nate Exp $
  */
 
 /* PCI/CardBus Device IDs */
@@ -49,6 +49,6 @@
 #define	CLPD6832_BCR_MGMT_IRQ_ENA	0x08000000
 #define	CLPD6832_BCR_ISA_IRQ		0x00800000
 #define	CLPD6832_COMMAND_DEFAULTS	0x00000045
-#define	CLPD6832_NUM_REGS		4
+#define	CLPD6832_NUM_REGS		2
 
 /* End of CL-PD6832 defines */
diff --git a/sys/pci/pcic_p.c b/sys/pci/pcic_p.c
index 6c9240e..f5a6aee 100644
--- a/sys/pci/pcic_p.c
+++ b/sys/pci/pcic_p.c
@@ -37,6 +37,7 @@
 #include <pci/pcireg.h>
 #include <pci/pcivar.h>
 #include <pci/pcic_p.h>
+#include <pccard/i82365.h>
 #include <vm/vm.h>
 #include <vm/pmap.h>
 
@@ -134,6 +135,19 @@ pd6832_legacy_init(pcici_t tag, int unit)
 {
 	u_long bcr; 		/* to set interrupts */
 	u_short io_port;	/* the io_port to map this slot on */
+	static int num6832 = 0; /* The number of 6832s initialized */
+
+	/*
+	 * Some BIOS leave the legacy address uninitialized.  This
+	 * insures that the PD6832 puts itself where the driver will
+	 * look.  We assume that multiple 6832's should be laid out
+	 * sequentially.  We only initialize the first socket's legacy port,
+	 * the other is a dummy.
+	 */
+	io_port = PCIC_INDEX_0 + num6832 * CLPD6832_NUM_REGS;
+	if (unit == 0)
+	    pci_conf_write(tag, CLPD6832_LEGACY_16BIT_IOADDR,
+		           io_port & ~PCI_MAP_IO);
 
 	/*
 	 * I think this should be a call to pci_map_port, but that
@@ -152,7 +166,7 @@ pd6832_legacy_init(pcici_t tag, int unit)
 	pci_conf_write(tag, CLPD6832_IO_LIMIT0,
 		       (io_port + CLPD6832_NUM_REGS) | 1);
 
-	pci_conf_write(tag, CLPD6832_IO_BASE1, (io_port +0x20) | 1);
+	pci_conf_write(tag, CLPD6832_IO_BASE1, (io_port + 0x20) | 1);
 	pci_conf_write(tag, CLPD6832_IO_LIMIT1, io_port | 1 );
 
 	/*
@@ -170,8 +184,12 @@ pd6832_legacy_init(pcici_t tag, int unit)
 	bcr |= (CLPD6832_BCR_ISA_IRQ|CLPD6832_BCR_MGMT_IRQ_ENA);
 	pci_conf_write(tag, CLPD6832_BRIDGE_CONTROL, bcr);
 
+	/* After initializing 2 sockets, the chip is fully configured */
+	if (unit == 1)
+		num6832++;
+
 	if (bootverbose)
 		printf("CardBus: Legacy PC-card 16bit I/O address [0x%x]\n",
-		   io_port);
+		       io_port);
 }
 #endif /* NPCI > 0 */
diff --git a/sys/pci/pcic_p.h b/sys/pci/pcic_p.h
index 81145b2..088193c 100644
--- a/sys/pci/pcic_p.h
+++ b/sys/pci/pcic_p.h
@@ -26,7 +26,7 @@
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
- * $Id$
+ * $Id: pcic_p.h,v 1.2 1997/12/02 22:13:59 nate Exp $
  */
 
 /* PCI/CardBus Device IDs */
@@ -49,6 +49,6 @@
 #define	CLPD6832_BCR_MGMT_IRQ_ENA	0x08000000
 #define	CLPD6832_BCR_ISA_IRQ		0x00800000
 #define	CLPD6832_COMMAND_DEFAULTS	0x00000045
-#define	CLPD6832_NUM_REGS		4
+#define	CLPD6832_NUM_REGS		2
 
 /* End of CL-PD6832 defines */