diff options
| author | marius <marius@FreeBSD.org> | 2007-01-20 14:57:51 +0000 |
|---|---|---|
| committer | marius <marius@FreeBSD.org> | 2007-01-20 14:57:51 +0000 |
| commit | de8f010827ae8f0e61df55a100777f1dddcb379d (patch) | |
| tree | 16de20ad59a22040ad6dba0edde54dca4a79eab5 | |
| parent | da9eaf073ea424a59bd647609632d2036a68ae77 (diff) | |
| download | FreeBSD-src-de8f010827ae8f0e61df55a100777f1dddcb379d.zip FreeBSD-src-de8f010827ae8f0e61df55a100777f1dddcb379d.tar.gz | |
Add macros for the individual divisor bits as some MC146818A-compatible
chips also use them for different purposes.
| -rw-r--r-- | sys/dev/mc146818/mc146818reg.h | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/sys/dev/mc146818/mc146818reg.h b/sys/dev/mc146818/mc146818reg.h index 3aab55f..7e17aa2 100644 --- a/sys/dev/mc146818/mc146818reg.h +++ b/sys/dev/mc146818/mc146818reg.h @@ -82,6 +82,9 @@ #define MC_REGA_RSMASK 0x0f /* Interrupt rate select mask (see below) */ #define MC_REGA_DVMASK 0x70 /* Divisor select mask (see below) */ +#define MC_REGA_DV0 0x10 /* Divisor 0 */ +#define MC_REGA_DV1 0x20 /* Divisor 1 */ +#define MC_REGA_DV2 0x40 /* Divisor 2 */ #define MC_REGA_UIP 0x80 /* Update in progress; read only. */ #define MC_REGB 0xb /* Control register B */ @@ -139,7 +142,7 @@ * Time base (divisor select) constants (Control register A) */ #define MC_BASE_4_MHz 0x00 /* 4MHz crystal */ -#define MC_BASE_1_MHz 0x10 /* 1MHz crystal */ -#define MC_BASE_32_KHz 0x20 /* 32KHz crystal */ -#define MC_BASE_NONE 0x60 /* actually, both of these reset */ -#define MC_BASE_RESET 0x70 +#define MC_BASE_1_MHz MC_REGA_DV0 /* 1MHz crystal */ +#define MC_BASE_32_KHz MC_REGA_DV1 /* 32KHz crystal */ +#define MC_BASE_NONE (MC_REGA_DV2 | MC_REGA_DV1) /* actually also resets */ +#define MC_BASE_RESET (MC_REGA_DV2 | MC_REGA_DV1 | MC_REGA_DV0) |
